Datasets:
rtl-llm
/
vhdl_github

Dataset card Data Studio Files Community
1
content
stringlengths
1
1.04M
⌀
-- William Fan -- 01/24/2011 -- Hamming Weight RTL library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity hamweight is generic (N: positive := 7); port (x: in bit_vector(N downto 0); y: out bit_vector(6 downto 0)); end entity; architecture hw of hamweight is type matrix is array (0 to N+1) of integer range 0 to N+1; signal count: matrix; begin count(0) <= 0; gen: for i in 0 to N generate count(i+1) <= count(i) + 1 WHEN x(i)='1' ELSE count(i); end generate; WITH count(N) SELECT y <= "0000001" when 0, "1001111" when 1, "0010010" when 2, "0000110" when 3, "1001100" when 4, "0100100" when 5, "0100000" when 6, "0001111" when 7, "0000000" when 8, "0110000" when others; end architecture;
-- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/> -- -- Copyright (C) 2014 Jakub Kicinski <[email protected]> library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; ENTITY tb_semaphore_cyclic IS END tb_semaphore_cyclic; ARCHITECTURE behavior OF tb_semaphore_cyclic IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT semaphore_cyclic generic (N_BITS : integer); port (Clk : in std_logic; Rst : in std_logic; Request : in std_logic_vector (N_BITS-1 downto 0); Grant : out std_logic_vector (N_BITS-1 downto 0)); END COMPONENT; --Inputs signal Clk : std_logic := '0'; signal Rst : std_logic := '0'; signal Request : std_logic_vector(2 downto 0) := (others => '0'); --Outputs signal Grant : std_logic_vector(2 downto 0); -- Clock period definitions constant Clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: semaphore_cyclic GENERIC MAP (N_BITS => 3) PORT MAP ( Clk => Clk, Rst => Rst, Request => Request, Grant => Grant ); -- Clock process definitions Clk_process :process begin Clk <= '0'; wait for Clk_period/2; Clk <= '1'; wait for Clk_period/2; end process; a1 :process begin Request(0) <= not Request(0); wait for Clk_period * 5; end process; a2 :process begin Request(1) <= not Request(1); wait for Clk_period * 6; end process; a3 :process begin Request(2) <= not Request(2); wait for Clk_period * 7; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for Clk_period*10; -- insert stimulus here wait; end process; END;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Debug Version 12.0 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from SinPiDPStratixVf400 -- VHDL created on Wed Sep 05 17:55:57 2012 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; USE work.SinPiDPStratixVf400_safe_path.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; -- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240 entity SinPiDPStratixVf400 is port ( xIn_v : in std_logic_vector(0 downto 0); xIn_c : in std_logic_vector(7 downto 0); xIn_0 : in std_logic_vector(63 downto 0); xOut_v : out std_logic_vector(0 downto 0); xOut_c : out std_logic_vector(7 downto 0); xOut_0 : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic; bus_clk : in std_logic; h_areset : in std_logic ); end; architecture normal of SinPiDPStratixVf400 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBias_uid12_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBiasPwF_uid13_fpSinPiTest_q : std_logic_vector (10 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0); signal biasM1_uid27_fpSinPiTest_q : std_logic_vector (10 downto 0); signal biasMwShift_uid29_fpSinPiTest_q : std_logic_vector (10 downto 0); signal shiftBias_uid32_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cst01pWShift_uid34_fpSinPiTest_q : std_logic_vector (27 downto 0); signal ozz_uid41_fpSinPiTest_q : std_logic_vector (78 downto 0); signal cOne_uid44_fpSinPiTest_q : std_logic_vector (80 downto 0); signal oneMinusY_uid45_fpSinPiTest_a : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_b : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_o : std_logic_vector (81 downto 0); signal oneMinusY_uid45_fpSinPiTest_q : std_logic_vector (81 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_a : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_b : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_o : std_logic_vector (84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_c : std_logic_vector (0 downto 0); signal piwFP2_uid67_fpSinPiTest_q : std_logic_vector (53 downto 0); signal or_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_b : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_c : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_q : std_logic_vector (51 downto 0); signal oneFracRPostExc2_uid90_fpSinPiTest_q : std_logic_vector (51 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (10 downto 0); signal InvXIsInt_uid100_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIsInt_uid100_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (31 downto 0); signal leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (63 downto 0); signal leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (15 downto 0); signal leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (23 downto 0); signal leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (5 downto 0); signal mO_uid148_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (48 downto 0); signal memoryC3_uid229_sinPiZTableGenerator_q : std_logic_vector(34 downto 0); signal memoryC4_uid230_sinPiZTableGenerator_q : std_logic_vector(25 downto 0); signal memoryC5_uid231_sinPiZTableGenerator_q : std_logic_vector(16 downto 0); signal rndBit_uid246_sinPiZPolyEval_q : std_logic_vector (1 downto 0); signal rndBit_uid258_sinPiZPolyEval_q : std_logic_vector (2 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_a : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 : std_logic_vector (33 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr : SIGNED (34 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_q : std_logic_vector (33 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_a : std_logic_vector (25 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_zero_36_q : std_logic_vector (26 downto 0); type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type; signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q : std_logic_vector (36 downto 0); type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o : std_logic_vector (90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o : std_logic_vector (21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q : std_logic_vector (19 downto 0); signal reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q : std_logic_vector (80 downto 0); signal reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q : std_logic_vector (80 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q : std_logic_vector (0 downto 0); signal reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (31 downto 0); signal reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (15 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (7 downto 0); signal reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q : std_logic_vector (7 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q : std_logic_vector (7 downto 0); signal reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q : std_logic_vector (78 downto 0); signal reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q : std_logic_vector (16 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q : std_logic_vector (25 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q : std_logic_vector (16 downto 0); signal reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q : std_logic_vector (17 downto 0); signal reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q : std_logic_vector (36 downto 0); signal reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q : std_logic_vector (44 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q : std_logic_vector (45 downto 0); signal reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q : std_logic_vector (51 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q : std_logic_vector (53 downto 0); signal reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q : std_logic_vector (60 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q : std_logic_vector (26 downto 0); signal reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q : std_logic_vector (6 downto 0); signal reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q : std_logic_vector (78 downto 0); signal ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q : std_logic_vector (78 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q : std_logic_vector (78 downto 0); signal ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q : std_logic_vector (14 downto 0); signal ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (63 downto 0); signal ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (31 downto 0); signal ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (31 downto 0); signal ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (15 downto 0); signal ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (15 downto 0); signal ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q : std_logic_vector (0 downto 0); signal ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q : std_logic_vector (0 downto 0); signal ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (1 downto 0); signal ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (42 downto 0); signal ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q : std_logic_vector (88 downto 0); signal ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q : std_logic_vector (79 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic; signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic; signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic; signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 : std_logic; signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i : unsigned(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q : std_logic_vector (3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i : unsigned(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q : std_logic_vector (6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i : unsigned(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q : std_logic_vector (2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (14 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ir : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i : unsigned(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q : std_logic_vector (2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ir : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ir : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 : std_logic; signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ir : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0); signal yIsZero_uid40_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (18 downto 0); signal pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal z_uid49_fpSinPiTest_s : std_logic_vector (0 downto 0); signal z_uid49_fpSinPiTest_q : std_logic_vector (78 downto 0); signal expHardCase_uid57_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expHardCase_uid57_fpSinPiTest_q : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_q : std_logic_vector (11 downto 0); signal rndExpUpdate_uid75_uid76_fpSinPiTest_q : std_logic_vector (53 downto 0); signal expFracComp_uid77_fpSinPiTest_a : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_b : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_o : std_logic_vector (64 downto 0); signal expFracComp_uid77_fpSinPiTest_q : std_logic_vector (64 downto 0); signal fracRPostExc_uid91_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc_uid91_fpSinPiTest_q : std_logic_vector (51 downto 0); signal expRPostExc_uid98_fpSinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid98_fpSinPiTest_q : std_logic_vector (10 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal memoryC0_uid226_sinPiZTableGenerator_q : std_logic_vector(57 downto 0); signal memoryC1_uid227_sinPiZTableGenerator_q : std_logic_vector(49 downto 0); signal memoryC2_uid228_sinPiZTableGenerator_q : std_logic_vector(42 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_a : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_b : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_o : std_logic_vector (35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_q : std_logic_vector (35 downto 0); signal ts3_uid248_sinPiZPolyEval_a : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_b : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_o : std_logic_vector (45 downto 0); signal ts3_uid248_sinPiZPolyEval_q : std_logic_vector (45 downto 0); signal ts4_uid254_sinPiZPolyEval_a : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_b : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_o : std_logic_vector (52 downto 0); signal ts4_uid254_sinPiZPolyEval_q : std_logic_vector (52 downto 0); signal ts5_uid260_sinPiZPolyEval_a : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_b : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_o : std_logic_vector (61 downto 0); signal ts5_uid260_sinPiZPolyEval_q : std_logic_vector (61 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal join_uid42_fpSinPiTest_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal expX_uid6_fpSinPiTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSinPiTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSinPiTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSinPiTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0); signal expXIsMax_uid16_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSinPiTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid15_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_q : std_logic_vector(0 downto 0); signal xIntExp_uid26_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xIntExp_uid26_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xIntExp_uid26_fpSinPiTest_c : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xFrac_uid28_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_n : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_a : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_b : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_o : std_logic_vector (13 downto 0); signal sinXIsX_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0); signal shiftValue_uid33_fpSinPiTest_a : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_b : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_o : std_logic_vector (11 downto 0); signal shiftValue_uid33_fpSinPiTest_q : std_logic_vector (11 downto 0); signal oMyBottom_uid47_fpSinPiTest_in : std_logic_vector (78 downto 0); signal oMyBottom_uid47_fpSinPiTest_b : std_logic_vector (78 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid150_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal cIncludingRoundingBit_uid247_sinPiZPolyEval_q : std_logic_vector (44 downto 0); signal cIncludingRoundingBit_uid253_sinPiZPolyEval_q : std_logic_vector (51 downto 0); signal cIncludingRoundingBit_uid259_sinPiZPolyEval_q : std_logic_vector (60 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q : std_logic_vector (107 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (29 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (46 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q : std_logic_vector (108 downto 0); signal yIsZero_uid43_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zPPolyEval_uid64_fpSinPiTest_in : std_logic_vector (71 downto 0); signal zPPolyEval_uid64_fpSinPiTest_b : std_logic_vector (44 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_q : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_c : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (31 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (15 downto 0); signal s2_uid240_uid243_sinPiZPolyEval_q : std_logic_vector (36 downto 0); signal add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (55 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (42 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (72 downto 0); signal add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal R_uid105_fpSinPiTest_q : std_logic_vector (63 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal yT3_uid244_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT3_uid244_sinPiZPolyEval_b : std_logic_vector (34 downto 0); signal yT4_uid250_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT4_uid250_sinPiZPolyEval_b : std_logic_vector (42 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q : std_logic_vector(0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_b : std_logic_vector (26 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zAddr_uid63_fpSinPiTest_in : std_logic_vector (78 downto 0); signal zAddr_uid63_fpSinPiTest_b : std_logic_vector (6 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (78 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (63 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (14 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (14 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (46 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (46 downto 0); signal expHardCaseR_uid60_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expHardCaseR_uid60_fpSinPiTest_b : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracRComp_uid78_fpSinPiTest_in : std_logic_vector (52 downto 0); signal fracRComp_uid78_fpSinPiTest_b : std_logic_vector (51 downto 0); signal expRComp_uid79_fpSinPiTest_in : std_logic_vector (63 downto 0); signal expRComp_uid79_fpSinPiTest_b : std_logic_vector (10 downto 0); signal intXParity_uid38_fpSinPiTest_in : std_logic_vector (80 downto 0); signal intXParity_uid38_fpSinPiTest_b : std_logic_vector (0 downto 0); signal y_uid39_fpSinPiTest_in : std_logic_vector (79 downto 0); signal y_uid39_fpSinPiTest_b : std_logic_vector (79 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (77 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (77 downto 0); signal s3_uid249_sinPiZPolyEval_in : std_logic_vector (45 downto 0); signal s3_uid249_sinPiZPolyEval_b : std_logic_vector (44 downto 0); signal s4_uid255_sinPiZPolyEval_in : std_logic_vector (52 downto 0); signal s4_uid255_sinPiZPolyEval_b : std_logic_vector (51 downto 0); signal s5_uid261_sinPiZPolyEval_in : std_logic_vector (61 downto 0); signal s5_uid261_sinPiZPolyEval_b : std_logic_vector (60 downto 0); signal oFracX_uid31_uid31_fpSinPiTest_q : std_logic_vector (52 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_in : std_logic_vector (6 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_b : std_logic_vector (6 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid235_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal highBBits_uid235_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid241_sinPiZPolyEval_in : std_logic_vector (28 downto 0); signal highBBits_uid241_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q : std_logic_vector(107 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (29 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (46 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal normBit_uid70_fpSinPiTest_in : std_logic_vector (106 downto 0); signal normBit_uid70_fpSinPiTest_b : std_logic_vector (0 downto 0); signal highRes_uid71_fpSinPiTest_in : std_logic_vector (105 downto 0); signal highRes_uid71_fpSinPiTest_b : std_logic_vector (52 downto 0); signal lowRes_uid72_fpSinPiTest_in : std_logic_vector (104 downto 0); signal lowRes_uid72_fpSinPiTest_b : std_logic_vector (52 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (70 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (70 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (62 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (62 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (54 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (54 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q : std_logic_vector(0 downto 0); signal yT1_uid232_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT1_uid232_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal yT2_uid238_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT2_uid238_sinPiZPolyEval_b : std_logic_vector (25 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (63 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (9 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (9 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (36 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (71 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (45 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (78 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (7 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (7 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (15 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (15 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expP_uid61_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expP_uid61_fpSinPiTest_q : std_logic_vector (10 downto 0); signal yBottom_uid48_fpSinPiTest_in : std_logic_vector (78 downto 0); signal yBottom_uid48_fpSinPiTest_b : std_logic_vector (78 downto 0); signal leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (51 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal fxpSinRes_uid66_fpSinPiTest_in : std_logic_vector (58 downto 0); signal fxpSinRes_uid66_fpSinPiTest_b : std_logic_vector (53 downto 0); signal extendedFracX_uid35_fpSinPiTest_q : std_logic_vector (80 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (0 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_a : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_b : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_o : std_logic_vector (26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q : std_logic_vector(107 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_q : std_logic_vector (52 downto 0); signal join_uid97_fpSinPiTest_q : std_logic_vector (1 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal signR_uid104_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (10 downto 0); signal pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (16 downto 0); signal pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal xIsInt_uid83_fpSinPiTest_a : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_b : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal multRightOp_uid68_fpSinPiTest_s : std_logic_vector (0 downto 0); signal multRightOp_uid68_fpSinPiTest_q : std_logic_vector (53 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (48 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (48 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (16 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (16 downto 0); signal s1_uid234_uid237_sinPiZPolyEval_q : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c : std_logic_vector (19 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in : std_logic_vector (106 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b : std_logic_vector (106 downto 0); signal expFracPreRnd_uid74_uid74_fpSinPiTest_q : std_logic_vector (63 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (17 downto 0); signal alignedZLow_uid53_fpSinPiTest_in : std_logic_vector (78 downto 0); signal alignedZLow_uid53_fpSinPiTest_b : std_logic_vector (51 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_b : std_logic_vector (26 downto 0); signal leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q : std_logic_vector (107 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (1 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (74 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (72 downto 0); signal pHardCase_uid54_fpSinPiTest_q : std_logic_vector (52 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q : std_logic_vector (108 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (0 downto 0); signal leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal p_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0); signal p_uid55_fpSinPiTest_q : std_logic_vector (52 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (72 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (64 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (64 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (56 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (56 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c : std_logic_vector (19 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal r_uid186_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (6 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (0 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (78 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (78 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (74 downto 0); signal leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (79 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (79 downto 0); signal leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); begin --ld_xIn_v_to_xOut_v_notEnable(LOGICAL,909) ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q; ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor(LOGICAL,1028) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q <= not (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a or ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top(CONSTANT,1024) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q <= "0100100"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp(LOGICAL,1025) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q <= "1" when ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a = ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b else "0"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg(REG,1026) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena(REG,1029) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q = "1") THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd(LOGICAL,1030) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a and ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b; --LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest(BITSELECT,134)@0 LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest(CONSTANT,133) leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q <= "000000"; --leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest(BITJOIN,135)@0 leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest(BITSELECT,131)@0 LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest(CONSTANT,130) leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q <= "0000"; --leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest(BITJOIN,132)@0 leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest(BITSELECT,128)@0 LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(78 downto 0); LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in(78 downto 0); --leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest(CONSTANT,127) leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q <= "00"; --leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest(BITJOIN,129)@0 leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest(BITSELECT,123)@0 LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(56 downto 0); LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in(56 downto 0); --leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest(CONSTANT,122) leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000"; --leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest(BITJOIN,124)@0 leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest(BITSELECT,120)@0 LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(64 downto 0); LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in(64 downto 0); --leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest(CONSTANT,119) leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000"; --leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest(BITJOIN,121)@0 leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest(BITSELECT,117)@0 LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(72 downto 0); LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in(72 downto 0); --leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest(CONSTANT,116) leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q <= "00000000"; --leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest(BITJOIN,118)@0 leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest(CONSTANT,113) leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; --X16dto0_uid112_fixedPointX_uid37_fpSinPiTest(BITSELECT,111)@0 X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(16 downto 0); X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in(16 downto 0); --leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest(CONSTANT,110) leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000"; --leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest(BITJOIN,112)@0 leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X48dto0_uid109_fixedPointX_uid37_fpSinPiTest(BITSELECT,108)@0 X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(48 downto 0); X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in(48 downto 0); --leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest(CONSTANT,107) leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q <= "00000000000000000000000000000000"; --leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest(BITJOIN,109)@0 leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --cst01pWShift_uid34_fpSinPiTest(CONSTANT,33) cst01pWShift_uid34_fpSinPiTest_q <= "0000000000000000000000000000"; --xIn(PORTIN,3)@0 --fracX_uid7_fpSinPiTest(BITSELECT,6)@0 fracX_uid7_fpSinPiTest_in <= xIn_0(51 downto 0); fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(51 downto 0); --oFracX_uid31_uid31_fpSinPiTest(BITJOIN,30)@0 oFracX_uid31_uid31_fpSinPiTest_q <= VCC_q & fracX_uid7_fpSinPiTest_b; --extendedFracX_uid35_fpSinPiTest(BITJOIN,34)@0 extendedFracX_uid35_fpSinPiTest_q <= cst01pWShift_uid34_fpSinPiTest_q & oFracX_uid31_uid31_fpSinPiTest_q; --shiftBias_uid32_fpSinPiTest(CONSTANT,31) shiftBias_uid32_fpSinPiTest_q <= "01111100011"; --expX_uid6_fpSinPiTest(BITSELECT,5)@0 expX_uid6_fpSinPiTest_in <= xIn_0(62 downto 0); expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(62 downto 52); --shiftValue_uid33_fpSinPiTest(SUB,32)@0 shiftValue_uid33_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b); shiftValue_uid33_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid32_fpSinPiTest_q); shiftValue_uid33_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid33_fpSinPiTest_a) - UNSIGNED(shiftValue_uid33_fpSinPiTest_b)); shiftValue_uid33_fpSinPiTest_q <= shiftValue_uid33_fpSinPiTest_o(11 downto 0); --fxpShifterBits_uid36_fpSinPiTest(BITSELECT,35)@0 fxpShifterBits_uid36_fpSinPiTest_in <= shiftValue_uid33_fpSinPiTest_q(6 downto 0); fxpShifterBits_uid36_fpSinPiTest_b <= fxpShifterBits_uid36_fpSinPiTest_in(6 downto 0); --leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest(BITSELECT,114)@0 leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b; leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in(6 downto 5); --leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest(MUX,115)@0 leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s, extendedFracX_uid35_fpSinPiTest_q, leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= extendedFracX_uid35_fpSinPiTest_q; WHEN "01" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest(BITSELECT,125)@0 leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(4 downto 0); leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in(4 downto 3); --leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest(MUX,126)@0 leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest(BITSELECT,136)@0 leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(2 downto 0); leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in(2 downto 1); --leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest(MUX,137)@0 leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest(BITSELECT,139)@0 LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in(79 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest(BITJOIN,140)@0 leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b & GND_q; --reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3(REG,357)@0 reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2(REG,358)@0 reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest(BITSELECT,141)@0 leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(0 downto 0); leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in(0 downto 0); --ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b(DELAY,581)@0 ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest(MUX,142)@1 leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q; leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s, reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q, reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q) BEGIN CASE leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q; WHEN "1" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q; WHEN OTHERS => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --intXParity_uid38_fpSinPiTest(BITSELECT,37)@1 intXParity_uid38_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q; intXParity_uid38_fpSinPiTest_b <= intXParity_uid38_fpSinPiTest_in(80 downto 80); --ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c(DELAY,536)@1 ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => intXParity_uid38_fpSinPiTest_b, xout => ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q, clk => clk, aclr => areset ); --biasM1_uid27_fpSinPiTest(CONSTANT,26) biasM1_uid27_fpSinPiTest_q <= "01111111110"; --xFrac_uid28_fpSinPiTest(COMPARE,27)@0 xFrac_uid28_fpSinPiTest_cin <= GND_q; xFrac_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid27_fpSinPiTest_q) & '0'; xFrac_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid28_fpSinPiTest_cin(0); xFrac_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid28_fpSinPiTest_a) - UNSIGNED(xFrac_uid28_fpSinPiTest_b)); xFrac_uid28_fpSinPiTest_n(0) <= not xFrac_uid28_fpSinPiTest_o(13); --ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a(DELAY,532)@0 ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => xFrac_uid28_fpSinPiTest_n, xout => ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvXFrac_uid99_fpSinPiTest(LOGICAL,98)@3 InvXFrac_uid99_fpSinPiTest_a <= ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q; InvXFrac_uid99_fpSinPiTest_q <= not InvXFrac_uid99_fpSinPiTest_a; --biasMwShift_uid29_fpSinPiTest(CONSTANT,28) biasMwShift_uid29_fpSinPiTest_q <= "01111100100"; --sinXIsX_uid30_fpSinPiTest(COMPARE,29)@0 sinXIsX_uid30_fpSinPiTest_cin <= GND_q; sinXIsX_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0'; sinXIsX_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid29_fpSinPiTest_q) & sinXIsX_uid30_fpSinPiTest_cin(0); sinXIsX_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid30_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid30_fpSinPiTest_b)); sinXIsX_uid30_fpSinPiTest_c(0) <= sinXIsX_uid30_fpSinPiTest_o(13); --ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a(DELAY,502)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvSinXIsX_uid80_fpSinPiTest(LOGICAL,79)@2 InvSinXIsX_uid80_fpSinPiTest_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q; InvSinXIsX_uid80_fpSinPiTest_q <= not InvSinXIsX_uid80_fpSinPiTest_a; --y_uid39_fpSinPiTest(BITSELECT,38)@1 y_uid39_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); y_uid39_fpSinPiTest_b <= y_uid39_fpSinPiTest_in(79 downto 0); --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0(REG,360)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid40_fpSinPiTest(LOGICAL,39)@2 yIsZero_uid40_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q; yIsZero_uid40_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000000000000000000000000000000000000000000000000" & GND_q); yIsZero_uid40_fpSinPiTest_q <= "1" when yIsZero_uid40_fpSinPiTest_a = yIsZero_uid40_fpSinPiTest_b else "0"; --And2YIsZeroInvSinXIsX_uid81_fpSinPiTest(LOGICAL,80)@2 And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a <= yIsZero_uid40_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b <= InvSinXIsX_uid80_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a and And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b; --cstBiasPwF_uid13_fpSinPiTest(CONSTANT,12) cstBiasPwF_uid13_fpSinPiTest_q <= "10000110011"; --xIntExp_uid26_fpSinPiTest(COMPARE,25)@0 xIntExp_uid26_fpSinPiTest_cin <= GND_q; xIntExp_uid26_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid13_fpSinPiTest_q) & '0'; xIntExp_uid26_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid26_fpSinPiTest_cin(0); xIntExp_uid26_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid26_fpSinPiTest_a) - UNSIGNED(xIntExp_uid26_fpSinPiTest_b)); xIntExp_uid26_fpSinPiTest_c(0) <= xIntExp_uid26_fpSinPiTest_o(13); --ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a(DELAY,505)@0 ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => xIntExp_uid26_fpSinPiTest_c, xout => ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q, clk => clk, aclr => areset ); --Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest(LOGICAL,81)@2 Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a or Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b; --cstAllZWF_uid10_fpSinPiTest(CONSTANT,9) cstAllZWF_uid10_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracXIsZero_uid17_fpSinPiTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b; fracXIsZero_uid17_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q; fracXIsZero_uid17_fpSinPiTest_q <= "1" when fracXIsZero_uid17_fpSinPiTest_a = fracXIsZero_uid17_fpSinPiTest_b else "0"; --ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a(DELAY,442)@0 ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => fracXIsZero_uid17_fpSinPiTest_q, xout => ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvFracXIsZero_uid19_fpSinPiTest(LOGICAL,18)@1 InvFracXIsZero_uid19_fpSinPiTest_a <= ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q; InvFracXIsZero_uid19_fpSinPiTest_q <= not InvFracXIsZero_uid19_fpSinPiTest_a; --cstAllOWE_uid9_fpSinPiTest(CONSTANT,8) cstAllOWE_uid9_fpSinPiTest_q <= "11111111111"; --expXIsMax_uid16_fpSinPiTest(LOGICAL,15)@0 expXIsMax_uid16_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsMax_uid16_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q; expXIsMax_uid16_fpSinPiTest_q <= "1" when expXIsMax_uid16_fpSinPiTest_a = expXIsMax_uid16_fpSinPiTest_b else "0"; --ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a(DELAY,443)@0 ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsMax_uid16_fpSinPiTest_q, xout => ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest(LOGICAL,19)@1 And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a <= ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b <= InvFracXIsZero_uid19_fpSinPiTest_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a and And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b; --InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest(LOGICAL,20)@1 InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q <= not InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a; --And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0 And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a <= expXIsMax_uid16_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b <= fracXIsZero_uid17_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a and And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b; --InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0 InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q; InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q <= not InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a; --cstAllZWE_uid11_fpSinPiTest(CONSTANT,10) cstAllZWE_uid11_fpSinPiTest_q <= "00000000000"; --expXIsZero_uid15_fpSinPiTest(LOGICAL,14)@0 expXIsZero_uid15_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsZero_uid15_fpSinPiTest_b <= cstAllZWE_uid11_fpSinPiTest_q; expXIsZero_uid15_fpSinPiTest_q <= "1" when expXIsZero_uid15_fpSinPiTest_a = expXIsZero_uid15_fpSinPiTest_b else "0"; --InvExpXIsZero_uid23_fpSinPiTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSinPiTest_a <= expXIsZero_uid15_fpSinPiTest_q; InvExpXIsZero_uid23_fpSinPiTest_q <= not InvExpXIsZero_uid23_fpSinPiTest_a; --And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0 And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a <= InvExpXIsZero_uid23_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b <= InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a and And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b; --ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a(DELAY,450)@0 ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q, xout => ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest(LOGICAL,24)@1 And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a <= ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b <= InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a and And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b; END IF; END PROCESS; --xIsInt_uid83_fpSinPiTest(LOGICAL,82)@2 xIsInt_uid83_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_b <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_q <= xIsInt_uid83_fpSinPiTest_a and xIsInt_uid83_fpSinPiTest_b; --InvXIsInt_uid100_fpSinPiTest(LOGICAL,99)@2 InvXIsInt_uid100_fpSinPiTest_a <= xIsInt_uid83_fpSinPiTest_q; InvXIsInt_uid100_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= not InvXIsInt_uid100_fpSinPiTest_a; END IF; END PROCESS; --signComp_uid101_fpSinPiTest(LOGICAL,100)@3 signComp_uid101_fpSinPiTest_a <= InvXIsInt_uid100_fpSinPiTest_q; signComp_uid101_fpSinPiTest_b <= InvXFrac_uid99_fpSinPiTest_q; signComp_uid101_fpSinPiTest_c <= ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q; signComp_uid101_fpSinPiTest_q <= signComp_uid101_fpSinPiTest_a and signComp_uid101_fpSinPiTest_b and signComp_uid101_fpSinPiTest_c; --ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a(DELAY,537)@2 ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => yIsZero_uid40_fpSinPiTest_q, xout => ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvYIsZero_uid102_fpSinPiTest(LOGICAL,101)@3 InvYIsZero_uid102_fpSinPiTest_a <= ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q; InvYIsZero_uid102_fpSinPiTest_q <= not InvYIsZero_uid102_fpSinPiTest_a; --And2InvYIsZeroSignComp_uid103_fpSinPiTest(LOGICAL,102)@3 And2InvYIsZeroSignComp_uid103_fpSinPiTest_a <= InvYIsZero_uid102_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_b <= signComp_uid101_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_q <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_a and And2InvYIsZeroSignComp_uid103_fpSinPiTest_b; --signX_uid8_fpSinPiTest(BITSELECT,7)@0 signX_uid8_fpSinPiTest_in <= xIn_0; signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(63 downto 63); --ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a(DELAY,540)@0 ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q, clk => clk, aclr => areset ); --signR_uid104_fpSinPiTest(LOGICAL,103)@3 signR_uid104_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q; signR_uid104_fpSinPiTest_b <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_q; signR_uid104_fpSinPiTest_q <= signR_uid104_fpSinPiTest_a xor signR_uid104_fpSinPiTest_b; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt(COUNTER,1020) -- every=1, low=0, high=36, step=1, init=1 ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i = 35 THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i - 36; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i,6)); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg(REG,1021) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --VCC(CONSTANT,1) VCC_q <= "1"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux(MUX,1022) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux: PROCESS (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem(DUALMEM,1019) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia <= signR_uid104_fpSinPiTest_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 37, width_b => 1, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq, address_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa, data_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia ); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq(0 downto 0); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg(DELAY,1018) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q, xout => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --cstBias_uid12_fpSinPiTest(CONSTANT,11) cstBias_uid12_fpSinPiTest_q <= "01111111111"; --piwFP2_uid67_fpSinPiTest(CONSTANT,66) piwFP2_uid67_fpSinPiTest_q <= "110010010000111111011010101000100010000101101000110001"; --reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1(REG,363)@1 reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --cOne_uid44_fpSinPiTest(CONSTANT,43) cOne_uid44_fpSinPiTest_q <= "100000000000000000000000000000000000000000000000000000000000000000000000000000000"; --oneMinusY_uid45_fpSinPiTest(SUB,44)@2 oneMinusY_uid45_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid44_fpSinPiTest_q); oneMinusY_uid45_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q); oneMinusY_uid45_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid45_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid45_fpSinPiTest_b)); END IF; END PROCESS; oneMinusY_uid45_fpSinPiTest_q <= oneMinusY_uid45_fpSinPiTest_o(81 downto 0); --oMyBottom_uid47_fpSinPiTest(BITSELECT,46)@3 oMyBottom_uid47_fpSinPiTest_in <= oneMinusY_uid45_fpSinPiTest_q(78 downto 0); oMyBottom_uid47_fpSinPiTest_b <= oMyBottom_uid47_fpSinPiTest_in(78 downto 0); --ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d(DELAY,471)@3 ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => oMyBottom_uid47_fpSinPiTest_b, xout => ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q, clk => clk, aclr => areset ); --yBottom_uid48_fpSinPiTest(BITSELECT,47)@1 yBottom_uid48_fpSinPiTest_in <= y_uid39_fpSinPiTest_b(78 downto 0); yBottom_uid48_fpSinPiTest_b <= yBottom_uid48_fpSinPiTest_in(78 downto 0); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c(DELAY,470)@1 ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 79, depth => 2 ) PORT MAP ( xin => yBottom_uid48_fpSinPiTest_b, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg(DELAY,926) ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a(DELAY,833)@1 ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a : dspba_delay GENERIC MAP ( width => 80, depth => 1 ) PORT MAP ( xin => y_uid39_fpSinPiTest_b, xout => ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q, clk => clk, aclr => areset ); --reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1(REG,364)@2 reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q; END IF; END PROCESS; --cmpYToOneMinusY_uid46_fpSinPiTest(COMPARE,45)@3 cmpYToOneMinusY_uid46_fpSinPiTest_cin <= GND_q; cmpYToOneMinusY_uid46_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & oneMinusY_uid45_fpSinPiTest_q) & '0'; cmpYToOneMinusY_uid46_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q) & cmpYToOneMinusY_uid46_fpSinPiTest_cin(0); cmpYToOneMinusY_uid46_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_b)); END IF; END PROCESS; cmpYToOneMinusY_uid46_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid46_fpSinPiTest_o(84); --z_uid49_fpSinPiTest(MUX,48)@4 z_uid49_fpSinPiTest_s <= cmpYToOneMinusY_uid46_fpSinPiTest_c; z_uid49_fpSinPiTest: PROCESS (z_uid49_fpSinPiTest_s, ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q) BEGIN CASE z_uid49_fpSinPiTest_s IS WHEN "0" => z_uid49_fpSinPiTest_q <= ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q; WHEN "1" => z_uid49_fpSinPiTest_q <= ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q; WHEN OTHERS => z_uid49_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --zAddr_uid63_fpSinPiTest(BITSELECT,62)@4 zAddr_uid63_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; zAddr_uid63_fpSinPiTest_b <= zAddr_uid63_fpSinPiTest_in(78 downto 72); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0(REG,382)@4 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= zAddr_uid63_fpSinPiTest_b; END IF; END PROCESS; --memoryC5_uid231_sinPiZTableGenerator(LOOKUP,230)@5 memoryC5_uid231_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; WHEN "0000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111110101101000"; WHEN "0000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111101101011101"; WHEN "0000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100110001110"; WHEN "0000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100000000010"; WHEN "0000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111011000000000"; WHEN "0000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111010001101101"; WHEN "0000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111001010010111"; WHEN "0001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111000010110010"; WHEN "0001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110111100010100"; WHEN "0001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110110100011111"; WHEN "0001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110101100101101"; WHEN "0001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110100101101011"; WHEN "0001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110011111011101"; WHEN "0001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010111001010"; WHEN "0001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010001011011"; WHEN "0010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110001010101011"; WHEN "0010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110000011011001"; WHEN "0010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101111011000001"; WHEN "0010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101110101001010"; WHEN "0010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101101110100110"; WHEN "0010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101100111100011"; WHEN "0010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011111111111"; WHEN "0010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011001001010"; WHEN "0011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101010010100110"; WHEN "0011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101001010011011"; WHEN "0011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101000100011100"; WHEN "0011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100111101010110"; WHEN "0011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100110110111000"; WHEN "0011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100101111110010"; WHEN "0011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100111110010"; WHEN "0011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100001010101"; WHEN "0100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100011011011111"; WHEN "0100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100010011110111"; WHEN "0100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100001110001010"; WHEN "0100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100000111000100"; WHEN "0100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111111110101"; WHEN "0100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111001010110"; WHEN "0100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011110011000111"; WHEN "0100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011101101000000"; WHEN "0101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011100110000011"; WHEN "0101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011111111001"; WHEN "0101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011000100110"; WHEN "0101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011010010101100"; WHEN "0101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011001100010010"; WHEN "0101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011000101010111"; WHEN "0101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111111101010"; WHEN "0101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111001010000"; WHEN "0110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010110011010011"; WHEN "0110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010101100101011"; WHEN "0110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010100110111110"; WHEN "0110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011111111000"; WHEN "0110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011010110010"; WHEN "0110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010010101001110"; WHEN "0110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001110010011"; WHEN "0110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001000111011"; WHEN "0111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010000001111011"; WHEN "0111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001111011111110"; WHEN "0111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110111001010"; WHEN "0111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110001110111"; WHEN "0111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001101011000100"; WHEN "0111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100101010010"; WHEN "0111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100000011111"; WHEN "0111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001011010001010"; WHEN "1000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001010100111110"; WHEN "1000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001110110010"; WHEN "1000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001010111000"; WHEN "1000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001000100111111"; WHEN "1000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111111001100"; WHEN "1000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111010001001"; WHEN "1000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110101010110"; WHEN "1000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110000011101"; WHEN "1001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000101001110100"; WHEN "1001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000100101111001"; WHEN "1001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011111111010"; WHEN "1001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011011110110"; WHEN "1001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010110001100"; WHEN "1001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010001001000"; WHEN "1001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001101111001"; WHEN "1001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001000000111"; WHEN "1010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000000010111001"; WHEN "1010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111110110110"; WHEN "1010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111001111111"; WHEN "1010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110110010100"; WHEN "1010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110001011000"; WHEN "1010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101100010111"; WHEN "1010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101000010010"; WHEN "1010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100100010000"; WHEN "1011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100000111100"; WHEN "1011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111011011111111"; WHEN "1011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010111100000"; WHEN "1011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010011110100"; WHEN "1011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010000011100"; WHEN "1011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111001011011110"; WHEN "1011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000111111101"; WHEN "1011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000100101011"; WHEN "1100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000001100100"; WHEN "1100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111101101110"; WHEN "1100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111010011000"; WHEN "1100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110110110000"; WHEN "1100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110010011010"; WHEN "1100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110000011110"; WHEN "1100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101100101100"; WHEN "1100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101000101110"; WHEN "1101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100110100000"; WHEN "1101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100100010001"; WHEN "1101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100001000000"; WHEN "1101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011101101110"; WHEN "1101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011011011111"; WHEN "1101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010111000100"; WHEN "1101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010101110011"; WHEN "1101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010001111100"; WHEN "1110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010000001111"; WHEN "1110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001110011001"; WHEN "1110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001010100010"; WHEN "1110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000111111000"; WHEN "1110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101110110"; WHEN "1110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101000100"; WHEN "1110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000010100010"; WHEN "1110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111111110011"; WHEN "1111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111110010000"; WHEN "1111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111100110111"; WHEN "1111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111010111000"; WHEN "1111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111000101000"; WHEN "1111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110110110100"; WHEN "1111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110101011010"; WHEN "1111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110100000011"; WHEN "1111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110010001011"; WHEN OTHERS => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; END CASE; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a(DELAY,485)@4 ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => z_uid49_fpSinPiTest_q, xout => ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q, clk => clk, aclr => areset ); --zPPolyEval_uid64_fpSinPiTest(BITSELECT,63)@5 zPPolyEval_uid64_fpSinPiTest_in <= ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q(71 downto 0); zPPolyEval_uid64_fpSinPiTest_b <= zPPolyEval_uid64_fpSinPiTest_in(71 downto 27); --yT1_uid232_sinPiZPolyEval(BITSELECT,231)@5 yT1_uid232_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT1_uid232_sinPiZPolyEval_b <= yT1_uid232_sinPiZPolyEval_in(44 downto 28); --reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0(REG,383)@5 reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= yT1_uid232_sinPiZPolyEval_b; END IF; END PROCESS; --prodXY_uid263_pT1_uid233_sinPiZPolyEval(MULT,262)@6 prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_a),18)) * SIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_b); prodXY_uid263_pT1_uid233_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= memoryC5_uid231_sinPiZTableGenerator_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr,34)); END IF; END PROCESS; prodXY_uid263_pT1_uid233_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval(BITSELECT,263)@9 prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_q; prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in(33 downto 16); --highBBits_uid235_sinPiZPolyEval(BITSELECT,234)@9 highBBits_uid235_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b; highBBits_uid235_sinPiZPolyEval_b <= highBBits_uid235_sinPiZPolyEval_in(17 downto 1); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a(DELAY,853)@4 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a : dspba_delay GENERIC MAP ( width => 7, depth => 3 ) PORT MAP ( xin => zAddr_uid63_fpSinPiTest_b, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0(REG,384)@7 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q; END IF; END PROCESS; --memoryC4_uid230_sinPiZTableGenerator(LOOKUP,229)@8 memoryC4_uid230_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; WHEN "0000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110011111111100"; WHEN "0000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100101101100110011"; WHEN "0000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100100010011000101"; WHEN "0000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100010010010010110"; WHEN "0000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011111110011000100"; WHEN "0000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011100101011001100"; WHEN "0000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011001000001111000"; WHEN "0001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010100110101100100"; WHEN "0001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010000000010110001"; WHEN "0001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001001010101111100100"; WHEN "0001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001000100111000100010"; WHEN "0001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000111110011011110101"; WHEN "0001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000110111011001010101"; WHEN "0001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000101111111000110001"; WHEN "0001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000100111101101111110"; WHEN "0010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000011111000010010110"; WHEN "0010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000010101110100101111"; WHEN "0010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000001100000110110101"; WHEN "0010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000000001101111000000"; WHEN "0010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111110110110101110011"; WHEN "0010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111101011011010111001"; WHEN "0010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111011111011110000110"; WHEN "0010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111010010111100110100"; WHEN "0011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111000101110111111001"; WHEN "0011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110111000010100011101"; WHEN "0011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110101010001000110011"; WHEN "0011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110011011011101100111"; WHEN "0011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110001100001110001111"; WHEN "0011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101111100011110001010"; WHEN "0011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101101100001110100101"; WHEN "0011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101011011011000110110"; WHEN "0100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101001001111111101110"; WHEN "0100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100111000001001001111"; WHEN "0100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100100101101100011001"; WHEN "0100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100010010110001110000"; WHEN "0100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011111111010101110110"; WHEN "0100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011101011010111000111"; WHEN "0100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011010110110110011110"; WHEN "0100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011000001110100011110"; WHEN "0101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010101100010100010011"; WHEN "0101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010010110010001000111"; WHEN "0101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001111111110001000100"; WHEN "0101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001101000101100110110"; WHEN "0101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001010001001001111011"; WHEN "0101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000111001001000001110"; WHEN "0101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000100000100011110110"; WHEN "0101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000000111100001111001"; WHEN "0110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111101101111111011111"; WHEN "0110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111010011111111100110"; WHEN "0110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110111001011110100100"; WHEN "0110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110011110100010000111"; WHEN "0110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110000011000010001001"; WHEN "0110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101100111000101000011"; WHEN "0110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101001010101101011111"; WHEN "0110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100101101110011101110"; WHEN "0111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100010000100000111110"; WHEN "0111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011110010101101110100"; WHEN "0111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011010100011010011110"; WHEN "0111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010110101101011010111"; WHEN "0111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010010110100011011101"; WHEN "0111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001110110111100001001"; WHEN "0111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001010110110110010000"; WHEN "0111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000110110011000001101"; WHEN "1000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000010101011011011001"; WHEN "1000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111110100000101110010"; WHEN "1000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111010010001110101001"; WHEN "1000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110110000000001101011"; WHEN "1000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110001101011001110011"; WHEN "1000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101101010010101011101"; WHEN "1000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101000110110101111111"; WHEN "1000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111100100010111100111100"; WHEN "1001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011111110101110100100"; WHEN "1001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011011001111111110100"; WHEN "1001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010110100111101000111"; WHEN "1001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010001111011100101001"; WHEN "1001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001101001100111100001"; WHEN "1001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001000011011000101011"; WHEN "1001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111000011100101100110010"; WHEN "1001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111110101110000000011"; WHEN "1010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111001110011001111101"; WHEN "1010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110110100110101001110001"; WHEN "1010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101111110100101001011"; WHEN "1010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101010110000110010110"; WHEN "1010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100101101010100111010"; WHEN "1010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100000100001101101101"; WHEN "1010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110011011010101110011000"; WHEN "1010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010110000111001010011"; WHEN "1011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010000110101101010010"; WHEN "1011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110001011100010001000010"; WHEN "1011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000110001011111001110"; WHEN "1011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000000110010110110100"; WHEN "1011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101111011010111010001000"; WHEN "1011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110101111001110001011"; WHEN "1011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110000011001011001100"; WHEN "1011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101101010110110100111111"; WHEN "1100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101100101010001011011001"; WHEN "1100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011111101010010000000"; WHEN "1100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011010000000101001000"; WHEN "1100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101010100010100111110111"; WHEN "1100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001110100111011010110"; WHEN "1100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001000110110111101100"; WHEN "1100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101000011000101000001000"; WHEN "1100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100111101010001001010101"; WHEN "1101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110111011010110000011"; WHEN "1101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110001100010011011010"; WHEN "1101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100101011101000100011001"; WHEN "1101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100100101101100110100111"; WHEN "1101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011111101110111111010"; WHEN "1101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011001110000000101100"; WHEN "1101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100010011101110011110101"; WHEN "1101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100001101101100000010000"; WHEN "1110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000111100111010001011"; WHEN "1110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000001100000111111010"; WHEN "1110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011111011011001110101000"; WHEN "1110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011110101010000110010111"; WHEN "1110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101111000110001000001"; WHEN "1110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101000111001101001001"; WHEN "1110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011100010101100011001010"; WHEN "1110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011011100011101111010110"; WHEN "1111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011010110001101110011110"; WHEN "1111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001111111100011010111"; WHEN "1111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001001101010000100101"; WHEN "1111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011000011010110101101110"; WHEN "1111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010111101000010001000000"; WHEN "1111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110110101100011000101"; WHEN "1111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110000010101101010111"; WHEN "1111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010101001111110001011010"; WHEN OTHERS => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; END CASE; END IF; END PROCESS; --sumAHighB_uid236_sinPiZPolyEval(ADD,235)@9 sumAHighB_uid236_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((26 downto 26 => memoryC4_uid230_sinPiZTableGenerator_q(25)) & memoryC4_uid230_sinPiZTableGenerator_q); sumAHighB_uid236_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((26 downto 17 => highBBits_uid235_sinPiZPolyEval_b(16)) & highBBits_uid235_sinPiZPolyEval_b); sumAHighB_uid236_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid236_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid236_sinPiZPolyEval_b)); sumAHighB_uid236_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_o(26 downto 0); --lowRangeB_uid234_sinPiZPolyEval(BITSELECT,233)@9 lowRangeB_uid234_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid234_sinPiZPolyEval_b <= lowRangeB_uid234_sinPiZPolyEval_in(0 downto 0); --s1_uid234_uid237_sinPiZPolyEval(BITJOIN,236)@9 s1_uid234_uid237_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_q & lowRangeB_uid234_sinPiZPolyEval_b; --reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1(REG,385)@9 reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= s1_uid234_uid237_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor(LOGICAL,1179) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q <= not (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a or ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg(REG,1177) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= VCC_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena(REG,1180) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q = "1") THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd(LOGICAL,1181) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a and ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b; --yT2_uid238_sinPiZPolyEval(BITSELECT,237)@5 yT2_uid238_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT2_uid238_sinPiZPolyEval_b <= yT2_uid238_sinPiZPolyEval_in(44 downto 19); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt(COUNTER,1173) -- every=1, low=0, high=1, step=1, init=1 ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i + 1; END IF; END PROCESS; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i,1)); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg(REG,1174) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux(MUX,1175) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q) BEGIN CASE ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s IS WHEN "0" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; WHEN "1" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem(DUALMEM,1172) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia <= yT2_uid238_sinPiZPolyEval_b; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 26, widthad_a => 1, numwords_a => 2, width_b => 26, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq, address_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa, data_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia ); ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq(25 downto 0); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg(DELAY,1171) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q, xout => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0(REG,386)@9 reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q; END IF; END PROCESS; --prodXY_uid266_pT2_uid239_sinPiZPolyEval(MULT,265)@10 prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_a),27)) * SIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_b); prodXY_uid266_pT2_uid239_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr,54)); END IF; END PROCESS; prodXY_uid266_pT2_uid239_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval(BITSELECT,266)@13 prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_q; prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in(53 downto 25); --highBBits_uid241_sinPiZPolyEval(BITSELECT,240)@13 highBBits_uid241_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b; highBBits_uid241_sinPiZPolyEval_b <= highBBits_uid241_sinPiZPolyEval_in(28 downto 1); --reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1(REG,388)@13 reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= highBBits_uid241_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor(LOGICAL,1192) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1188) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q <= "0101"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp(LOGICAL,1189) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg(REG,1190) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena(REG,1193) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1194) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1184) -- every=1, low=0, high=5, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i = 4 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i - 5; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i,3)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg(REG,1185) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1186) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1183) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 3, numwords_a => 6, width_b => 7, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg(DELAY,1182) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0(REG,387)@12 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC3_uid229_sinPiZTableGenerator(LOOKUP,228)@13 memoryC3_uid229_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; WHEN "0000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000001010001100110101000111010101"; WHEN "0000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000010100011001100101101010110011"; WHEN "0000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000011110100110001101010100011011"; WHEN "0000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000101000110010100111100101110011"; WHEN "0000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000110010111110101111101101101000"; WHEN "0000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000111101001010100001100001001101"; WHEN "0000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001000111010101111000010100001000"; WHEN "0001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001010001100000101111101001011010"; WHEN "0001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001011011101011000011001000111110"; WHEN "0001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001100101110100101110001001110101"; WHEN "0001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001101111111101101100010100000001"; WHEN "0001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001111010000101111001001101010110"; WHEN "0001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010000100001101010000011000110101"; WHEN "0001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010001110010011101101001010101000"; WHEN "0001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010011000011001001011011101011111"; WHEN "0010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010100010011101100110100011101011"; WHEN "0010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010101100100000111010000011110001"; WHEN "0010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010110110100011000001011111010110"; WHEN "0010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011000000100011111000101110110101"; WHEN "0010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011001010100011011011001000001011"; WHEN "0010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011010100100001100100010010100101"; WHEN "0010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011011110011110001111110110101010"; WHEN "0010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011101000011001011001100000011011"; WHEN "0011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011110010010010111100111000010100"; WHEN "0011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011111100001010110101011110000110"; WHEN "0011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100000110000000111111001110100010"; WHEN "0011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100001111110101010101100100101101"; WHEN "0011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100011001100111110100010110001111"; WHEN "0011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100100011011000010111001001011111"; WHEN "0011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100101101000110111001101001101001"; WHEN "0011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100110110110011010111110011001100"; WHEN "0100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101000000011101101101010000100110"; WHEN "0100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101001010000101110101101000010110"; WHEN "0100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101010011101011101100111100100100"; WHEN "0100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101011101001111001110110000110010"; WHEN "0100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101100110110000010111000000110011"; WHEN "0100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101110000001111000001100011110100"; WHEN "0100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101111001101011001010010000000001"; WHEN "0100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110000011000100101100111100001110"; WHEN "0101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110001100011011100101011010100101"; WHEN "0101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110010101101111101111110000010101"; WHEN "0101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110011111000001000111101011101100"; WHEN "0101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110101000001111101001011001100010"; WHEN "0101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110110001011011010000101101010010"; WHEN "0101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110111010100011111001100111101100"; WHEN "0101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111000011101001100000010000100010"; WHEN "0101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111001100101100000000100001010000"; WHEN "0110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111010101101011010110100011101100"; WHEN "0110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111011110100111011110011000011110"; WHEN "0110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111100111100000010100001101010000"; WHEN "0110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111110000010101110100000001010000"; WHEN "0110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111111001000111111010001101010001"; WHEN "0110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000000001110110100010110001111010"; WHEN "0110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000001010100001101001110111110101"; WHEN "0110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000010011001001001011111110000001"; WHEN "0111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000011011101101000101000010101111"; WHEN "0111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000100100001101010001101000100100"; WHEN "0111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000101100101001101110000011010101"; WHEN "0111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000110101000010010110100001011010"; WHEN "0111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000111101010111000111010101011110"; WHEN "0111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001000101100111111101000110111000"; WHEN "0111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001001101110100110100001111001100"; WHEN "0111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001010101111101101001000001001010"; WHEN "1000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001011110000010011000001001000011"; WHEN "1000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001100110000010111101111101010011"; WHEN "1000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001101101111111010111010011001111"; WHEN "1000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001110101110111100000011010000110"; WHEN "1000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001111101101011010110000011010010"; WHEN "1000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010000101011010110100111100000101"; WHEN "1000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010001101000101111001101110100011"; WHEN "1000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010010100101100100001000101010010"; WHEN "1001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010011100001110100111101001010100"; WHEN "1001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010100011101100001010100001011100"; WHEN "1001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010101011000101000110001011100100"; WHEN "1001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010110010011001010111110000100100"; WHEN "1001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010111001101000111011111001000111"; WHEN "1001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000000110011101111101001011111"; WHEN "1001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000111111001110000000110011110"; WHEN "1001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011001110111010111001110111111110"; WHEN "1010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011010101110111001010010001110110"; WHEN "1010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011011100101110011110011000111101"; WHEN "1010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011100011100000110011001001001001"; WHEN "1010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011101010001110000101111000101100"; WHEN "1010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110000110110010011100011000111"; WHEN "1010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110111011001011001011101010011"; WHEN "1010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011111101110111010100111100011100"; WHEN "1010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100000100010000000011001111101101"; WHEN "1011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100001010100011100001101110011100"; WHEN "1011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010000110001101101100011100011"; WHEN "1011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010110111010100100010100000100"; WHEN "1011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100011100111110000011100000001010"; WHEN "1011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100100010111100001000100001101001"; WHEN "1011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101000110100110000110001111011"; WHEN "1011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101110100111111010000100111001"; WHEN "1011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100110100010101100001111010001101"; WHEN "1100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111001111101100101111101110000"; WHEN "1100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111111100000000011110011100101"; WHEN "1100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101000100111100111001010011110100"; WHEN "1100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001010010100000100001001001101"; WHEN "1100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001111100101100010000111001000"; WHEN "1100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101010100110001010001010100001101"; WHEN "1100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011001110111001111010101110101"; WHEN "1100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011110110111011010001101111010"; WHEN "1101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101100011110001110000000111001111"; WHEN "1101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101000100110001110111010010001"; WHEN "1101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101101010100110100100110101101"; WHEN "1101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110001111101011111011001010101"; WHEN "1101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110110100000001101100000100000"; WHEN "1101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111010111100111100111010111000"; WHEN "1101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111111010011101100010000110110"; WHEN "1101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000011100100011001011010100000"; WHEN "1110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000111101111000011000011110011"; WHEN "1110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001011110011100111011010000000"; WHEN "1110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001111110010000100101111100001"; WHEN "1110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010011101010011001110010000111"; WHEN "1110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010111011100100100111111111001"; WHEN "1110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011011001000100101000000101011"; WHEN "1110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011110101110011000001011101010"; WHEN "1110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100010001101111101010010100010"; WHEN "1111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100101100111010011001000110011"; WHEN "1111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101000111010011000011010000011"; WHEN "1111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101100000111001011110100010010"; WHEN "1111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101111001101101100001110011100"; WHEN "1111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110010001101111000100101110110"; WHEN "1111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110101000111101111110101001010"; WHEN "1111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110111111011010000111000110000"; WHEN "1111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110111010101000011010110000100000"; WHEN OTHERS => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; END CASE; END IF; END PROCESS; --sumAHighB_uid242_sinPiZPolyEval(ADD,241)@14 sumAHighB_uid242_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid229_sinPiZTableGenerator_q(34)) & memoryC3_uid229_sinPiZTableGenerator_q); sumAHighB_uid242_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((35 downto 28 => reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q(27)) & reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q); sumAHighB_uid242_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid242_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid242_sinPiZPolyEval_b)); sumAHighB_uid242_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_o(35 downto 0); --lowRangeB_uid240_sinPiZPolyEval(BITSELECT,239)@13 lowRangeB_uid240_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid240_sinPiZPolyEval_b <= lowRangeB_uid240_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a(DELAY,686)@13 ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid240_sinPiZPolyEval_b, xout => ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --s2_uid240_uid243_sinPiZPolyEval(BITJOIN,242)@14 s2_uid240_uid243_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_q & ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q; --yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval(BITSELECT,274)@14 yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in(36 downto 19); --reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9(REG,389)@14 reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor(LOGICAL,950) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top(CONSTANT,946) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q <= "0110"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp(LOGICAL,947) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b else "0"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg(REG,948) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena(REG,951) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q = "1") THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd(LOGICAL,952) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt(COUNTER,942) -- every=1, low=0, high=6, step=1, init=1 ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i = 5 THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i - 6; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i,3)); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg(REG,943) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux(MUX,944) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q) BEGIN CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s IS WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem(DUALMEM,1069) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 3, numwords_a => 7, width_b => 45, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg(DELAY,1068) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT3_uid244_sinPiZPolyEval(BITSELECT,243)@14 yT3_uid244_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q; yT3_uid244_sinPiZPolyEval_b <= yT3_uid244_sinPiZPolyEval_in(44 downto 10); --xBottomBits_uid274_pT3_uid245_sinPiZPolyEval(BITSELECT,273)@14 xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b(7 downto 0); xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in(7 downto 0); --pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval(BITJOIN,276)@14 pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7(REG,391)@14 reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid273_pT3_uid245_sinPiZPolyEval(BITSELECT,272)@14 yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q(9 downto 0); yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b <= yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in(9 downto 0); --spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval(BITJOIN,275)@14 spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q <= GND_q & yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b; --pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval(BITJOIN,277)@14 pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q <= spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6(REG,390)@14 reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval(BITSELECT,271)@14 xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in(34 downto 17); --reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4(REG,392)@14 reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma(CHAINMULTADD,345)@15 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1),38); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0); END IF; END PROCESS; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0),37)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval(BITSELECT,279)@18 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in(36 downto 7); --highBBits_uid282_pT3_uid245_sinPiZPolyEval(BITSELECT,281)@18 highBBits_uid282_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b; highBBits_uid282_pT3_uid245_sinPiZPolyEval_b <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_in(29 downto 1); --reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1(REG,395)@18 reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval(BITSELECT,269)@14 yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in(36 downto 10); --reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1(REG,393)@14 reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval(BITSELECT,268)@14 xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in(34 downto 8); --reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0(REG,394)@14 reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid271_pT3_uid245_sinPiZPolyEval(MULT,270)@15 topProd_uid271_pT3_uid245_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_b); topProd_uid271_pT3_uid245_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid271_pT3_uid245_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid271_pT3_uid245_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0(REG,396)@18 reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid283_pT3_uid245_sinPiZPolyEval(ADD,282)@19 sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q(53)) & reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b)); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid281_pT3_uid245_sinPiZPolyEval(BITSELECT,280)@18 lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b <= lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a(DELAY,724)@18 ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b, xout => ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid281_uid284_pT3_uid245_sinPiZPolyEval(BITJOIN,283)@19 add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q & ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q; --R_uid285_pT3_uid245_sinPiZPolyEval(BITSELECT,284)@19 R_uid285_pT3_uid245_sinPiZPolyEval_in <= add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q(54 downto 0); R_uid285_pT3_uid245_sinPiZPolyEval_b <= R_uid285_pT3_uid245_sinPiZPolyEval_in(54 downto 18); --reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1(REG,397)@19 reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= R_uid285_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor(LOGICAL,1168) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1164) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q <= "01011"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp(LOGICAL,1165) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg(REG,1166) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena(REG,1169) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1170) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1160) -- every=1, low=0, high=11, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i = 10 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i - 11; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i,4)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg(REG,1161) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1162) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1159) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 4, numwords_a => 12, width_b => 7, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg(DELAY,1158) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0(REG,381)@18 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC2_uid228_sinPiZTableGenerator(LOOKUP,227)@19 memoryC2_uid228_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; WHEN "0000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010010000000010011011110101101000"; WHEN "0000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010100110111111010000111001000101"; WHEN "0000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101011001101001111001000101101101011"; WHEN "0000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101100000010110001110010011100100110"; WHEN "0000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101101000111100110110110100100001100"; WHEN "0000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101110011011101101110110101011000001"; WHEN "0000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101111111111000110001101110000001000"; WHEN "0001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110001110001101111010000000001001001"; WHEN "0001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110011110011101000001010111100010011"; WHEN "0001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110110000100110000000101010101010010"; WHEN "0001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111000100101000101111111001111001110"; WHEN "0001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111011010100101000110010000000110000"; WHEN "0001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111110010011010111010000010100101101"; WHEN "0001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000001100001010000000110001101010110"; WHEN "0001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000100111110010001111000111001110001"; WHEN "0010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001000101010011011000111000110111111"; WHEN "0010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001100100101101010001000110100001110"; WHEN "0010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010000101111111101001111011000110110"; WHEN "0010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010101001001010010100101011111010000"; WHEN "0010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011001110001101000001111010001111100"; WHEN "0010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011110101000111100001010010001101000"; WHEN "0010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111100011101111001100001101011001010011"; WHEN "0010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101001000100010110001000111111011001"; WHEN "0011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101110101000010111100110110111011101"; WHEN "0011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111110100011011001110001010010101001001"; WHEN "0011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111111010011100110111010000000101010000"; WHEN "0011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000000101101010000001110011011110111"; WHEN "0011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000111001100010110010101001001001010"; WHEN "0011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000001101111010000110101101100011101100"; WHEN "0011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000010100110110011110011010100101011100"; WHEN "0011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000011100000001011010011000101010010101"; WHEN "0100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000100011011010110111011101111001100010"; WHEN "0100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000101011000010110010011010000011100100"; WHEN "0100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000110010111001000111110110011110000010"; WHEN "0100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000111010111101110100010110010000011111"; WHEN "0100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001000011010000110100010110001010111111"; WHEN "0100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001001011110010000100001100101110011011"; WHEN "0100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001010100100001100000001010001100011000"; WHEN "0100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001011101011111000100011000101001100001"; WHEN "0101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001100110101010101100111100000000011011"; WHEN "0101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001110000000100010101110001111101110010"; WHEN "0101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001111001101011111010110010001100011010"; WHEN "0101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010000011100001010111101110001010011110"; WHEN "0101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010001101100100101000010001011000100111"; WHEN "0101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010010111110101101000000001010011000010"; WHEN "0101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010100010010100010010011101010101101010"; WHEN "0101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010101101000000100010111111000010000011"; WHEN "0110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010110111111010010100111001111011100110"; WHEN "0110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011000011000001100011011011101110111001"; WHEN "0110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011001110010110001001101100001111110101"; WHEN "0110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011011001111000000010101101100000111100"; WHEN "0110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011100101100111001001011011101110011000"; WHEN "0110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011110001100011011000101101011001110101"; WHEN "0110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011111101101100101011010011010110110001"; WHEN "0110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100001010000010111011111000101001101100"; WHEN "0111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100010110100110000101000010110110110100"; WHEN "0111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100100011010110000001010001110101000110"; WHEN "0111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100110000010010101010111111111100101100"; WHEN "0111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100111101011011111100100010000110111111"; WHEN "0111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101001010110001110000000111101111100101"; WHEN "0111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101011000010011111111111010110011011100"; WHEN "0111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101100110000010100101111111111011010100"; WHEN "0111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101110011111101011100010110011100010110"; WHEN "1000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110000010000100011100111000010100111110"; WHEN "1000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110010000010111100001011010011001010101"; WHEN "1000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110011110110110100011101100001011001000"; WHEN "1000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110101101100001011101011000001011011001"; WHEN "1000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110111100011000001000000011101110001111"; WHEN "1000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111001011011010011101001111000101110001"; WHEN "1000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111011010101000010110010101100101000110"; WHEN "1000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111101010000001101100101101100010111111"; WHEN "1001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111111001100110011001101000011100111011"; WHEN "1001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000001001010110010110010010110100011100"; WHEN "1001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000011001010001011011110100100000011000"; WHEN "1001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000101001010111100011010000011111011101"; WHEN "1001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000111001101000100101100101001010011111"; WHEN "1001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001001010000100011011101100001100000010"; WHEN "1001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001011010101010111110011010101000110000"; WHEN "1001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001101011011100000110100001001001100100"; WHEN "1010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001111100010111101100101011101111001100"; WHEN "1010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010001101011101101001100010000010111010"; WHEN "1010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010011110101101110101100111011000000101"; WHEN "1010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010110000001000001001011010101000000100"; WHEN "1010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011000001101100011101010110100010000110"; WHEN "1010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011010011011010101001110001100010110011"; WHEN "1010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011100101010010100110111101111101101001"; WHEN "1010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011110111010100001101001010000001101110"; WHEN "1011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100001001011111010100011111111010110111"; WHEN "1011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100011011110011110101000101111001011001"; WHEN "1011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100101110010001100110111110001101101110"; WHEN "1011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101000000111000100010000111010010100101"; WHEN "1011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101010011101000011110011011110001111001"; WHEN "1011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101100110100001010011110010100110010101"; WHEN "1011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101111001100010111001111110111010001011"; WHEN "1011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110001100101101001000110000010101000001"; WHEN "1100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110011111111111110111110010111000010010"; WHEN "1100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110110011011010111110101111001000100111"; WHEN "1100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111000110111110010101001010001010011010"; WHEN "1100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111011010101001110010100101101110010111"; WHEN "1100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111101110011101001110100000001111101010"; WHEN "1100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000000010011000100000010100110110100000"; WHEN "1100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000010110011011011111011011100110110011"; WHEN "1100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000101010100110000011001001011000000001"; WHEN "1101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000111110111000000010101111111100010101"; WHEN "1101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001010011010001010101011110001011010100"; WHEN "1101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001100111110001110010100000000000010111"; WHEN "1101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001111100011001010000111110011101110000"; WHEN "1101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010010001000111100111111111110011011101"; WHEN "1101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010100101111100101110100111100110010101"; WHEN "1101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010111010111000011011110110101001010101"; WHEN "1101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011001111111010100110101011010011011011"; WHEN "1110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011100101000011000110000001010000000100"; WHEN "1110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011111010010001110000110001110011111011"; WHEN "1110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100001111100110011101110011111001111111"; WHEN "1110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100100101000001000011111100000011011011"; WHEN "1110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100111010100001011001111100100100101001"; WHEN "1110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101010000000111010110100101100100010111"; WHEN "1110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101100101110010110000100101000101101101"; WHEN "1110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101111011100011011110100111000011010111"; WHEN "1111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110010001011001010111010101011001010001"; WHEN "1111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110100111010100010001011000001010110100"; WHEN "1111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110111101010100000011010101100101100011"; WHEN "1111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111010011011000100011110010000011111011"; WHEN "1111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111101001100001101001010000010010001011"; WHEN "1111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111111111101111001010010001010101000011"; WHEN "1111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000010110000000111101010100101101001001"; WHEN "1111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000101100010110111000111000011010110101"; WHEN OTHERS => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid246_sinPiZPolyEval(CONSTANT,245) rndBit_uid246_sinPiZPolyEval_q <= "01"; --cIncludingRoundingBit_uid247_sinPiZPolyEval(BITJOIN,246)@19 cIncludingRoundingBit_uid247_sinPiZPolyEval_q <= memoryC2_uid228_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0(REG,398)@19 reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid247_sinPiZPolyEval_q; END IF; END PROCESS; --ts3_uid248_sinPiZPolyEval(ADD,247)@20 ts3_uid248_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q); ts3_uid248_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q(36)) & reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q); ts3_uid248_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid248_sinPiZPolyEval_a) + SIGNED(ts3_uid248_sinPiZPolyEval_b)); ts3_uid248_sinPiZPolyEval_q <= ts3_uid248_sinPiZPolyEval_o(45 downto 0); --s3_uid249_sinPiZPolyEval(BITSELECT,248)@20 s3_uid249_sinPiZPolyEval_in <= ts3_uid248_sinPiZPolyEval_q; s3_uid249_sinPiZPolyEval_b <= s3_uid249_sinPiZPolyEval_in(45 downto 1); --yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval(BITSELECT,286)@20 yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b; yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in(44 downto 18); --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9(REG,399)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor(LOGICAL,1091) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top(CONSTANT,1087) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q <= "01100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp(LOGICAL,1088) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg(REG,1089) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena(REG,1092) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd(LOGICAL,1093) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1083) -- every=1, low=0, high=12, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i = 11 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i - 12; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i,4)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg(REG,1084) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux(MUX,1085) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem(DUALMEM,1082) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 13, width_b => 45, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg(DELAY,1081) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT4_uid250_sinPiZPolyEval(BITSELECT,249)@20 yT4_uid250_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q; yT4_uid250_sinPiZPolyEval_b <= yT4_uid250_sinPiZPolyEval_in(44 downto 2); --xBottomBits_uid290_pT4_uid251_sinPiZPolyEval(BITSELECT,289)@20 xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in <= yT4_uid250_sinPiZPolyEval_b(15 downto 0); xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in(15 downto 0); --pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval(BITJOIN,291)@20 pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7(REG,401)@20 reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid289_pT4_uid251_sinPiZPolyEval(BITSELECT,288)@20 yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b(17 downto 0); yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b <= yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a(DELAY,733)@20 ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b, xout => ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval(BITJOIN,290)@21 spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q; --pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval(BITJOIN,292)@21 pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q <= spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6(REG,400)@21 reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a(DELAY,727)@20 ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 43, depth => 1 ) PORT MAP ( xin => yT4_uid250_sinPiZPolyEval_b, xout => ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval(BITSELECT,285)@21 xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in <= ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q; xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in(42 downto 16); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4(REG,402)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma(CHAINMULTADD,346)@22 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval(BITSELECT,294)@25 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in(54 downto 8); --highBBits_uid297_pT4_uid251_sinPiZPolyEval(BITSELECT,296)@25 highBBits_uid297_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b; highBBits_uid297_pT4_uid251_sinPiZPolyEval_b <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_in(46 downto 18); --reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1(REG,405)@25 reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1(REG,403)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b(DELAY,730)@21 ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0(REG,404)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid288_pT4_uid251_sinPiZPolyEval(MULT,287)@22 topProd_uid288_pT4_uid251_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_b); topProd_uid288_pT4_uid251_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid288_pT4_uid251_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid288_pT4_uid251_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0(REG,406)@25 reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid298_pT4_uid251_sinPiZPolyEval(ADD,297)@26 sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q(53)) & reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b)); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid296_pT4_uid251_sinPiZPolyEval(BITSELECT,295)@25 lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b(17 downto 0); lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b <= lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a(DELAY,741)@25 ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b, xout => ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid296_uid299_pT4_uid251_sinPiZPolyEval(BITJOIN,298)@26 add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q & ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q; --R_uid300_pT4_uid251_sinPiZPolyEval(BITSELECT,299)@26 R_uid300_pT4_uid251_sinPiZPolyEval_in <= add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q(71 downto 0); R_uid300_pT4_uid251_sinPiZPolyEval_b <= R_uid300_pT4_uid251_sinPiZPolyEval_in(71 downto 26); --reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1(REG,407)@26 reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= R_uid300_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor(LOGICAL,1155) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1151) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q <= "010010"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp(LOGICAL,1152) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg(REG,1153) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena(REG,1156) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1157) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1147) -- every=1, low=0, high=18, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i = 17 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i - 18; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg(REG,1148) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1149) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1146) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 19, width_b => 7, widthad_b => 5, numwords_b => 19, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg(DELAY,1145) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0(REG,380)@25 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC1_uid227_sinPiZTableGenerator(LOOKUP,226)@26 memoryC1_uid227_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; WHEN "0000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111110101101010100010101111000000010001111100011"; WHEN "0000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111101011010101001001010010110100010110001011110"; WHEN "0000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111100000111111110111100000001110010011010000110"; WHEN "0000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111010110101010110001001011111100110111111100011"; WHEN "0000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111001100010101111010001010101001101111010110100"; WHEN "0000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111000010000001010110010000110111110101011111000"; WHEN "0000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110110111101101001001010011000001101011000111010"; WHEN "0001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110101101011001010111000101010111101010010100111"; WHEN "0001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110100011000110000011011011111110011010111001110"; WHEN "0001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110011000110011010010001010101101000110101101101"; WHEN "0001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110001110100001000111000101001011101110011011101"; WHEN "0001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110000100001111100101111110110001011110001011001"; WHEN "0001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101111001111110110010101010100011000010010100110"; WHEN "0001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101101111101110110000111011010000111100011100100"; WHEN "0001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101100101011111100100100011010101111000101000111"; WHEN "0010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101011011010001010001010100110101000010011111000"; WHEN "0010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101010001000011111011000001011000011010110000100"; WHEN "0010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101000110110111100101011010001111001100111110010"; WHEN "0010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100111100101100010100010000001100000101010111010"; WHEN "0010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100110010100010001011010011100011100110101011100"; WHEN "0010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100101000011001001110010100001010100000101101100"; WHEN "0010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100011110010001100001000001010100000110110000000"; WHEN "0010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100010100001011000111001001110000100110010111000"; WHEN "0011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100001010000110000100011011101011011110011010110"; WHEN "0011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100000000000010011100100100101001110110011000010"; WHEN "0011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011110110000000010011010001101000110110000011100"; WHEN "0011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011101011111111101100001110111011111101010000000"; WHEN "0011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011100010000000101011001000001011011100001111010"; WHEN "0011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011011000000011010011101000010010101100000110110"; WHEN "0011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011001110000111101001011001011110100111101110010"; WHEN "0011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011000100001101110000000101001100000101000010010"; WHEN "0100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010111010010101101011010100000110001110011110001"; WHEN "0100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010110000011111011110101110000100111100111110101"; WHEN "0100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010100110101011001101111010001011010010011110011"; WHEN "0100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010011100111000111100011110100101110100010111000"; WHEN "0100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010010011001000101110000000101001000110111000111"; WHEN "0100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010001001011010100110000100110000001000100101001"; WHEN "0100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001111111101110101000001110011010101110010001110"; WHEN "0100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001110110000100111000000000001011111111100011001"; WHEN "0101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001101100011101011000111011101000110011100100000"; WHEN "0101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001100010111000001110100001010110001110100101001"; WHEN "0101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001011001010101011100010000110111111111100011001"; WHEN "0101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001001111110101000101101000101110111110101110110"; WHEN "0101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001000110010111001110000110010111101100001101110"; WHEN "0101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000111100111011111001000110001000101111011110000"; WHEN "0101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000110011100011001010000011010001010111001000100"; WHEN "0101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000101010001101000100010111110111111001010110011"; WHEN "0110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000100000111001101011011100111000010100110100100"; WHEN "0110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000010111101001000010101010000010110010001100101"; WHEN "0110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000001110011011001101010101111010000110001110001"; WHEN "0110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000000101010000001110110101110010010100010001010"; WHEN "0110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111111100001000001010011101101111010001101110100"; WHEN "0110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111110011000011000011100000100011001001100111111"; WHEN "0110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111101010000000111101001111101101000001001100111"; WHEN "0110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111100001000001111010111011010111011101000011000"; WHEN "0111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111011000000101111111110010010111000110100000100"; WHEN "0111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111001111001101001111000010001001010010011000111"; WHEN "0111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111000110010111101011110110110010100111101001111"; WHEN "0111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110111101100101011001011010111101100111001001111"; WHEN "0111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110110100110110011010110111111001010011111110011"; WHEN "0111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110101100001010110011010101010111111100100001011"; WHEN "0111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110100011100010100101111001101101100100000011010"; WHEN "0111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110011010111101110101101001101110101101001000101"; WHEN "1000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110010010011100100101101000101111000100111000101"; WHEN "1000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110001001111110111000111000100000001110100110010"; WHEN "1000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110000001100100110010011001010000010000100100001"; WHEN "1000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101111001001110010101001001101000100001000011111"; WHEN "1000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101110000111011100100000110101100010100101111011"; WHEN "1000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101101000101100100010001011110111101101010011001"; WHEN "1000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101100000100001010010010010111110001001000100100"; WHEN "1000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101011000011001110111010100001001010011011010001"; WHEN "1001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101010000010110010100000101110111110101110111011"; WHEN "1001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101001000010110101011011100111100001010010001010"; WHEN "1001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101000000011011000000001100011011001101001101101"; WHEN "1001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100111000100011010101000101101011010001111110100"; WHEN "1001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100110000101111101100111000010010110110101001010"; WHEN "1001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100101001000000001010010010000111011001100101001"; WHEN "1001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100100001010100101111111111001100001111011011000"; WHEN "1001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100011001101101100000101001110001011001110111100"; WHEN "1010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100010010001010011110111010010010011111110100100"; WHEN "1010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100001010101011101101010111010101100101110000010"; WHEN "1010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100000011010001001110100101101010000111010011101"; WHEN "1010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011111011111011000101001000000111110001110111111"; WHEN "1010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011110100101001010011011111101101011111101000010"; WHEN "1010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011101101011011111100001011100000010100000001101"; WHEN "1010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011100110010011000001101000101010011000110001101"; WHEN "1010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011111001110100110010010011001111011110111011"; WHEN "1011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011000001110101100100010000000001110100011101"; WHEN "1011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011010001010011010110101110110000100101001100010"; WHEN "1011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011001010011100100111001101111111011000001100001"; WHEN "1011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011000011101010100000010011000001000101101011001"; WHEN "1011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010111100111101000100001111001001010100001001100"; WHEN "1011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010110110010100010101010001101001110110001111011"; WHEN "1011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101111110000010101100111110001101111011011100"; WHEN "1011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101001010001000111011100101100011001011100101"; WHEN "1100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010100010110110101100111001100000101011000010000"; WHEN "1100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010011100100001001000000101001111111111010110011"; WHEN "1100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010110010000011011000100110101011110110000011"; WHEN "1100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010000000100100111111011000101001000001000001"; WHEN "1100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010001001111101110000101000101010111011100100101"; WHEN "1100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010000011111011110111001100001010000110000001000"; WHEN "1100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111101111110111101100001111100001101100011111"; WHEN "1100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111000000111000101100100010000011111010101010"; WHEN "1101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001110010010100010001001011001010111110000100010"; WHEN "1101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001101100100110100010001100100011110001100110110"; WHEN "1101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100110111101111010011100000110010111101110011"; WHEN "1101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100001011010011011101011010000110101111000110"; WHEN "1101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001011011111100000111101001010011001011111101101"; WHEN "1101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010110100011000000000011001110101000000001010"; WHEN "1101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010001001111000110100011110100111011011010110"; WHEN "1101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001001100000000011100110011100111110000011010110"; WHEN "1110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000110110111000100011000111000000001100101100"; WHEN "1110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000001110010111110110111100101010001100011100"; WHEN "1110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000111100110100001101110001011101000100010101000"; WHEN "1110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110111111010110010100101111010011001100111001"; WHEN "1110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110011000110101110110010000101000111111101001"; WHEN "1110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101110011000000011110000110001011001010001101"; WHEN "1110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101001101110110010111010011111001000001110011"; WHEN "1110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100101001010111101100101011001011110111111001"; WHEN "1111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100000101100100101000101010110010110110110011"; WHEN "1111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011100010011101010101011110101111000111101111"; WHEN "1111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011000000000001111101000000010000000010001101"; WHEN "1111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000010011110010010101000110101101111100100010110"; WHEN "1111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001111101001111100010010010101110110011110010"; WHEN "1111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001011100111000110010010111110010100110111110"; WHEN "1111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000111101001110100001110010100000011000001001"; WHEN "1111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000011110010000111000111101011011000001000111"; WHEN OTHERS => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; END CASE; -- End reserved scope level END PROCESS; --cIncludingRoundingBit_uid253_sinPiZPolyEval(BITJOIN,252)@26 cIncludingRoundingBit_uid253_sinPiZPolyEval_q <= memoryC1_uid227_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0(REG,408)@26 reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid253_sinPiZPolyEval_q; END IF; END PROCESS; --ts4_uid254_sinPiZPolyEval(ADD,253)@27 ts4_uid254_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((52 downto 52 => reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q(51)) & reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q); ts4_uid254_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((52 downto 46 => reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q(45)) & reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q); ts4_uid254_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid254_sinPiZPolyEval_a) + SIGNED(ts4_uid254_sinPiZPolyEval_b)); ts4_uid254_sinPiZPolyEval_q <= ts4_uid254_sinPiZPolyEval_o(52 downto 0); --s4_uid255_sinPiZPolyEval(BITSELECT,254)@27 s4_uid255_sinPiZPolyEval_in <= ts4_uid254_sinPiZPolyEval_q; s4_uid255_sinPiZPolyEval_b <= s4_uid255_sinPiZPolyEval_in(52 downto 1); --yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval(BITSELECT,301)@27 yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b; yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in(51 downto 25); --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9(REG,409)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor(LOGICAL,1117) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q <= not (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a or ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top(CONSTANT,1113) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q <= "010011"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp(LOGICAL,1114) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a = ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b else "0"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg(REG,1115) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena(REG,1118) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q = "1") THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd(LOGICAL,1119) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a and ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b; --xBottomBits_uid305_pT5_uid257_sinPiZPolyEval(BITSELECT,304)@5 xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b(17 downto 0); xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt(COUNTER,1109) -- every=1, low=0, high=19, step=1, init=1 ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i = 18 THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '1'; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i - 19; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i,5)); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg(REG,1110) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux(MUX,1111) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q) BEGIN CASE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s IS WHEN "0" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; WHEN "1" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; WHEN OTHERS => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem(DUALMEM,1108) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 <= areset; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 5, numwords_a => 20, width_b => 18, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0, clock1 => clk, address_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq, address_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa, data_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia ); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg(DELAY,1107) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q, xout => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q, clk => clk, aclr => areset ); --pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval(BITJOIN,306)@27 pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7(REG,411)@27 reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid304_pT5_uid257_sinPiZPolyEval(BITSELECT,303)@27 yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b(24 downto 0); yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b <= yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a(DELAY,750)@27 ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b, xout => ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval(BITJOIN,305)@28 spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q; --pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval(BITJOIN,307)@28 pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q <= spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q & GND_q; --reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6(REG,410)@28 reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor(LOGICAL,1104) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top(CONSTANT,1100) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q <= "010100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp(LOGICAL,1101) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg(REG,1102) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena(REG,1105) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd(LOGICAL,1106) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1096) -- every=1, low=0, high=20, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i = 19 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i - 20; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i,5)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg(REG,1097) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux(MUX,1098) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem(DUALMEM,1095) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 5, numwords_a => 21, width_b => 45, widthad_b => 5, numwords_b => 21, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg(DELAY,1094) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval(BITSELECT,300)@28 xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q; xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in(44 downto 18); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4(REG,412)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma(CHAINMULTADD,347)@29 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval(BITSELECT,309)@32 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in(54 downto 1); --highBBits_uid312_pT5_uid257_sinPiZPolyEval(BITSELECT,311)@32 highBBits_uid312_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b; highBBits_uid312_pT5_uid257_sinPiZPolyEval_b <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_in(53 downto 25); --reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1(REG,415)@32 reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1(REG,413)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b(DELAY,747)@28 ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0(REG,414)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid303_pT5_uid257_sinPiZPolyEval(MULT,302)@29 topProd_uid303_pT5_uid257_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_b); topProd_uid303_pT5_uid257_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid303_pT5_uid257_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid303_pT5_uid257_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0(REG,416)@32 reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid313_pT5_uid257_sinPiZPolyEval(ADD,312)@33 sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q(53)) & reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b)); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid311_pT5_uid257_sinPiZPolyEval(BITSELECT,310)@32 lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b(24 downto 0); lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b <= lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a(DELAY,758)@32 ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b, xout => ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid311_uid314_pT5_uid257_sinPiZPolyEval(BITJOIN,313)@33 add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q & ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q; --R_uid315_pT5_uid257_sinPiZPolyEval(BITSELECT,314)@33 R_uid315_pT5_uid257_sinPiZPolyEval_in <= add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q(78 downto 0); R_uid315_pT5_uid257_sinPiZPolyEval_b <= R_uid315_pT5_uid257_sinPiZPolyEval_in(78 downto 25); --reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1(REG,417)@33 reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= R_uid315_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor(LOGICAL,1142) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1138) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q <= "011001"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp(LOGICAL,1139) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg(REG,1140) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena(REG,1143) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1144) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1134) -- every=1, low=0, high=25, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i = 24 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i - 25; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg(REG,1135) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1136) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1133) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 26, width_b => 7, widthad_b => 5, numwords_b => 26, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg(DELAY,1132) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0(REG,379)@32 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC0_uid226_sinPiZTableGenerator(LOOKUP,225)@33 memoryC0_uid226_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; WHEN "0000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111010001111111001101111011000111100001001010"; WHEN "0000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000101010101111101111010001101100110011111100100"; WHEN "0000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000010000111010001110111000001110010011001110001"; WHEN "0000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001111101100101111100010000110111011000000101000010"; WHEN "0000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110111110001111110110010110011100111000110011101"; WHEN "0000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110000101011011011100110100000100010100111010101"; WHEN "0000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001101000010010010101010100001100000100101011101101"; WHEN "0001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001011110100110101111000010100110110100001011000010"; WHEN "0001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001010011101000101100010111000010101101001011110101"; WHEN "0001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001000111011000010001010101010001011100000010111010"; WHEN "0001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000111001110101100010011111100010101010110110110111"; WHEN "0001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000101011000000100100110110100010000001101000110010"; WHEN "0001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000011010111001011101111001010100111001000011000110"; WHEN "0001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000001001100000010011100101010111111111101111100110"; WHEN "0001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111110110110101001100010110011100110010010101101111"; WHEN "0010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111100010111000001111000110100110100110000010101111"; WHEN "0010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111001101101001100011001110000111100101111100011100"; WHEN "0010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110110111001001010000100011011101100011000000101111"; WHEN "0010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110011111010111011111011011001110010110110010111000"; WHEN "0010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110000110010100011000101000000100011000111000100110"; WHEN "0010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101101100000000000101011010101010100111001000011100"; WHEN "0010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101010000011010101111100001101000100000101011011110"; WHEN "0010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100110011100100100001001001011101110011110100001011"; WHEN "0011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100010101011101100100111100011101111110101100100111"; WHEN "0011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011110110000110000110000010101011100010111110000011"; WHEN "0011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011010101011110010000000001110011001100010100001001"; WHEN "0011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010110011100110001110111101000110101001111110010101"; WHEN "0011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010010000011110001111010101010111011011010001011111"; WHEN "0011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001101100000110011110001000110001001111001100110001"; WHEN "0011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001000110011111001000110010110100010111000011111111"; WHEN "0011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001000011111101000011101001100001111101100010010011001"; WHEN "0100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111110111100010101001101010111010101001011000110001"; WHEN "0100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111001110001101111101000001101110110110001001100100"; WHEN "0100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000110100011101010100110100000100001100111000110001110"; WHEN "0100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101110111111000110101110011111101010000010000111000"; WHEN "0100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101001010111000111011000101011010001011010101011100"; WHEN "0100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000100011100101011000110111010110111110001001101100111"; WHEN "0100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000011101101001111101010010110110101000111000011000010"; WHEN "0100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010111100100110110110111000001001011110110011001101"; WHEN "0101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010001010110000111110011001111100101011011000101100"; WHEN "0101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000001010111101110010011010011011111001000011101001111"; WHEN "0101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000000100011011111001000011000000001110101111000110101"; WHEN "0101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111111101110000011110000110110101110000111000001001000"; WHEN "0101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111110110111011100100000011010011101000101101101101111"; WHEN "0101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101111111101001101011001001101111001001010100111010"; WHEN "0101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101000110101011100101100110100011000001100101000111"; WHEN "0101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111100001100100010100100101110001100110101011111100110"; WHEN "0110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111011010001001110111101111001001100110110011000001101"; WHEN "0110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111010010100110001000110111011000110000110111110111111"; WHEN "0110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111001010111001001010110000010010100110110110111111101"; WHEN "0110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111000011000011000000001111000000100110010000101101101"; WHEN "0110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110111011000011101100001100000000111000101001011011010"; WHEN "0110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110110010111011010001100011000101000010101101011001001"; WHEN "0110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110101010101001110011010011010000110001111000101001011"; WHEN "0110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110100010001111010100011110111000101000100011101001111"; WHEN "0111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110011001101011111000001011100000101000110101010111101"; WHEN "0111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110010000111111100001100001111010111101111011010000110"; WHEN "0111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110001000001010010011101110000110100100001000000010111"; WHEN "0111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101111111001100010001111111001101101111011001101100100"; WHEN "0111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101110110000101011111100111100100110000100111011101101"; WHEN "0111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101101100110101111111111100101000011001011000100010101"; WHEN "0111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101100011011101110110010110111100011110100100000110011"; WHEN "0111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101011001111101000110010010001010011001011011010110110"; WHEN "1000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101010000010011110011001100111111100111011110011001101"; WHEN "1000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101000110100010000000101001001100001000111100100001001"; WHEN "1000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100111100100111110010001011100000111110000000101011101"; WHEN "1000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100110010100101001011011011101110100010101011000001110"; WHEN "1000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100101000011010010000000100100011001001010111111110011"; WHEN "1000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100011110000111000011110011101001010100010101110100101"; WHEN "1000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100010011101011101010011001100110001101101001100010111"; WHEN "1000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100001001001000000111101001110111111110000011100100111"; WHEN "1001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011111110011100011111011010110100000010100101010111001"; WHEN "1001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011110011101000110101100101100101100000111000011110001"; WHEN "1001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011101000101101001110000110001011011010011000000110010"; WHEN "1001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011011101101001101100111011010110111110001101101101010"; WHEN "1001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011010010011110010110000110101001111010000001101101100"; WHEN "1001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011000111001011001101101100010100101001100000111100110"; WHEN "1001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010111011110000010111110011010100100100110111110110011"; WHEN "1001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010110000001101111000100101010010001110000100000110101"; WHEN "1010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010100100100011110100001110011111011100111101101011110"; WHEN "1010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010011000110010001110111101110101101010011000000111111"; WHEN "1010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010001100111001001101000100110011111001111100111000001"; WHEN "1010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010000000111000110010110111011101000010111111101010001"; WHEN "1010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001110100110001000100101100010101111000001101101010100"; WHEN "1010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001101000100010000110111100100011001110011000100010010"; WHEN "1010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001011100001011111110000011101000000001111110000000000"; WHEN "1010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001001111101110101110011111100011011011101101000101110"; WHEN "1011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001000011001010011100110000101110110100001001110110000"; WHEN "1011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000110110011111001101011001111011110110010000011100000"; WHEN "1011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000101001101101000101000000010010100000111000101001110"; WHEN "1011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000011100110100001000001011001111000111011010101001101"; WHEN "1011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000001111110100011011100100100000010001010101111111000"; WHEN "1011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000000010101110000011111000000100111000111011110010110"; WHEN "1011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111110101100001000101110100001010001000111101001001101"; WHEN "1011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111101000001101100110001001001001011001011110100011010"; WHEN "1100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111011010110011101001101001100110001011110001011110000"; WHEN "1100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111001101010011010101001010001100000101010101000000111"; WHEN "1100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110111111101100101101100001101100101001111110101000001"; WHEN "1100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110110001111111110111101000111101010101001011110111000"; WHEN "1100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110100100001100111000011010110101010010011110001011110"; WHEN "1100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110010110010011110100110100001011010101000001111000001"; WHEN "1100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110001000010100110001110011110011101110100000111111001"; WHEN "1100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101111010001111110100011010011110000101000011010111010"; WHEN "1101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101101100000101000001101010110011001000011100110100101"; WHEN "1101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101011101110100011110101001010010100110101010011100110"; WHEN "1101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101001111011110010000011100010000111111100000000100011"; WHEN "1101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101000001000010011100001011110101010111100110111011100"; WHEN "1101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100110010100001000111000001110111001010101110101010001"; WHEN "1101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100100011111010010110001001111011111101010001100000100"; WHEN "1101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100010101001110001110110001010101001101001100111101111"; WHEN "1101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100000110011100110110000110111110000010001111110011101"; WHEN "1110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011110111100110010001011011011000111101011110100101010"; WHEN "1110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011101000101010100110000000101101101000001111101101101"; WHEN "1110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011011001101001111001001010100110100010100000001010111"; WHEN "1110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011001010100100010000001110001110110000100001110111001"; WHEN "1110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010111011011001110000100010001111101000000100110100000"; WHEN "1110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010101100001010011111011110101110011100111100001100101"; WHEN "1110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010011100110110100010011101001010001101000000010101011"; WHEN "1110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010001101011101111110111000011001001011101110101101100"; WHEN "1111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001111110000000111010001100100110101101001001001010110"; WHEN "1111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001101110011111011001110111010000110000010101010100001"; WHEN "1111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001011110111001100011010111000101101001011101010010011"; WHEN "1111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001001111001111011100001100000001101011010010111101001"; WHEN "1111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000111111100001001001110111001100110000010110101011110"; WHEN "1111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000101111101110110001111010111000000011100010110001010"; WHEN "1111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000011111111000011001111010011011101000011100101001111"; WHEN "1111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000001111111110000111011010010100000011001101000010011"; WHEN OTHERS => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid258_sinPiZPolyEval(CONSTANT,257) rndBit_uid258_sinPiZPolyEval_q <= "001"; --cIncludingRoundingBit_uid259_sinPiZPolyEval(BITJOIN,258)@33 cIncludingRoundingBit_uid259_sinPiZPolyEval_q <= memoryC0_uid226_sinPiZTableGenerator_q & rndBit_uid258_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0(REG,418)@33 reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid259_sinPiZPolyEval_q; END IF; END PROCESS; --ts5_uid260_sinPiZPolyEval(ADD,259)@34 ts5_uid260_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q); ts5_uid260_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((61 downto 54 => reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q(53)) & reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q); ts5_uid260_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid260_sinPiZPolyEval_a) + SIGNED(ts5_uid260_sinPiZPolyEval_b)); ts5_uid260_sinPiZPolyEval_q <= ts5_uid260_sinPiZPolyEval_o(61 downto 0); --s5_uid261_sinPiZPolyEval(BITSELECT,260)@34 s5_uid261_sinPiZPolyEval_in <= ts5_uid260_sinPiZPolyEval_q; s5_uid261_sinPiZPolyEval_b <= s5_uid261_sinPiZPolyEval_in(61 downto 1); --fxpSinRes_uid66_fpSinPiTest(BITSELECT,65)@34 fxpSinRes_uid66_fpSinPiTest_in <= s5_uid261_sinPiZPolyEval_b(58 downto 0); fxpSinRes_uid66_fpSinPiTest_b <= fxpSinRes_uid66_fpSinPiTest_in(58 downto 5); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor(LOGICAL,963) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q <= not (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a or ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top(CONSTANT,959) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q <= "011111"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp(LOGICAL,960) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q <= "1" when ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a = ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b else "0"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg(REG,961) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena(REG,964) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q = "1") THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd(LOGICAL,965) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a and ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt(COUNTER,955) -- every=1, low=0, high=31, step=1, init=1 ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ELSIF (clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg(REG,956) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux(MUX,957) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux: PROCESS (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem(DUALMEM,954) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia <= sinXIsX_uid30_fpSinPiTest_c; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 32, width_b => 1, widthad_b => 5, numwords_b => 32, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq, address_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa, data_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia ); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg(DELAY,953) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --multRightOp_uid68_fpSinPiTest(MUX,67)@34 multRightOp_uid68_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q; multRightOp_uid68_fpSinPiTest: PROCESS (multRightOp_uid68_fpSinPiTest_s, fxpSinRes_uid66_fpSinPiTest_b) BEGIN CASE multRightOp_uid68_fpSinPiTest_s IS WHEN "0" => multRightOp_uid68_fpSinPiTest_q <= fxpSinRes_uid66_fpSinPiTest_b; WHEN "1" => multRightOp_uid68_fpSinPiTest_q <= piwFP2_uid67_fpSinPiTest_q; WHEN OTHERS => multRightOp_uid68_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_b_1(BITSELECT,318)@34 mul2xSinRes_uid69_fpSinPiTest_b_1_in <= multRightOp_uid68_fpSinPiTest_q; mul2xSinRes_uid69_fpSinPiTest_b_1_b <= mul2xSinRes_uid69_fpSinPiTest_b_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1(REG,423)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor(LOGICAL,1129) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q <= not (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a or ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top(CONSTANT,1125) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q <= "010110"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp(LOGICAL,1126) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q <= "1" when ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a = ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b else "0"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg(REG,1127) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena(REG,1130) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q = "1") THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd(LOGICAL,1131) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a and ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor(LOGICAL,937) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a or ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top(CONSTANT,933) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q <= "0111"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp(LOGICAL,934) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a = ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b else "0"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg(REG,935) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena(REG,938) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q = "1") THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd(LOGICAL,939) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt(COUNTER,929) -- every=1, low=0, high=7, step=1, init=1 ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,3); ELSIF (clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i + 1; END IF; END PROCESS; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i,3)); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg(REG,930) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux(MUX,931) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q) BEGIN CASE ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s IS WHEN "0" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; WHEN "1" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; WHEN OTHERS => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem(DUALMEM,928) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 <= areset; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia <= oFracX_uid31_uid31_fpSinPiTest_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 3, numwords_a => 8, width_b => 53, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq, address_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa, data_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia ); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq(52 downto 0); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg(DELAY,927) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg : dspba_delay GENERIC MAP ( width => 53, depth => 1 ) PORT MAP ( xin => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q, xout => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q, clk => clk, aclr => areset ); --LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest(BITSELECT,220)@10 LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q(77 downto 0); LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in(77 downto 0); --leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest(BITJOIN,221)@10 leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b & GND_q; --LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest(BITSELECT,204)@9 LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(54 downto 0); LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in(54 downto 0); --leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest(BITJOIN,205)@9 leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest(BITSELECT,201)@9 LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(62 downto 0); LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in(62 downto 0); --leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest(BITJOIN,202)@9 leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest(BITSELECT,198)@9 LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(70 downto 0); LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in(70 downto 0); --leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest(BITJOIN,199)@9 leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --ozz_uid41_fpSinPiTest(CONSTANT,40) ozz_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor(LOGICAL,1040) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q <= not (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a or ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top(CONSTANT,1036) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q <= "011"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp(LOGICAL,1037) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q <= "1" when ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a = ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b else "0"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg(REG,1038) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena(REG,1041) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q = "1") THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd(LOGICAL,1042) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a and ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b; --vStage_uid149_lzcZ_uid51_fpSinPiTest(BITSELECT,148)@4 vStage_uid149_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(14 downto 0); vStage_uid149_lzcZ_uid51_fpSinPiTest_b <= vStage_uid149_lzcZ_uid51_fpSinPiTest_in(14 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt(COUNTER,1032) -- every=1, low=0, high=3, step=1, init=1 ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,2); ELSIF (clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i,2)); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg(REG,1033) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux(MUX,1034) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1043) ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= vStage_uid149_lzcZ_uid51_fpSinPiTest_b; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 2, numwords_a => 4, width_b => 15, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(14 downto 0); --leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest(BITJOIN,193)@9 leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X46dto0_uid190_alignedZ_uid52_fpSinPiTest(BITSELECT,189)@4 X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(46 downto 0); X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in(46 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1031) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 47, widthad_a => 2, numwords_a => 4, width_b => 47, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(46 downto 0); --leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest(BITJOIN,190)@9 leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor(LOGICAL,1065) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q <= not (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a or ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top(CONSTANT,1061) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q <= "010"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp(LOGICAL,1062) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q <= "1" when ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a = ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b else "0"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg(REG,1063) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena(REG,1066) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q = "1") THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd(LOGICAL,1067) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a and ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt(COUNTER,1057) -- every=1, low=0, high=2, step=1, init=1 ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i = 1 THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i - 2; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i,2)); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg(REG,1058) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux(MUX,1059) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux: PROCESS (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem(DUALMEM,1056) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia <= z_uid49_fpSinPiTest_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 79, widthad_a => 2, numwords_a => 3, width_b => 79, widthad_b => 2, numwords_b => 3, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq, address_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa, data_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia ); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq(78 downto 0); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg(DELAY,1055) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q, xout => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --rVStage_uid146_lzcZ_uid51_fpSinPiTest(BITSELECT,145)@4 rVStage_uid146_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; rVStage_uid146_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_in(78 downto 15); --reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0(REG,365)@4 reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid147_lzcZ_uid51_fpSinPiTest(LOGICAL,146)@5 vCount_uid147_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid147_lzcZ_uid51_fpSinPiTest_a = vCount_uid147_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g(DELAY,629)@5 ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => vCount_uid147_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q, clk => clk, aclr => areset ); --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b(DELAY,587)@4 ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => vStage_uid149_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q, clk => clk, aclr => areset ); --mO_uid148_lzcZ_uid51_fpSinPiTest(CONSTANT,147) mO_uid148_lzcZ_uid51_fpSinPiTest_q <= "1111111111111111111111111111111111111111111111111"; --cStage_uid150_lzcZ_uid51_fpSinPiTest(BITJOIN,149)@5 cStage_uid150_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q & mO_uid148_lzcZ_uid51_fpSinPiTest_q; --ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c(DELAY,589)@4 ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 64, depth => 1 ) PORT MAP ( xin => rVStage_uid146_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid152_lzcZ_uid51_fpSinPiTest(MUX,151)@5 vStagei_uid152_lzcZ_uid51_fpSinPiTest_s <= vCount_uid147_lzcZ_uid51_fpSinPiTest_q; vStagei_uid152_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid152_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, cStage_uid150_lzcZ_uid51_fpSinPiTest_q) BEGIN CASE vStagei_uid152_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= cStage_uid150_lzcZ_uid51_fpSinPiTest_q; WHEN OTHERS => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid154_lzcZ_uid51_fpSinPiTest(BITSELECT,153)@5 rVStage_uid154_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q; rVStage_uid154_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_in(63 downto 32); --reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0(REG,366)@5 reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= "00000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid155_lzcZ_uid51_fpSinPiTest(LOGICAL,154)@6 vCount_uid155_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid155_lzcZ_uid51_fpSinPiTest_a = vCount_uid155_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f(DELAY,628)@6 ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid155_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q, clk => clk, aclr => areset ); --vStage_uid156_lzcZ_uid51_fpSinPiTest(BITSELECT,155)@5 vStage_uid156_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q(31 downto 0); vStage_uid156_lzcZ_uid51_fpSinPiTest_b <= vStage_uid156_lzcZ_uid51_fpSinPiTest_in(31 downto 0); --ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d(DELAY,596)@5 ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => vStage_uid156_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c(DELAY,595)@5 ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => rVStage_uid154_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid158_lzcZ_uid51_fpSinPiTest(MUX,157)@6 vStagei_uid158_lzcZ_uid51_fpSinPiTest_s <= vCount_uid155_lzcZ_uid51_fpSinPiTest_q; vStagei_uid158_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid158_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid158_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid160_lzcZ_uid51_fpSinPiTest(BITSELECT,159)@6 rVStage_uid160_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q; rVStage_uid160_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_in(31 downto 16); --reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0(REG,367)@6 reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid161_lzcZ_uid51_fpSinPiTest(LOGICAL,160)@7 vCount_uid161_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid161_lzcZ_uid51_fpSinPiTest_a = vCount_uid161_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e(DELAY,627)@7 ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid161_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q, clk => clk, aclr => areset ); --vStage_uid162_lzcZ_uid51_fpSinPiTest(BITSELECT,161)@6 vStage_uid162_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q(15 downto 0); vStage_uid162_lzcZ_uid51_fpSinPiTest_b <= vStage_uid162_lzcZ_uid51_fpSinPiTest_in(15 downto 0); --ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d(DELAY,602)@6 ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => vStage_uid162_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c(DELAY,601)@6 ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => rVStage_uid160_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid164_lzcZ_uid51_fpSinPiTest(MUX,163)@7 vStagei_uid164_lzcZ_uid51_fpSinPiTest_s <= vCount_uid161_lzcZ_uid51_fpSinPiTest_q; vStagei_uid164_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid164_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid164_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid166_lzcZ_uid51_fpSinPiTest(BITSELECT,165)@7 rVStage_uid166_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q; rVStage_uid166_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_in(15 downto 8); --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0(REG,368)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid167_lzcZ_uid51_fpSinPiTest(LOGICAL,166)@8 vCount_uid167_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid167_lzcZ_uid51_fpSinPiTest_a = vCount_uid167_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid168_lzcZ_uid51_fpSinPiTest(BITSELECT,167)@7 vStage_uid168_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q(7 downto 0); vStage_uid168_lzcZ_uid51_fpSinPiTest_b <= vStage_uid168_lzcZ_uid51_fpSinPiTest_in(7 downto 0); --reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3(REG,369)@7 reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= vStage_uid168_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2(REG,370)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vStagei_uid170_lzcZ_uid51_fpSinPiTest(MUX,169)@8 vStagei_uid170_lzcZ_uid51_fpSinPiTest_s <= vCount_uid167_lzcZ_uid51_fpSinPiTest_q; vStagei_uid170_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid170_lzcZ_uid51_fpSinPiTest_s, reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q, reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q) BEGIN CASE vStagei_uid170_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q; WHEN "1" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q; WHEN OTHERS => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid172_lzcZ_uid51_fpSinPiTest(BITSELECT,171)@8 rVStage_uid172_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q; rVStage_uid172_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_in(7 downto 4); --vCount_uid173_lzcZ_uid51_fpSinPiTest(LOGICAL,172)@8 vCount_uid173_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; vCount_uid173_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; vCount_uid173_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid173_lzcZ_uid51_fpSinPiTest_a = vCount_uid173_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid174_lzcZ_uid51_fpSinPiTest(BITSELECT,173)@8 vStage_uid174_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q(3 downto 0); vStage_uid174_lzcZ_uid51_fpSinPiTest_b <= vStage_uid174_lzcZ_uid51_fpSinPiTest_in(3 downto 0); --vStagei_uid176_lzcZ_uid51_fpSinPiTest(MUX,175)@8 vStagei_uid176_lzcZ_uid51_fpSinPiTest_s <= vCount_uid173_lzcZ_uid51_fpSinPiTest_q; vStagei_uid176_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid176_lzcZ_uid51_fpSinPiTest_s, rVStage_uid172_lzcZ_uid51_fpSinPiTest_b, vStage_uid174_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid176_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= vStage_uid174_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid178_lzcZ_uid51_fpSinPiTest(BITSELECT,177)@8 rVStage_uid178_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q; rVStage_uid178_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_in(3 downto 2); --vCount_uid179_lzcZ_uid51_fpSinPiTest(LOGICAL,178)@8 vCount_uid179_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; vCount_uid179_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; vCount_uid179_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid179_lzcZ_uid51_fpSinPiTest_a = vCount_uid179_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid180_lzcZ_uid51_fpSinPiTest(BITSELECT,179)@8 vStage_uid180_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q(1 downto 0); vStage_uid180_lzcZ_uid51_fpSinPiTest_b <= vStage_uid180_lzcZ_uid51_fpSinPiTest_in(1 downto 0); --vStagei_uid182_lzcZ_uid51_fpSinPiTest(MUX,181)@8 vStagei_uid182_lzcZ_uid51_fpSinPiTest_s <= vCount_uid179_lzcZ_uid51_fpSinPiTest_q; vStagei_uid182_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid182_lzcZ_uid51_fpSinPiTest_s, rVStage_uid178_lzcZ_uid51_fpSinPiTest_b, vStage_uid180_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid182_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= vStage_uid180_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid184_lzcZ_uid51_fpSinPiTest(BITSELECT,183)@8 rVStage_uid184_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid51_fpSinPiTest_q; rVStage_uid184_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_in(1 downto 1); --vCount_uid185_lzcZ_uid51_fpSinPiTest(LOGICAL,184)@8 vCount_uid185_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_b; vCount_uid185_lzcZ_uid51_fpSinPiTest_b <= GND_q; vCount_uid185_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid185_lzcZ_uid51_fpSinPiTest_a = vCount_uid185_lzcZ_uid51_fpSinPiTest_b else "0"; --r_uid186_lzcZ_uid51_fpSinPiTest(BITJOIN,185)@8 r_uid186_lzcZ_uid51_fpSinPiTest_q <= ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q & ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q & ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q & vCount_uid167_lzcZ_uid51_fpSinPiTest_q & vCount_uid173_lzcZ_uid51_fpSinPiTest_q & vCount_uid179_lzcZ_uid51_fpSinPiTest_q & vCount_uid185_lzcZ_uid51_fpSinPiTest_q; --leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest(BITSELECT,195)@8 leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q; leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in(6 downto 5); --reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1(REG,371)@8 reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest(MUX,196)@9 leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q, leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q; WHEN "01" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ozz_uid41_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest(BITSELECT,206)@8 leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(4 downto 0); leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in(4 downto 3); --reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1(REG,372)@8 reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest(MUX,207)@9 leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s, leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest(BITSELECT,215)@9 LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(72 downto 0); LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in(72 downto 0); --leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest(BITJOIN,216)@9 leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5(REG,374)@9 reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest(BITSELECT,212)@9 LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest(BITJOIN,213)@9 leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4(REG,375)@9 reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest(BITSELECT,209)@9 LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest(BITJOIN,210)@9 leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3(REG,376)@9 reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2(REG,377)@9 reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest(BITSELECT,217)@8 leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(2 downto 0); leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in(2 downto 1); --reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1(REG,373)@8 reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b(DELAY,657)@9 ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest(MUX,218)@10 leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s, reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q, reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q, reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q, reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q) BEGIN CASE leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q; WHEN "01" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q; WHEN "10" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q; WHEN "11" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q; WHEN OTHERS => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest(BITSELECT,222)@8 leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(0 downto 0); leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in(0 downto 0); --reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1(REG,378)@8 reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b(DELAY,665)@9 ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest(MUX,223)@10 leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s, leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q, leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q; WHEN "1" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --alignedZLow_uid53_fpSinPiTest(BITSELECT,52)@10 alignedZLow_uid53_fpSinPiTest_in <= leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q; alignedZLow_uid53_fpSinPiTest_b <= alignedZLow_uid53_fpSinPiTest_in(78 downto 27); --pHardCase_uid54_fpSinPiTest(BITJOIN,53)@10 pHardCase_uid54_fpSinPiTest_q <= alignedZLow_uid53_fpSinPiTest_b & GND_q; --ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b(DELAY,474)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 10 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q, clk => clk, aclr => areset ); --p_uid55_fpSinPiTest(MUX,54)@10 p_uid55_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q; p_uid55_fpSinPiTest: PROCESS (p_uid55_fpSinPiTest_s, pHardCase_uid54_fpSinPiTest_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q) BEGIN CASE p_uid55_fpSinPiTest_s IS WHEN "0" => p_uid55_fpSinPiTest_q <= pHardCase_uid54_fpSinPiTest_q; WHEN "1" => p_uid55_fpSinPiTest_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q; WHEN OTHERS => p_uid55_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt(COUNTER,1121) -- every=1, low=0, high=22, step=1, init=1 ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i = 21 THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i - 22; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i,5)); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg(REG,1122) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux(MUX,1123) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux: PROCESS (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q) BEGIN CASE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s IS WHEN "0" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; WHEN "1" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem(DUALMEM,1120) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 <= areset; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia <= p_uid55_fpSinPiTest_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 5, numwords_a => 23, width_b => 53, widthad_b => 5, numwords_b => 23, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq, address_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa, data_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia ); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq(52 downto 0); --mul2xSinRes_uid69_fpSinPiTest_a_1(BITSELECT,316)@34 mul2xSinRes_uid69_fpSinPiTest_a_1_in <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q); mul2xSinRes_uid69_fpSinPiTest_a_1_b <= mul2xSinRes_uid69_fpSinPiTest_a_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0(REG,424)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b1(MULT,322)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_b); mul2xSinRes_uid69_fpSinPiTest_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1(BITSELECT,329)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1(REG,425)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a_0(BITSELECT,315)@34 mul2xSinRes_uid69_fpSinPiTest_a_0_in <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_a_0_b <= mul2xSinRes_uid69_fpSinPiTest_a_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0(REG,426)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b1(MULT,321)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_b); mul2xSinRes_uid69_fpSinPiTest_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1(BITSELECT,327)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_zero_36(CONSTANT,332) mul2xSinRes_uid69_fpSinPiTest_zero_36_q <= "000000000000000000000000000"; --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2(BITJOIN,336)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1(BITSELECT,328)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_b_0(BITSELECT,317)@34 mul2xSinRes_uid69_fpSinPiTest_b_0_in <= multRightOp_uid68_fpSinPiTest_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_b_0_b <= mul2xSinRes_uid69_fpSinPiTest_b_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1(REG,421)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0(REG,422)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b0(MULT,320)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_b); mul2xSinRes_uid69_fpSinPiTest_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0(BITSELECT,325)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1(BITJOIN,335)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC(LOGICAL,340)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b; --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1(BITSELECT,330)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0(BITSELECT,326)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1(REG,419)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0(REG,420)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b0(MULT,319)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_b); mul2xSinRes_uid69_fpSinPiTest_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0(BITSELECT,324)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0(BITSELECT,323)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0(BITJOIN,334)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC(LOGICAL,339)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB(LOGICAL,338)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne(LOGICAL,341)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c; --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS(BITSELECT,342)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q(106 downto 0); mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in(106 downto 0); --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ(BITJOIN,343)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b & GND_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b(BITJOIN,350)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b(BITSELECT,353)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne(LOGICAL,337)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a(BITJOIN,348)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a(BITSELECT,352)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2(ADD,354)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin <= GND_q; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b) & mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c(0) <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(90); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(89 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b(DELAY,822)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q, clk => clk, aclr => areset ); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a(DELAY,821)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2(ADD,355)@39 mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q) & mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o(20 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a(DELAY,824)@39 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a : dspba_delay GENERIC MAP ( width => 89, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q(BITJOIN,356)@40 mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q; --normBit_uid70_fpSinPiTest(BITSELECT,69)@40 normBit_uid70_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(106 downto 0); normBit_uid70_fpSinPiTest_b <= normBit_uid70_fpSinPiTest_in(106 downto 106); --ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c(DELAY,497)@40 ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => normBit_uid70_fpSinPiTest_b, xout => ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q, clk => clk, aclr => areset ); --rndExpUpdate_uid75_uid76_fpSinPiTest(BITJOIN,75)@41 rndExpUpdate_uid75_uid76_fpSinPiTest_q <= ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q & cstAllZWF_uid10_fpSinPiTest_q & VCC_q; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor(LOGICAL,976) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q <= not (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a or ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top(CONSTANT,972) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q <= "011100"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp(LOGICAL,973) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a = ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b else "0"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg(REG,974) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena(REG,977) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q = "1") THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd(LOGICAL,978) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a and ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem(DUALMEM,941) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 <= areset; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia <= expX_uid6_fpSinPiTest_b; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 3, numwords_a => 7, width_b => 11, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq, address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa, data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia ); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq(10 downto 0); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg(DELAY,940) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q, clk => clk, aclr => areset ); --expXP1_uid58_fpSinPiTest(ADD,57)@9 expXP1_uid58_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q); expXP1_uid58_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & VCC_q); expXP1_uid58_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid58_fpSinPiTest_a) + UNSIGNED(expXP1_uid58_fpSinPiTest_b)); expXP1_uid58_fpSinPiTest_q <= expXP1_uid58_fpSinPiTest_o(11 downto 0); --expXP1R_uid59_fpSinPiTest(BITSELECT,58)@9 expXP1R_uid59_fpSinPiTest_in <= expXP1_uid58_fpSinPiTest_q(10 downto 0); expXP1R_uid59_fpSinPiTest_b <= expXP1R_uid59_fpSinPiTest_in(10 downto 0); --reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1(REG,427)@8 reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= r_uid186_lzcZ_uid51_fpSinPiTest_q; END IF; END PROCESS; --expHardCase_uid57_fpSinPiTest(SUB,56)@9 expHardCase_uid57_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid27_fpSinPiTest_q); expHardCase_uid57_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000" & reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q); expHardCase_uid57_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid57_fpSinPiTest_a) - UNSIGNED(expHardCase_uid57_fpSinPiTest_b)); expHardCase_uid57_fpSinPiTest_q <= expHardCase_uid57_fpSinPiTest_o(11 downto 0); --expHardCaseR_uid60_fpSinPiTest(BITSELECT,59)@9 expHardCaseR_uid60_fpSinPiTest_in <= expHardCase_uid57_fpSinPiTest_q(10 downto 0); expHardCaseR_uid60_fpSinPiTest_b <= expHardCaseR_uid60_fpSinPiTest_in(10 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b(DELAY,481)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 9 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q, clk => clk, aclr => areset ); --expP_uid61_fpSinPiTest(MUX,60)@9 expP_uid61_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q; expP_uid61_fpSinPiTest: PROCESS (expP_uid61_fpSinPiTest_s, expHardCaseR_uid60_fpSinPiTest_b, expXP1R_uid59_fpSinPiTest_b) BEGIN CASE expP_uid61_fpSinPiTest_s IS WHEN "0" => expP_uid61_fpSinPiTest_q <= expHardCaseR_uid60_fpSinPiTest_b; WHEN "1" => expP_uid61_fpSinPiTest_q <= expXP1R_uid59_fpSinPiTest_b; WHEN OTHERS => expP_uid61_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt(COUNTER,968) -- every=1, low=0, high=28, step=1, init=1 ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i = 27 THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i - 28; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg(REG,969) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux(MUX,970) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem(DUALMEM,967) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia <= expP_uid61_fpSinPiTest_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 29, width_b => 11, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq, address_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa, data_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia ); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq(10 downto 0); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg(DELAY,966) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q, xout => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --highRes_uid71_fpSinPiTest(BITSELECT,70)@40 highRes_uid71_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(105 downto 0); highRes_uid71_fpSinPiTest_b <= highRes_uid71_fpSinPiTest_in(105 downto 53); --lowRes_uid72_fpSinPiTest(BITSELECT,71)@40 lowRes_uid72_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(104 downto 0); lowRes_uid72_fpSinPiTest_b <= lowRes_uid72_fpSinPiTest_in(104 downto 52); --fracRCompPreRnd_uid73_fpSinPiTest(MUX,72)@40 fracRCompPreRnd_uid73_fpSinPiTest_s <= normBit_uid70_fpSinPiTest_b; fracRCompPreRnd_uid73_fpSinPiTest: PROCESS (fracRCompPreRnd_uid73_fpSinPiTest_s, lowRes_uid72_fpSinPiTest_b, highRes_uid71_fpSinPiTest_b) BEGIN CASE fracRCompPreRnd_uid73_fpSinPiTest_s IS WHEN "0" => fracRCompPreRnd_uid73_fpSinPiTest_q <= lowRes_uid72_fpSinPiTest_b; WHEN "1" => fracRCompPreRnd_uid73_fpSinPiTest_q <= highRes_uid71_fpSinPiTest_b; WHEN OTHERS => fracRCompPreRnd_uid73_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracPreRnd_uid74_uid74_fpSinPiTest(BITJOIN,73)@40 expFracPreRnd_uid74_uid74_fpSinPiTest_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q & fracRCompPreRnd_uid73_fpSinPiTest_q; --reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0(REG,428)@40 reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= expFracPreRnd_uid74_uid74_fpSinPiTest_q; END IF; END PROCESS; --expFracComp_uid77_fpSinPiTest(ADD,76)@41 expFracComp_uid77_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q); expFracComp_uid77_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & rndExpUpdate_uid75_uid76_fpSinPiTest_q); expFracComp_uid77_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid77_fpSinPiTest_a) + UNSIGNED(expFracComp_uid77_fpSinPiTest_b)); expFracComp_uid77_fpSinPiTest_q <= expFracComp_uid77_fpSinPiTest_o(64 downto 0); --expRComp_uid79_fpSinPiTest(BITSELECT,78)@41 expRComp_uid79_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(63 downto 0); expRComp_uid79_fpSinPiTest_b <= expRComp_uid79_fpSinPiTest_in(63 downto 53); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor(LOGICAL,1015) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q <= not (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a or ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top(CONSTANT,1011) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q <= "0100010"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp(LOGICAL,1012) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q <= "1" when ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a = ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b else "0"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg(REG,1013) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena(REG,1016) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q = "1") THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd(LOGICAL,1017) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a and ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b; --reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1(REG,429)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c(DELAY,516)@0 ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q, xout => ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b(DELAY,515)@0 ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => expXIsZero_uid15_fpSinPiTest_q, xout => ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q, clk => clk, aclr => areset ); --reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0(REG,361)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --excRZero_uid87_fpSinPiTest(LOGICAL,86)@3 excRZero_uid87_fpSinPiTest_a <= reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q; excRZero_uid87_fpSinPiTest_b <= ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q; excRZero_uid87_fpSinPiTest_c <= ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q; excRZero_uid87_fpSinPiTest_q <= excRZero_uid87_fpSinPiTest_a or excRZero_uid87_fpSinPiTest_b or excRZero_uid87_fpSinPiTest_c; --Or2ExcRZeroXIsInt_uid92_fpSinPiTest(LOGICAL,91)@3 Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a <= excRZero_uid87_fpSinPiTest_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b <= reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a or Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt(COUNTER,1007) -- every=1, low=0, high=34, step=1, init=1 ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i = 33 THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i - 34; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg(REG,1008) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux(MUX,1009) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux: PROCESS (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem(DUALMEM,1006) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 35, width_b => 1, widthad_b => 6, numwords_b => 35, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq, address_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa, data_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia ); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg(DELAY,1005) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q, xout => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --expRPostExc1_uid95_fpSinPiTest(MUX,94)@41 expRPostExc1_uid95_fpSinPiTest_s <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q; expRPostExc1_uid95_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE expRPostExc1_uid95_fpSinPiTest_s IS WHEN "0" => expRPostExc1_uid95_fpSinPiTest_q <= expRComp_uid79_fpSinPiTest_b; WHEN "1" => expRPostExc1_uid95_fpSinPiTest_q <= cstAllZWE_uid11_fpSinPiTest_q; WHEN OTHERS => expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --InvXIntExp_uid84_fpSinPiTest(LOGICAL,83)@2 InvXIntExp_uid84_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; InvXIntExp_uid84_fpSinPiTest_q <= not InvXIntExp_uid84_fpSinPiTest_a; --join_uid42_fpSinPiTest(BITJOIN,41)@2 join_uid42_fpSinPiTest_q <= VCC_q & ozz_uid41_fpSinPiTest_q; --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0(REG,359)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid43_fpSinPiTest(LOGICAL,42)@2 yIsZero_uid43_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q; yIsZero_uid43_fpSinPiTest_b <= join_uid42_fpSinPiTest_q; yIsZero_uid43_fpSinPiTest_q <= "1" when yIsZero_uid43_fpSinPiTest_a = yIsZero_uid43_fpSinPiTest_b else "0"; --And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest(LOGICAL,85)@2 And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b <= yIsZero_uid43_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c <= InvSinXIsX_uid80_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d <= InvXIntExp_uid84_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d; --Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest(LOGICAL,95)@1 Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a <= GND_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q <= Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a or Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b; --ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a(DELAY,528)@1 ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q, xout => ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q, clk => clk, aclr => areset ); --join_uid97_fpSinPiTest(BITJOIN,96)@2 join_uid97_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q & ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q; --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg(DELAY,1195) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => join_uid97_fpSinPiTest_q, xout => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q, clk => clk, aclr => areset ); --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem(DUALMEM,1196) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 <= areset; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 6, numwords_a => 37, width_b => 2, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0, clock1 => clk, address_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq, address_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa, data_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia ); ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq(1 downto 0); --reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1(REG,430)@41 reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q; END IF; END PROCESS; --expRPostExc_uid98_fpSinPiTest(MUX,97)@42 expRPostExc_uid98_fpSinPiTest_s <= reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q; expRPostExc_uid98_fpSinPiTest: PROCESS (expRPostExc_uid98_fpSinPiTest_s, expRPostExc1_uid95_fpSinPiTest_q) BEGIN CASE expRPostExc_uid98_fpSinPiTest_s IS WHEN "00" => expRPostExc_uid98_fpSinPiTest_q <= expRPostExc1_uid95_fpSinPiTest_q; WHEN "01" => expRPostExc_uid98_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q; WHEN "10" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN "11" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN OTHERS => expRPostExc_uid98_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --oneFracRPostExc2_uid90_fpSinPiTest(CONSTANT,89) oneFracRPostExc2_uid90_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracRComp_uid78_fpSinPiTest(BITSELECT,77)@41 fracRComp_uid78_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(52 downto 0); fracRComp_uid78_fpSinPiTest_b <= fracRComp_uid78_fpSinPiTest_in(52 downto 1); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor(LOGICAL,989) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q <= not (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a or ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top(CONSTANT,985) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q <= "0100001"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp(LOGICAL,986) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q <= "1" when ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a = ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b else "0"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg(REG,987) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena(REG,990) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q = "1") THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd(LOGICAL,991) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a and ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b; --reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1(REG,362)@3 reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= excRZero_uid87_fpSinPiTest_q; END IF; END PROCESS; --ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a(DELAY,517)@2 ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q, xout => ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q, clk => clk, aclr => areset ); --or_uid88_fpSinPiTest(LOGICAL,87)@4 or_uid88_fpSinPiTest_a <= ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q; or_uid88_fpSinPiTest_b <= reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q; or_uid88_fpSinPiTest_c <= GND_q; or_uid88_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN or_uid88_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN or_uid88_fpSinPiTest_q <= or_uid88_fpSinPiTest_a or or_uid88_fpSinPiTest_b or or_uid88_fpSinPiTest_c; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt(COUNTER,981) -- every=1, low=0, high=33, step=1, init=1 ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i = 32 THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i - 33; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg(REG,982) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux(MUX,983) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux: PROCESS (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem(DUALMEM,980) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia <= or_uid88_fpSinPiTest_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 34, width_b => 1, widthad_b => 6, numwords_b => 34, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq, address_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa, data_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia ); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg(DELAY,979) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q, xout => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --fracRPostExc1_uid89_fpSinPiTest(MUX,88)@41 fracRPostExc1_uid89_fpSinPiTest_s <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q; fracRPostExc1_uid89_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE fracRPostExc1_uid89_fpSinPiTest_s IS WHEN "0" => fracRPostExc1_uid89_fpSinPiTest_q <= fracRComp_uid78_fpSinPiTest_b; WHEN "1" => fracRPostExc1_uid89_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q; WHEN OTHERS => fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor(LOGICAL,1002) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q <= not (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a or ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top(CONSTANT,998) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q <= "0100110"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp(LOGICAL,999) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q <= "1" when ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a = ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b else "0"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg(REG,1000) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena(REG,1003) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q = "1") THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd(LOGICAL,1004) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a and ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg(DELAY,992) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q, xout => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q, clk => clk, aclr => areset ); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt(COUNTER,994) -- every=1, low=0, high=38, step=1, init=1 ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i = 37 THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i - 38; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg(REG,995) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux(MUX,996) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux: PROCESS (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem(DUALMEM,993) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 39, width_b => 1, widthad_b => 6, numwords_b => 39, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq, address_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa, data_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia ); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq(0 downto 0); --fracRPostExc_uid91_fpSinPiTest(MUX,90)@42 fracRPostExc_uid91_fpSinPiTest_s <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q; fracRPostExc_uid91_fpSinPiTest: PROCESS (fracRPostExc_uid91_fpSinPiTest_s, fracRPostExc1_uid89_fpSinPiTest_q) BEGIN CASE fracRPostExc_uid91_fpSinPiTest_s IS WHEN "0" => fracRPostExc_uid91_fpSinPiTest_q <= fracRPostExc1_uid89_fpSinPiTest_q; WHEN "1" => fracRPostExc_uid91_fpSinPiTest_q <= oneFracRPostExc2_uid90_fpSinPiTest_q; WHEN OTHERS => fracRPostExc_uid91_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid105_fpSinPiTest(BITJOIN,104)@42 R_uid105_fpSinPiTest_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q & expRPostExc_uid98_fpSinPiTest_q & fracRPostExc_uid91_fpSinPiTest_q; --ld_xIn_v_to_xOut_v_nor(LOGICAL,910) ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b); --ld_xIn_v_to_xOut_v_mem_top(CONSTANT,906) ld_xIn_v_to_xOut_v_mem_top_q <= "0100111"; --ld_xIn_v_to_xOut_v_cmp(LOGICAL,907) ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q; ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q); ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0"; --ld_xIn_v_to_xOut_v_cmpReg(REG,908) ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_sticky_ena(REG,911) ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q; END IF; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,912) ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q; ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b; --ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,902) -- every=1, low=0, high=39, step=1, init=1 ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 38 THEN ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1'; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; END IF; IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 39; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,6)); --ld_xIn_v_to_xOut_v_replace_rdreg(REG,903) ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_replace_rdmux(MUX,904) ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q; ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q) BEGIN CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q; WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,914) ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset; ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c; ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 6, numwords_a => 40, width_b => 8, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_c_to_xOut_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_c_to_xOut_c_replace_mem_iq, address_a => ld_xIn_c_to_xOut_c_replace_mem_aa, data_a => ld_xIn_c_to_xOut_c_replace_mem_ia ); ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0); --ld_xIn_c_to_xOut_c_outputreg(DELAY,913) ld_xIn_c_to_xOut_c_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset ); --ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,901) ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset; ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v; ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 40, width_b => 1, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_v_to_xOut_v_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_v_to_xOut_v_replace_mem_iq, address_a => ld_xIn_v_to_xOut_v_replace_mem_aa, data_a => ld_xIn_v_to_xOut_v_replace_mem_ia ); ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0); --ld_xIn_v_to_xOut_v_outputreg(DELAY,900) ld_xIn_v_to_xOut_v_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset ); --xOut(PORTOUT,4)@42 xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q; xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q; xOut_0 <= R_uid105_fpSinPiTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Debug Version 12.0 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from SinPiDPStratixVf400 -- VHDL created on Wed Sep 05 17:55:57 2012 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; USE work.SinPiDPStratixVf400_safe_path.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; -- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240 entity SinPiDPStratixVf400 is port ( xIn_v : in std_logic_vector(0 downto 0); xIn_c : in std_logic_vector(7 downto 0); xIn_0 : in std_logic_vector(63 downto 0); xOut_v : out std_logic_vector(0 downto 0); xOut_c : out std_logic_vector(7 downto 0); xOut_0 : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic; bus_clk : in std_logic; h_areset : in std_logic ); end; architecture normal of SinPiDPStratixVf400 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBias_uid12_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBiasPwF_uid13_fpSinPiTest_q : std_logic_vector (10 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0); signal biasM1_uid27_fpSinPiTest_q : std_logic_vector (10 downto 0); signal biasMwShift_uid29_fpSinPiTest_q : std_logic_vector (10 downto 0); signal shiftBias_uid32_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cst01pWShift_uid34_fpSinPiTest_q : std_logic_vector (27 downto 0); signal ozz_uid41_fpSinPiTest_q : std_logic_vector (78 downto 0); signal cOne_uid44_fpSinPiTest_q : std_logic_vector (80 downto 0); signal oneMinusY_uid45_fpSinPiTest_a : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_b : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_o : std_logic_vector (81 downto 0); signal oneMinusY_uid45_fpSinPiTest_q : std_logic_vector (81 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_a : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_b : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_o : std_logic_vector (84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_c : std_logic_vector (0 downto 0); signal piwFP2_uid67_fpSinPiTest_q : std_logic_vector (53 downto 0); signal or_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_b : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_c : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_q : std_logic_vector (51 downto 0); signal oneFracRPostExc2_uid90_fpSinPiTest_q : std_logic_vector (51 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (10 downto 0); signal InvXIsInt_uid100_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIsInt_uid100_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (31 downto 0); signal leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (63 downto 0); signal leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (15 downto 0); signal leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (23 downto 0); signal leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (5 downto 0); signal mO_uid148_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (48 downto 0); signal memoryC3_uid229_sinPiZTableGenerator_q : std_logic_vector(34 downto 0); signal memoryC4_uid230_sinPiZTableGenerator_q : std_logic_vector(25 downto 0); signal memoryC5_uid231_sinPiZTableGenerator_q : std_logic_vector(16 downto 0); signal rndBit_uid246_sinPiZPolyEval_q : std_logic_vector (1 downto 0); signal rndBit_uid258_sinPiZPolyEval_q : std_logic_vector (2 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_a : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 : std_logic_vector (33 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr : SIGNED (34 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_q : std_logic_vector (33 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_a : std_logic_vector (25 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_zero_36_q : std_logic_vector (26 downto 0); type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type; signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q : std_logic_vector (36 downto 0); type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o : std_logic_vector (90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o : std_logic_vector (21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q : std_logic_vector (19 downto 0); signal reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q : std_logic_vector (80 downto 0); signal reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q : std_logic_vector (80 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q : std_logic_vector (0 downto 0); signal reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (31 downto 0); signal reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (15 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (7 downto 0); signal reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q : std_logic_vector (7 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q : std_logic_vector (7 downto 0); signal reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q : std_logic_vector (78 downto 0); signal reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q : std_logic_vector (16 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q : std_logic_vector (25 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q : std_logic_vector (16 downto 0); signal reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q : std_logic_vector (17 downto 0); signal reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q : std_logic_vector (36 downto 0); signal reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q : std_logic_vector (44 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q : std_logic_vector (45 downto 0); signal reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q : std_logic_vector (51 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q : std_logic_vector (53 downto 0); signal reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q : std_logic_vector (60 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q : std_logic_vector (26 downto 0); signal reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q : std_logic_vector (6 downto 0); signal reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q : std_logic_vector (78 downto 0); signal ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q : std_logic_vector (78 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q : std_logic_vector (78 downto 0); signal ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q : std_logic_vector (14 downto 0); signal ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (63 downto 0); signal ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (31 downto 0); signal ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (31 downto 0); signal ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (15 downto 0); signal ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (15 downto 0); signal ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q : std_logic_vector (0 downto 0); signal ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q : std_logic_vector (0 downto 0); signal ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (1 downto 0); signal ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (42 downto 0); signal ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q : std_logic_vector (88 downto 0); signal ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q : std_logic_vector (79 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic; signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic; signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic; signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 : std_logic; signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i : unsigned(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q : std_logic_vector (3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i : unsigned(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q : std_logic_vector (6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i : unsigned(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q : std_logic_vector (2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (14 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ir : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i : unsigned(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q : std_logic_vector (2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ir : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ir : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 : std_logic; signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ir : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0); signal yIsZero_uid40_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (18 downto 0); signal pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal z_uid49_fpSinPiTest_s : std_logic_vector (0 downto 0); signal z_uid49_fpSinPiTest_q : std_logic_vector (78 downto 0); signal expHardCase_uid57_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expHardCase_uid57_fpSinPiTest_q : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_q : std_logic_vector (11 downto 0); signal rndExpUpdate_uid75_uid76_fpSinPiTest_q : std_logic_vector (53 downto 0); signal expFracComp_uid77_fpSinPiTest_a : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_b : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_o : std_logic_vector (64 downto 0); signal expFracComp_uid77_fpSinPiTest_q : std_logic_vector (64 downto 0); signal fracRPostExc_uid91_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc_uid91_fpSinPiTest_q : std_logic_vector (51 downto 0); signal expRPostExc_uid98_fpSinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid98_fpSinPiTest_q : std_logic_vector (10 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal memoryC0_uid226_sinPiZTableGenerator_q : std_logic_vector(57 downto 0); signal memoryC1_uid227_sinPiZTableGenerator_q : std_logic_vector(49 downto 0); signal memoryC2_uid228_sinPiZTableGenerator_q : std_logic_vector(42 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_a : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_b : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_o : std_logic_vector (35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_q : std_logic_vector (35 downto 0); signal ts3_uid248_sinPiZPolyEval_a : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_b : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_o : std_logic_vector (45 downto 0); signal ts3_uid248_sinPiZPolyEval_q : std_logic_vector (45 downto 0); signal ts4_uid254_sinPiZPolyEval_a : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_b : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_o : std_logic_vector (52 downto 0); signal ts4_uid254_sinPiZPolyEval_q : std_logic_vector (52 downto 0); signal ts5_uid260_sinPiZPolyEval_a : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_b : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_o : std_logic_vector (61 downto 0); signal ts5_uid260_sinPiZPolyEval_q : std_logic_vector (61 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal join_uid42_fpSinPiTest_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal expX_uid6_fpSinPiTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSinPiTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSinPiTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSinPiTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0); signal expXIsMax_uid16_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSinPiTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid15_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_q : std_logic_vector(0 downto 0); signal xIntExp_uid26_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xIntExp_uid26_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xIntExp_uid26_fpSinPiTest_c : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xFrac_uid28_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_n : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_a : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_b : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_o : std_logic_vector (13 downto 0); signal sinXIsX_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0); signal shiftValue_uid33_fpSinPiTest_a : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_b : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_o : std_logic_vector (11 downto 0); signal shiftValue_uid33_fpSinPiTest_q : std_logic_vector (11 downto 0); signal oMyBottom_uid47_fpSinPiTest_in : std_logic_vector (78 downto 0); signal oMyBottom_uid47_fpSinPiTest_b : std_logic_vector (78 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid150_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal cIncludingRoundingBit_uid247_sinPiZPolyEval_q : std_logic_vector (44 downto 0); signal cIncludingRoundingBit_uid253_sinPiZPolyEval_q : std_logic_vector (51 downto 0); signal cIncludingRoundingBit_uid259_sinPiZPolyEval_q : std_logic_vector (60 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q : std_logic_vector (107 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (29 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (46 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q : std_logic_vector (108 downto 0); signal yIsZero_uid43_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zPPolyEval_uid64_fpSinPiTest_in : std_logic_vector (71 downto 0); signal zPPolyEval_uid64_fpSinPiTest_b : std_logic_vector (44 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_q : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_c : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (31 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (15 downto 0); signal s2_uid240_uid243_sinPiZPolyEval_q : std_logic_vector (36 downto 0); signal add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (55 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (42 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (72 downto 0); signal add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal R_uid105_fpSinPiTest_q : std_logic_vector (63 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal yT3_uid244_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT3_uid244_sinPiZPolyEval_b : std_logic_vector (34 downto 0); signal yT4_uid250_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT4_uid250_sinPiZPolyEval_b : std_logic_vector (42 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q : std_logic_vector(0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_b : std_logic_vector (26 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zAddr_uid63_fpSinPiTest_in : std_logic_vector (78 downto 0); signal zAddr_uid63_fpSinPiTest_b : std_logic_vector (6 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (78 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (63 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (14 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (14 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (46 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (46 downto 0); signal expHardCaseR_uid60_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expHardCaseR_uid60_fpSinPiTest_b : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracRComp_uid78_fpSinPiTest_in : std_logic_vector (52 downto 0); signal fracRComp_uid78_fpSinPiTest_b : std_logic_vector (51 downto 0); signal expRComp_uid79_fpSinPiTest_in : std_logic_vector (63 downto 0); signal expRComp_uid79_fpSinPiTest_b : std_logic_vector (10 downto 0); signal intXParity_uid38_fpSinPiTest_in : std_logic_vector (80 downto 0); signal intXParity_uid38_fpSinPiTest_b : std_logic_vector (0 downto 0); signal y_uid39_fpSinPiTest_in : std_logic_vector (79 downto 0); signal y_uid39_fpSinPiTest_b : std_logic_vector (79 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (77 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (77 downto 0); signal s3_uid249_sinPiZPolyEval_in : std_logic_vector (45 downto 0); signal s3_uid249_sinPiZPolyEval_b : std_logic_vector (44 downto 0); signal s4_uid255_sinPiZPolyEval_in : std_logic_vector (52 downto 0); signal s4_uid255_sinPiZPolyEval_b : std_logic_vector (51 downto 0); signal s5_uid261_sinPiZPolyEval_in : std_logic_vector (61 downto 0); signal s5_uid261_sinPiZPolyEval_b : std_logic_vector (60 downto 0); signal oFracX_uid31_uid31_fpSinPiTest_q : std_logic_vector (52 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_in : std_logic_vector (6 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_b : std_logic_vector (6 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid235_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal highBBits_uid235_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid241_sinPiZPolyEval_in : std_logic_vector (28 downto 0); signal highBBits_uid241_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q : std_logic_vector(107 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (29 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (46 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal normBit_uid70_fpSinPiTest_in : std_logic_vector (106 downto 0); signal normBit_uid70_fpSinPiTest_b : std_logic_vector (0 downto 0); signal highRes_uid71_fpSinPiTest_in : std_logic_vector (105 downto 0); signal highRes_uid71_fpSinPiTest_b : std_logic_vector (52 downto 0); signal lowRes_uid72_fpSinPiTest_in : std_logic_vector (104 downto 0); signal lowRes_uid72_fpSinPiTest_b : std_logic_vector (52 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (70 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (70 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (62 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (62 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (54 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (54 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q : std_logic_vector(0 downto 0); signal yT1_uid232_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT1_uid232_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal yT2_uid238_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT2_uid238_sinPiZPolyEval_b : std_logic_vector (25 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (63 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (9 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (9 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (36 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (71 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (45 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (78 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (7 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (7 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (15 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (15 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expP_uid61_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expP_uid61_fpSinPiTest_q : std_logic_vector (10 downto 0); signal yBottom_uid48_fpSinPiTest_in : std_logic_vector (78 downto 0); signal yBottom_uid48_fpSinPiTest_b : std_logic_vector (78 downto 0); signal leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (51 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal fxpSinRes_uid66_fpSinPiTest_in : std_logic_vector (58 downto 0); signal fxpSinRes_uid66_fpSinPiTest_b : std_logic_vector (53 downto 0); signal extendedFracX_uid35_fpSinPiTest_q : std_logic_vector (80 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (0 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_a : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_b : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_o : std_logic_vector (26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q : std_logic_vector(107 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_q : std_logic_vector (52 downto 0); signal join_uid97_fpSinPiTest_q : std_logic_vector (1 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal signR_uid104_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (10 downto 0); signal pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (16 downto 0); signal pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal xIsInt_uid83_fpSinPiTest_a : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_b : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal multRightOp_uid68_fpSinPiTest_s : std_logic_vector (0 downto 0); signal multRightOp_uid68_fpSinPiTest_q : std_logic_vector (53 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (48 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (48 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (16 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (16 downto 0); signal s1_uid234_uid237_sinPiZPolyEval_q : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c : std_logic_vector (19 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in : std_logic_vector (106 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b : std_logic_vector (106 downto 0); signal expFracPreRnd_uid74_uid74_fpSinPiTest_q : std_logic_vector (63 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (17 downto 0); signal alignedZLow_uid53_fpSinPiTest_in : std_logic_vector (78 downto 0); signal alignedZLow_uid53_fpSinPiTest_b : std_logic_vector (51 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_b : std_logic_vector (26 downto 0); signal leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q : std_logic_vector (107 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (1 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (74 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (72 downto 0); signal pHardCase_uid54_fpSinPiTest_q : std_logic_vector (52 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q : std_logic_vector (108 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (0 downto 0); signal leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal p_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0); signal p_uid55_fpSinPiTest_q : std_logic_vector (52 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (72 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (64 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (64 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (56 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (56 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c : std_logic_vector (19 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal r_uid186_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (6 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (0 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (78 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (78 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (74 downto 0); signal leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (79 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (79 downto 0); signal leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); begin --ld_xIn_v_to_xOut_v_notEnable(LOGICAL,909) ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q; ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor(LOGICAL,1028) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q <= not (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a or ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top(CONSTANT,1024) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q <= "0100100"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp(LOGICAL,1025) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q <= "1" when ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a = ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b else "0"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg(REG,1026) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena(REG,1029) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q = "1") THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd(LOGICAL,1030) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a and ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b; --LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest(BITSELECT,134)@0 LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest(CONSTANT,133) leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q <= "000000"; --leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest(BITJOIN,135)@0 leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest(BITSELECT,131)@0 LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest(CONSTANT,130) leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q <= "0000"; --leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest(BITJOIN,132)@0 leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest(BITSELECT,128)@0 LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(78 downto 0); LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in(78 downto 0); --leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest(CONSTANT,127) leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q <= "00"; --leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest(BITJOIN,129)@0 leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest(BITSELECT,123)@0 LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(56 downto 0); LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in(56 downto 0); --leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest(CONSTANT,122) leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000"; --leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest(BITJOIN,124)@0 leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest(BITSELECT,120)@0 LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(64 downto 0); LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in(64 downto 0); --leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest(CONSTANT,119) leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000"; --leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest(BITJOIN,121)@0 leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest(BITSELECT,117)@0 LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(72 downto 0); LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in(72 downto 0); --leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest(CONSTANT,116) leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q <= "00000000"; --leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest(BITJOIN,118)@0 leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest(CONSTANT,113) leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; --X16dto0_uid112_fixedPointX_uid37_fpSinPiTest(BITSELECT,111)@0 X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(16 downto 0); X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in(16 downto 0); --leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest(CONSTANT,110) leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000"; --leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest(BITJOIN,112)@0 leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X48dto0_uid109_fixedPointX_uid37_fpSinPiTest(BITSELECT,108)@0 X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(48 downto 0); X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in(48 downto 0); --leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest(CONSTANT,107) leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q <= "00000000000000000000000000000000"; --leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest(BITJOIN,109)@0 leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --cst01pWShift_uid34_fpSinPiTest(CONSTANT,33) cst01pWShift_uid34_fpSinPiTest_q <= "0000000000000000000000000000"; --xIn(PORTIN,3)@0 --fracX_uid7_fpSinPiTest(BITSELECT,6)@0 fracX_uid7_fpSinPiTest_in <= xIn_0(51 downto 0); fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(51 downto 0); --oFracX_uid31_uid31_fpSinPiTest(BITJOIN,30)@0 oFracX_uid31_uid31_fpSinPiTest_q <= VCC_q & fracX_uid7_fpSinPiTest_b; --extendedFracX_uid35_fpSinPiTest(BITJOIN,34)@0 extendedFracX_uid35_fpSinPiTest_q <= cst01pWShift_uid34_fpSinPiTest_q & oFracX_uid31_uid31_fpSinPiTest_q; --shiftBias_uid32_fpSinPiTest(CONSTANT,31) shiftBias_uid32_fpSinPiTest_q <= "01111100011"; --expX_uid6_fpSinPiTest(BITSELECT,5)@0 expX_uid6_fpSinPiTest_in <= xIn_0(62 downto 0); expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(62 downto 52); --shiftValue_uid33_fpSinPiTest(SUB,32)@0 shiftValue_uid33_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b); shiftValue_uid33_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid32_fpSinPiTest_q); shiftValue_uid33_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid33_fpSinPiTest_a) - UNSIGNED(shiftValue_uid33_fpSinPiTest_b)); shiftValue_uid33_fpSinPiTest_q <= shiftValue_uid33_fpSinPiTest_o(11 downto 0); --fxpShifterBits_uid36_fpSinPiTest(BITSELECT,35)@0 fxpShifterBits_uid36_fpSinPiTest_in <= shiftValue_uid33_fpSinPiTest_q(6 downto 0); fxpShifterBits_uid36_fpSinPiTest_b <= fxpShifterBits_uid36_fpSinPiTest_in(6 downto 0); --leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest(BITSELECT,114)@0 leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b; leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in(6 downto 5); --leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest(MUX,115)@0 leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s, extendedFracX_uid35_fpSinPiTest_q, leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= extendedFracX_uid35_fpSinPiTest_q; WHEN "01" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest(BITSELECT,125)@0 leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(4 downto 0); leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in(4 downto 3); --leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest(MUX,126)@0 leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest(BITSELECT,136)@0 leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(2 downto 0); leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in(2 downto 1); --leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest(MUX,137)@0 leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest(BITSELECT,139)@0 LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in(79 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest(BITJOIN,140)@0 leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b & GND_q; --reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3(REG,357)@0 reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2(REG,358)@0 reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest(BITSELECT,141)@0 leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(0 downto 0); leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in(0 downto 0); --ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b(DELAY,581)@0 ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest(MUX,142)@1 leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q; leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s, reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q, reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q) BEGIN CASE leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q; WHEN "1" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q; WHEN OTHERS => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --intXParity_uid38_fpSinPiTest(BITSELECT,37)@1 intXParity_uid38_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q; intXParity_uid38_fpSinPiTest_b <= intXParity_uid38_fpSinPiTest_in(80 downto 80); --ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c(DELAY,536)@1 ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => intXParity_uid38_fpSinPiTest_b, xout => ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q, clk => clk, aclr => areset ); --biasM1_uid27_fpSinPiTest(CONSTANT,26) biasM1_uid27_fpSinPiTest_q <= "01111111110"; --xFrac_uid28_fpSinPiTest(COMPARE,27)@0 xFrac_uid28_fpSinPiTest_cin <= GND_q; xFrac_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid27_fpSinPiTest_q) & '0'; xFrac_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid28_fpSinPiTest_cin(0); xFrac_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid28_fpSinPiTest_a) - UNSIGNED(xFrac_uid28_fpSinPiTest_b)); xFrac_uid28_fpSinPiTest_n(0) <= not xFrac_uid28_fpSinPiTest_o(13); --ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a(DELAY,532)@0 ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => xFrac_uid28_fpSinPiTest_n, xout => ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvXFrac_uid99_fpSinPiTest(LOGICAL,98)@3 InvXFrac_uid99_fpSinPiTest_a <= ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q; InvXFrac_uid99_fpSinPiTest_q <= not InvXFrac_uid99_fpSinPiTest_a; --biasMwShift_uid29_fpSinPiTest(CONSTANT,28) biasMwShift_uid29_fpSinPiTest_q <= "01111100100"; --sinXIsX_uid30_fpSinPiTest(COMPARE,29)@0 sinXIsX_uid30_fpSinPiTest_cin <= GND_q; sinXIsX_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0'; sinXIsX_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid29_fpSinPiTest_q) & sinXIsX_uid30_fpSinPiTest_cin(0); sinXIsX_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid30_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid30_fpSinPiTest_b)); sinXIsX_uid30_fpSinPiTest_c(0) <= sinXIsX_uid30_fpSinPiTest_o(13); --ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a(DELAY,502)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvSinXIsX_uid80_fpSinPiTest(LOGICAL,79)@2 InvSinXIsX_uid80_fpSinPiTest_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q; InvSinXIsX_uid80_fpSinPiTest_q <= not InvSinXIsX_uid80_fpSinPiTest_a; --y_uid39_fpSinPiTest(BITSELECT,38)@1 y_uid39_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); y_uid39_fpSinPiTest_b <= y_uid39_fpSinPiTest_in(79 downto 0); --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0(REG,360)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid40_fpSinPiTest(LOGICAL,39)@2 yIsZero_uid40_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q; yIsZero_uid40_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000000000000000000000000000000000000000000000000" & GND_q); yIsZero_uid40_fpSinPiTest_q <= "1" when yIsZero_uid40_fpSinPiTest_a = yIsZero_uid40_fpSinPiTest_b else "0"; --And2YIsZeroInvSinXIsX_uid81_fpSinPiTest(LOGICAL,80)@2 And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a <= yIsZero_uid40_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b <= InvSinXIsX_uid80_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a and And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b; --cstBiasPwF_uid13_fpSinPiTest(CONSTANT,12) cstBiasPwF_uid13_fpSinPiTest_q <= "10000110011"; --xIntExp_uid26_fpSinPiTest(COMPARE,25)@0 xIntExp_uid26_fpSinPiTest_cin <= GND_q; xIntExp_uid26_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid13_fpSinPiTest_q) & '0'; xIntExp_uid26_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid26_fpSinPiTest_cin(0); xIntExp_uid26_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid26_fpSinPiTest_a) - UNSIGNED(xIntExp_uid26_fpSinPiTest_b)); xIntExp_uid26_fpSinPiTest_c(0) <= xIntExp_uid26_fpSinPiTest_o(13); --ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a(DELAY,505)@0 ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => xIntExp_uid26_fpSinPiTest_c, xout => ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q, clk => clk, aclr => areset ); --Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest(LOGICAL,81)@2 Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a or Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b; --cstAllZWF_uid10_fpSinPiTest(CONSTANT,9) cstAllZWF_uid10_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracXIsZero_uid17_fpSinPiTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b; fracXIsZero_uid17_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q; fracXIsZero_uid17_fpSinPiTest_q <= "1" when fracXIsZero_uid17_fpSinPiTest_a = fracXIsZero_uid17_fpSinPiTest_b else "0"; --ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a(DELAY,442)@0 ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => fracXIsZero_uid17_fpSinPiTest_q, xout => ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvFracXIsZero_uid19_fpSinPiTest(LOGICAL,18)@1 InvFracXIsZero_uid19_fpSinPiTest_a <= ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q; InvFracXIsZero_uid19_fpSinPiTest_q <= not InvFracXIsZero_uid19_fpSinPiTest_a; --cstAllOWE_uid9_fpSinPiTest(CONSTANT,8) cstAllOWE_uid9_fpSinPiTest_q <= "11111111111"; --expXIsMax_uid16_fpSinPiTest(LOGICAL,15)@0 expXIsMax_uid16_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsMax_uid16_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q; expXIsMax_uid16_fpSinPiTest_q <= "1" when expXIsMax_uid16_fpSinPiTest_a = expXIsMax_uid16_fpSinPiTest_b else "0"; --ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a(DELAY,443)@0 ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsMax_uid16_fpSinPiTest_q, xout => ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest(LOGICAL,19)@1 And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a <= ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b <= InvFracXIsZero_uid19_fpSinPiTest_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a and And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b; --InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest(LOGICAL,20)@1 InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q <= not InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a; --And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0 And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a <= expXIsMax_uid16_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b <= fracXIsZero_uid17_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a and And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b; --InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0 InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q; InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q <= not InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a; --cstAllZWE_uid11_fpSinPiTest(CONSTANT,10) cstAllZWE_uid11_fpSinPiTest_q <= "00000000000"; --expXIsZero_uid15_fpSinPiTest(LOGICAL,14)@0 expXIsZero_uid15_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsZero_uid15_fpSinPiTest_b <= cstAllZWE_uid11_fpSinPiTest_q; expXIsZero_uid15_fpSinPiTest_q <= "1" when expXIsZero_uid15_fpSinPiTest_a = expXIsZero_uid15_fpSinPiTest_b else "0"; --InvExpXIsZero_uid23_fpSinPiTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSinPiTest_a <= expXIsZero_uid15_fpSinPiTest_q; InvExpXIsZero_uid23_fpSinPiTest_q <= not InvExpXIsZero_uid23_fpSinPiTest_a; --And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0 And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a <= InvExpXIsZero_uid23_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b <= InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a and And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b; --ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a(DELAY,450)@0 ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q, xout => ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest(LOGICAL,24)@1 And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a <= ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b <= InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a and And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b; END IF; END PROCESS; --xIsInt_uid83_fpSinPiTest(LOGICAL,82)@2 xIsInt_uid83_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_b <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_q <= xIsInt_uid83_fpSinPiTest_a and xIsInt_uid83_fpSinPiTest_b; --InvXIsInt_uid100_fpSinPiTest(LOGICAL,99)@2 InvXIsInt_uid100_fpSinPiTest_a <= xIsInt_uid83_fpSinPiTest_q; InvXIsInt_uid100_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= not InvXIsInt_uid100_fpSinPiTest_a; END IF; END PROCESS; --signComp_uid101_fpSinPiTest(LOGICAL,100)@3 signComp_uid101_fpSinPiTest_a <= InvXIsInt_uid100_fpSinPiTest_q; signComp_uid101_fpSinPiTest_b <= InvXFrac_uid99_fpSinPiTest_q; signComp_uid101_fpSinPiTest_c <= ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q; signComp_uid101_fpSinPiTest_q <= signComp_uid101_fpSinPiTest_a and signComp_uid101_fpSinPiTest_b and signComp_uid101_fpSinPiTest_c; --ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a(DELAY,537)@2 ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => yIsZero_uid40_fpSinPiTest_q, xout => ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvYIsZero_uid102_fpSinPiTest(LOGICAL,101)@3 InvYIsZero_uid102_fpSinPiTest_a <= ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q; InvYIsZero_uid102_fpSinPiTest_q <= not InvYIsZero_uid102_fpSinPiTest_a; --And2InvYIsZeroSignComp_uid103_fpSinPiTest(LOGICAL,102)@3 And2InvYIsZeroSignComp_uid103_fpSinPiTest_a <= InvYIsZero_uid102_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_b <= signComp_uid101_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_q <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_a and And2InvYIsZeroSignComp_uid103_fpSinPiTest_b; --signX_uid8_fpSinPiTest(BITSELECT,7)@0 signX_uid8_fpSinPiTest_in <= xIn_0; signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(63 downto 63); --ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a(DELAY,540)@0 ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q, clk => clk, aclr => areset ); --signR_uid104_fpSinPiTest(LOGICAL,103)@3 signR_uid104_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q; signR_uid104_fpSinPiTest_b <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_q; signR_uid104_fpSinPiTest_q <= signR_uid104_fpSinPiTest_a xor signR_uid104_fpSinPiTest_b; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt(COUNTER,1020) -- every=1, low=0, high=36, step=1, init=1 ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i = 35 THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i - 36; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i,6)); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg(REG,1021) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --VCC(CONSTANT,1) VCC_q <= "1"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux(MUX,1022) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux: PROCESS (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem(DUALMEM,1019) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia <= signR_uid104_fpSinPiTest_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 37, width_b => 1, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq, address_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa, data_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia ); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq(0 downto 0); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg(DELAY,1018) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q, xout => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --cstBias_uid12_fpSinPiTest(CONSTANT,11) cstBias_uid12_fpSinPiTest_q <= "01111111111"; --piwFP2_uid67_fpSinPiTest(CONSTANT,66) piwFP2_uid67_fpSinPiTest_q <= "110010010000111111011010101000100010000101101000110001"; --reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1(REG,363)@1 reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --cOne_uid44_fpSinPiTest(CONSTANT,43) cOne_uid44_fpSinPiTest_q <= "100000000000000000000000000000000000000000000000000000000000000000000000000000000"; --oneMinusY_uid45_fpSinPiTest(SUB,44)@2 oneMinusY_uid45_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid44_fpSinPiTest_q); oneMinusY_uid45_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q); oneMinusY_uid45_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid45_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid45_fpSinPiTest_b)); END IF; END PROCESS; oneMinusY_uid45_fpSinPiTest_q <= oneMinusY_uid45_fpSinPiTest_o(81 downto 0); --oMyBottom_uid47_fpSinPiTest(BITSELECT,46)@3 oMyBottom_uid47_fpSinPiTest_in <= oneMinusY_uid45_fpSinPiTest_q(78 downto 0); oMyBottom_uid47_fpSinPiTest_b <= oMyBottom_uid47_fpSinPiTest_in(78 downto 0); --ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d(DELAY,471)@3 ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => oMyBottom_uid47_fpSinPiTest_b, xout => ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q, clk => clk, aclr => areset ); --yBottom_uid48_fpSinPiTest(BITSELECT,47)@1 yBottom_uid48_fpSinPiTest_in <= y_uid39_fpSinPiTest_b(78 downto 0); yBottom_uid48_fpSinPiTest_b <= yBottom_uid48_fpSinPiTest_in(78 downto 0); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c(DELAY,470)@1 ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 79, depth => 2 ) PORT MAP ( xin => yBottom_uid48_fpSinPiTest_b, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg(DELAY,926) ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a(DELAY,833)@1 ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a : dspba_delay GENERIC MAP ( width => 80, depth => 1 ) PORT MAP ( xin => y_uid39_fpSinPiTest_b, xout => ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q, clk => clk, aclr => areset ); --reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1(REG,364)@2 reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q; END IF; END PROCESS; --cmpYToOneMinusY_uid46_fpSinPiTest(COMPARE,45)@3 cmpYToOneMinusY_uid46_fpSinPiTest_cin <= GND_q; cmpYToOneMinusY_uid46_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & oneMinusY_uid45_fpSinPiTest_q) & '0'; cmpYToOneMinusY_uid46_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q) & cmpYToOneMinusY_uid46_fpSinPiTest_cin(0); cmpYToOneMinusY_uid46_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_b)); END IF; END PROCESS; cmpYToOneMinusY_uid46_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid46_fpSinPiTest_o(84); --z_uid49_fpSinPiTest(MUX,48)@4 z_uid49_fpSinPiTest_s <= cmpYToOneMinusY_uid46_fpSinPiTest_c; z_uid49_fpSinPiTest: PROCESS (z_uid49_fpSinPiTest_s, ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q) BEGIN CASE z_uid49_fpSinPiTest_s IS WHEN "0" => z_uid49_fpSinPiTest_q <= ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q; WHEN "1" => z_uid49_fpSinPiTest_q <= ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q; WHEN OTHERS => z_uid49_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --zAddr_uid63_fpSinPiTest(BITSELECT,62)@4 zAddr_uid63_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; zAddr_uid63_fpSinPiTest_b <= zAddr_uid63_fpSinPiTest_in(78 downto 72); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0(REG,382)@4 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= zAddr_uid63_fpSinPiTest_b; END IF; END PROCESS; --memoryC5_uid231_sinPiZTableGenerator(LOOKUP,230)@5 memoryC5_uid231_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; WHEN "0000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111110101101000"; WHEN "0000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111101101011101"; WHEN "0000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100110001110"; WHEN "0000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100000000010"; WHEN "0000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111011000000000"; WHEN "0000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111010001101101"; WHEN "0000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111001010010111"; WHEN "0001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111000010110010"; WHEN "0001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110111100010100"; WHEN "0001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110110100011111"; WHEN "0001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110101100101101"; WHEN "0001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110100101101011"; WHEN "0001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110011111011101"; WHEN "0001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010111001010"; WHEN "0001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010001011011"; WHEN "0010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110001010101011"; WHEN "0010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110000011011001"; WHEN "0010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101111011000001"; WHEN "0010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101110101001010"; WHEN "0010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101101110100110"; WHEN "0010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101100111100011"; WHEN "0010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011111111111"; WHEN "0010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011001001010"; WHEN "0011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101010010100110"; WHEN "0011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101001010011011"; WHEN "0011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101000100011100"; WHEN "0011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100111101010110"; WHEN "0011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100110110111000"; WHEN "0011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100101111110010"; WHEN "0011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100111110010"; WHEN "0011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100001010101"; WHEN "0100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100011011011111"; WHEN "0100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100010011110111"; WHEN "0100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100001110001010"; WHEN "0100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100000111000100"; WHEN "0100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111111110101"; WHEN "0100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111001010110"; WHEN "0100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011110011000111"; WHEN "0100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011101101000000"; WHEN "0101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011100110000011"; WHEN "0101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011111111001"; WHEN "0101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011000100110"; WHEN "0101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011010010101100"; WHEN "0101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011001100010010"; WHEN "0101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011000101010111"; WHEN "0101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111111101010"; WHEN "0101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111001010000"; WHEN "0110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010110011010011"; WHEN "0110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010101100101011"; WHEN "0110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010100110111110"; WHEN "0110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011111111000"; WHEN "0110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011010110010"; WHEN "0110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010010101001110"; WHEN "0110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001110010011"; WHEN "0110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001000111011"; WHEN "0111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010000001111011"; WHEN "0111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001111011111110"; WHEN "0111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110111001010"; WHEN "0111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110001110111"; WHEN "0111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001101011000100"; WHEN "0111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100101010010"; WHEN "0111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100000011111"; WHEN "0111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001011010001010"; WHEN "1000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001010100111110"; WHEN "1000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001110110010"; WHEN "1000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001010111000"; WHEN "1000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001000100111111"; WHEN "1000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111111001100"; WHEN "1000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111010001001"; WHEN "1000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110101010110"; WHEN "1000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110000011101"; WHEN "1001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000101001110100"; WHEN "1001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000100101111001"; WHEN "1001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011111111010"; WHEN "1001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011011110110"; WHEN "1001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010110001100"; WHEN "1001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010001001000"; WHEN "1001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001101111001"; WHEN "1001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001000000111"; WHEN "1010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000000010111001"; WHEN "1010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111110110110"; WHEN "1010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111001111111"; WHEN "1010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110110010100"; WHEN "1010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110001011000"; WHEN "1010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101100010111"; WHEN "1010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101000010010"; WHEN "1010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100100010000"; WHEN "1011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100000111100"; WHEN "1011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111011011111111"; WHEN "1011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010111100000"; WHEN "1011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010011110100"; WHEN "1011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010000011100"; WHEN "1011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111001011011110"; WHEN "1011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000111111101"; WHEN "1011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000100101011"; WHEN "1100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000001100100"; WHEN "1100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111101101110"; WHEN "1100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111010011000"; WHEN "1100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110110110000"; WHEN "1100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110010011010"; WHEN "1100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110000011110"; WHEN "1100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101100101100"; WHEN "1100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101000101110"; WHEN "1101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100110100000"; WHEN "1101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100100010001"; WHEN "1101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100001000000"; WHEN "1101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011101101110"; WHEN "1101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011011011111"; WHEN "1101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010111000100"; WHEN "1101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010101110011"; WHEN "1101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010001111100"; WHEN "1110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010000001111"; WHEN "1110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001110011001"; WHEN "1110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001010100010"; WHEN "1110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000111111000"; WHEN "1110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101110110"; WHEN "1110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101000100"; WHEN "1110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000010100010"; WHEN "1110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111111110011"; WHEN "1111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111110010000"; WHEN "1111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111100110111"; WHEN "1111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111010111000"; WHEN "1111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111000101000"; WHEN "1111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110110110100"; WHEN "1111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110101011010"; WHEN "1111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110100000011"; WHEN "1111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110010001011"; WHEN OTHERS => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; END CASE; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a(DELAY,485)@4 ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => z_uid49_fpSinPiTest_q, xout => ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q, clk => clk, aclr => areset ); --zPPolyEval_uid64_fpSinPiTest(BITSELECT,63)@5 zPPolyEval_uid64_fpSinPiTest_in <= ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q(71 downto 0); zPPolyEval_uid64_fpSinPiTest_b <= zPPolyEval_uid64_fpSinPiTest_in(71 downto 27); --yT1_uid232_sinPiZPolyEval(BITSELECT,231)@5 yT1_uid232_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT1_uid232_sinPiZPolyEval_b <= yT1_uid232_sinPiZPolyEval_in(44 downto 28); --reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0(REG,383)@5 reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= yT1_uid232_sinPiZPolyEval_b; END IF; END PROCESS; --prodXY_uid263_pT1_uid233_sinPiZPolyEval(MULT,262)@6 prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_a),18)) * SIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_b); prodXY_uid263_pT1_uid233_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= memoryC5_uid231_sinPiZTableGenerator_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr,34)); END IF; END PROCESS; prodXY_uid263_pT1_uid233_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval(BITSELECT,263)@9 prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_q; prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in(33 downto 16); --highBBits_uid235_sinPiZPolyEval(BITSELECT,234)@9 highBBits_uid235_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b; highBBits_uid235_sinPiZPolyEval_b <= highBBits_uid235_sinPiZPolyEval_in(17 downto 1); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a(DELAY,853)@4 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a : dspba_delay GENERIC MAP ( width => 7, depth => 3 ) PORT MAP ( xin => zAddr_uid63_fpSinPiTest_b, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0(REG,384)@7 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q; END IF; END PROCESS; --memoryC4_uid230_sinPiZTableGenerator(LOOKUP,229)@8 memoryC4_uid230_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; WHEN "0000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110011111111100"; WHEN "0000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100101101100110011"; WHEN "0000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100100010011000101"; WHEN "0000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100010010010010110"; WHEN "0000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011111110011000100"; WHEN "0000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011100101011001100"; WHEN "0000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011001000001111000"; WHEN "0001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010100110101100100"; WHEN "0001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010000000010110001"; WHEN "0001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001001010101111100100"; WHEN "0001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001000100111000100010"; WHEN "0001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000111110011011110101"; WHEN "0001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000110111011001010101"; WHEN "0001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000101111111000110001"; WHEN "0001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000100111101101111110"; WHEN "0010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000011111000010010110"; WHEN "0010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000010101110100101111"; WHEN "0010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000001100000110110101"; WHEN "0010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000000001101111000000"; WHEN "0010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111110110110101110011"; WHEN "0010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111101011011010111001"; WHEN "0010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111011111011110000110"; WHEN "0010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111010010111100110100"; WHEN "0011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111000101110111111001"; WHEN "0011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110111000010100011101"; WHEN "0011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110101010001000110011"; WHEN "0011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110011011011101100111"; WHEN "0011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110001100001110001111"; WHEN "0011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101111100011110001010"; WHEN "0011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101101100001110100101"; WHEN "0011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101011011011000110110"; WHEN "0100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101001001111111101110"; WHEN "0100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100111000001001001111"; WHEN "0100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100100101101100011001"; WHEN "0100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100010010110001110000"; WHEN "0100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011111111010101110110"; WHEN "0100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011101011010111000111"; WHEN "0100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011010110110110011110"; WHEN "0100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011000001110100011110"; WHEN "0101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010101100010100010011"; WHEN "0101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010010110010001000111"; WHEN "0101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001111111110001000100"; WHEN "0101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001101000101100110110"; WHEN "0101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001010001001001111011"; WHEN "0101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000111001001000001110"; WHEN "0101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000100000100011110110"; WHEN "0101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000000111100001111001"; WHEN "0110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111101101111111011111"; WHEN "0110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111010011111111100110"; WHEN "0110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110111001011110100100"; WHEN "0110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110011110100010000111"; WHEN "0110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110000011000010001001"; WHEN "0110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101100111000101000011"; WHEN "0110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101001010101101011111"; WHEN "0110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100101101110011101110"; WHEN "0111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100010000100000111110"; WHEN "0111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011110010101101110100"; WHEN "0111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011010100011010011110"; WHEN "0111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010110101101011010111"; WHEN "0111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010010110100011011101"; WHEN "0111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001110110111100001001"; WHEN "0111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001010110110110010000"; WHEN "0111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000110110011000001101"; WHEN "1000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000010101011011011001"; WHEN "1000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111110100000101110010"; WHEN "1000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111010010001110101001"; WHEN "1000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110110000000001101011"; WHEN "1000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110001101011001110011"; WHEN "1000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101101010010101011101"; WHEN "1000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101000110110101111111"; WHEN "1000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111100100010111100111100"; WHEN "1001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011111110101110100100"; WHEN "1001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011011001111111110100"; WHEN "1001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010110100111101000111"; WHEN "1001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010001111011100101001"; WHEN "1001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001101001100111100001"; WHEN "1001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001000011011000101011"; WHEN "1001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111000011100101100110010"; WHEN "1001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111110101110000000011"; WHEN "1010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111001110011001111101"; WHEN "1010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110110100110101001110001"; WHEN "1010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101111110100101001011"; WHEN "1010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101010110000110010110"; WHEN "1010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100101101010100111010"; WHEN "1010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100000100001101101101"; WHEN "1010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110011011010101110011000"; WHEN "1010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010110000111001010011"; WHEN "1011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010000110101101010010"; WHEN "1011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110001011100010001000010"; WHEN "1011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000110001011111001110"; WHEN "1011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000000110010110110100"; WHEN "1011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101111011010111010001000"; WHEN "1011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110101111001110001011"; WHEN "1011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110000011001011001100"; WHEN "1011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101101010110110100111111"; WHEN "1100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101100101010001011011001"; WHEN "1100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011111101010010000000"; WHEN "1100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011010000000101001000"; WHEN "1100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101010100010100111110111"; WHEN "1100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001110100111011010110"; WHEN "1100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001000110110111101100"; WHEN "1100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101000011000101000001000"; WHEN "1100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100111101010001001010101"; WHEN "1101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110111011010110000011"; WHEN "1101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110001100010011011010"; WHEN "1101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100101011101000100011001"; WHEN "1101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100100101101100110100111"; WHEN "1101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011111101110111111010"; WHEN "1101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011001110000000101100"; WHEN "1101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100010011101110011110101"; WHEN "1101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100001101101100000010000"; WHEN "1110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000111100111010001011"; WHEN "1110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000001100000111111010"; WHEN "1110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011111011011001110101000"; WHEN "1110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011110101010000110010111"; WHEN "1110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101111000110001000001"; WHEN "1110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101000111001101001001"; WHEN "1110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011100010101100011001010"; WHEN "1110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011011100011101111010110"; WHEN "1111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011010110001101110011110"; WHEN "1111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001111111100011010111"; WHEN "1111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001001101010000100101"; WHEN "1111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011000011010110101101110"; WHEN "1111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010111101000010001000000"; WHEN "1111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110110101100011000101"; WHEN "1111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110000010101101010111"; WHEN "1111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010101001111110001011010"; WHEN OTHERS => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; END CASE; END IF; END PROCESS; --sumAHighB_uid236_sinPiZPolyEval(ADD,235)@9 sumAHighB_uid236_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((26 downto 26 => memoryC4_uid230_sinPiZTableGenerator_q(25)) & memoryC4_uid230_sinPiZTableGenerator_q); sumAHighB_uid236_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((26 downto 17 => highBBits_uid235_sinPiZPolyEval_b(16)) & highBBits_uid235_sinPiZPolyEval_b); sumAHighB_uid236_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid236_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid236_sinPiZPolyEval_b)); sumAHighB_uid236_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_o(26 downto 0); --lowRangeB_uid234_sinPiZPolyEval(BITSELECT,233)@9 lowRangeB_uid234_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid234_sinPiZPolyEval_b <= lowRangeB_uid234_sinPiZPolyEval_in(0 downto 0); --s1_uid234_uid237_sinPiZPolyEval(BITJOIN,236)@9 s1_uid234_uid237_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_q & lowRangeB_uid234_sinPiZPolyEval_b; --reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1(REG,385)@9 reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= s1_uid234_uid237_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor(LOGICAL,1179) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q <= not (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a or ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg(REG,1177) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= VCC_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena(REG,1180) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q = "1") THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd(LOGICAL,1181) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a and ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b; --yT2_uid238_sinPiZPolyEval(BITSELECT,237)@5 yT2_uid238_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT2_uid238_sinPiZPolyEval_b <= yT2_uid238_sinPiZPolyEval_in(44 downto 19); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt(COUNTER,1173) -- every=1, low=0, high=1, step=1, init=1 ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i + 1; END IF; END PROCESS; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i,1)); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg(REG,1174) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux(MUX,1175) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q) BEGIN CASE ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s IS WHEN "0" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; WHEN "1" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem(DUALMEM,1172) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia <= yT2_uid238_sinPiZPolyEval_b; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 26, widthad_a => 1, numwords_a => 2, width_b => 26, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq, address_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa, data_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia ); ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq(25 downto 0); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg(DELAY,1171) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q, xout => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0(REG,386)@9 reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q; END IF; END PROCESS; --prodXY_uid266_pT2_uid239_sinPiZPolyEval(MULT,265)@10 prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_a),27)) * SIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_b); prodXY_uid266_pT2_uid239_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr,54)); END IF; END PROCESS; prodXY_uid266_pT2_uid239_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval(BITSELECT,266)@13 prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_q; prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in(53 downto 25); --highBBits_uid241_sinPiZPolyEval(BITSELECT,240)@13 highBBits_uid241_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b; highBBits_uid241_sinPiZPolyEval_b <= highBBits_uid241_sinPiZPolyEval_in(28 downto 1); --reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1(REG,388)@13 reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= highBBits_uid241_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor(LOGICAL,1192) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1188) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q <= "0101"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp(LOGICAL,1189) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg(REG,1190) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena(REG,1193) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1194) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1184) -- every=1, low=0, high=5, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i = 4 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i - 5; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i,3)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg(REG,1185) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1186) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1183) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 3, numwords_a => 6, width_b => 7, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg(DELAY,1182) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0(REG,387)@12 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC3_uid229_sinPiZTableGenerator(LOOKUP,228)@13 memoryC3_uid229_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; WHEN "0000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000001010001100110101000111010101"; WHEN "0000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000010100011001100101101010110011"; WHEN "0000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000011110100110001101010100011011"; WHEN "0000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000101000110010100111100101110011"; WHEN "0000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000110010111110101111101101101000"; WHEN "0000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000111101001010100001100001001101"; WHEN "0000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001000111010101111000010100001000"; WHEN "0001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001010001100000101111101001011010"; WHEN "0001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001011011101011000011001000111110"; WHEN "0001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001100101110100101110001001110101"; WHEN "0001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001101111111101101100010100000001"; WHEN "0001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001111010000101111001001101010110"; WHEN "0001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010000100001101010000011000110101"; WHEN "0001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010001110010011101101001010101000"; WHEN "0001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010011000011001001011011101011111"; WHEN "0010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010100010011101100110100011101011"; WHEN "0010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010101100100000111010000011110001"; WHEN "0010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010110110100011000001011111010110"; WHEN "0010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011000000100011111000101110110101"; WHEN "0010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011001010100011011011001000001011"; WHEN "0010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011010100100001100100010010100101"; WHEN "0010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011011110011110001111110110101010"; WHEN "0010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011101000011001011001100000011011"; WHEN "0011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011110010010010111100111000010100"; WHEN "0011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011111100001010110101011110000110"; WHEN "0011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100000110000000111111001110100010"; WHEN "0011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100001111110101010101100100101101"; WHEN "0011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100011001100111110100010110001111"; WHEN "0011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100100011011000010111001001011111"; WHEN "0011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100101101000110111001101001101001"; WHEN "0011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100110110110011010111110011001100"; WHEN "0100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101000000011101101101010000100110"; WHEN "0100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101001010000101110101101000010110"; WHEN "0100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101010011101011101100111100100100"; WHEN "0100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101011101001111001110110000110010"; WHEN "0100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101100110110000010111000000110011"; WHEN "0100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101110000001111000001100011110100"; WHEN "0100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101111001101011001010010000000001"; WHEN "0100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110000011000100101100111100001110"; WHEN "0101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110001100011011100101011010100101"; WHEN "0101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110010101101111101111110000010101"; WHEN "0101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110011111000001000111101011101100"; WHEN "0101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110101000001111101001011001100010"; WHEN "0101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110110001011011010000101101010010"; WHEN "0101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110111010100011111001100111101100"; WHEN "0101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111000011101001100000010000100010"; WHEN "0101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111001100101100000000100001010000"; WHEN "0110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111010101101011010110100011101100"; WHEN "0110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111011110100111011110011000011110"; WHEN "0110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111100111100000010100001101010000"; WHEN "0110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111110000010101110100000001010000"; WHEN "0110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111111001000111111010001101010001"; WHEN "0110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000000001110110100010110001111010"; WHEN "0110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000001010100001101001110111110101"; WHEN "0110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000010011001001001011111110000001"; WHEN "0111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000011011101101000101000010101111"; WHEN "0111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000100100001101010001101000100100"; WHEN "0111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000101100101001101110000011010101"; WHEN "0111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000110101000010010110100001011010"; WHEN "0111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000111101010111000111010101011110"; WHEN "0111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001000101100111111101000110111000"; WHEN "0111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001001101110100110100001111001100"; WHEN "0111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001010101111101101001000001001010"; WHEN "1000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001011110000010011000001001000011"; WHEN "1000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001100110000010111101111101010011"; WHEN "1000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001101101111111010111010011001111"; WHEN "1000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001110101110111100000011010000110"; WHEN "1000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001111101101011010110000011010010"; WHEN "1000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010000101011010110100111100000101"; WHEN "1000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010001101000101111001101110100011"; WHEN "1000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010010100101100100001000101010010"; WHEN "1001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010011100001110100111101001010100"; WHEN "1001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010100011101100001010100001011100"; WHEN "1001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010101011000101000110001011100100"; WHEN "1001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010110010011001010111110000100100"; WHEN "1001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010111001101000111011111001000111"; WHEN "1001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000000110011101111101001011111"; WHEN "1001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000111111001110000000110011110"; WHEN "1001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011001110111010111001110111111110"; WHEN "1010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011010101110111001010010001110110"; WHEN "1010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011011100101110011110011000111101"; WHEN "1010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011100011100000110011001001001001"; WHEN "1010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011101010001110000101111000101100"; WHEN "1010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110000110110010011100011000111"; WHEN "1010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110111011001011001011101010011"; WHEN "1010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011111101110111010100111100011100"; WHEN "1010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100000100010000000011001111101101"; WHEN "1011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100001010100011100001101110011100"; WHEN "1011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010000110001101101100011100011"; WHEN "1011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010110111010100100010100000100"; WHEN "1011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100011100111110000011100000001010"; WHEN "1011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100100010111100001000100001101001"; WHEN "1011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101000110100110000110001111011"; WHEN "1011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101110100111111010000100111001"; WHEN "1011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100110100010101100001111010001101"; WHEN "1100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111001111101100101111101110000"; WHEN "1100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111111100000000011110011100101"; WHEN "1100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101000100111100111001010011110100"; WHEN "1100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001010010100000100001001001101"; WHEN "1100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001111100101100010000111001000"; WHEN "1100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101010100110001010001010100001101"; WHEN "1100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011001110111001111010101110101"; WHEN "1100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011110110111011010001101111010"; WHEN "1101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101100011110001110000000111001111"; WHEN "1101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101000100110001110111010010001"; WHEN "1101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101101010100110100100110101101"; WHEN "1101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110001111101011111011001010101"; WHEN "1101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110110100000001101100000100000"; WHEN "1101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111010111100111100111010111000"; WHEN "1101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111111010011101100010000110110"; WHEN "1101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000011100100011001011010100000"; WHEN "1110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000111101111000011000011110011"; WHEN "1110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001011110011100111011010000000"; WHEN "1110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001111110010000100101111100001"; WHEN "1110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010011101010011001110010000111"; WHEN "1110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010111011100100100111111111001"; WHEN "1110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011011001000100101000000101011"; WHEN "1110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011110101110011000001011101010"; WHEN "1110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100010001101111101010010100010"; WHEN "1111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100101100111010011001000110011"; WHEN "1111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101000111010011000011010000011"; WHEN "1111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101100000111001011110100010010"; WHEN "1111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101111001101101100001110011100"; WHEN "1111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110010001101111000100101110110"; WHEN "1111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110101000111101111110101001010"; WHEN "1111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110111111011010000111000110000"; WHEN "1111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110111010101000011010110000100000"; WHEN OTHERS => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; END CASE; END IF; END PROCESS; --sumAHighB_uid242_sinPiZPolyEval(ADD,241)@14 sumAHighB_uid242_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid229_sinPiZTableGenerator_q(34)) & memoryC3_uid229_sinPiZTableGenerator_q); sumAHighB_uid242_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((35 downto 28 => reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q(27)) & reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q); sumAHighB_uid242_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid242_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid242_sinPiZPolyEval_b)); sumAHighB_uid242_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_o(35 downto 0); --lowRangeB_uid240_sinPiZPolyEval(BITSELECT,239)@13 lowRangeB_uid240_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid240_sinPiZPolyEval_b <= lowRangeB_uid240_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a(DELAY,686)@13 ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid240_sinPiZPolyEval_b, xout => ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --s2_uid240_uid243_sinPiZPolyEval(BITJOIN,242)@14 s2_uid240_uid243_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_q & ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q; --yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval(BITSELECT,274)@14 yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in(36 downto 19); --reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9(REG,389)@14 reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor(LOGICAL,950) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top(CONSTANT,946) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q <= "0110"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp(LOGICAL,947) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b else "0"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg(REG,948) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena(REG,951) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q = "1") THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd(LOGICAL,952) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt(COUNTER,942) -- every=1, low=0, high=6, step=1, init=1 ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i = 5 THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i - 6; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i,3)); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg(REG,943) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux(MUX,944) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q) BEGIN CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s IS WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem(DUALMEM,1069) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 3, numwords_a => 7, width_b => 45, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg(DELAY,1068) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT3_uid244_sinPiZPolyEval(BITSELECT,243)@14 yT3_uid244_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q; yT3_uid244_sinPiZPolyEval_b <= yT3_uid244_sinPiZPolyEval_in(44 downto 10); --xBottomBits_uid274_pT3_uid245_sinPiZPolyEval(BITSELECT,273)@14 xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b(7 downto 0); xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in(7 downto 0); --pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval(BITJOIN,276)@14 pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7(REG,391)@14 reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid273_pT3_uid245_sinPiZPolyEval(BITSELECT,272)@14 yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q(9 downto 0); yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b <= yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in(9 downto 0); --spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval(BITJOIN,275)@14 spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q <= GND_q & yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b; --pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval(BITJOIN,277)@14 pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q <= spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6(REG,390)@14 reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval(BITSELECT,271)@14 xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in(34 downto 17); --reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4(REG,392)@14 reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma(CHAINMULTADD,345)@15 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1),38); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0); END IF; END PROCESS; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0),37)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval(BITSELECT,279)@18 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in(36 downto 7); --highBBits_uid282_pT3_uid245_sinPiZPolyEval(BITSELECT,281)@18 highBBits_uid282_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b; highBBits_uid282_pT3_uid245_sinPiZPolyEval_b <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_in(29 downto 1); --reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1(REG,395)@18 reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval(BITSELECT,269)@14 yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in(36 downto 10); --reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1(REG,393)@14 reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval(BITSELECT,268)@14 xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in(34 downto 8); --reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0(REG,394)@14 reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid271_pT3_uid245_sinPiZPolyEval(MULT,270)@15 topProd_uid271_pT3_uid245_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_b); topProd_uid271_pT3_uid245_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid271_pT3_uid245_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid271_pT3_uid245_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0(REG,396)@18 reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid283_pT3_uid245_sinPiZPolyEval(ADD,282)@19 sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q(53)) & reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b)); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid281_pT3_uid245_sinPiZPolyEval(BITSELECT,280)@18 lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b <= lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a(DELAY,724)@18 ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b, xout => ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid281_uid284_pT3_uid245_sinPiZPolyEval(BITJOIN,283)@19 add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q & ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q; --R_uid285_pT3_uid245_sinPiZPolyEval(BITSELECT,284)@19 R_uid285_pT3_uid245_sinPiZPolyEval_in <= add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q(54 downto 0); R_uid285_pT3_uid245_sinPiZPolyEval_b <= R_uid285_pT3_uid245_sinPiZPolyEval_in(54 downto 18); --reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1(REG,397)@19 reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= R_uid285_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor(LOGICAL,1168) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1164) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q <= "01011"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp(LOGICAL,1165) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg(REG,1166) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena(REG,1169) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1170) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1160) -- every=1, low=0, high=11, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i = 10 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i - 11; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i,4)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg(REG,1161) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1162) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1159) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 4, numwords_a => 12, width_b => 7, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg(DELAY,1158) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0(REG,381)@18 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC2_uid228_sinPiZTableGenerator(LOOKUP,227)@19 memoryC2_uid228_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; WHEN "0000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010010000000010011011110101101000"; WHEN "0000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010100110111111010000111001000101"; WHEN "0000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101011001101001111001000101101101011"; WHEN "0000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101100000010110001110010011100100110"; WHEN "0000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101101000111100110110110100100001100"; WHEN "0000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101110011011101101110110101011000001"; WHEN "0000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101111111111000110001101110000001000"; WHEN "0001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110001110001101111010000000001001001"; WHEN "0001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110011110011101000001010111100010011"; WHEN "0001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110110000100110000000101010101010010"; WHEN "0001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111000100101000101111111001111001110"; WHEN "0001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111011010100101000110010000000110000"; WHEN "0001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111110010011010111010000010100101101"; WHEN "0001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000001100001010000000110001101010110"; WHEN "0001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000100111110010001111000111001110001"; WHEN "0010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001000101010011011000111000110111111"; WHEN "0010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001100100101101010001000110100001110"; WHEN "0010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010000101111111101001111011000110110"; WHEN "0010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010101001001010010100101011111010000"; WHEN "0010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011001110001101000001111010001111100"; WHEN "0010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011110101000111100001010010001101000"; WHEN "0010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111100011101111001100001101011001010011"; WHEN "0010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101001000100010110001000111111011001"; WHEN "0011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101110101000010111100110110111011101"; WHEN "0011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111110100011011001110001010010101001001"; WHEN "0011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111111010011100110111010000000101010000"; WHEN "0011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000000101101010000001110011011110111"; WHEN "0011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000111001100010110010101001001001010"; WHEN "0011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000001101111010000110101101100011101100"; WHEN "0011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000010100110110011110011010100101011100"; WHEN "0011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000011100000001011010011000101010010101"; WHEN "0100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000100011011010110111011101111001100010"; WHEN "0100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000101011000010110010011010000011100100"; WHEN "0100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000110010111001000111110110011110000010"; WHEN "0100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000111010111101110100010110010000011111"; WHEN "0100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001000011010000110100010110001010111111"; WHEN "0100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001001011110010000100001100101110011011"; WHEN "0100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001010100100001100000001010001100011000"; WHEN "0100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001011101011111000100011000101001100001"; WHEN "0101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001100110101010101100111100000000011011"; WHEN "0101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001110000000100010101110001111101110010"; WHEN "0101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001111001101011111010110010001100011010"; WHEN "0101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010000011100001010111101110001010011110"; WHEN "0101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010001101100100101000010001011000100111"; WHEN "0101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010010111110101101000000001010011000010"; WHEN "0101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010100010010100010010011101010101101010"; WHEN "0101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010101101000000100010111111000010000011"; WHEN "0110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010110111111010010100111001111011100110"; WHEN "0110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011000011000001100011011011101110111001"; WHEN "0110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011001110010110001001101100001111110101"; WHEN "0110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011011001111000000010101101100000111100"; WHEN "0110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011100101100111001001011011101110011000"; WHEN "0110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011110001100011011000101101011001110101"; WHEN "0110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011111101101100101011010011010110110001"; WHEN "0110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100001010000010111011111000101001101100"; WHEN "0111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100010110100110000101000010110110110100"; WHEN "0111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100100011010110000001010001110101000110"; WHEN "0111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100110000010010101010111111111100101100"; WHEN "0111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100111101011011111100100010000110111111"; WHEN "0111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101001010110001110000000111101111100101"; WHEN "0111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101011000010011111111111010110011011100"; WHEN "0111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101100110000010100101111111111011010100"; WHEN "0111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101110011111101011100010110011100010110"; WHEN "1000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110000010000100011100111000010100111110"; WHEN "1000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110010000010111100001011010011001010101"; WHEN "1000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110011110110110100011101100001011001000"; WHEN "1000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110101101100001011101011000001011011001"; WHEN "1000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110111100011000001000000011101110001111"; WHEN "1000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111001011011010011101001111000101110001"; WHEN "1000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111011010101000010110010101100101000110"; WHEN "1000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111101010000001101100101101100010111111"; WHEN "1001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111111001100110011001101000011100111011"; WHEN "1001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000001001010110010110010010110100011100"; WHEN "1001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000011001010001011011110100100000011000"; WHEN "1001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000101001010111100011010000011111011101"; WHEN "1001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000111001101000100101100101001010011111"; WHEN "1001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001001010000100011011101100001100000010"; WHEN "1001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001011010101010111110011010101000110000"; WHEN "1001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001101011011100000110100001001001100100"; WHEN "1010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001111100010111101100101011101111001100"; WHEN "1010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010001101011101101001100010000010111010"; WHEN "1010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010011110101101110101100111011000000101"; WHEN "1010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010110000001000001001011010101000000100"; WHEN "1010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011000001101100011101010110100010000110"; WHEN "1010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011010011011010101001110001100010110011"; WHEN "1010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011100101010010100110111101111101101001"; WHEN "1010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011110111010100001101001010000001101110"; WHEN "1011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100001001011111010100011111111010110111"; WHEN "1011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100011011110011110101000101111001011001"; WHEN "1011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100101110010001100110111110001101101110"; WHEN "1011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101000000111000100010000111010010100101"; WHEN "1011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101010011101000011110011011110001111001"; WHEN "1011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101100110100001010011110010100110010101"; WHEN "1011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101111001100010111001111110111010001011"; WHEN "1011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110001100101101001000110000010101000001"; WHEN "1100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110011111111111110111110010111000010010"; WHEN "1100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110110011011010111110101111001000100111"; WHEN "1100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111000110111110010101001010001010011010"; WHEN "1100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111011010101001110010100101101110010111"; WHEN "1100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111101110011101001110100000001111101010"; WHEN "1100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000000010011000100000010100110110100000"; WHEN "1100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000010110011011011111011011100110110011"; WHEN "1100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000101010100110000011001001011000000001"; WHEN "1101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000111110111000000010101111111100010101"; WHEN "1101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001010011010001010101011110001011010100"; WHEN "1101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001100111110001110010100000000000010111"; WHEN "1101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001111100011001010000111110011101110000"; WHEN "1101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010010001000111100111111111110011011101"; WHEN "1101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010100101111100101110100111100110010101"; WHEN "1101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010111010111000011011110110101001010101"; WHEN "1101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011001111111010100110101011010011011011"; WHEN "1110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011100101000011000110000001010000000100"; WHEN "1110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011111010010001110000110001110011111011"; WHEN "1110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100001111100110011101110011111001111111"; WHEN "1110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100100101000001000011111100000011011011"; WHEN "1110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100111010100001011001111100100100101001"; WHEN "1110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101010000000111010110100101100100010111"; WHEN "1110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101100101110010110000100101000101101101"; WHEN "1110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101111011100011011110100111000011010111"; WHEN "1111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110010001011001010111010101011001010001"; WHEN "1111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110100111010100010001011000001010110100"; WHEN "1111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110111101010100000011010101100101100011"; WHEN "1111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111010011011000100011110010000011111011"; WHEN "1111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111101001100001101001010000010010001011"; WHEN "1111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111111111101111001010010001010101000011"; WHEN "1111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000010110000000111101010100101101001001"; WHEN "1111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000101100010110111000111000011010110101"; WHEN OTHERS => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid246_sinPiZPolyEval(CONSTANT,245) rndBit_uid246_sinPiZPolyEval_q <= "01"; --cIncludingRoundingBit_uid247_sinPiZPolyEval(BITJOIN,246)@19 cIncludingRoundingBit_uid247_sinPiZPolyEval_q <= memoryC2_uid228_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0(REG,398)@19 reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid247_sinPiZPolyEval_q; END IF; END PROCESS; --ts3_uid248_sinPiZPolyEval(ADD,247)@20 ts3_uid248_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q); ts3_uid248_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q(36)) & reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q); ts3_uid248_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid248_sinPiZPolyEval_a) + SIGNED(ts3_uid248_sinPiZPolyEval_b)); ts3_uid248_sinPiZPolyEval_q <= ts3_uid248_sinPiZPolyEval_o(45 downto 0); --s3_uid249_sinPiZPolyEval(BITSELECT,248)@20 s3_uid249_sinPiZPolyEval_in <= ts3_uid248_sinPiZPolyEval_q; s3_uid249_sinPiZPolyEval_b <= s3_uid249_sinPiZPolyEval_in(45 downto 1); --yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval(BITSELECT,286)@20 yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b; yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in(44 downto 18); --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9(REG,399)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor(LOGICAL,1091) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top(CONSTANT,1087) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q <= "01100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp(LOGICAL,1088) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg(REG,1089) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena(REG,1092) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd(LOGICAL,1093) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1083) -- every=1, low=0, high=12, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i = 11 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i - 12; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i,4)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg(REG,1084) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux(MUX,1085) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem(DUALMEM,1082) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 13, width_b => 45, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg(DELAY,1081) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT4_uid250_sinPiZPolyEval(BITSELECT,249)@20 yT4_uid250_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q; yT4_uid250_sinPiZPolyEval_b <= yT4_uid250_sinPiZPolyEval_in(44 downto 2); --xBottomBits_uid290_pT4_uid251_sinPiZPolyEval(BITSELECT,289)@20 xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in <= yT4_uid250_sinPiZPolyEval_b(15 downto 0); xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in(15 downto 0); --pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval(BITJOIN,291)@20 pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7(REG,401)@20 reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid289_pT4_uid251_sinPiZPolyEval(BITSELECT,288)@20 yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b(17 downto 0); yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b <= yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a(DELAY,733)@20 ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b, xout => ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval(BITJOIN,290)@21 spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q; --pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval(BITJOIN,292)@21 pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q <= spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6(REG,400)@21 reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a(DELAY,727)@20 ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 43, depth => 1 ) PORT MAP ( xin => yT4_uid250_sinPiZPolyEval_b, xout => ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval(BITSELECT,285)@21 xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in <= ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q; xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in(42 downto 16); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4(REG,402)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma(CHAINMULTADD,346)@22 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval(BITSELECT,294)@25 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in(54 downto 8); --highBBits_uid297_pT4_uid251_sinPiZPolyEval(BITSELECT,296)@25 highBBits_uid297_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b; highBBits_uid297_pT4_uid251_sinPiZPolyEval_b <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_in(46 downto 18); --reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1(REG,405)@25 reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1(REG,403)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b(DELAY,730)@21 ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0(REG,404)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid288_pT4_uid251_sinPiZPolyEval(MULT,287)@22 topProd_uid288_pT4_uid251_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_b); topProd_uid288_pT4_uid251_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid288_pT4_uid251_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid288_pT4_uid251_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0(REG,406)@25 reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid298_pT4_uid251_sinPiZPolyEval(ADD,297)@26 sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q(53)) & reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b)); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid296_pT4_uid251_sinPiZPolyEval(BITSELECT,295)@25 lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b(17 downto 0); lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b <= lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a(DELAY,741)@25 ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b, xout => ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid296_uid299_pT4_uid251_sinPiZPolyEval(BITJOIN,298)@26 add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q & ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q; --R_uid300_pT4_uid251_sinPiZPolyEval(BITSELECT,299)@26 R_uid300_pT4_uid251_sinPiZPolyEval_in <= add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q(71 downto 0); R_uid300_pT4_uid251_sinPiZPolyEval_b <= R_uid300_pT4_uid251_sinPiZPolyEval_in(71 downto 26); --reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1(REG,407)@26 reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= R_uid300_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor(LOGICAL,1155) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1151) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q <= "010010"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp(LOGICAL,1152) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg(REG,1153) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena(REG,1156) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1157) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1147) -- every=1, low=0, high=18, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i = 17 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i - 18; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg(REG,1148) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1149) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1146) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 19, width_b => 7, widthad_b => 5, numwords_b => 19, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg(DELAY,1145) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0(REG,380)@25 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC1_uid227_sinPiZTableGenerator(LOOKUP,226)@26 memoryC1_uid227_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; WHEN "0000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111110101101010100010101111000000010001111100011"; WHEN "0000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111101011010101001001010010110100010110001011110"; WHEN "0000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111100000111111110111100000001110010011010000110"; WHEN "0000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111010110101010110001001011111100110111111100011"; WHEN "0000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111001100010101111010001010101001101111010110100"; WHEN "0000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111000010000001010110010000110111110101011111000"; WHEN "0000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110110111101101001001010011000001101011000111010"; WHEN "0001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110101101011001010111000101010111101010010100111"; WHEN "0001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110100011000110000011011011111110011010111001110"; WHEN "0001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110011000110011010010001010101101000110101101101"; WHEN "0001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110001110100001000111000101001011101110011011101"; WHEN "0001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110000100001111100101111110110001011110001011001"; WHEN "0001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101111001111110110010101010100011000010010100110"; WHEN "0001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101101111101110110000111011010000111100011100100"; WHEN "0001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101100101011111100100100011010101111000101000111"; WHEN "0010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101011011010001010001010100110101000010011111000"; WHEN "0010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101010001000011111011000001011000011010110000100"; WHEN "0010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101000110110111100101011010001111001100111110010"; WHEN "0010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100111100101100010100010000001100000101010111010"; WHEN "0010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100110010100010001011010011100011100110101011100"; WHEN "0010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100101000011001001110010100001010100000101101100"; WHEN "0010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100011110010001100001000001010100000110110000000"; WHEN "0010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100010100001011000111001001110000100110010111000"; WHEN "0011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100001010000110000100011011101011011110011010110"; WHEN "0011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100000000000010011100100100101001110110011000010"; WHEN "0011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011110110000000010011010001101000110110000011100"; WHEN "0011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011101011111111101100001110111011111101010000000"; WHEN "0011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011100010000000101011001000001011011100001111010"; WHEN "0011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011011000000011010011101000010010101100000110110"; WHEN "0011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011001110000111101001011001011110100111101110010"; WHEN "0011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011000100001101110000000101001100000101000010010"; WHEN "0100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010111010010101101011010100000110001110011110001"; WHEN "0100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010110000011111011110101110000100111100111110101"; WHEN "0100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010100110101011001101111010001011010010011110011"; WHEN "0100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010011100111000111100011110100101110100010111000"; WHEN "0100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010010011001000101110000000101001000110111000111"; WHEN "0100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010001001011010100110000100110000001000100101001"; WHEN "0100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001111111101110101000001110011010101110010001110"; WHEN "0100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001110110000100111000000000001011111111100011001"; WHEN "0101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001101100011101011000111011101000110011100100000"; WHEN "0101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001100010111000001110100001010110001110100101001"; WHEN "0101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001011001010101011100010000110111111111100011001"; WHEN "0101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001001111110101000101101000101110111110101110110"; WHEN "0101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001000110010111001110000110010111101100001101110"; WHEN "0101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000111100111011111001000110001000101111011110000"; WHEN "0101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000110011100011001010000011010001010111001000100"; WHEN "0101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000101010001101000100010111110111111001010110011"; WHEN "0110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000100000111001101011011100111000010100110100100"; WHEN "0110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000010111101001000010101010000010110010001100101"; WHEN "0110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000001110011011001101010101111010000110001110001"; WHEN "0110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000000101010000001110110101110010010100010001010"; WHEN "0110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111111100001000001010011101101111010001101110100"; WHEN "0110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111110011000011000011100000100011001001100111111"; WHEN "0110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111101010000000111101001111101101000001001100111"; WHEN "0110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111100001000001111010111011010111011101000011000"; WHEN "0111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111011000000101111111110010010111000110100000100"; WHEN "0111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111001111001101001111000010001001010010011000111"; WHEN "0111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111000110010111101011110110110010100111101001111"; WHEN "0111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110111101100101011001011010111101100111001001111"; WHEN "0111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110110100110110011010110111111001010011111110011"; WHEN "0111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110101100001010110011010101010111111100100001011"; WHEN "0111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110100011100010100101111001101101100100000011010"; WHEN "0111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110011010111101110101101001101110101101001000101"; WHEN "1000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110010010011100100101101000101111000100111000101"; WHEN "1000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110001001111110111000111000100000001110100110010"; WHEN "1000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110000001100100110010011001010000010000100100001"; WHEN "1000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101111001001110010101001001101000100001000011111"; WHEN "1000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101110000111011100100000110101100010100101111011"; WHEN "1000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101101000101100100010001011110111101101010011001"; WHEN "1000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101100000100001010010010010111110001001000100100"; WHEN "1000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101011000011001110111010100001001010011011010001"; WHEN "1001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101010000010110010100000101110111110101110111011"; WHEN "1001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101001000010110101011011100111100001010010001010"; WHEN "1001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101000000011011000000001100011011001101001101101"; WHEN "1001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100111000100011010101000101101011010001111110100"; WHEN "1001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100110000101111101100111000010010110110101001010"; WHEN "1001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100101001000000001010010010000111011001100101001"; WHEN "1001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100100001010100101111111111001100001111011011000"; WHEN "1001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100011001101101100000101001110001011001110111100"; WHEN "1010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100010010001010011110111010010010011111110100100"; WHEN "1010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100001010101011101101010111010101100101110000010"; WHEN "1010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100000011010001001110100101101010000111010011101"; WHEN "1010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011111011111011000101001000000111110001110111111"; WHEN "1010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011110100101001010011011111101101011111101000010"; WHEN "1010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011101101011011111100001011100000010100000001101"; WHEN "1010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011100110010011000001101000101010011000110001101"; WHEN "1010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011111001110100110010010011001111011110111011"; WHEN "1011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011000001110101100100010000000001110100011101"; WHEN "1011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011010001010011010110101110110000100101001100010"; WHEN "1011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011001010011100100111001101111111011000001100001"; WHEN "1011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011000011101010100000010011000001000101101011001"; WHEN "1011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010111100111101000100001111001001010100001001100"; WHEN "1011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010110110010100010101010001101001110110001111011"; WHEN "1011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101111110000010101100111110001101111011011100"; WHEN "1011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101001010001000111011100101100011001011100101"; WHEN "1100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010100010110110101100111001100000101011000010000"; WHEN "1100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010011100100001001000000101001111111111010110011"; WHEN "1100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010110010000011011000100110101011110110000011"; WHEN "1100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010000000100100111111011000101001000001000001"; WHEN "1100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010001001111101110000101000101010111011100100101"; WHEN "1100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010000011111011110111001100001010000110000001000"; WHEN "1100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111101111110111101100001111100001101100011111"; WHEN "1100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111000000111000101100100010000011111010101010"; WHEN "1101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001110010010100010001001011001010111110000100010"; WHEN "1101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001101100100110100010001100100011110001100110110"; WHEN "1101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100110111101111010011100000110010111101110011"; WHEN "1101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100001011010011011101011010000110101111000110"; WHEN "1101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001011011111100000111101001010011001011111101101"; WHEN "1101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010110100011000000000011001110101000000001010"; WHEN "1101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010001001111000110100011110100111011011010110"; WHEN "1101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001001100000000011100110011100111110000011010110"; WHEN "1110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000110110111000100011000111000000001100101100"; WHEN "1110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000001110010111110110111100101010001100011100"; WHEN "1110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000111100110100001101110001011101000100010101000"; WHEN "1110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110111111010110010100101111010011001100111001"; WHEN "1110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110011000110101110110010000101000111111101001"; WHEN "1110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101110011000000011110000110001011001010001101"; WHEN "1110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101001101110110010111010011111001000001110011"; WHEN "1110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100101001010111101100101011001011110111111001"; WHEN "1111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100000101100100101000101010110010110110110011"; WHEN "1111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011100010011101010101011110101111000111101111"; WHEN "1111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011000000000001111101000000010000000010001101"; WHEN "1111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000010011110010010101000110101101111100100010110"; WHEN "1111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001111101001111100010010010101110110011110010"; WHEN "1111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001011100111000110010010111110010100110111110"; WHEN "1111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000111101001110100001110010100000011000001001"; WHEN "1111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000011110010000111000111101011011000001000111"; WHEN OTHERS => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; END CASE; -- End reserved scope level END PROCESS; --cIncludingRoundingBit_uid253_sinPiZPolyEval(BITJOIN,252)@26 cIncludingRoundingBit_uid253_sinPiZPolyEval_q <= memoryC1_uid227_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0(REG,408)@26 reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid253_sinPiZPolyEval_q; END IF; END PROCESS; --ts4_uid254_sinPiZPolyEval(ADD,253)@27 ts4_uid254_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((52 downto 52 => reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q(51)) & reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q); ts4_uid254_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((52 downto 46 => reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q(45)) & reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q); ts4_uid254_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid254_sinPiZPolyEval_a) + SIGNED(ts4_uid254_sinPiZPolyEval_b)); ts4_uid254_sinPiZPolyEval_q <= ts4_uid254_sinPiZPolyEval_o(52 downto 0); --s4_uid255_sinPiZPolyEval(BITSELECT,254)@27 s4_uid255_sinPiZPolyEval_in <= ts4_uid254_sinPiZPolyEval_q; s4_uid255_sinPiZPolyEval_b <= s4_uid255_sinPiZPolyEval_in(52 downto 1); --yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval(BITSELECT,301)@27 yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b; yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in(51 downto 25); --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9(REG,409)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor(LOGICAL,1117) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q <= not (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a or ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top(CONSTANT,1113) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q <= "010011"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp(LOGICAL,1114) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a = ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b else "0"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg(REG,1115) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena(REG,1118) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q = "1") THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd(LOGICAL,1119) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a and ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b; --xBottomBits_uid305_pT5_uid257_sinPiZPolyEval(BITSELECT,304)@5 xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b(17 downto 0); xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt(COUNTER,1109) -- every=1, low=0, high=19, step=1, init=1 ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i = 18 THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '1'; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i - 19; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i,5)); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg(REG,1110) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux(MUX,1111) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q) BEGIN CASE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s IS WHEN "0" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; WHEN "1" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; WHEN OTHERS => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem(DUALMEM,1108) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 <= areset; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 5, numwords_a => 20, width_b => 18, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0, clock1 => clk, address_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq, address_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa, data_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia ); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg(DELAY,1107) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q, xout => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q, clk => clk, aclr => areset ); --pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval(BITJOIN,306)@27 pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7(REG,411)@27 reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid304_pT5_uid257_sinPiZPolyEval(BITSELECT,303)@27 yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b(24 downto 0); yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b <= yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a(DELAY,750)@27 ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b, xout => ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval(BITJOIN,305)@28 spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q; --pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval(BITJOIN,307)@28 pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q <= spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q & GND_q; --reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6(REG,410)@28 reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor(LOGICAL,1104) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top(CONSTANT,1100) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q <= "010100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp(LOGICAL,1101) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg(REG,1102) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena(REG,1105) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd(LOGICAL,1106) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1096) -- every=1, low=0, high=20, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i = 19 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i - 20; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i,5)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg(REG,1097) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux(MUX,1098) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem(DUALMEM,1095) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 5, numwords_a => 21, width_b => 45, widthad_b => 5, numwords_b => 21, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg(DELAY,1094) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval(BITSELECT,300)@28 xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q; xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in(44 downto 18); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4(REG,412)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma(CHAINMULTADD,347)@29 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval(BITSELECT,309)@32 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in(54 downto 1); --highBBits_uid312_pT5_uid257_sinPiZPolyEval(BITSELECT,311)@32 highBBits_uid312_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b; highBBits_uid312_pT5_uid257_sinPiZPolyEval_b <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_in(53 downto 25); --reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1(REG,415)@32 reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1(REG,413)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b(DELAY,747)@28 ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0(REG,414)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid303_pT5_uid257_sinPiZPolyEval(MULT,302)@29 topProd_uid303_pT5_uid257_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_b); topProd_uid303_pT5_uid257_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid303_pT5_uid257_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid303_pT5_uid257_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0(REG,416)@32 reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid313_pT5_uid257_sinPiZPolyEval(ADD,312)@33 sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q(53)) & reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b)); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid311_pT5_uid257_sinPiZPolyEval(BITSELECT,310)@32 lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b(24 downto 0); lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b <= lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a(DELAY,758)@32 ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b, xout => ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid311_uid314_pT5_uid257_sinPiZPolyEval(BITJOIN,313)@33 add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q & ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q; --R_uid315_pT5_uid257_sinPiZPolyEval(BITSELECT,314)@33 R_uid315_pT5_uid257_sinPiZPolyEval_in <= add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q(78 downto 0); R_uid315_pT5_uid257_sinPiZPolyEval_b <= R_uid315_pT5_uid257_sinPiZPolyEval_in(78 downto 25); --reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1(REG,417)@33 reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= R_uid315_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor(LOGICAL,1142) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1138) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q <= "011001"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp(LOGICAL,1139) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg(REG,1140) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena(REG,1143) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1144) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1134) -- every=1, low=0, high=25, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i = 24 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i - 25; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg(REG,1135) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1136) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1133) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 26, width_b => 7, widthad_b => 5, numwords_b => 26, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg(DELAY,1132) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0(REG,379)@32 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC0_uid226_sinPiZTableGenerator(LOOKUP,225)@33 memoryC0_uid226_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; WHEN "0000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111010001111111001101111011000111100001001010"; WHEN "0000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000101010101111101111010001101100110011111100100"; WHEN "0000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000010000111010001110111000001110010011001110001"; WHEN "0000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001111101100101111100010000110111011000000101000010"; WHEN "0000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110111110001111110110010110011100111000110011101"; WHEN "0000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110000101011011011100110100000100010100111010101"; WHEN "0000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001101000010010010101010100001100000100101011101101"; WHEN "0001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001011110100110101111000010100110110100001011000010"; WHEN "0001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001010011101000101100010111000010101101001011110101"; WHEN "0001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001000111011000010001010101010001011100000010111010"; WHEN "0001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000111001110101100010011111100010101010110110110111"; WHEN "0001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000101011000000100100110110100010000001101000110010"; WHEN "0001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000011010111001011101111001010100111001000011000110"; WHEN "0001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000001001100000010011100101010111111111101111100110"; WHEN "0001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111110110110101001100010110011100110010010101101111"; WHEN "0010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111100010111000001111000110100110100110000010101111"; WHEN "0010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111001101101001100011001110000111100101111100011100"; WHEN "0010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110110111001001010000100011011101100011000000101111"; WHEN "0010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110011111010111011111011011001110010110110010111000"; WHEN "0010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110000110010100011000101000000100011000111000100110"; WHEN "0010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101101100000000000101011010101010100111001000011100"; WHEN "0010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101010000011010101111100001101000100000101011011110"; WHEN "0010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100110011100100100001001001011101110011110100001011"; WHEN "0011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100010101011101100100111100011101111110101100100111"; WHEN "0011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011110110000110000110000010101011100010111110000011"; WHEN "0011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011010101011110010000000001110011001100010100001001"; WHEN "0011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010110011100110001110111101000110101001111110010101"; WHEN "0011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010010000011110001111010101010111011011010001011111"; WHEN "0011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001101100000110011110001000110001001111001100110001"; WHEN "0011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001000110011111001000110010110100010111000011111111"; WHEN "0011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001000011111101000011101001100001111101100010010011001"; WHEN "0100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111110111100010101001101010111010101001011000110001"; WHEN "0100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111001110001101111101000001101110110110001001100100"; WHEN "0100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000110100011101010100110100000100001100111000110001110"; WHEN "0100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101110111111000110101110011111101010000010000111000"; WHEN "0100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101001010111000111011000101011010001011010101011100"; WHEN "0100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000100011100101011000110111010110111110001001101100111"; WHEN "0100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000011101101001111101010010110110101000111000011000010"; WHEN "0100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010111100100110110110111000001001011110110011001101"; WHEN "0101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010001010110000111110011001111100101011011000101100"; WHEN "0101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000001010111101110010011010011011111001000011101001111"; WHEN "0101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000000100011011111001000011000000001110101111000110101"; WHEN "0101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111111101110000011110000110110101110000111000001001000"; WHEN "0101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111110110111011100100000011010011101000101101101101111"; WHEN "0101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101111111101001101011001001101111001001010100111010"; WHEN "0101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101000110101011100101100110100011000001100101000111"; WHEN "0101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111100001100100010100100101110001100110101011111100110"; WHEN "0110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111011010001001110111101111001001100110110011000001101"; WHEN "0110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111010010100110001000110111011000110000110111110111111"; WHEN "0110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111001010111001001010110000010010100110110110111111101"; WHEN "0110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111000011000011000000001111000000100110010000101101101"; WHEN "0110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110111011000011101100001100000000111000101001011011010"; WHEN "0110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110110010111011010001100011000101000010101101011001001"; WHEN "0110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110101010101001110011010011010000110001111000101001011"; WHEN "0110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110100010001111010100011110111000101000100011101001111"; WHEN "0111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110011001101011111000001011100000101000110101010111101"; WHEN "0111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110010000111111100001100001111010111101111011010000110"; WHEN "0111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110001000001010010011101110000110100100001000000010111"; WHEN "0111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101111111001100010001111111001101101111011001101100100"; WHEN "0111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101110110000101011111100111100100110000100111011101101"; WHEN "0111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101101100110101111111111100101000011001011000100010101"; WHEN "0111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101100011011101110110010110111100011110100100000110011"; WHEN "0111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101011001111101000110010010001010011001011011010110110"; WHEN "1000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101010000010011110011001100111111100111011110011001101"; WHEN "1000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101000110100010000000101001001100001000111100100001001"; WHEN "1000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100111100100111110010001011100000111110000000101011101"; WHEN "1000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100110010100101001011011011101110100010101011000001110"; WHEN "1000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100101000011010010000000100100011001001010111111110011"; WHEN "1000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100011110000111000011110011101001010100010101110100101"; WHEN "1000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100010011101011101010011001100110001101101001100010111"; WHEN "1000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100001001001000000111101001110111111110000011100100111"; WHEN "1001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011111110011100011111011010110100000010100101010111001"; WHEN "1001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011110011101000110101100101100101100000111000011110001"; WHEN "1001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011101000101101001110000110001011011010011000000110010"; WHEN "1001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011011101101001101100111011010110111110001101101101010"; WHEN "1001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011010010011110010110000110101001111010000001101101100"; WHEN "1001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011000111001011001101101100010100101001100000111100110"; WHEN "1001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010111011110000010111110011010100100100110111110110011"; WHEN "1001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010110000001101111000100101010010001110000100000110101"; WHEN "1010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010100100100011110100001110011111011100111101101011110"; WHEN "1010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010011000110010001110111101110101101010011000000111111"; WHEN "1010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010001100111001001101000100110011111001111100111000001"; WHEN "1010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010000000111000110010110111011101000010111111101010001"; WHEN "1010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001110100110001000100101100010101111000001101101010100"; WHEN "1010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001101000100010000110111100100011001110011000100010010"; WHEN "1010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001011100001011111110000011101000000001111110000000000"; WHEN "1010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001001111101110101110011111100011011011101101000101110"; WHEN "1011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001000011001010011100110000101110110100001001110110000"; WHEN "1011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000110110011111001101011001111011110110010000011100000"; WHEN "1011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000101001101101000101000000010010100000111000101001110"; WHEN "1011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000011100110100001000001011001111000111011010101001101"; WHEN "1011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000001111110100011011100100100000010001010101111111000"; WHEN "1011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000000010101110000011111000000100111000111011110010110"; WHEN "1011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111110101100001000101110100001010001000111101001001101"; WHEN "1011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111101000001101100110001001001001011001011110100011010"; WHEN "1100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111011010110011101001101001100110001011110001011110000"; WHEN "1100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111001101010011010101001010001100000101010101000000111"; WHEN "1100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110111111101100101101100001101100101001111110101000001"; WHEN "1100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110110001111111110111101000111101010101001011110111000"; WHEN "1100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110100100001100111000011010110101010010011110001011110"; WHEN "1100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110010110010011110100110100001011010101000001111000001"; WHEN "1100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110001000010100110001110011110011101110100000111111001"; WHEN "1100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101111010001111110100011010011110000101000011010111010"; WHEN "1101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101101100000101000001101010110011001000011100110100101"; WHEN "1101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101011101110100011110101001010010100110101010011100110"; WHEN "1101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101001111011110010000011100010000111111100000000100011"; WHEN "1101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101000001000010011100001011110101010111100110111011100"; WHEN "1101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100110010100001000111000001110111001010101110101010001"; WHEN "1101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100100011111010010110001001111011111101010001100000100"; WHEN "1101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100010101001110001110110001010101001101001100111101111"; WHEN "1101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100000110011100110110000110111110000010001111110011101"; WHEN "1110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011110111100110010001011011011000111101011110100101010"; WHEN "1110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011101000101010100110000000101101101000001111101101101"; WHEN "1110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011011001101001111001001010100110100010100000001010111"; WHEN "1110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011001010100100010000001110001110110000100001110111001"; WHEN "1110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010111011011001110000100010001111101000000100110100000"; WHEN "1110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010101100001010011111011110101110011100111100001100101"; WHEN "1110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010011100110110100010011101001010001101000000010101011"; WHEN "1110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010001101011101111110111000011001001011101110101101100"; WHEN "1111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001111110000000111010001100100110101101001001001010110"; WHEN "1111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001101110011111011001110111010000110000010101010100001"; WHEN "1111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001011110111001100011010111000101101001011101010010011"; WHEN "1111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001001111001111011100001100000001101011010010111101001"; WHEN "1111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000111111100001001001110111001100110000010110101011110"; WHEN "1111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000101111101110110001111010111000000011100010110001010"; WHEN "1111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000011111111000011001111010011011101000011100101001111"; WHEN "1111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000001111111110000111011010010100000011001101000010011"; WHEN OTHERS => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid258_sinPiZPolyEval(CONSTANT,257) rndBit_uid258_sinPiZPolyEval_q <= "001"; --cIncludingRoundingBit_uid259_sinPiZPolyEval(BITJOIN,258)@33 cIncludingRoundingBit_uid259_sinPiZPolyEval_q <= memoryC0_uid226_sinPiZTableGenerator_q & rndBit_uid258_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0(REG,418)@33 reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid259_sinPiZPolyEval_q; END IF; END PROCESS; --ts5_uid260_sinPiZPolyEval(ADD,259)@34 ts5_uid260_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q); ts5_uid260_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((61 downto 54 => reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q(53)) & reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q); ts5_uid260_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid260_sinPiZPolyEval_a) + SIGNED(ts5_uid260_sinPiZPolyEval_b)); ts5_uid260_sinPiZPolyEval_q <= ts5_uid260_sinPiZPolyEval_o(61 downto 0); --s5_uid261_sinPiZPolyEval(BITSELECT,260)@34 s5_uid261_sinPiZPolyEval_in <= ts5_uid260_sinPiZPolyEval_q; s5_uid261_sinPiZPolyEval_b <= s5_uid261_sinPiZPolyEval_in(61 downto 1); --fxpSinRes_uid66_fpSinPiTest(BITSELECT,65)@34 fxpSinRes_uid66_fpSinPiTest_in <= s5_uid261_sinPiZPolyEval_b(58 downto 0); fxpSinRes_uid66_fpSinPiTest_b <= fxpSinRes_uid66_fpSinPiTest_in(58 downto 5); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor(LOGICAL,963) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q <= not (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a or ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top(CONSTANT,959) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q <= "011111"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp(LOGICAL,960) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q <= "1" when ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a = ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b else "0"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg(REG,961) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena(REG,964) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q = "1") THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd(LOGICAL,965) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a and ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt(COUNTER,955) -- every=1, low=0, high=31, step=1, init=1 ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ELSIF (clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg(REG,956) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux(MUX,957) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux: PROCESS (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem(DUALMEM,954) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia <= sinXIsX_uid30_fpSinPiTest_c; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 32, width_b => 1, widthad_b => 5, numwords_b => 32, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq, address_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa, data_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia ); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg(DELAY,953) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --multRightOp_uid68_fpSinPiTest(MUX,67)@34 multRightOp_uid68_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q; multRightOp_uid68_fpSinPiTest: PROCESS (multRightOp_uid68_fpSinPiTest_s, fxpSinRes_uid66_fpSinPiTest_b) BEGIN CASE multRightOp_uid68_fpSinPiTest_s IS WHEN "0" => multRightOp_uid68_fpSinPiTest_q <= fxpSinRes_uid66_fpSinPiTest_b; WHEN "1" => multRightOp_uid68_fpSinPiTest_q <= piwFP2_uid67_fpSinPiTest_q; WHEN OTHERS => multRightOp_uid68_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_b_1(BITSELECT,318)@34 mul2xSinRes_uid69_fpSinPiTest_b_1_in <= multRightOp_uid68_fpSinPiTest_q; mul2xSinRes_uid69_fpSinPiTest_b_1_b <= mul2xSinRes_uid69_fpSinPiTest_b_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1(REG,423)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor(LOGICAL,1129) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q <= not (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a or ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top(CONSTANT,1125) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q <= "010110"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp(LOGICAL,1126) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q <= "1" when ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a = ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b else "0"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg(REG,1127) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena(REG,1130) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q = "1") THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd(LOGICAL,1131) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a and ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor(LOGICAL,937) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a or ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top(CONSTANT,933) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q <= "0111"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp(LOGICAL,934) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a = ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b else "0"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg(REG,935) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena(REG,938) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q = "1") THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd(LOGICAL,939) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt(COUNTER,929) -- every=1, low=0, high=7, step=1, init=1 ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,3); ELSIF (clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i + 1; END IF; END PROCESS; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i,3)); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg(REG,930) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux(MUX,931) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q) BEGIN CASE ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s IS WHEN "0" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; WHEN "1" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; WHEN OTHERS => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem(DUALMEM,928) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 <= areset; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia <= oFracX_uid31_uid31_fpSinPiTest_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 3, numwords_a => 8, width_b => 53, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq, address_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa, data_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia ); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq(52 downto 0); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg(DELAY,927) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg : dspba_delay GENERIC MAP ( width => 53, depth => 1 ) PORT MAP ( xin => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q, xout => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q, clk => clk, aclr => areset ); --LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest(BITSELECT,220)@10 LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q(77 downto 0); LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in(77 downto 0); --leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest(BITJOIN,221)@10 leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b & GND_q; --LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest(BITSELECT,204)@9 LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(54 downto 0); LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in(54 downto 0); --leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest(BITJOIN,205)@9 leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest(BITSELECT,201)@9 LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(62 downto 0); LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in(62 downto 0); --leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest(BITJOIN,202)@9 leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest(BITSELECT,198)@9 LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(70 downto 0); LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in(70 downto 0); --leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest(BITJOIN,199)@9 leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --ozz_uid41_fpSinPiTest(CONSTANT,40) ozz_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor(LOGICAL,1040) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q <= not (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a or ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top(CONSTANT,1036) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q <= "011"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp(LOGICAL,1037) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q <= "1" when ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a = ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b else "0"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg(REG,1038) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena(REG,1041) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q = "1") THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd(LOGICAL,1042) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a and ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b; --vStage_uid149_lzcZ_uid51_fpSinPiTest(BITSELECT,148)@4 vStage_uid149_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(14 downto 0); vStage_uid149_lzcZ_uid51_fpSinPiTest_b <= vStage_uid149_lzcZ_uid51_fpSinPiTest_in(14 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt(COUNTER,1032) -- every=1, low=0, high=3, step=1, init=1 ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,2); ELSIF (clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i,2)); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg(REG,1033) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux(MUX,1034) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1043) ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= vStage_uid149_lzcZ_uid51_fpSinPiTest_b; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 2, numwords_a => 4, width_b => 15, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(14 downto 0); --leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest(BITJOIN,193)@9 leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X46dto0_uid190_alignedZ_uid52_fpSinPiTest(BITSELECT,189)@4 X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(46 downto 0); X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in(46 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1031) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 47, widthad_a => 2, numwords_a => 4, width_b => 47, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(46 downto 0); --leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest(BITJOIN,190)@9 leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor(LOGICAL,1065) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q <= not (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a or ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top(CONSTANT,1061) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q <= "010"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp(LOGICAL,1062) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q <= "1" when ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a = ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b else "0"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg(REG,1063) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena(REG,1066) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q = "1") THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd(LOGICAL,1067) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a and ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt(COUNTER,1057) -- every=1, low=0, high=2, step=1, init=1 ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i = 1 THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i - 2; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i,2)); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg(REG,1058) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux(MUX,1059) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux: PROCESS (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem(DUALMEM,1056) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia <= z_uid49_fpSinPiTest_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 79, widthad_a => 2, numwords_a => 3, width_b => 79, widthad_b => 2, numwords_b => 3, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq, address_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa, data_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia ); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq(78 downto 0); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg(DELAY,1055) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q, xout => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --rVStage_uid146_lzcZ_uid51_fpSinPiTest(BITSELECT,145)@4 rVStage_uid146_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; rVStage_uid146_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_in(78 downto 15); --reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0(REG,365)@4 reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid147_lzcZ_uid51_fpSinPiTest(LOGICAL,146)@5 vCount_uid147_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid147_lzcZ_uid51_fpSinPiTest_a = vCount_uid147_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g(DELAY,629)@5 ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => vCount_uid147_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q, clk => clk, aclr => areset ); --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b(DELAY,587)@4 ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => vStage_uid149_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q, clk => clk, aclr => areset ); --mO_uid148_lzcZ_uid51_fpSinPiTest(CONSTANT,147) mO_uid148_lzcZ_uid51_fpSinPiTest_q <= "1111111111111111111111111111111111111111111111111"; --cStage_uid150_lzcZ_uid51_fpSinPiTest(BITJOIN,149)@5 cStage_uid150_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q & mO_uid148_lzcZ_uid51_fpSinPiTest_q; --ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c(DELAY,589)@4 ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 64, depth => 1 ) PORT MAP ( xin => rVStage_uid146_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid152_lzcZ_uid51_fpSinPiTest(MUX,151)@5 vStagei_uid152_lzcZ_uid51_fpSinPiTest_s <= vCount_uid147_lzcZ_uid51_fpSinPiTest_q; vStagei_uid152_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid152_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, cStage_uid150_lzcZ_uid51_fpSinPiTest_q) BEGIN CASE vStagei_uid152_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= cStage_uid150_lzcZ_uid51_fpSinPiTest_q; WHEN OTHERS => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid154_lzcZ_uid51_fpSinPiTest(BITSELECT,153)@5 rVStage_uid154_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q; rVStage_uid154_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_in(63 downto 32); --reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0(REG,366)@5 reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= "00000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid155_lzcZ_uid51_fpSinPiTest(LOGICAL,154)@6 vCount_uid155_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid155_lzcZ_uid51_fpSinPiTest_a = vCount_uid155_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f(DELAY,628)@6 ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid155_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q, clk => clk, aclr => areset ); --vStage_uid156_lzcZ_uid51_fpSinPiTest(BITSELECT,155)@5 vStage_uid156_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q(31 downto 0); vStage_uid156_lzcZ_uid51_fpSinPiTest_b <= vStage_uid156_lzcZ_uid51_fpSinPiTest_in(31 downto 0); --ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d(DELAY,596)@5 ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => vStage_uid156_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c(DELAY,595)@5 ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => rVStage_uid154_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid158_lzcZ_uid51_fpSinPiTest(MUX,157)@6 vStagei_uid158_lzcZ_uid51_fpSinPiTest_s <= vCount_uid155_lzcZ_uid51_fpSinPiTest_q; vStagei_uid158_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid158_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid158_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid160_lzcZ_uid51_fpSinPiTest(BITSELECT,159)@6 rVStage_uid160_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q; rVStage_uid160_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_in(31 downto 16); --reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0(REG,367)@6 reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid161_lzcZ_uid51_fpSinPiTest(LOGICAL,160)@7 vCount_uid161_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid161_lzcZ_uid51_fpSinPiTest_a = vCount_uid161_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e(DELAY,627)@7 ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid161_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q, clk => clk, aclr => areset ); --vStage_uid162_lzcZ_uid51_fpSinPiTest(BITSELECT,161)@6 vStage_uid162_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q(15 downto 0); vStage_uid162_lzcZ_uid51_fpSinPiTest_b <= vStage_uid162_lzcZ_uid51_fpSinPiTest_in(15 downto 0); --ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d(DELAY,602)@6 ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => vStage_uid162_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c(DELAY,601)@6 ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => rVStage_uid160_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid164_lzcZ_uid51_fpSinPiTest(MUX,163)@7 vStagei_uid164_lzcZ_uid51_fpSinPiTest_s <= vCount_uid161_lzcZ_uid51_fpSinPiTest_q; vStagei_uid164_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid164_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid164_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid166_lzcZ_uid51_fpSinPiTest(BITSELECT,165)@7 rVStage_uid166_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q; rVStage_uid166_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_in(15 downto 8); --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0(REG,368)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid167_lzcZ_uid51_fpSinPiTest(LOGICAL,166)@8 vCount_uid167_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid167_lzcZ_uid51_fpSinPiTest_a = vCount_uid167_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid168_lzcZ_uid51_fpSinPiTest(BITSELECT,167)@7 vStage_uid168_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q(7 downto 0); vStage_uid168_lzcZ_uid51_fpSinPiTest_b <= vStage_uid168_lzcZ_uid51_fpSinPiTest_in(7 downto 0); --reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3(REG,369)@7 reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= vStage_uid168_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2(REG,370)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vStagei_uid170_lzcZ_uid51_fpSinPiTest(MUX,169)@8 vStagei_uid170_lzcZ_uid51_fpSinPiTest_s <= vCount_uid167_lzcZ_uid51_fpSinPiTest_q; vStagei_uid170_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid170_lzcZ_uid51_fpSinPiTest_s, reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q, reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q) BEGIN CASE vStagei_uid170_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q; WHEN "1" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q; WHEN OTHERS => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid172_lzcZ_uid51_fpSinPiTest(BITSELECT,171)@8 rVStage_uid172_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q; rVStage_uid172_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_in(7 downto 4); --vCount_uid173_lzcZ_uid51_fpSinPiTest(LOGICAL,172)@8 vCount_uid173_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; vCount_uid173_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; vCount_uid173_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid173_lzcZ_uid51_fpSinPiTest_a = vCount_uid173_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid174_lzcZ_uid51_fpSinPiTest(BITSELECT,173)@8 vStage_uid174_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q(3 downto 0); vStage_uid174_lzcZ_uid51_fpSinPiTest_b <= vStage_uid174_lzcZ_uid51_fpSinPiTest_in(3 downto 0); --vStagei_uid176_lzcZ_uid51_fpSinPiTest(MUX,175)@8 vStagei_uid176_lzcZ_uid51_fpSinPiTest_s <= vCount_uid173_lzcZ_uid51_fpSinPiTest_q; vStagei_uid176_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid176_lzcZ_uid51_fpSinPiTest_s, rVStage_uid172_lzcZ_uid51_fpSinPiTest_b, vStage_uid174_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid176_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= vStage_uid174_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid178_lzcZ_uid51_fpSinPiTest(BITSELECT,177)@8 rVStage_uid178_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q; rVStage_uid178_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_in(3 downto 2); --vCount_uid179_lzcZ_uid51_fpSinPiTest(LOGICAL,178)@8 vCount_uid179_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; vCount_uid179_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; vCount_uid179_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid179_lzcZ_uid51_fpSinPiTest_a = vCount_uid179_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid180_lzcZ_uid51_fpSinPiTest(BITSELECT,179)@8 vStage_uid180_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q(1 downto 0); vStage_uid180_lzcZ_uid51_fpSinPiTest_b <= vStage_uid180_lzcZ_uid51_fpSinPiTest_in(1 downto 0); --vStagei_uid182_lzcZ_uid51_fpSinPiTest(MUX,181)@8 vStagei_uid182_lzcZ_uid51_fpSinPiTest_s <= vCount_uid179_lzcZ_uid51_fpSinPiTest_q; vStagei_uid182_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid182_lzcZ_uid51_fpSinPiTest_s, rVStage_uid178_lzcZ_uid51_fpSinPiTest_b, vStage_uid180_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid182_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= vStage_uid180_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid184_lzcZ_uid51_fpSinPiTest(BITSELECT,183)@8 rVStage_uid184_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid51_fpSinPiTest_q; rVStage_uid184_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_in(1 downto 1); --vCount_uid185_lzcZ_uid51_fpSinPiTest(LOGICAL,184)@8 vCount_uid185_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_b; vCount_uid185_lzcZ_uid51_fpSinPiTest_b <= GND_q; vCount_uid185_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid185_lzcZ_uid51_fpSinPiTest_a = vCount_uid185_lzcZ_uid51_fpSinPiTest_b else "0"; --r_uid186_lzcZ_uid51_fpSinPiTest(BITJOIN,185)@8 r_uid186_lzcZ_uid51_fpSinPiTest_q <= ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q & ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q & ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q & vCount_uid167_lzcZ_uid51_fpSinPiTest_q & vCount_uid173_lzcZ_uid51_fpSinPiTest_q & vCount_uid179_lzcZ_uid51_fpSinPiTest_q & vCount_uid185_lzcZ_uid51_fpSinPiTest_q; --leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest(BITSELECT,195)@8 leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q; leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in(6 downto 5); --reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1(REG,371)@8 reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest(MUX,196)@9 leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q, leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q; WHEN "01" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ozz_uid41_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest(BITSELECT,206)@8 leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(4 downto 0); leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in(4 downto 3); --reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1(REG,372)@8 reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest(MUX,207)@9 leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s, leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest(BITSELECT,215)@9 LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(72 downto 0); LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in(72 downto 0); --leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest(BITJOIN,216)@9 leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5(REG,374)@9 reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest(BITSELECT,212)@9 LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest(BITJOIN,213)@9 leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4(REG,375)@9 reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest(BITSELECT,209)@9 LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest(BITJOIN,210)@9 leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3(REG,376)@9 reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2(REG,377)@9 reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest(BITSELECT,217)@8 leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(2 downto 0); leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in(2 downto 1); --reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1(REG,373)@8 reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b(DELAY,657)@9 ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest(MUX,218)@10 leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s, reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q, reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q, reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q, reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q) BEGIN CASE leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q; WHEN "01" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q; WHEN "10" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q; WHEN "11" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q; WHEN OTHERS => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest(BITSELECT,222)@8 leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(0 downto 0); leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in(0 downto 0); --reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1(REG,378)@8 reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b(DELAY,665)@9 ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest(MUX,223)@10 leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s, leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q, leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q; WHEN "1" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --alignedZLow_uid53_fpSinPiTest(BITSELECT,52)@10 alignedZLow_uid53_fpSinPiTest_in <= leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q; alignedZLow_uid53_fpSinPiTest_b <= alignedZLow_uid53_fpSinPiTest_in(78 downto 27); --pHardCase_uid54_fpSinPiTest(BITJOIN,53)@10 pHardCase_uid54_fpSinPiTest_q <= alignedZLow_uid53_fpSinPiTest_b & GND_q; --ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b(DELAY,474)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 10 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q, clk => clk, aclr => areset ); --p_uid55_fpSinPiTest(MUX,54)@10 p_uid55_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q; p_uid55_fpSinPiTest: PROCESS (p_uid55_fpSinPiTest_s, pHardCase_uid54_fpSinPiTest_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q) BEGIN CASE p_uid55_fpSinPiTest_s IS WHEN "0" => p_uid55_fpSinPiTest_q <= pHardCase_uid54_fpSinPiTest_q; WHEN "1" => p_uid55_fpSinPiTest_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q; WHEN OTHERS => p_uid55_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt(COUNTER,1121) -- every=1, low=0, high=22, step=1, init=1 ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i = 21 THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i - 22; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i,5)); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg(REG,1122) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux(MUX,1123) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux: PROCESS (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q) BEGIN CASE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s IS WHEN "0" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; WHEN "1" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem(DUALMEM,1120) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 <= areset; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia <= p_uid55_fpSinPiTest_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 5, numwords_a => 23, width_b => 53, widthad_b => 5, numwords_b => 23, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq, address_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa, data_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia ); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq(52 downto 0); --mul2xSinRes_uid69_fpSinPiTest_a_1(BITSELECT,316)@34 mul2xSinRes_uid69_fpSinPiTest_a_1_in <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q); mul2xSinRes_uid69_fpSinPiTest_a_1_b <= mul2xSinRes_uid69_fpSinPiTest_a_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0(REG,424)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b1(MULT,322)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_b); mul2xSinRes_uid69_fpSinPiTest_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1(BITSELECT,329)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1(REG,425)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a_0(BITSELECT,315)@34 mul2xSinRes_uid69_fpSinPiTest_a_0_in <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_a_0_b <= mul2xSinRes_uid69_fpSinPiTest_a_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0(REG,426)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b1(MULT,321)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_b); mul2xSinRes_uid69_fpSinPiTest_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1(BITSELECT,327)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_zero_36(CONSTANT,332) mul2xSinRes_uid69_fpSinPiTest_zero_36_q <= "000000000000000000000000000"; --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2(BITJOIN,336)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1(BITSELECT,328)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_b_0(BITSELECT,317)@34 mul2xSinRes_uid69_fpSinPiTest_b_0_in <= multRightOp_uid68_fpSinPiTest_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_b_0_b <= mul2xSinRes_uid69_fpSinPiTest_b_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1(REG,421)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0(REG,422)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b0(MULT,320)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_b); mul2xSinRes_uid69_fpSinPiTest_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0(BITSELECT,325)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1(BITJOIN,335)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC(LOGICAL,340)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b; --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1(BITSELECT,330)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0(BITSELECT,326)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1(REG,419)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0(REG,420)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b0(MULT,319)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_b); mul2xSinRes_uid69_fpSinPiTest_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0(BITSELECT,324)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0(BITSELECT,323)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0(BITJOIN,334)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC(LOGICAL,339)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB(LOGICAL,338)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne(LOGICAL,341)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c; --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS(BITSELECT,342)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q(106 downto 0); mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in(106 downto 0); --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ(BITJOIN,343)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b & GND_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b(BITJOIN,350)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b(BITSELECT,353)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne(LOGICAL,337)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a(BITJOIN,348)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a(BITSELECT,352)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2(ADD,354)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin <= GND_q; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b) & mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c(0) <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(90); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(89 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b(DELAY,822)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q, clk => clk, aclr => areset ); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a(DELAY,821)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2(ADD,355)@39 mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q) & mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o(20 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a(DELAY,824)@39 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a : dspba_delay GENERIC MAP ( width => 89, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q(BITJOIN,356)@40 mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q; --normBit_uid70_fpSinPiTest(BITSELECT,69)@40 normBit_uid70_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(106 downto 0); normBit_uid70_fpSinPiTest_b <= normBit_uid70_fpSinPiTest_in(106 downto 106); --ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c(DELAY,497)@40 ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => normBit_uid70_fpSinPiTest_b, xout => ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q, clk => clk, aclr => areset ); --rndExpUpdate_uid75_uid76_fpSinPiTest(BITJOIN,75)@41 rndExpUpdate_uid75_uid76_fpSinPiTest_q <= ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q & cstAllZWF_uid10_fpSinPiTest_q & VCC_q; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor(LOGICAL,976) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q <= not (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a or ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top(CONSTANT,972) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q <= "011100"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp(LOGICAL,973) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a = ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b else "0"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg(REG,974) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena(REG,977) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q = "1") THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd(LOGICAL,978) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a and ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem(DUALMEM,941) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 <= areset; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia <= expX_uid6_fpSinPiTest_b; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 3, numwords_a => 7, width_b => 11, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq, address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa, data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia ); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq(10 downto 0); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg(DELAY,940) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q, clk => clk, aclr => areset ); --expXP1_uid58_fpSinPiTest(ADD,57)@9 expXP1_uid58_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q); expXP1_uid58_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & VCC_q); expXP1_uid58_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid58_fpSinPiTest_a) + UNSIGNED(expXP1_uid58_fpSinPiTest_b)); expXP1_uid58_fpSinPiTest_q <= expXP1_uid58_fpSinPiTest_o(11 downto 0); --expXP1R_uid59_fpSinPiTest(BITSELECT,58)@9 expXP1R_uid59_fpSinPiTest_in <= expXP1_uid58_fpSinPiTest_q(10 downto 0); expXP1R_uid59_fpSinPiTest_b <= expXP1R_uid59_fpSinPiTest_in(10 downto 0); --reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1(REG,427)@8 reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= r_uid186_lzcZ_uid51_fpSinPiTest_q; END IF; END PROCESS; --expHardCase_uid57_fpSinPiTest(SUB,56)@9 expHardCase_uid57_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid27_fpSinPiTest_q); expHardCase_uid57_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000" & reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q); expHardCase_uid57_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid57_fpSinPiTest_a) - UNSIGNED(expHardCase_uid57_fpSinPiTest_b)); expHardCase_uid57_fpSinPiTest_q <= expHardCase_uid57_fpSinPiTest_o(11 downto 0); --expHardCaseR_uid60_fpSinPiTest(BITSELECT,59)@9 expHardCaseR_uid60_fpSinPiTest_in <= expHardCase_uid57_fpSinPiTest_q(10 downto 0); expHardCaseR_uid60_fpSinPiTest_b <= expHardCaseR_uid60_fpSinPiTest_in(10 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b(DELAY,481)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 9 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q, clk => clk, aclr => areset ); --expP_uid61_fpSinPiTest(MUX,60)@9 expP_uid61_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q; expP_uid61_fpSinPiTest: PROCESS (expP_uid61_fpSinPiTest_s, expHardCaseR_uid60_fpSinPiTest_b, expXP1R_uid59_fpSinPiTest_b) BEGIN CASE expP_uid61_fpSinPiTest_s IS WHEN "0" => expP_uid61_fpSinPiTest_q <= expHardCaseR_uid60_fpSinPiTest_b; WHEN "1" => expP_uid61_fpSinPiTest_q <= expXP1R_uid59_fpSinPiTest_b; WHEN OTHERS => expP_uid61_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt(COUNTER,968) -- every=1, low=0, high=28, step=1, init=1 ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i = 27 THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i - 28; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg(REG,969) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux(MUX,970) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem(DUALMEM,967) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia <= expP_uid61_fpSinPiTest_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 29, width_b => 11, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq, address_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa, data_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia ); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq(10 downto 0); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg(DELAY,966) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q, xout => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --highRes_uid71_fpSinPiTest(BITSELECT,70)@40 highRes_uid71_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(105 downto 0); highRes_uid71_fpSinPiTest_b <= highRes_uid71_fpSinPiTest_in(105 downto 53); --lowRes_uid72_fpSinPiTest(BITSELECT,71)@40 lowRes_uid72_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(104 downto 0); lowRes_uid72_fpSinPiTest_b <= lowRes_uid72_fpSinPiTest_in(104 downto 52); --fracRCompPreRnd_uid73_fpSinPiTest(MUX,72)@40 fracRCompPreRnd_uid73_fpSinPiTest_s <= normBit_uid70_fpSinPiTest_b; fracRCompPreRnd_uid73_fpSinPiTest: PROCESS (fracRCompPreRnd_uid73_fpSinPiTest_s, lowRes_uid72_fpSinPiTest_b, highRes_uid71_fpSinPiTest_b) BEGIN CASE fracRCompPreRnd_uid73_fpSinPiTest_s IS WHEN "0" => fracRCompPreRnd_uid73_fpSinPiTest_q <= lowRes_uid72_fpSinPiTest_b; WHEN "1" => fracRCompPreRnd_uid73_fpSinPiTest_q <= highRes_uid71_fpSinPiTest_b; WHEN OTHERS => fracRCompPreRnd_uid73_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracPreRnd_uid74_uid74_fpSinPiTest(BITJOIN,73)@40 expFracPreRnd_uid74_uid74_fpSinPiTest_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q & fracRCompPreRnd_uid73_fpSinPiTest_q; --reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0(REG,428)@40 reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= expFracPreRnd_uid74_uid74_fpSinPiTest_q; END IF; END PROCESS; --expFracComp_uid77_fpSinPiTest(ADD,76)@41 expFracComp_uid77_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q); expFracComp_uid77_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & rndExpUpdate_uid75_uid76_fpSinPiTest_q); expFracComp_uid77_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid77_fpSinPiTest_a) + UNSIGNED(expFracComp_uid77_fpSinPiTest_b)); expFracComp_uid77_fpSinPiTest_q <= expFracComp_uid77_fpSinPiTest_o(64 downto 0); --expRComp_uid79_fpSinPiTest(BITSELECT,78)@41 expRComp_uid79_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(63 downto 0); expRComp_uid79_fpSinPiTest_b <= expRComp_uid79_fpSinPiTest_in(63 downto 53); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor(LOGICAL,1015) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q <= not (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a or ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top(CONSTANT,1011) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q <= "0100010"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp(LOGICAL,1012) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q <= "1" when ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a = ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b else "0"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg(REG,1013) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena(REG,1016) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q = "1") THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd(LOGICAL,1017) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a and ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b; --reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1(REG,429)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c(DELAY,516)@0 ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q, xout => ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b(DELAY,515)@0 ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => expXIsZero_uid15_fpSinPiTest_q, xout => ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q, clk => clk, aclr => areset ); --reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0(REG,361)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --excRZero_uid87_fpSinPiTest(LOGICAL,86)@3 excRZero_uid87_fpSinPiTest_a <= reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q; excRZero_uid87_fpSinPiTest_b <= ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q; excRZero_uid87_fpSinPiTest_c <= ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q; excRZero_uid87_fpSinPiTest_q <= excRZero_uid87_fpSinPiTest_a or excRZero_uid87_fpSinPiTest_b or excRZero_uid87_fpSinPiTest_c; --Or2ExcRZeroXIsInt_uid92_fpSinPiTest(LOGICAL,91)@3 Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a <= excRZero_uid87_fpSinPiTest_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b <= reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a or Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt(COUNTER,1007) -- every=1, low=0, high=34, step=1, init=1 ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i = 33 THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i - 34; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg(REG,1008) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux(MUX,1009) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux: PROCESS (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem(DUALMEM,1006) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 35, width_b => 1, widthad_b => 6, numwords_b => 35, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq, address_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa, data_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia ); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg(DELAY,1005) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q, xout => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --expRPostExc1_uid95_fpSinPiTest(MUX,94)@41 expRPostExc1_uid95_fpSinPiTest_s <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q; expRPostExc1_uid95_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE expRPostExc1_uid95_fpSinPiTest_s IS WHEN "0" => expRPostExc1_uid95_fpSinPiTest_q <= expRComp_uid79_fpSinPiTest_b; WHEN "1" => expRPostExc1_uid95_fpSinPiTest_q <= cstAllZWE_uid11_fpSinPiTest_q; WHEN OTHERS => expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --InvXIntExp_uid84_fpSinPiTest(LOGICAL,83)@2 InvXIntExp_uid84_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; InvXIntExp_uid84_fpSinPiTest_q <= not InvXIntExp_uid84_fpSinPiTest_a; --join_uid42_fpSinPiTest(BITJOIN,41)@2 join_uid42_fpSinPiTest_q <= VCC_q & ozz_uid41_fpSinPiTest_q; --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0(REG,359)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid43_fpSinPiTest(LOGICAL,42)@2 yIsZero_uid43_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q; yIsZero_uid43_fpSinPiTest_b <= join_uid42_fpSinPiTest_q; yIsZero_uid43_fpSinPiTest_q <= "1" when yIsZero_uid43_fpSinPiTest_a = yIsZero_uid43_fpSinPiTest_b else "0"; --And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest(LOGICAL,85)@2 And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b <= yIsZero_uid43_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c <= InvSinXIsX_uid80_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d <= InvXIntExp_uid84_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d; --Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest(LOGICAL,95)@1 Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a <= GND_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q <= Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a or Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b; --ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a(DELAY,528)@1 ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q, xout => ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q, clk => clk, aclr => areset ); --join_uid97_fpSinPiTest(BITJOIN,96)@2 join_uid97_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q & ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q; --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg(DELAY,1195) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => join_uid97_fpSinPiTest_q, xout => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q, clk => clk, aclr => areset ); --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem(DUALMEM,1196) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 <= areset; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 6, numwords_a => 37, width_b => 2, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0, clock1 => clk, address_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq, address_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa, data_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia ); ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq(1 downto 0); --reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1(REG,430)@41 reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q; END IF; END PROCESS; --expRPostExc_uid98_fpSinPiTest(MUX,97)@42 expRPostExc_uid98_fpSinPiTest_s <= reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q; expRPostExc_uid98_fpSinPiTest: PROCESS (expRPostExc_uid98_fpSinPiTest_s, expRPostExc1_uid95_fpSinPiTest_q) BEGIN CASE expRPostExc_uid98_fpSinPiTest_s IS WHEN "00" => expRPostExc_uid98_fpSinPiTest_q <= expRPostExc1_uid95_fpSinPiTest_q; WHEN "01" => expRPostExc_uid98_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q; WHEN "10" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN "11" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN OTHERS => expRPostExc_uid98_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --oneFracRPostExc2_uid90_fpSinPiTest(CONSTANT,89) oneFracRPostExc2_uid90_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracRComp_uid78_fpSinPiTest(BITSELECT,77)@41 fracRComp_uid78_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(52 downto 0); fracRComp_uid78_fpSinPiTest_b <= fracRComp_uid78_fpSinPiTest_in(52 downto 1); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor(LOGICAL,989) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q <= not (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a or ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top(CONSTANT,985) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q <= "0100001"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp(LOGICAL,986) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q <= "1" when ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a = ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b else "0"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg(REG,987) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena(REG,990) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q = "1") THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd(LOGICAL,991) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a and ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b; --reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1(REG,362)@3 reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= excRZero_uid87_fpSinPiTest_q; END IF; END PROCESS; --ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a(DELAY,517)@2 ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q, xout => ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q, clk => clk, aclr => areset ); --or_uid88_fpSinPiTest(LOGICAL,87)@4 or_uid88_fpSinPiTest_a <= ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q; or_uid88_fpSinPiTest_b <= reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q; or_uid88_fpSinPiTest_c <= GND_q; or_uid88_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN or_uid88_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN or_uid88_fpSinPiTest_q <= or_uid88_fpSinPiTest_a or or_uid88_fpSinPiTest_b or or_uid88_fpSinPiTest_c; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt(COUNTER,981) -- every=1, low=0, high=33, step=1, init=1 ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i = 32 THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i - 33; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg(REG,982) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux(MUX,983) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux: PROCESS (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem(DUALMEM,980) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia <= or_uid88_fpSinPiTest_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 34, width_b => 1, widthad_b => 6, numwords_b => 34, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq, address_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa, data_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia ); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg(DELAY,979) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q, xout => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --fracRPostExc1_uid89_fpSinPiTest(MUX,88)@41 fracRPostExc1_uid89_fpSinPiTest_s <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q; fracRPostExc1_uid89_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE fracRPostExc1_uid89_fpSinPiTest_s IS WHEN "0" => fracRPostExc1_uid89_fpSinPiTest_q <= fracRComp_uid78_fpSinPiTest_b; WHEN "1" => fracRPostExc1_uid89_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q; WHEN OTHERS => fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor(LOGICAL,1002) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q <= not (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a or ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top(CONSTANT,998) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q <= "0100110"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp(LOGICAL,999) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q <= "1" when ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a = ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b else "0"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg(REG,1000) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena(REG,1003) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q = "1") THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd(LOGICAL,1004) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a and ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg(DELAY,992) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q, xout => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q, clk => clk, aclr => areset ); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt(COUNTER,994) -- every=1, low=0, high=38, step=1, init=1 ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i = 37 THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i - 38; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg(REG,995) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux(MUX,996) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux: PROCESS (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem(DUALMEM,993) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 39, width_b => 1, widthad_b => 6, numwords_b => 39, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq, address_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa, data_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia ); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq(0 downto 0); --fracRPostExc_uid91_fpSinPiTest(MUX,90)@42 fracRPostExc_uid91_fpSinPiTest_s <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q; fracRPostExc_uid91_fpSinPiTest: PROCESS (fracRPostExc_uid91_fpSinPiTest_s, fracRPostExc1_uid89_fpSinPiTest_q) BEGIN CASE fracRPostExc_uid91_fpSinPiTest_s IS WHEN "0" => fracRPostExc_uid91_fpSinPiTest_q <= fracRPostExc1_uid89_fpSinPiTest_q; WHEN "1" => fracRPostExc_uid91_fpSinPiTest_q <= oneFracRPostExc2_uid90_fpSinPiTest_q; WHEN OTHERS => fracRPostExc_uid91_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid105_fpSinPiTest(BITJOIN,104)@42 R_uid105_fpSinPiTest_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q & expRPostExc_uid98_fpSinPiTest_q & fracRPostExc_uid91_fpSinPiTest_q; --ld_xIn_v_to_xOut_v_nor(LOGICAL,910) ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b); --ld_xIn_v_to_xOut_v_mem_top(CONSTANT,906) ld_xIn_v_to_xOut_v_mem_top_q <= "0100111"; --ld_xIn_v_to_xOut_v_cmp(LOGICAL,907) ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q; ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q); ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0"; --ld_xIn_v_to_xOut_v_cmpReg(REG,908) ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_sticky_ena(REG,911) ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q; END IF; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,912) ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q; ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b; --ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,902) -- every=1, low=0, high=39, step=1, init=1 ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 38 THEN ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1'; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; END IF; IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 39; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,6)); --ld_xIn_v_to_xOut_v_replace_rdreg(REG,903) ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_replace_rdmux(MUX,904) ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q; ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q) BEGIN CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q; WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,914) ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset; ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c; ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 6, numwords_a => 40, width_b => 8, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_c_to_xOut_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_c_to_xOut_c_replace_mem_iq, address_a => ld_xIn_c_to_xOut_c_replace_mem_aa, data_a => ld_xIn_c_to_xOut_c_replace_mem_ia ); ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0); --ld_xIn_c_to_xOut_c_outputreg(DELAY,913) ld_xIn_c_to_xOut_c_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset ); --ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,901) ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset; ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v; ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 40, width_b => 1, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_v_to_xOut_v_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_v_to_xOut_v_replace_mem_iq, address_a => ld_xIn_v_to_xOut_v_replace_mem_aa, data_a => ld_xIn_v_to_xOut_v_replace_mem_ia ); ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0); --ld_xIn_v_to_xOut_v_outputreg(DELAY,900) ld_xIn_v_to_xOut_v_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset ); --xOut(PORTOUT,4)@42 xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q; xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q; xOut_0 <= R_uid105_fpSinPiTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Debug Version 12.0 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from SinPiDPStratixVf400 -- VHDL created on Wed Sep 05 17:55:57 2012 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; USE work.SinPiDPStratixVf400_safe_path.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; -- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240 entity SinPiDPStratixVf400 is port ( xIn_v : in std_logic_vector(0 downto 0); xIn_c : in std_logic_vector(7 downto 0); xIn_0 : in std_logic_vector(63 downto 0); xOut_v : out std_logic_vector(0 downto 0); xOut_c : out std_logic_vector(7 downto 0); xOut_0 : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic; bus_clk : in std_logic; h_areset : in std_logic ); end; architecture normal of SinPiDPStratixVf400 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBias_uid12_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBiasPwF_uid13_fpSinPiTest_q : std_logic_vector (10 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0); signal biasM1_uid27_fpSinPiTest_q : std_logic_vector (10 downto 0); signal biasMwShift_uid29_fpSinPiTest_q : std_logic_vector (10 downto 0); signal shiftBias_uid32_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cst01pWShift_uid34_fpSinPiTest_q : std_logic_vector (27 downto 0); signal ozz_uid41_fpSinPiTest_q : std_logic_vector (78 downto 0); signal cOne_uid44_fpSinPiTest_q : std_logic_vector (80 downto 0); signal oneMinusY_uid45_fpSinPiTest_a : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_b : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_o : std_logic_vector (81 downto 0); signal oneMinusY_uid45_fpSinPiTest_q : std_logic_vector (81 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_a : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_b : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_o : std_logic_vector (84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_c : std_logic_vector (0 downto 0); signal piwFP2_uid67_fpSinPiTest_q : std_logic_vector (53 downto 0); signal or_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_b : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_c : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_q : std_logic_vector (51 downto 0); signal oneFracRPostExc2_uid90_fpSinPiTest_q : std_logic_vector (51 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (10 downto 0); signal InvXIsInt_uid100_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIsInt_uid100_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (31 downto 0); signal leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (63 downto 0); signal leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (15 downto 0); signal leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (23 downto 0); signal leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (5 downto 0); signal mO_uid148_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (48 downto 0); signal memoryC3_uid229_sinPiZTableGenerator_q : std_logic_vector(34 downto 0); signal memoryC4_uid230_sinPiZTableGenerator_q : std_logic_vector(25 downto 0); signal memoryC5_uid231_sinPiZTableGenerator_q : std_logic_vector(16 downto 0); signal rndBit_uid246_sinPiZPolyEval_q : std_logic_vector (1 downto 0); signal rndBit_uid258_sinPiZPolyEval_q : std_logic_vector (2 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_a : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 : std_logic_vector (33 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr : SIGNED (34 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_q : std_logic_vector (33 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_a : std_logic_vector (25 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_zero_36_q : std_logic_vector (26 downto 0); type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type; signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q : std_logic_vector (36 downto 0); type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o : std_logic_vector (90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o : std_logic_vector (21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q : std_logic_vector (19 downto 0); signal reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q : std_logic_vector (80 downto 0); signal reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q : std_logic_vector (80 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q : std_logic_vector (0 downto 0); signal reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (31 downto 0); signal reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (15 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (7 downto 0); signal reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q : std_logic_vector (7 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q : std_logic_vector (7 downto 0); signal reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q : std_logic_vector (78 downto 0); signal reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q : std_logic_vector (16 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q : std_logic_vector (25 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q : std_logic_vector (16 downto 0); signal reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q : std_logic_vector (17 downto 0); signal reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q : std_logic_vector (36 downto 0); signal reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q : std_logic_vector (44 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q : std_logic_vector (45 downto 0); signal reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q : std_logic_vector (51 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q : std_logic_vector (53 downto 0); signal reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q : std_logic_vector (60 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q : std_logic_vector (26 downto 0); signal reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q : std_logic_vector (6 downto 0); signal reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q : std_logic_vector (78 downto 0); signal ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q : std_logic_vector (78 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q : std_logic_vector (78 downto 0); signal ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q : std_logic_vector (14 downto 0); signal ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (63 downto 0); signal ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (31 downto 0); signal ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (31 downto 0); signal ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (15 downto 0); signal ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (15 downto 0); signal ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q : std_logic_vector (0 downto 0); signal ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q : std_logic_vector (0 downto 0); signal ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (1 downto 0); signal ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (42 downto 0); signal ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q : std_logic_vector (88 downto 0); signal ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q : std_logic_vector (79 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic; signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic; signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic; signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 : std_logic; signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i : unsigned(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q : std_logic_vector (3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i : unsigned(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q : std_logic_vector (6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i : unsigned(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q : std_logic_vector (2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (14 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ir : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i : unsigned(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q : std_logic_vector (2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ir : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ir : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 : std_logic; signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ir : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0); signal yIsZero_uid40_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (18 downto 0); signal pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal z_uid49_fpSinPiTest_s : std_logic_vector (0 downto 0); signal z_uid49_fpSinPiTest_q : std_logic_vector (78 downto 0); signal expHardCase_uid57_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expHardCase_uid57_fpSinPiTest_q : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_q : std_logic_vector (11 downto 0); signal rndExpUpdate_uid75_uid76_fpSinPiTest_q : std_logic_vector (53 downto 0); signal expFracComp_uid77_fpSinPiTest_a : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_b : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_o : std_logic_vector (64 downto 0); signal expFracComp_uid77_fpSinPiTest_q : std_logic_vector (64 downto 0); signal fracRPostExc_uid91_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc_uid91_fpSinPiTest_q : std_logic_vector (51 downto 0); signal expRPostExc_uid98_fpSinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid98_fpSinPiTest_q : std_logic_vector (10 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal memoryC0_uid226_sinPiZTableGenerator_q : std_logic_vector(57 downto 0); signal memoryC1_uid227_sinPiZTableGenerator_q : std_logic_vector(49 downto 0); signal memoryC2_uid228_sinPiZTableGenerator_q : std_logic_vector(42 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_a : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_b : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_o : std_logic_vector (35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_q : std_logic_vector (35 downto 0); signal ts3_uid248_sinPiZPolyEval_a : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_b : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_o : std_logic_vector (45 downto 0); signal ts3_uid248_sinPiZPolyEval_q : std_logic_vector (45 downto 0); signal ts4_uid254_sinPiZPolyEval_a : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_b : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_o : std_logic_vector (52 downto 0); signal ts4_uid254_sinPiZPolyEval_q : std_logic_vector (52 downto 0); signal ts5_uid260_sinPiZPolyEval_a : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_b : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_o : std_logic_vector (61 downto 0); signal ts5_uid260_sinPiZPolyEval_q : std_logic_vector (61 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal join_uid42_fpSinPiTest_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal expX_uid6_fpSinPiTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSinPiTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSinPiTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSinPiTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0); signal expXIsMax_uid16_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSinPiTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid15_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_q : std_logic_vector(0 downto 0); signal xIntExp_uid26_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xIntExp_uid26_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xIntExp_uid26_fpSinPiTest_c : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xFrac_uid28_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_n : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_a : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_b : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_o : std_logic_vector (13 downto 0); signal sinXIsX_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0); signal shiftValue_uid33_fpSinPiTest_a : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_b : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_o : std_logic_vector (11 downto 0); signal shiftValue_uid33_fpSinPiTest_q : std_logic_vector (11 downto 0); signal oMyBottom_uid47_fpSinPiTest_in : std_logic_vector (78 downto 0); signal oMyBottom_uid47_fpSinPiTest_b : std_logic_vector (78 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid150_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal cIncludingRoundingBit_uid247_sinPiZPolyEval_q : std_logic_vector (44 downto 0); signal cIncludingRoundingBit_uid253_sinPiZPolyEval_q : std_logic_vector (51 downto 0); signal cIncludingRoundingBit_uid259_sinPiZPolyEval_q : std_logic_vector (60 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q : std_logic_vector (107 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (29 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (46 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q : std_logic_vector (108 downto 0); signal yIsZero_uid43_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zPPolyEval_uid64_fpSinPiTest_in : std_logic_vector (71 downto 0); signal zPPolyEval_uid64_fpSinPiTest_b : std_logic_vector (44 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_q : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_c : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (31 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (15 downto 0); signal s2_uid240_uid243_sinPiZPolyEval_q : std_logic_vector (36 downto 0); signal add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (55 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (42 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (72 downto 0); signal add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal R_uid105_fpSinPiTest_q : std_logic_vector (63 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal yT3_uid244_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT3_uid244_sinPiZPolyEval_b : std_logic_vector (34 downto 0); signal yT4_uid250_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT4_uid250_sinPiZPolyEval_b : std_logic_vector (42 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q : std_logic_vector(0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_b : std_logic_vector (26 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zAddr_uid63_fpSinPiTest_in : std_logic_vector (78 downto 0); signal zAddr_uid63_fpSinPiTest_b : std_logic_vector (6 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (78 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (63 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (14 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (14 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (46 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (46 downto 0); signal expHardCaseR_uid60_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expHardCaseR_uid60_fpSinPiTest_b : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracRComp_uid78_fpSinPiTest_in : std_logic_vector (52 downto 0); signal fracRComp_uid78_fpSinPiTest_b : std_logic_vector (51 downto 0); signal expRComp_uid79_fpSinPiTest_in : std_logic_vector (63 downto 0); signal expRComp_uid79_fpSinPiTest_b : std_logic_vector (10 downto 0); signal intXParity_uid38_fpSinPiTest_in : std_logic_vector (80 downto 0); signal intXParity_uid38_fpSinPiTest_b : std_logic_vector (0 downto 0); signal y_uid39_fpSinPiTest_in : std_logic_vector (79 downto 0); signal y_uid39_fpSinPiTest_b : std_logic_vector (79 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (77 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (77 downto 0); signal s3_uid249_sinPiZPolyEval_in : std_logic_vector (45 downto 0); signal s3_uid249_sinPiZPolyEval_b : std_logic_vector (44 downto 0); signal s4_uid255_sinPiZPolyEval_in : std_logic_vector (52 downto 0); signal s4_uid255_sinPiZPolyEval_b : std_logic_vector (51 downto 0); signal s5_uid261_sinPiZPolyEval_in : std_logic_vector (61 downto 0); signal s5_uid261_sinPiZPolyEval_b : std_logic_vector (60 downto 0); signal oFracX_uid31_uid31_fpSinPiTest_q : std_logic_vector (52 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_in : std_logic_vector (6 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_b : std_logic_vector (6 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid235_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal highBBits_uid235_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid241_sinPiZPolyEval_in : std_logic_vector (28 downto 0); signal highBBits_uid241_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q : std_logic_vector(107 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (29 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (46 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal normBit_uid70_fpSinPiTest_in : std_logic_vector (106 downto 0); signal normBit_uid70_fpSinPiTest_b : std_logic_vector (0 downto 0); signal highRes_uid71_fpSinPiTest_in : std_logic_vector (105 downto 0); signal highRes_uid71_fpSinPiTest_b : std_logic_vector (52 downto 0); signal lowRes_uid72_fpSinPiTest_in : std_logic_vector (104 downto 0); signal lowRes_uid72_fpSinPiTest_b : std_logic_vector (52 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (70 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (70 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (62 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (62 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (54 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (54 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q : std_logic_vector(0 downto 0); signal yT1_uid232_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT1_uid232_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal yT2_uid238_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT2_uid238_sinPiZPolyEval_b : std_logic_vector (25 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (63 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (9 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (9 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (36 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (71 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (45 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (78 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (7 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (7 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (15 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (15 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expP_uid61_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expP_uid61_fpSinPiTest_q : std_logic_vector (10 downto 0); signal yBottom_uid48_fpSinPiTest_in : std_logic_vector (78 downto 0); signal yBottom_uid48_fpSinPiTest_b : std_logic_vector (78 downto 0); signal leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (51 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal fxpSinRes_uid66_fpSinPiTest_in : std_logic_vector (58 downto 0); signal fxpSinRes_uid66_fpSinPiTest_b : std_logic_vector (53 downto 0); signal extendedFracX_uid35_fpSinPiTest_q : std_logic_vector (80 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (0 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_a : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_b : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_o : std_logic_vector (26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q : std_logic_vector(107 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_q : std_logic_vector (52 downto 0); signal join_uid97_fpSinPiTest_q : std_logic_vector (1 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal signR_uid104_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (10 downto 0); signal pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (16 downto 0); signal pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal xIsInt_uid83_fpSinPiTest_a : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_b : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal multRightOp_uid68_fpSinPiTest_s : std_logic_vector (0 downto 0); signal multRightOp_uid68_fpSinPiTest_q : std_logic_vector (53 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (48 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (48 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (16 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (16 downto 0); signal s1_uid234_uid237_sinPiZPolyEval_q : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c : std_logic_vector (19 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in : std_logic_vector (106 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b : std_logic_vector (106 downto 0); signal expFracPreRnd_uid74_uid74_fpSinPiTest_q : std_logic_vector (63 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (17 downto 0); signal alignedZLow_uid53_fpSinPiTest_in : std_logic_vector (78 downto 0); signal alignedZLow_uid53_fpSinPiTest_b : std_logic_vector (51 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_b : std_logic_vector (26 downto 0); signal leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q : std_logic_vector (107 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (1 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (74 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (72 downto 0); signal pHardCase_uid54_fpSinPiTest_q : std_logic_vector (52 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q : std_logic_vector (108 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (0 downto 0); signal leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal p_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0); signal p_uid55_fpSinPiTest_q : std_logic_vector (52 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (72 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (64 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (64 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (56 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (56 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c : std_logic_vector (19 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal r_uid186_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (6 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (0 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (78 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (78 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (74 downto 0); signal leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (79 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (79 downto 0); signal leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); begin --ld_xIn_v_to_xOut_v_notEnable(LOGICAL,909) ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q; ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor(LOGICAL,1028) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q <= not (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a or ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top(CONSTANT,1024) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q <= "0100100"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp(LOGICAL,1025) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q <= "1" when ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a = ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b else "0"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg(REG,1026) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena(REG,1029) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q = "1") THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd(LOGICAL,1030) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a and ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b; --LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest(BITSELECT,134)@0 LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest(CONSTANT,133) leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q <= "000000"; --leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest(BITJOIN,135)@0 leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest(BITSELECT,131)@0 LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest(CONSTANT,130) leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q <= "0000"; --leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest(BITJOIN,132)@0 leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest(BITSELECT,128)@0 LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(78 downto 0); LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in(78 downto 0); --leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest(CONSTANT,127) leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q <= "00"; --leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest(BITJOIN,129)@0 leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest(BITSELECT,123)@0 LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(56 downto 0); LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in(56 downto 0); --leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest(CONSTANT,122) leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000"; --leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest(BITJOIN,124)@0 leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest(BITSELECT,120)@0 LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(64 downto 0); LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in(64 downto 0); --leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest(CONSTANT,119) leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000"; --leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest(BITJOIN,121)@0 leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest(BITSELECT,117)@0 LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(72 downto 0); LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in(72 downto 0); --leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest(CONSTANT,116) leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q <= "00000000"; --leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest(BITJOIN,118)@0 leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest(CONSTANT,113) leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; --X16dto0_uid112_fixedPointX_uid37_fpSinPiTest(BITSELECT,111)@0 X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(16 downto 0); X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in(16 downto 0); --leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest(CONSTANT,110) leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000"; --leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest(BITJOIN,112)@0 leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X48dto0_uid109_fixedPointX_uid37_fpSinPiTest(BITSELECT,108)@0 X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(48 downto 0); X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in(48 downto 0); --leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest(CONSTANT,107) leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q <= "00000000000000000000000000000000"; --leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest(BITJOIN,109)@0 leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --cst01pWShift_uid34_fpSinPiTest(CONSTANT,33) cst01pWShift_uid34_fpSinPiTest_q <= "0000000000000000000000000000"; --xIn(PORTIN,3)@0 --fracX_uid7_fpSinPiTest(BITSELECT,6)@0 fracX_uid7_fpSinPiTest_in <= xIn_0(51 downto 0); fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(51 downto 0); --oFracX_uid31_uid31_fpSinPiTest(BITJOIN,30)@0 oFracX_uid31_uid31_fpSinPiTest_q <= VCC_q & fracX_uid7_fpSinPiTest_b; --extendedFracX_uid35_fpSinPiTest(BITJOIN,34)@0 extendedFracX_uid35_fpSinPiTest_q <= cst01pWShift_uid34_fpSinPiTest_q & oFracX_uid31_uid31_fpSinPiTest_q; --shiftBias_uid32_fpSinPiTest(CONSTANT,31) shiftBias_uid32_fpSinPiTest_q <= "01111100011"; --expX_uid6_fpSinPiTest(BITSELECT,5)@0 expX_uid6_fpSinPiTest_in <= xIn_0(62 downto 0); expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(62 downto 52); --shiftValue_uid33_fpSinPiTest(SUB,32)@0 shiftValue_uid33_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b); shiftValue_uid33_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid32_fpSinPiTest_q); shiftValue_uid33_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid33_fpSinPiTest_a) - UNSIGNED(shiftValue_uid33_fpSinPiTest_b)); shiftValue_uid33_fpSinPiTest_q <= shiftValue_uid33_fpSinPiTest_o(11 downto 0); --fxpShifterBits_uid36_fpSinPiTest(BITSELECT,35)@0 fxpShifterBits_uid36_fpSinPiTest_in <= shiftValue_uid33_fpSinPiTest_q(6 downto 0); fxpShifterBits_uid36_fpSinPiTest_b <= fxpShifterBits_uid36_fpSinPiTest_in(6 downto 0); --leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest(BITSELECT,114)@0 leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b; leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in(6 downto 5); --leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest(MUX,115)@0 leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s, extendedFracX_uid35_fpSinPiTest_q, leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= extendedFracX_uid35_fpSinPiTest_q; WHEN "01" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest(BITSELECT,125)@0 leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(4 downto 0); leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in(4 downto 3); --leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest(MUX,126)@0 leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest(BITSELECT,136)@0 leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(2 downto 0); leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in(2 downto 1); --leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest(MUX,137)@0 leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest(BITSELECT,139)@0 LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in(79 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest(BITJOIN,140)@0 leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b & GND_q; --reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3(REG,357)@0 reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2(REG,358)@0 reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest(BITSELECT,141)@0 leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(0 downto 0); leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in(0 downto 0); --ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b(DELAY,581)@0 ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest(MUX,142)@1 leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q; leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s, reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q, reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q) BEGIN CASE leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q; WHEN "1" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q; WHEN OTHERS => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --intXParity_uid38_fpSinPiTest(BITSELECT,37)@1 intXParity_uid38_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q; intXParity_uid38_fpSinPiTest_b <= intXParity_uid38_fpSinPiTest_in(80 downto 80); --ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c(DELAY,536)@1 ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => intXParity_uid38_fpSinPiTest_b, xout => ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q, clk => clk, aclr => areset ); --biasM1_uid27_fpSinPiTest(CONSTANT,26) biasM1_uid27_fpSinPiTest_q <= "01111111110"; --xFrac_uid28_fpSinPiTest(COMPARE,27)@0 xFrac_uid28_fpSinPiTest_cin <= GND_q; xFrac_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid27_fpSinPiTest_q) & '0'; xFrac_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid28_fpSinPiTest_cin(0); xFrac_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid28_fpSinPiTest_a) - UNSIGNED(xFrac_uid28_fpSinPiTest_b)); xFrac_uid28_fpSinPiTest_n(0) <= not xFrac_uid28_fpSinPiTest_o(13); --ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a(DELAY,532)@0 ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => xFrac_uid28_fpSinPiTest_n, xout => ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvXFrac_uid99_fpSinPiTest(LOGICAL,98)@3 InvXFrac_uid99_fpSinPiTest_a <= ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q; InvXFrac_uid99_fpSinPiTest_q <= not InvXFrac_uid99_fpSinPiTest_a; --biasMwShift_uid29_fpSinPiTest(CONSTANT,28) biasMwShift_uid29_fpSinPiTest_q <= "01111100100"; --sinXIsX_uid30_fpSinPiTest(COMPARE,29)@0 sinXIsX_uid30_fpSinPiTest_cin <= GND_q; sinXIsX_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0'; sinXIsX_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid29_fpSinPiTest_q) & sinXIsX_uid30_fpSinPiTest_cin(0); sinXIsX_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid30_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid30_fpSinPiTest_b)); sinXIsX_uid30_fpSinPiTest_c(0) <= sinXIsX_uid30_fpSinPiTest_o(13); --ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a(DELAY,502)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvSinXIsX_uid80_fpSinPiTest(LOGICAL,79)@2 InvSinXIsX_uid80_fpSinPiTest_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q; InvSinXIsX_uid80_fpSinPiTest_q <= not InvSinXIsX_uid80_fpSinPiTest_a; --y_uid39_fpSinPiTest(BITSELECT,38)@1 y_uid39_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); y_uid39_fpSinPiTest_b <= y_uid39_fpSinPiTest_in(79 downto 0); --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0(REG,360)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid40_fpSinPiTest(LOGICAL,39)@2 yIsZero_uid40_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q; yIsZero_uid40_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000000000000000000000000000000000000000000000000" & GND_q); yIsZero_uid40_fpSinPiTest_q <= "1" when yIsZero_uid40_fpSinPiTest_a = yIsZero_uid40_fpSinPiTest_b else "0"; --And2YIsZeroInvSinXIsX_uid81_fpSinPiTest(LOGICAL,80)@2 And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a <= yIsZero_uid40_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b <= InvSinXIsX_uid80_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a and And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b; --cstBiasPwF_uid13_fpSinPiTest(CONSTANT,12) cstBiasPwF_uid13_fpSinPiTest_q <= "10000110011"; --xIntExp_uid26_fpSinPiTest(COMPARE,25)@0 xIntExp_uid26_fpSinPiTest_cin <= GND_q; xIntExp_uid26_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid13_fpSinPiTest_q) & '0'; xIntExp_uid26_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid26_fpSinPiTest_cin(0); xIntExp_uid26_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid26_fpSinPiTest_a) - UNSIGNED(xIntExp_uid26_fpSinPiTest_b)); xIntExp_uid26_fpSinPiTest_c(0) <= xIntExp_uid26_fpSinPiTest_o(13); --ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a(DELAY,505)@0 ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => xIntExp_uid26_fpSinPiTest_c, xout => ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q, clk => clk, aclr => areset ); --Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest(LOGICAL,81)@2 Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a or Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b; --cstAllZWF_uid10_fpSinPiTest(CONSTANT,9) cstAllZWF_uid10_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracXIsZero_uid17_fpSinPiTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b; fracXIsZero_uid17_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q; fracXIsZero_uid17_fpSinPiTest_q <= "1" when fracXIsZero_uid17_fpSinPiTest_a = fracXIsZero_uid17_fpSinPiTest_b else "0"; --ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a(DELAY,442)@0 ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => fracXIsZero_uid17_fpSinPiTest_q, xout => ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvFracXIsZero_uid19_fpSinPiTest(LOGICAL,18)@1 InvFracXIsZero_uid19_fpSinPiTest_a <= ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q; InvFracXIsZero_uid19_fpSinPiTest_q <= not InvFracXIsZero_uid19_fpSinPiTest_a; --cstAllOWE_uid9_fpSinPiTest(CONSTANT,8) cstAllOWE_uid9_fpSinPiTest_q <= "11111111111"; --expXIsMax_uid16_fpSinPiTest(LOGICAL,15)@0 expXIsMax_uid16_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsMax_uid16_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q; expXIsMax_uid16_fpSinPiTest_q <= "1" when expXIsMax_uid16_fpSinPiTest_a = expXIsMax_uid16_fpSinPiTest_b else "0"; --ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a(DELAY,443)@0 ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsMax_uid16_fpSinPiTest_q, xout => ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest(LOGICAL,19)@1 And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a <= ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b <= InvFracXIsZero_uid19_fpSinPiTest_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a and And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b; --InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest(LOGICAL,20)@1 InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q <= not InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a; --And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0 And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a <= expXIsMax_uid16_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b <= fracXIsZero_uid17_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a and And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b; --InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0 InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q; InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q <= not InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a; --cstAllZWE_uid11_fpSinPiTest(CONSTANT,10) cstAllZWE_uid11_fpSinPiTest_q <= "00000000000"; --expXIsZero_uid15_fpSinPiTest(LOGICAL,14)@0 expXIsZero_uid15_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsZero_uid15_fpSinPiTest_b <= cstAllZWE_uid11_fpSinPiTest_q; expXIsZero_uid15_fpSinPiTest_q <= "1" when expXIsZero_uid15_fpSinPiTest_a = expXIsZero_uid15_fpSinPiTest_b else "0"; --InvExpXIsZero_uid23_fpSinPiTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSinPiTest_a <= expXIsZero_uid15_fpSinPiTest_q; InvExpXIsZero_uid23_fpSinPiTest_q <= not InvExpXIsZero_uid23_fpSinPiTest_a; --And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0 And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a <= InvExpXIsZero_uid23_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b <= InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a and And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b; --ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a(DELAY,450)@0 ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q, xout => ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest(LOGICAL,24)@1 And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a <= ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b <= InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a and And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b; END IF; END PROCESS; --xIsInt_uid83_fpSinPiTest(LOGICAL,82)@2 xIsInt_uid83_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_b <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_q <= xIsInt_uid83_fpSinPiTest_a and xIsInt_uid83_fpSinPiTest_b; --InvXIsInt_uid100_fpSinPiTest(LOGICAL,99)@2 InvXIsInt_uid100_fpSinPiTest_a <= xIsInt_uid83_fpSinPiTest_q; InvXIsInt_uid100_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= not InvXIsInt_uid100_fpSinPiTest_a; END IF; END PROCESS; --signComp_uid101_fpSinPiTest(LOGICAL,100)@3 signComp_uid101_fpSinPiTest_a <= InvXIsInt_uid100_fpSinPiTest_q; signComp_uid101_fpSinPiTest_b <= InvXFrac_uid99_fpSinPiTest_q; signComp_uid101_fpSinPiTest_c <= ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q; signComp_uid101_fpSinPiTest_q <= signComp_uid101_fpSinPiTest_a and signComp_uid101_fpSinPiTest_b and signComp_uid101_fpSinPiTest_c; --ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a(DELAY,537)@2 ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => yIsZero_uid40_fpSinPiTest_q, xout => ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvYIsZero_uid102_fpSinPiTest(LOGICAL,101)@3 InvYIsZero_uid102_fpSinPiTest_a <= ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q; InvYIsZero_uid102_fpSinPiTest_q <= not InvYIsZero_uid102_fpSinPiTest_a; --And2InvYIsZeroSignComp_uid103_fpSinPiTest(LOGICAL,102)@3 And2InvYIsZeroSignComp_uid103_fpSinPiTest_a <= InvYIsZero_uid102_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_b <= signComp_uid101_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_q <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_a and And2InvYIsZeroSignComp_uid103_fpSinPiTest_b; --signX_uid8_fpSinPiTest(BITSELECT,7)@0 signX_uid8_fpSinPiTest_in <= xIn_0; signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(63 downto 63); --ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a(DELAY,540)@0 ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q, clk => clk, aclr => areset ); --signR_uid104_fpSinPiTest(LOGICAL,103)@3 signR_uid104_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q; signR_uid104_fpSinPiTest_b <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_q; signR_uid104_fpSinPiTest_q <= signR_uid104_fpSinPiTest_a xor signR_uid104_fpSinPiTest_b; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt(COUNTER,1020) -- every=1, low=0, high=36, step=1, init=1 ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i = 35 THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i - 36; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i,6)); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg(REG,1021) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --VCC(CONSTANT,1) VCC_q <= "1"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux(MUX,1022) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux: PROCESS (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem(DUALMEM,1019) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia <= signR_uid104_fpSinPiTest_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 37, width_b => 1, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq, address_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa, data_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia ); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq(0 downto 0); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg(DELAY,1018) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q, xout => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --cstBias_uid12_fpSinPiTest(CONSTANT,11) cstBias_uid12_fpSinPiTest_q <= "01111111111"; --piwFP2_uid67_fpSinPiTest(CONSTANT,66) piwFP2_uid67_fpSinPiTest_q <= "110010010000111111011010101000100010000101101000110001"; --reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1(REG,363)@1 reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --cOne_uid44_fpSinPiTest(CONSTANT,43) cOne_uid44_fpSinPiTest_q <= "100000000000000000000000000000000000000000000000000000000000000000000000000000000"; --oneMinusY_uid45_fpSinPiTest(SUB,44)@2 oneMinusY_uid45_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid44_fpSinPiTest_q); oneMinusY_uid45_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q); oneMinusY_uid45_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid45_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid45_fpSinPiTest_b)); END IF; END PROCESS; oneMinusY_uid45_fpSinPiTest_q <= oneMinusY_uid45_fpSinPiTest_o(81 downto 0); --oMyBottom_uid47_fpSinPiTest(BITSELECT,46)@3 oMyBottom_uid47_fpSinPiTest_in <= oneMinusY_uid45_fpSinPiTest_q(78 downto 0); oMyBottom_uid47_fpSinPiTest_b <= oMyBottom_uid47_fpSinPiTest_in(78 downto 0); --ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d(DELAY,471)@3 ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => oMyBottom_uid47_fpSinPiTest_b, xout => ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q, clk => clk, aclr => areset ); --yBottom_uid48_fpSinPiTest(BITSELECT,47)@1 yBottom_uid48_fpSinPiTest_in <= y_uid39_fpSinPiTest_b(78 downto 0); yBottom_uid48_fpSinPiTest_b <= yBottom_uid48_fpSinPiTest_in(78 downto 0); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c(DELAY,470)@1 ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 79, depth => 2 ) PORT MAP ( xin => yBottom_uid48_fpSinPiTest_b, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg(DELAY,926) ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a(DELAY,833)@1 ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a : dspba_delay GENERIC MAP ( width => 80, depth => 1 ) PORT MAP ( xin => y_uid39_fpSinPiTest_b, xout => ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q, clk => clk, aclr => areset ); --reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1(REG,364)@2 reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q; END IF; END PROCESS; --cmpYToOneMinusY_uid46_fpSinPiTest(COMPARE,45)@3 cmpYToOneMinusY_uid46_fpSinPiTest_cin <= GND_q; cmpYToOneMinusY_uid46_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & oneMinusY_uid45_fpSinPiTest_q) & '0'; cmpYToOneMinusY_uid46_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q) & cmpYToOneMinusY_uid46_fpSinPiTest_cin(0); cmpYToOneMinusY_uid46_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_b)); END IF; END PROCESS; cmpYToOneMinusY_uid46_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid46_fpSinPiTest_o(84); --z_uid49_fpSinPiTest(MUX,48)@4 z_uid49_fpSinPiTest_s <= cmpYToOneMinusY_uid46_fpSinPiTest_c; z_uid49_fpSinPiTest: PROCESS (z_uid49_fpSinPiTest_s, ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q) BEGIN CASE z_uid49_fpSinPiTest_s IS WHEN "0" => z_uid49_fpSinPiTest_q <= ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q; WHEN "1" => z_uid49_fpSinPiTest_q <= ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q; WHEN OTHERS => z_uid49_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --zAddr_uid63_fpSinPiTest(BITSELECT,62)@4 zAddr_uid63_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; zAddr_uid63_fpSinPiTest_b <= zAddr_uid63_fpSinPiTest_in(78 downto 72); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0(REG,382)@4 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= zAddr_uid63_fpSinPiTest_b; END IF; END PROCESS; --memoryC5_uid231_sinPiZTableGenerator(LOOKUP,230)@5 memoryC5_uid231_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; WHEN "0000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111110101101000"; WHEN "0000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111101101011101"; WHEN "0000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100110001110"; WHEN "0000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100000000010"; WHEN "0000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111011000000000"; WHEN "0000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111010001101101"; WHEN "0000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111001010010111"; WHEN "0001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111000010110010"; WHEN "0001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110111100010100"; WHEN "0001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110110100011111"; WHEN "0001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110101100101101"; WHEN "0001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110100101101011"; WHEN "0001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110011111011101"; WHEN "0001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010111001010"; WHEN "0001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010001011011"; WHEN "0010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110001010101011"; WHEN "0010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110000011011001"; WHEN "0010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101111011000001"; WHEN "0010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101110101001010"; WHEN "0010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101101110100110"; WHEN "0010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101100111100011"; WHEN "0010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011111111111"; WHEN "0010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011001001010"; WHEN "0011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101010010100110"; WHEN "0011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101001010011011"; WHEN "0011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101000100011100"; WHEN "0011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100111101010110"; WHEN "0011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100110110111000"; WHEN "0011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100101111110010"; WHEN "0011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100111110010"; WHEN "0011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100001010101"; WHEN "0100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100011011011111"; WHEN "0100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100010011110111"; WHEN "0100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100001110001010"; WHEN "0100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100000111000100"; WHEN "0100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111111110101"; WHEN "0100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111001010110"; WHEN "0100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011110011000111"; WHEN "0100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011101101000000"; WHEN "0101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011100110000011"; WHEN "0101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011111111001"; WHEN "0101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011000100110"; WHEN "0101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011010010101100"; WHEN "0101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011001100010010"; WHEN "0101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011000101010111"; WHEN "0101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111111101010"; WHEN "0101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111001010000"; WHEN "0110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010110011010011"; WHEN "0110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010101100101011"; WHEN "0110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010100110111110"; WHEN "0110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011111111000"; WHEN "0110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011010110010"; WHEN "0110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010010101001110"; WHEN "0110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001110010011"; WHEN "0110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001000111011"; WHEN "0111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010000001111011"; WHEN "0111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001111011111110"; WHEN "0111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110111001010"; WHEN "0111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110001110111"; WHEN "0111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001101011000100"; WHEN "0111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100101010010"; WHEN "0111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100000011111"; WHEN "0111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001011010001010"; WHEN "1000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001010100111110"; WHEN "1000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001110110010"; WHEN "1000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001010111000"; WHEN "1000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001000100111111"; WHEN "1000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111111001100"; WHEN "1000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111010001001"; WHEN "1000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110101010110"; WHEN "1000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110000011101"; WHEN "1001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000101001110100"; WHEN "1001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000100101111001"; WHEN "1001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011111111010"; WHEN "1001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011011110110"; WHEN "1001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010110001100"; WHEN "1001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010001001000"; WHEN "1001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001101111001"; WHEN "1001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001000000111"; WHEN "1010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000000010111001"; WHEN "1010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111110110110"; WHEN "1010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111001111111"; WHEN "1010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110110010100"; WHEN "1010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110001011000"; WHEN "1010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101100010111"; WHEN "1010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101000010010"; WHEN "1010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100100010000"; WHEN "1011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100000111100"; WHEN "1011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111011011111111"; WHEN "1011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010111100000"; WHEN "1011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010011110100"; WHEN "1011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010000011100"; WHEN "1011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111001011011110"; WHEN "1011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000111111101"; WHEN "1011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000100101011"; WHEN "1100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000001100100"; WHEN "1100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111101101110"; WHEN "1100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111010011000"; WHEN "1100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110110110000"; WHEN "1100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110010011010"; WHEN "1100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110000011110"; WHEN "1100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101100101100"; WHEN "1100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101000101110"; WHEN "1101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100110100000"; WHEN "1101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100100010001"; WHEN "1101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100001000000"; WHEN "1101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011101101110"; WHEN "1101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011011011111"; WHEN "1101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010111000100"; WHEN "1101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010101110011"; WHEN "1101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010001111100"; WHEN "1110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010000001111"; WHEN "1110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001110011001"; WHEN "1110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001010100010"; WHEN "1110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000111111000"; WHEN "1110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101110110"; WHEN "1110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101000100"; WHEN "1110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000010100010"; WHEN "1110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111111110011"; WHEN "1111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111110010000"; WHEN "1111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111100110111"; WHEN "1111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111010111000"; WHEN "1111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111000101000"; WHEN "1111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110110110100"; WHEN "1111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110101011010"; WHEN "1111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110100000011"; WHEN "1111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110010001011"; WHEN OTHERS => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; END CASE; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a(DELAY,485)@4 ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => z_uid49_fpSinPiTest_q, xout => ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q, clk => clk, aclr => areset ); --zPPolyEval_uid64_fpSinPiTest(BITSELECT,63)@5 zPPolyEval_uid64_fpSinPiTest_in <= ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q(71 downto 0); zPPolyEval_uid64_fpSinPiTest_b <= zPPolyEval_uid64_fpSinPiTest_in(71 downto 27); --yT1_uid232_sinPiZPolyEval(BITSELECT,231)@5 yT1_uid232_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT1_uid232_sinPiZPolyEval_b <= yT1_uid232_sinPiZPolyEval_in(44 downto 28); --reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0(REG,383)@5 reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= yT1_uid232_sinPiZPolyEval_b; END IF; END PROCESS; --prodXY_uid263_pT1_uid233_sinPiZPolyEval(MULT,262)@6 prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_a),18)) * SIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_b); prodXY_uid263_pT1_uid233_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= memoryC5_uid231_sinPiZTableGenerator_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr,34)); END IF; END PROCESS; prodXY_uid263_pT1_uid233_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval(BITSELECT,263)@9 prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_q; prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in(33 downto 16); --highBBits_uid235_sinPiZPolyEval(BITSELECT,234)@9 highBBits_uid235_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b; highBBits_uid235_sinPiZPolyEval_b <= highBBits_uid235_sinPiZPolyEval_in(17 downto 1); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a(DELAY,853)@4 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a : dspba_delay GENERIC MAP ( width => 7, depth => 3 ) PORT MAP ( xin => zAddr_uid63_fpSinPiTest_b, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0(REG,384)@7 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q; END IF; END PROCESS; --memoryC4_uid230_sinPiZTableGenerator(LOOKUP,229)@8 memoryC4_uid230_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; WHEN "0000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110011111111100"; WHEN "0000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100101101100110011"; WHEN "0000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100100010011000101"; WHEN "0000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100010010010010110"; WHEN "0000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011111110011000100"; WHEN "0000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011100101011001100"; WHEN "0000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011001000001111000"; WHEN "0001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010100110101100100"; WHEN "0001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010000000010110001"; WHEN "0001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001001010101111100100"; WHEN "0001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001000100111000100010"; WHEN "0001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000111110011011110101"; WHEN "0001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000110111011001010101"; WHEN "0001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000101111111000110001"; WHEN "0001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000100111101101111110"; WHEN "0010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000011111000010010110"; WHEN "0010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000010101110100101111"; WHEN "0010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000001100000110110101"; WHEN "0010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000000001101111000000"; WHEN "0010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111110110110101110011"; WHEN "0010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111101011011010111001"; WHEN "0010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111011111011110000110"; WHEN "0010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111010010111100110100"; WHEN "0011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111000101110111111001"; WHEN "0011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110111000010100011101"; WHEN "0011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110101010001000110011"; WHEN "0011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110011011011101100111"; WHEN "0011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110001100001110001111"; WHEN "0011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101111100011110001010"; WHEN "0011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101101100001110100101"; WHEN "0011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101011011011000110110"; WHEN "0100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101001001111111101110"; WHEN "0100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100111000001001001111"; WHEN "0100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100100101101100011001"; WHEN "0100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100010010110001110000"; WHEN "0100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011111111010101110110"; WHEN "0100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011101011010111000111"; WHEN "0100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011010110110110011110"; WHEN "0100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011000001110100011110"; WHEN "0101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010101100010100010011"; WHEN "0101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010010110010001000111"; WHEN "0101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001111111110001000100"; WHEN "0101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001101000101100110110"; WHEN "0101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001010001001001111011"; WHEN "0101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000111001001000001110"; WHEN "0101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000100000100011110110"; WHEN "0101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000000111100001111001"; WHEN "0110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111101101111111011111"; WHEN "0110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111010011111111100110"; WHEN "0110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110111001011110100100"; WHEN "0110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110011110100010000111"; WHEN "0110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110000011000010001001"; WHEN "0110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101100111000101000011"; WHEN "0110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101001010101101011111"; WHEN "0110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100101101110011101110"; WHEN "0111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100010000100000111110"; WHEN "0111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011110010101101110100"; WHEN "0111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011010100011010011110"; WHEN "0111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010110101101011010111"; WHEN "0111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010010110100011011101"; WHEN "0111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001110110111100001001"; WHEN "0111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001010110110110010000"; WHEN "0111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000110110011000001101"; WHEN "1000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000010101011011011001"; WHEN "1000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111110100000101110010"; WHEN "1000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111010010001110101001"; WHEN "1000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110110000000001101011"; WHEN "1000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110001101011001110011"; WHEN "1000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101101010010101011101"; WHEN "1000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101000110110101111111"; WHEN "1000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111100100010111100111100"; WHEN "1001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011111110101110100100"; WHEN "1001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011011001111111110100"; WHEN "1001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010110100111101000111"; WHEN "1001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010001111011100101001"; WHEN "1001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001101001100111100001"; WHEN "1001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001000011011000101011"; WHEN "1001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111000011100101100110010"; WHEN "1001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111110101110000000011"; WHEN "1010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111001110011001111101"; WHEN "1010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110110100110101001110001"; WHEN "1010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101111110100101001011"; WHEN "1010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101010110000110010110"; WHEN "1010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100101101010100111010"; WHEN "1010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100000100001101101101"; WHEN "1010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110011011010101110011000"; WHEN "1010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010110000111001010011"; WHEN "1011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010000110101101010010"; WHEN "1011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110001011100010001000010"; WHEN "1011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000110001011111001110"; WHEN "1011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000000110010110110100"; WHEN "1011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101111011010111010001000"; WHEN "1011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110101111001110001011"; WHEN "1011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110000011001011001100"; WHEN "1011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101101010110110100111111"; WHEN "1100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101100101010001011011001"; WHEN "1100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011111101010010000000"; WHEN "1100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011010000000101001000"; WHEN "1100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101010100010100111110111"; WHEN "1100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001110100111011010110"; WHEN "1100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001000110110111101100"; WHEN "1100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101000011000101000001000"; WHEN "1100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100111101010001001010101"; WHEN "1101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110111011010110000011"; WHEN "1101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110001100010011011010"; WHEN "1101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100101011101000100011001"; WHEN "1101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100100101101100110100111"; WHEN "1101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011111101110111111010"; WHEN "1101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011001110000000101100"; WHEN "1101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100010011101110011110101"; WHEN "1101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100001101101100000010000"; WHEN "1110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000111100111010001011"; WHEN "1110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000001100000111111010"; WHEN "1110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011111011011001110101000"; WHEN "1110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011110101010000110010111"; WHEN "1110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101111000110001000001"; WHEN "1110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101000111001101001001"; WHEN "1110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011100010101100011001010"; WHEN "1110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011011100011101111010110"; WHEN "1111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011010110001101110011110"; WHEN "1111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001111111100011010111"; WHEN "1111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001001101010000100101"; WHEN "1111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011000011010110101101110"; WHEN "1111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010111101000010001000000"; WHEN "1111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110110101100011000101"; WHEN "1111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110000010101101010111"; WHEN "1111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010101001111110001011010"; WHEN OTHERS => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; END CASE; END IF; END PROCESS; --sumAHighB_uid236_sinPiZPolyEval(ADD,235)@9 sumAHighB_uid236_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((26 downto 26 => memoryC4_uid230_sinPiZTableGenerator_q(25)) & memoryC4_uid230_sinPiZTableGenerator_q); sumAHighB_uid236_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((26 downto 17 => highBBits_uid235_sinPiZPolyEval_b(16)) & highBBits_uid235_sinPiZPolyEval_b); sumAHighB_uid236_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid236_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid236_sinPiZPolyEval_b)); sumAHighB_uid236_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_o(26 downto 0); --lowRangeB_uid234_sinPiZPolyEval(BITSELECT,233)@9 lowRangeB_uid234_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid234_sinPiZPolyEval_b <= lowRangeB_uid234_sinPiZPolyEval_in(0 downto 0); --s1_uid234_uid237_sinPiZPolyEval(BITJOIN,236)@9 s1_uid234_uid237_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_q & lowRangeB_uid234_sinPiZPolyEval_b; --reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1(REG,385)@9 reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= s1_uid234_uid237_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor(LOGICAL,1179) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q <= not (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a or ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg(REG,1177) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= VCC_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena(REG,1180) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q = "1") THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd(LOGICAL,1181) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a and ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b; --yT2_uid238_sinPiZPolyEval(BITSELECT,237)@5 yT2_uid238_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT2_uid238_sinPiZPolyEval_b <= yT2_uid238_sinPiZPolyEval_in(44 downto 19); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt(COUNTER,1173) -- every=1, low=0, high=1, step=1, init=1 ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i + 1; END IF; END PROCESS; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i,1)); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg(REG,1174) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux(MUX,1175) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q) BEGIN CASE ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s IS WHEN "0" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; WHEN "1" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem(DUALMEM,1172) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia <= yT2_uid238_sinPiZPolyEval_b; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 26, widthad_a => 1, numwords_a => 2, width_b => 26, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq, address_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa, data_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia ); ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq(25 downto 0); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg(DELAY,1171) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q, xout => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0(REG,386)@9 reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q; END IF; END PROCESS; --prodXY_uid266_pT2_uid239_sinPiZPolyEval(MULT,265)@10 prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_a),27)) * SIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_b); prodXY_uid266_pT2_uid239_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr,54)); END IF; END PROCESS; prodXY_uid266_pT2_uid239_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval(BITSELECT,266)@13 prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_q; prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in(53 downto 25); --highBBits_uid241_sinPiZPolyEval(BITSELECT,240)@13 highBBits_uid241_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b; highBBits_uid241_sinPiZPolyEval_b <= highBBits_uid241_sinPiZPolyEval_in(28 downto 1); --reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1(REG,388)@13 reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= highBBits_uid241_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor(LOGICAL,1192) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1188) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q <= "0101"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp(LOGICAL,1189) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg(REG,1190) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena(REG,1193) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1194) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1184) -- every=1, low=0, high=5, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i = 4 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i - 5; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i,3)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg(REG,1185) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1186) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1183) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 3, numwords_a => 6, width_b => 7, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg(DELAY,1182) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0(REG,387)@12 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC3_uid229_sinPiZTableGenerator(LOOKUP,228)@13 memoryC3_uid229_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; WHEN "0000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000001010001100110101000111010101"; WHEN "0000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000010100011001100101101010110011"; WHEN "0000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000011110100110001101010100011011"; WHEN "0000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000101000110010100111100101110011"; WHEN "0000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000110010111110101111101101101000"; WHEN "0000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000111101001010100001100001001101"; WHEN "0000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001000111010101111000010100001000"; WHEN "0001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001010001100000101111101001011010"; WHEN "0001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001011011101011000011001000111110"; WHEN "0001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001100101110100101110001001110101"; WHEN "0001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001101111111101101100010100000001"; WHEN "0001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001111010000101111001001101010110"; WHEN "0001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010000100001101010000011000110101"; WHEN "0001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010001110010011101101001010101000"; WHEN "0001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010011000011001001011011101011111"; WHEN "0010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010100010011101100110100011101011"; WHEN "0010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010101100100000111010000011110001"; WHEN "0010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010110110100011000001011111010110"; WHEN "0010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011000000100011111000101110110101"; WHEN "0010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011001010100011011011001000001011"; WHEN "0010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011010100100001100100010010100101"; WHEN "0010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011011110011110001111110110101010"; WHEN "0010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011101000011001011001100000011011"; WHEN "0011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011110010010010111100111000010100"; WHEN "0011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011111100001010110101011110000110"; WHEN "0011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100000110000000111111001110100010"; WHEN "0011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100001111110101010101100100101101"; WHEN "0011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100011001100111110100010110001111"; WHEN "0011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100100011011000010111001001011111"; WHEN "0011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100101101000110111001101001101001"; WHEN "0011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100110110110011010111110011001100"; WHEN "0100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101000000011101101101010000100110"; WHEN "0100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101001010000101110101101000010110"; WHEN "0100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101010011101011101100111100100100"; WHEN "0100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101011101001111001110110000110010"; WHEN "0100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101100110110000010111000000110011"; WHEN "0100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101110000001111000001100011110100"; WHEN "0100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101111001101011001010010000000001"; WHEN "0100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110000011000100101100111100001110"; WHEN "0101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110001100011011100101011010100101"; WHEN "0101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110010101101111101111110000010101"; WHEN "0101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110011111000001000111101011101100"; WHEN "0101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110101000001111101001011001100010"; WHEN "0101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110110001011011010000101101010010"; WHEN "0101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110111010100011111001100111101100"; WHEN "0101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111000011101001100000010000100010"; WHEN "0101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111001100101100000000100001010000"; WHEN "0110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111010101101011010110100011101100"; WHEN "0110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111011110100111011110011000011110"; WHEN "0110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111100111100000010100001101010000"; WHEN "0110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111110000010101110100000001010000"; WHEN "0110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111111001000111111010001101010001"; WHEN "0110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000000001110110100010110001111010"; WHEN "0110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000001010100001101001110111110101"; WHEN "0110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000010011001001001011111110000001"; WHEN "0111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000011011101101000101000010101111"; WHEN "0111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000100100001101010001101000100100"; WHEN "0111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000101100101001101110000011010101"; WHEN "0111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000110101000010010110100001011010"; WHEN "0111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000111101010111000111010101011110"; WHEN "0111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001000101100111111101000110111000"; WHEN "0111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001001101110100110100001111001100"; WHEN "0111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001010101111101101001000001001010"; WHEN "1000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001011110000010011000001001000011"; WHEN "1000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001100110000010111101111101010011"; WHEN "1000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001101101111111010111010011001111"; WHEN "1000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001110101110111100000011010000110"; WHEN "1000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001111101101011010110000011010010"; WHEN "1000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010000101011010110100111100000101"; WHEN "1000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010001101000101111001101110100011"; WHEN "1000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010010100101100100001000101010010"; WHEN "1001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010011100001110100111101001010100"; WHEN "1001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010100011101100001010100001011100"; WHEN "1001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010101011000101000110001011100100"; WHEN "1001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010110010011001010111110000100100"; WHEN "1001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010111001101000111011111001000111"; WHEN "1001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000000110011101111101001011111"; WHEN "1001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000111111001110000000110011110"; WHEN "1001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011001110111010111001110111111110"; WHEN "1010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011010101110111001010010001110110"; WHEN "1010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011011100101110011110011000111101"; WHEN "1010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011100011100000110011001001001001"; WHEN "1010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011101010001110000101111000101100"; WHEN "1010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110000110110010011100011000111"; WHEN "1010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110111011001011001011101010011"; WHEN "1010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011111101110111010100111100011100"; WHEN "1010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100000100010000000011001111101101"; WHEN "1011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100001010100011100001101110011100"; WHEN "1011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010000110001101101100011100011"; WHEN "1011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010110111010100100010100000100"; WHEN "1011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100011100111110000011100000001010"; WHEN "1011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100100010111100001000100001101001"; WHEN "1011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101000110100110000110001111011"; WHEN "1011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101110100111111010000100111001"; WHEN "1011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100110100010101100001111010001101"; WHEN "1100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111001111101100101111101110000"; WHEN "1100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111111100000000011110011100101"; WHEN "1100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101000100111100111001010011110100"; WHEN "1100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001010010100000100001001001101"; WHEN "1100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001111100101100010000111001000"; WHEN "1100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101010100110001010001010100001101"; WHEN "1100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011001110111001111010101110101"; WHEN "1100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011110110111011010001101111010"; WHEN "1101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101100011110001110000000111001111"; WHEN "1101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101000100110001110111010010001"; WHEN "1101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101101010100110100100110101101"; WHEN "1101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110001111101011111011001010101"; WHEN "1101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110110100000001101100000100000"; WHEN "1101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111010111100111100111010111000"; WHEN "1101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111111010011101100010000110110"; WHEN "1101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000011100100011001011010100000"; WHEN "1110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000111101111000011000011110011"; WHEN "1110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001011110011100111011010000000"; WHEN "1110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001111110010000100101111100001"; WHEN "1110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010011101010011001110010000111"; WHEN "1110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010111011100100100111111111001"; WHEN "1110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011011001000100101000000101011"; WHEN "1110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011110101110011000001011101010"; WHEN "1110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100010001101111101010010100010"; WHEN "1111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100101100111010011001000110011"; WHEN "1111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101000111010011000011010000011"; WHEN "1111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101100000111001011110100010010"; WHEN "1111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101111001101101100001110011100"; WHEN "1111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110010001101111000100101110110"; WHEN "1111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110101000111101111110101001010"; WHEN "1111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110111111011010000111000110000"; WHEN "1111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110111010101000011010110000100000"; WHEN OTHERS => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; END CASE; END IF; END PROCESS; --sumAHighB_uid242_sinPiZPolyEval(ADD,241)@14 sumAHighB_uid242_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid229_sinPiZTableGenerator_q(34)) & memoryC3_uid229_sinPiZTableGenerator_q); sumAHighB_uid242_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((35 downto 28 => reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q(27)) & reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q); sumAHighB_uid242_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid242_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid242_sinPiZPolyEval_b)); sumAHighB_uid242_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_o(35 downto 0); --lowRangeB_uid240_sinPiZPolyEval(BITSELECT,239)@13 lowRangeB_uid240_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid240_sinPiZPolyEval_b <= lowRangeB_uid240_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a(DELAY,686)@13 ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid240_sinPiZPolyEval_b, xout => ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --s2_uid240_uid243_sinPiZPolyEval(BITJOIN,242)@14 s2_uid240_uid243_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_q & ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q; --yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval(BITSELECT,274)@14 yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in(36 downto 19); --reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9(REG,389)@14 reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor(LOGICAL,950) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top(CONSTANT,946) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q <= "0110"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp(LOGICAL,947) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b else "0"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg(REG,948) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena(REG,951) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q = "1") THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd(LOGICAL,952) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt(COUNTER,942) -- every=1, low=0, high=6, step=1, init=1 ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i = 5 THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i - 6; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i,3)); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg(REG,943) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux(MUX,944) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q) BEGIN CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s IS WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem(DUALMEM,1069) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 3, numwords_a => 7, width_b => 45, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg(DELAY,1068) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT3_uid244_sinPiZPolyEval(BITSELECT,243)@14 yT3_uid244_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q; yT3_uid244_sinPiZPolyEval_b <= yT3_uid244_sinPiZPolyEval_in(44 downto 10); --xBottomBits_uid274_pT3_uid245_sinPiZPolyEval(BITSELECT,273)@14 xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b(7 downto 0); xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in(7 downto 0); --pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval(BITJOIN,276)@14 pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7(REG,391)@14 reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid273_pT3_uid245_sinPiZPolyEval(BITSELECT,272)@14 yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q(9 downto 0); yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b <= yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in(9 downto 0); --spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval(BITJOIN,275)@14 spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q <= GND_q & yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b; --pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval(BITJOIN,277)@14 pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q <= spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6(REG,390)@14 reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval(BITSELECT,271)@14 xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in(34 downto 17); --reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4(REG,392)@14 reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma(CHAINMULTADD,345)@15 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1),38); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0); END IF; END PROCESS; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0),37)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval(BITSELECT,279)@18 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in(36 downto 7); --highBBits_uid282_pT3_uid245_sinPiZPolyEval(BITSELECT,281)@18 highBBits_uid282_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b; highBBits_uid282_pT3_uid245_sinPiZPolyEval_b <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_in(29 downto 1); --reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1(REG,395)@18 reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval(BITSELECT,269)@14 yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in(36 downto 10); --reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1(REG,393)@14 reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval(BITSELECT,268)@14 xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in(34 downto 8); --reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0(REG,394)@14 reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid271_pT3_uid245_sinPiZPolyEval(MULT,270)@15 topProd_uid271_pT3_uid245_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_b); topProd_uid271_pT3_uid245_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid271_pT3_uid245_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid271_pT3_uid245_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0(REG,396)@18 reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid283_pT3_uid245_sinPiZPolyEval(ADD,282)@19 sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q(53)) & reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b)); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid281_pT3_uid245_sinPiZPolyEval(BITSELECT,280)@18 lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b <= lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a(DELAY,724)@18 ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b, xout => ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid281_uid284_pT3_uid245_sinPiZPolyEval(BITJOIN,283)@19 add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q & ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q; --R_uid285_pT3_uid245_sinPiZPolyEval(BITSELECT,284)@19 R_uid285_pT3_uid245_sinPiZPolyEval_in <= add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q(54 downto 0); R_uid285_pT3_uid245_sinPiZPolyEval_b <= R_uid285_pT3_uid245_sinPiZPolyEval_in(54 downto 18); --reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1(REG,397)@19 reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= R_uid285_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor(LOGICAL,1168) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1164) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q <= "01011"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp(LOGICAL,1165) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg(REG,1166) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena(REG,1169) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1170) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1160) -- every=1, low=0, high=11, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i = 10 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i - 11; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i,4)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg(REG,1161) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1162) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1159) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 4, numwords_a => 12, width_b => 7, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg(DELAY,1158) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0(REG,381)@18 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC2_uid228_sinPiZTableGenerator(LOOKUP,227)@19 memoryC2_uid228_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; WHEN "0000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010010000000010011011110101101000"; WHEN "0000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010100110111111010000111001000101"; WHEN "0000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101011001101001111001000101101101011"; WHEN "0000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101100000010110001110010011100100110"; WHEN "0000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101101000111100110110110100100001100"; WHEN "0000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101110011011101101110110101011000001"; WHEN "0000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101111111111000110001101110000001000"; WHEN "0001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110001110001101111010000000001001001"; WHEN "0001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110011110011101000001010111100010011"; WHEN "0001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110110000100110000000101010101010010"; WHEN "0001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111000100101000101111111001111001110"; WHEN "0001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111011010100101000110010000000110000"; WHEN "0001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111110010011010111010000010100101101"; WHEN "0001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000001100001010000000110001101010110"; WHEN "0001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000100111110010001111000111001110001"; WHEN "0010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001000101010011011000111000110111111"; WHEN "0010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001100100101101010001000110100001110"; WHEN "0010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010000101111111101001111011000110110"; WHEN "0010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010101001001010010100101011111010000"; WHEN "0010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011001110001101000001111010001111100"; WHEN "0010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011110101000111100001010010001101000"; WHEN "0010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111100011101111001100001101011001010011"; WHEN "0010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101001000100010110001000111111011001"; WHEN "0011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101110101000010111100110110111011101"; WHEN "0011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111110100011011001110001010010101001001"; WHEN "0011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111111010011100110111010000000101010000"; WHEN "0011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000000101101010000001110011011110111"; WHEN "0011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000111001100010110010101001001001010"; WHEN "0011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000001101111010000110101101100011101100"; WHEN "0011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000010100110110011110011010100101011100"; WHEN "0011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000011100000001011010011000101010010101"; WHEN "0100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000100011011010110111011101111001100010"; WHEN "0100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000101011000010110010011010000011100100"; WHEN "0100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000110010111001000111110110011110000010"; WHEN "0100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000111010111101110100010110010000011111"; WHEN "0100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001000011010000110100010110001010111111"; WHEN "0100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001001011110010000100001100101110011011"; WHEN "0100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001010100100001100000001010001100011000"; WHEN "0100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001011101011111000100011000101001100001"; WHEN "0101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001100110101010101100111100000000011011"; WHEN "0101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001110000000100010101110001111101110010"; WHEN "0101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001111001101011111010110010001100011010"; WHEN "0101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010000011100001010111101110001010011110"; WHEN "0101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010001101100100101000010001011000100111"; WHEN "0101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010010111110101101000000001010011000010"; WHEN "0101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010100010010100010010011101010101101010"; WHEN "0101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010101101000000100010111111000010000011"; WHEN "0110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010110111111010010100111001111011100110"; WHEN "0110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011000011000001100011011011101110111001"; WHEN "0110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011001110010110001001101100001111110101"; WHEN "0110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011011001111000000010101101100000111100"; WHEN "0110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011100101100111001001011011101110011000"; WHEN "0110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011110001100011011000101101011001110101"; WHEN "0110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011111101101100101011010011010110110001"; WHEN "0110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100001010000010111011111000101001101100"; WHEN "0111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100010110100110000101000010110110110100"; WHEN "0111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100100011010110000001010001110101000110"; WHEN "0111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100110000010010101010111111111100101100"; WHEN "0111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100111101011011111100100010000110111111"; WHEN "0111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101001010110001110000000111101111100101"; WHEN "0111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101011000010011111111111010110011011100"; WHEN "0111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101100110000010100101111111111011010100"; WHEN "0111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101110011111101011100010110011100010110"; WHEN "1000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110000010000100011100111000010100111110"; WHEN "1000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110010000010111100001011010011001010101"; WHEN "1000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110011110110110100011101100001011001000"; WHEN "1000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110101101100001011101011000001011011001"; WHEN "1000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110111100011000001000000011101110001111"; WHEN "1000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111001011011010011101001111000101110001"; WHEN "1000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111011010101000010110010101100101000110"; WHEN "1000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111101010000001101100101101100010111111"; WHEN "1001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111111001100110011001101000011100111011"; WHEN "1001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000001001010110010110010010110100011100"; WHEN "1001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000011001010001011011110100100000011000"; WHEN "1001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000101001010111100011010000011111011101"; WHEN "1001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000111001101000100101100101001010011111"; WHEN "1001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001001010000100011011101100001100000010"; WHEN "1001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001011010101010111110011010101000110000"; WHEN "1001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001101011011100000110100001001001100100"; WHEN "1010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001111100010111101100101011101111001100"; WHEN "1010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010001101011101101001100010000010111010"; WHEN "1010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010011110101101110101100111011000000101"; WHEN "1010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010110000001000001001011010101000000100"; WHEN "1010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011000001101100011101010110100010000110"; WHEN "1010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011010011011010101001110001100010110011"; WHEN "1010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011100101010010100110111101111101101001"; WHEN "1010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011110111010100001101001010000001101110"; WHEN "1011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100001001011111010100011111111010110111"; WHEN "1011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100011011110011110101000101111001011001"; WHEN "1011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100101110010001100110111110001101101110"; WHEN "1011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101000000111000100010000111010010100101"; WHEN "1011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101010011101000011110011011110001111001"; WHEN "1011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101100110100001010011110010100110010101"; WHEN "1011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101111001100010111001111110111010001011"; WHEN "1011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110001100101101001000110000010101000001"; WHEN "1100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110011111111111110111110010111000010010"; WHEN "1100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110110011011010111110101111001000100111"; WHEN "1100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111000110111110010101001010001010011010"; WHEN "1100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111011010101001110010100101101110010111"; WHEN "1100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111101110011101001110100000001111101010"; WHEN "1100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000000010011000100000010100110110100000"; WHEN "1100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000010110011011011111011011100110110011"; WHEN "1100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000101010100110000011001001011000000001"; WHEN "1101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000111110111000000010101111111100010101"; WHEN "1101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001010011010001010101011110001011010100"; WHEN "1101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001100111110001110010100000000000010111"; WHEN "1101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001111100011001010000111110011101110000"; WHEN "1101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010010001000111100111111111110011011101"; WHEN "1101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010100101111100101110100111100110010101"; WHEN "1101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010111010111000011011110110101001010101"; WHEN "1101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011001111111010100110101011010011011011"; WHEN "1110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011100101000011000110000001010000000100"; WHEN "1110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011111010010001110000110001110011111011"; WHEN "1110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100001111100110011101110011111001111111"; WHEN "1110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100100101000001000011111100000011011011"; WHEN "1110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100111010100001011001111100100100101001"; WHEN "1110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101010000000111010110100101100100010111"; WHEN "1110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101100101110010110000100101000101101101"; WHEN "1110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101111011100011011110100111000011010111"; WHEN "1111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110010001011001010111010101011001010001"; WHEN "1111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110100111010100010001011000001010110100"; WHEN "1111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110111101010100000011010101100101100011"; WHEN "1111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111010011011000100011110010000011111011"; WHEN "1111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111101001100001101001010000010010001011"; WHEN "1111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111111111101111001010010001010101000011"; WHEN "1111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000010110000000111101010100101101001001"; WHEN "1111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000101100010110111000111000011010110101"; WHEN OTHERS => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid246_sinPiZPolyEval(CONSTANT,245) rndBit_uid246_sinPiZPolyEval_q <= "01"; --cIncludingRoundingBit_uid247_sinPiZPolyEval(BITJOIN,246)@19 cIncludingRoundingBit_uid247_sinPiZPolyEval_q <= memoryC2_uid228_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0(REG,398)@19 reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid247_sinPiZPolyEval_q; END IF; END PROCESS; --ts3_uid248_sinPiZPolyEval(ADD,247)@20 ts3_uid248_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q); ts3_uid248_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q(36)) & reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q); ts3_uid248_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid248_sinPiZPolyEval_a) + SIGNED(ts3_uid248_sinPiZPolyEval_b)); ts3_uid248_sinPiZPolyEval_q <= ts3_uid248_sinPiZPolyEval_o(45 downto 0); --s3_uid249_sinPiZPolyEval(BITSELECT,248)@20 s3_uid249_sinPiZPolyEval_in <= ts3_uid248_sinPiZPolyEval_q; s3_uid249_sinPiZPolyEval_b <= s3_uid249_sinPiZPolyEval_in(45 downto 1); --yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval(BITSELECT,286)@20 yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b; yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in(44 downto 18); --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9(REG,399)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor(LOGICAL,1091) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top(CONSTANT,1087) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q <= "01100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp(LOGICAL,1088) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg(REG,1089) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena(REG,1092) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd(LOGICAL,1093) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1083) -- every=1, low=0, high=12, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i = 11 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i - 12; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i,4)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg(REG,1084) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux(MUX,1085) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem(DUALMEM,1082) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 13, width_b => 45, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg(DELAY,1081) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT4_uid250_sinPiZPolyEval(BITSELECT,249)@20 yT4_uid250_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q; yT4_uid250_sinPiZPolyEval_b <= yT4_uid250_sinPiZPolyEval_in(44 downto 2); --xBottomBits_uid290_pT4_uid251_sinPiZPolyEval(BITSELECT,289)@20 xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in <= yT4_uid250_sinPiZPolyEval_b(15 downto 0); xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in(15 downto 0); --pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval(BITJOIN,291)@20 pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7(REG,401)@20 reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid289_pT4_uid251_sinPiZPolyEval(BITSELECT,288)@20 yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b(17 downto 0); yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b <= yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a(DELAY,733)@20 ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b, xout => ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval(BITJOIN,290)@21 spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q; --pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval(BITJOIN,292)@21 pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q <= spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6(REG,400)@21 reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a(DELAY,727)@20 ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 43, depth => 1 ) PORT MAP ( xin => yT4_uid250_sinPiZPolyEval_b, xout => ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval(BITSELECT,285)@21 xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in <= ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q; xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in(42 downto 16); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4(REG,402)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma(CHAINMULTADD,346)@22 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval(BITSELECT,294)@25 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in(54 downto 8); --highBBits_uid297_pT4_uid251_sinPiZPolyEval(BITSELECT,296)@25 highBBits_uid297_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b; highBBits_uid297_pT4_uid251_sinPiZPolyEval_b <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_in(46 downto 18); --reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1(REG,405)@25 reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1(REG,403)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b(DELAY,730)@21 ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0(REG,404)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid288_pT4_uid251_sinPiZPolyEval(MULT,287)@22 topProd_uid288_pT4_uid251_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_b); topProd_uid288_pT4_uid251_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid288_pT4_uid251_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid288_pT4_uid251_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0(REG,406)@25 reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid298_pT4_uid251_sinPiZPolyEval(ADD,297)@26 sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q(53)) & reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b)); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid296_pT4_uid251_sinPiZPolyEval(BITSELECT,295)@25 lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b(17 downto 0); lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b <= lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a(DELAY,741)@25 ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b, xout => ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid296_uid299_pT4_uid251_sinPiZPolyEval(BITJOIN,298)@26 add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q & ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q; --R_uid300_pT4_uid251_sinPiZPolyEval(BITSELECT,299)@26 R_uid300_pT4_uid251_sinPiZPolyEval_in <= add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q(71 downto 0); R_uid300_pT4_uid251_sinPiZPolyEval_b <= R_uid300_pT4_uid251_sinPiZPolyEval_in(71 downto 26); --reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1(REG,407)@26 reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= R_uid300_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor(LOGICAL,1155) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1151) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q <= "010010"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp(LOGICAL,1152) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg(REG,1153) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena(REG,1156) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1157) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1147) -- every=1, low=0, high=18, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i = 17 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i - 18; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg(REG,1148) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1149) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1146) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 19, width_b => 7, widthad_b => 5, numwords_b => 19, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg(DELAY,1145) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0(REG,380)@25 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC1_uid227_sinPiZTableGenerator(LOOKUP,226)@26 memoryC1_uid227_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; WHEN "0000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111110101101010100010101111000000010001111100011"; WHEN "0000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111101011010101001001010010110100010110001011110"; WHEN "0000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111100000111111110111100000001110010011010000110"; WHEN "0000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111010110101010110001001011111100110111111100011"; WHEN "0000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111001100010101111010001010101001101111010110100"; WHEN "0000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111000010000001010110010000110111110101011111000"; WHEN "0000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110110111101101001001010011000001101011000111010"; WHEN "0001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110101101011001010111000101010111101010010100111"; WHEN "0001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110100011000110000011011011111110011010111001110"; WHEN "0001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110011000110011010010001010101101000110101101101"; WHEN "0001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110001110100001000111000101001011101110011011101"; WHEN "0001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110000100001111100101111110110001011110001011001"; WHEN "0001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101111001111110110010101010100011000010010100110"; WHEN "0001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101101111101110110000111011010000111100011100100"; WHEN "0001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101100101011111100100100011010101111000101000111"; WHEN "0010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101011011010001010001010100110101000010011111000"; WHEN "0010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101010001000011111011000001011000011010110000100"; WHEN "0010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101000110110111100101011010001111001100111110010"; WHEN "0010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100111100101100010100010000001100000101010111010"; WHEN "0010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100110010100010001011010011100011100110101011100"; WHEN "0010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100101000011001001110010100001010100000101101100"; WHEN "0010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100011110010001100001000001010100000110110000000"; WHEN "0010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100010100001011000111001001110000100110010111000"; WHEN "0011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100001010000110000100011011101011011110011010110"; WHEN "0011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100000000000010011100100100101001110110011000010"; WHEN "0011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011110110000000010011010001101000110110000011100"; WHEN "0011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011101011111111101100001110111011111101010000000"; WHEN "0011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011100010000000101011001000001011011100001111010"; WHEN "0011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011011000000011010011101000010010101100000110110"; WHEN "0011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011001110000111101001011001011110100111101110010"; WHEN "0011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011000100001101110000000101001100000101000010010"; WHEN "0100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010111010010101101011010100000110001110011110001"; WHEN "0100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010110000011111011110101110000100111100111110101"; WHEN "0100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010100110101011001101111010001011010010011110011"; WHEN "0100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010011100111000111100011110100101110100010111000"; WHEN "0100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010010011001000101110000000101001000110111000111"; WHEN "0100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010001001011010100110000100110000001000100101001"; WHEN "0100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001111111101110101000001110011010101110010001110"; WHEN "0100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001110110000100111000000000001011111111100011001"; WHEN "0101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001101100011101011000111011101000110011100100000"; WHEN "0101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001100010111000001110100001010110001110100101001"; WHEN "0101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001011001010101011100010000110111111111100011001"; WHEN "0101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001001111110101000101101000101110111110101110110"; WHEN "0101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001000110010111001110000110010111101100001101110"; WHEN "0101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000111100111011111001000110001000101111011110000"; WHEN "0101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000110011100011001010000011010001010111001000100"; WHEN "0101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000101010001101000100010111110111111001010110011"; WHEN "0110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000100000111001101011011100111000010100110100100"; WHEN "0110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000010111101001000010101010000010110010001100101"; WHEN "0110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000001110011011001101010101111010000110001110001"; WHEN "0110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000000101010000001110110101110010010100010001010"; WHEN "0110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111111100001000001010011101101111010001101110100"; WHEN "0110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111110011000011000011100000100011001001100111111"; WHEN "0110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111101010000000111101001111101101000001001100111"; WHEN "0110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111100001000001111010111011010111011101000011000"; WHEN "0111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111011000000101111111110010010111000110100000100"; WHEN "0111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111001111001101001111000010001001010010011000111"; WHEN "0111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111000110010111101011110110110010100111101001111"; WHEN "0111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110111101100101011001011010111101100111001001111"; WHEN "0111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110110100110110011010110111111001010011111110011"; WHEN "0111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110101100001010110011010101010111111100100001011"; WHEN "0111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110100011100010100101111001101101100100000011010"; WHEN "0111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110011010111101110101101001101110101101001000101"; WHEN "1000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110010010011100100101101000101111000100111000101"; WHEN "1000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110001001111110111000111000100000001110100110010"; WHEN "1000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110000001100100110010011001010000010000100100001"; WHEN "1000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101111001001110010101001001101000100001000011111"; WHEN "1000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101110000111011100100000110101100010100101111011"; WHEN "1000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101101000101100100010001011110111101101010011001"; WHEN "1000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101100000100001010010010010111110001001000100100"; WHEN "1000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101011000011001110111010100001001010011011010001"; WHEN "1001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101010000010110010100000101110111110101110111011"; WHEN "1001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101001000010110101011011100111100001010010001010"; WHEN "1001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101000000011011000000001100011011001101001101101"; WHEN "1001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100111000100011010101000101101011010001111110100"; WHEN "1001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100110000101111101100111000010010110110101001010"; WHEN "1001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100101001000000001010010010000111011001100101001"; WHEN "1001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100100001010100101111111111001100001111011011000"; WHEN "1001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100011001101101100000101001110001011001110111100"; WHEN "1010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100010010001010011110111010010010011111110100100"; WHEN "1010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100001010101011101101010111010101100101110000010"; WHEN "1010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100000011010001001110100101101010000111010011101"; WHEN "1010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011111011111011000101001000000111110001110111111"; WHEN "1010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011110100101001010011011111101101011111101000010"; WHEN "1010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011101101011011111100001011100000010100000001101"; WHEN "1010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011100110010011000001101000101010011000110001101"; WHEN "1010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011111001110100110010010011001111011110111011"; WHEN "1011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011000001110101100100010000000001110100011101"; WHEN "1011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011010001010011010110101110110000100101001100010"; WHEN "1011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011001010011100100111001101111111011000001100001"; WHEN "1011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011000011101010100000010011000001000101101011001"; WHEN "1011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010111100111101000100001111001001010100001001100"; WHEN "1011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010110110010100010101010001101001110110001111011"; WHEN "1011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101111110000010101100111110001101111011011100"; WHEN "1011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101001010001000111011100101100011001011100101"; WHEN "1100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010100010110110101100111001100000101011000010000"; WHEN "1100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010011100100001001000000101001111111111010110011"; WHEN "1100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010110010000011011000100110101011110110000011"; WHEN "1100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010000000100100111111011000101001000001000001"; WHEN "1100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010001001111101110000101000101010111011100100101"; WHEN "1100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010000011111011110111001100001010000110000001000"; WHEN "1100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111101111110111101100001111100001101100011111"; WHEN "1100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111000000111000101100100010000011111010101010"; WHEN "1101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001110010010100010001001011001010111110000100010"; WHEN "1101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001101100100110100010001100100011110001100110110"; WHEN "1101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100110111101111010011100000110010111101110011"; WHEN "1101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100001011010011011101011010000110101111000110"; WHEN "1101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001011011111100000111101001010011001011111101101"; WHEN "1101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010110100011000000000011001110101000000001010"; WHEN "1101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010001001111000110100011110100111011011010110"; WHEN "1101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001001100000000011100110011100111110000011010110"; WHEN "1110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000110110111000100011000111000000001100101100"; WHEN "1110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000001110010111110110111100101010001100011100"; WHEN "1110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000111100110100001101110001011101000100010101000"; WHEN "1110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110111111010110010100101111010011001100111001"; WHEN "1110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110011000110101110110010000101000111111101001"; WHEN "1110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101110011000000011110000110001011001010001101"; WHEN "1110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101001101110110010111010011111001000001110011"; WHEN "1110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100101001010111101100101011001011110111111001"; WHEN "1111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100000101100100101000101010110010110110110011"; WHEN "1111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011100010011101010101011110101111000111101111"; WHEN "1111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011000000000001111101000000010000000010001101"; WHEN "1111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000010011110010010101000110101101111100100010110"; WHEN "1111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001111101001111100010010010101110110011110010"; WHEN "1111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001011100111000110010010111110010100110111110"; WHEN "1111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000111101001110100001110010100000011000001001"; WHEN "1111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000011110010000111000111101011011000001000111"; WHEN OTHERS => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; END CASE; -- End reserved scope level END PROCESS; --cIncludingRoundingBit_uid253_sinPiZPolyEval(BITJOIN,252)@26 cIncludingRoundingBit_uid253_sinPiZPolyEval_q <= memoryC1_uid227_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0(REG,408)@26 reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid253_sinPiZPolyEval_q; END IF; END PROCESS; --ts4_uid254_sinPiZPolyEval(ADD,253)@27 ts4_uid254_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((52 downto 52 => reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q(51)) & reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q); ts4_uid254_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((52 downto 46 => reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q(45)) & reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q); ts4_uid254_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid254_sinPiZPolyEval_a) + SIGNED(ts4_uid254_sinPiZPolyEval_b)); ts4_uid254_sinPiZPolyEval_q <= ts4_uid254_sinPiZPolyEval_o(52 downto 0); --s4_uid255_sinPiZPolyEval(BITSELECT,254)@27 s4_uid255_sinPiZPolyEval_in <= ts4_uid254_sinPiZPolyEval_q; s4_uid255_sinPiZPolyEval_b <= s4_uid255_sinPiZPolyEval_in(52 downto 1); --yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval(BITSELECT,301)@27 yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b; yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in(51 downto 25); --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9(REG,409)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor(LOGICAL,1117) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q <= not (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a or ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top(CONSTANT,1113) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q <= "010011"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp(LOGICAL,1114) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a = ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b else "0"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg(REG,1115) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena(REG,1118) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q = "1") THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd(LOGICAL,1119) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a and ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b; --xBottomBits_uid305_pT5_uid257_sinPiZPolyEval(BITSELECT,304)@5 xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b(17 downto 0); xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt(COUNTER,1109) -- every=1, low=0, high=19, step=1, init=1 ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i = 18 THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '1'; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i - 19; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i,5)); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg(REG,1110) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux(MUX,1111) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q) BEGIN CASE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s IS WHEN "0" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; WHEN "1" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; WHEN OTHERS => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem(DUALMEM,1108) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 <= areset; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 5, numwords_a => 20, width_b => 18, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0, clock1 => clk, address_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq, address_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa, data_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia ); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg(DELAY,1107) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q, xout => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q, clk => clk, aclr => areset ); --pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval(BITJOIN,306)@27 pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7(REG,411)@27 reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid304_pT5_uid257_sinPiZPolyEval(BITSELECT,303)@27 yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b(24 downto 0); yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b <= yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a(DELAY,750)@27 ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b, xout => ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval(BITJOIN,305)@28 spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q; --pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval(BITJOIN,307)@28 pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q <= spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q & GND_q; --reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6(REG,410)@28 reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor(LOGICAL,1104) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top(CONSTANT,1100) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q <= "010100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp(LOGICAL,1101) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg(REG,1102) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena(REG,1105) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd(LOGICAL,1106) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1096) -- every=1, low=0, high=20, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i = 19 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i - 20; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i,5)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg(REG,1097) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux(MUX,1098) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem(DUALMEM,1095) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 5, numwords_a => 21, width_b => 45, widthad_b => 5, numwords_b => 21, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg(DELAY,1094) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval(BITSELECT,300)@28 xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q; xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in(44 downto 18); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4(REG,412)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma(CHAINMULTADD,347)@29 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval(BITSELECT,309)@32 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in(54 downto 1); --highBBits_uid312_pT5_uid257_sinPiZPolyEval(BITSELECT,311)@32 highBBits_uid312_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b; highBBits_uid312_pT5_uid257_sinPiZPolyEval_b <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_in(53 downto 25); --reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1(REG,415)@32 reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1(REG,413)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b(DELAY,747)@28 ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0(REG,414)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid303_pT5_uid257_sinPiZPolyEval(MULT,302)@29 topProd_uid303_pT5_uid257_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_b); topProd_uid303_pT5_uid257_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid303_pT5_uid257_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid303_pT5_uid257_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0(REG,416)@32 reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid313_pT5_uid257_sinPiZPolyEval(ADD,312)@33 sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q(53)) & reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b)); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid311_pT5_uid257_sinPiZPolyEval(BITSELECT,310)@32 lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b(24 downto 0); lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b <= lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a(DELAY,758)@32 ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b, xout => ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid311_uid314_pT5_uid257_sinPiZPolyEval(BITJOIN,313)@33 add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q & ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q; --R_uid315_pT5_uid257_sinPiZPolyEval(BITSELECT,314)@33 R_uid315_pT5_uid257_sinPiZPolyEval_in <= add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q(78 downto 0); R_uid315_pT5_uid257_sinPiZPolyEval_b <= R_uid315_pT5_uid257_sinPiZPolyEval_in(78 downto 25); --reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1(REG,417)@33 reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= R_uid315_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor(LOGICAL,1142) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1138) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q <= "011001"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp(LOGICAL,1139) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg(REG,1140) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena(REG,1143) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1144) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1134) -- every=1, low=0, high=25, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i = 24 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i - 25; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg(REG,1135) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1136) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1133) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 26, width_b => 7, widthad_b => 5, numwords_b => 26, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg(DELAY,1132) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0(REG,379)@32 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC0_uid226_sinPiZTableGenerator(LOOKUP,225)@33 memoryC0_uid226_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; WHEN "0000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111010001111111001101111011000111100001001010"; WHEN "0000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000101010101111101111010001101100110011111100100"; WHEN "0000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000010000111010001110111000001110010011001110001"; WHEN "0000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001111101100101111100010000110111011000000101000010"; WHEN "0000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110111110001111110110010110011100111000110011101"; WHEN "0000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110000101011011011100110100000100010100111010101"; WHEN "0000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001101000010010010101010100001100000100101011101101"; WHEN "0001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001011110100110101111000010100110110100001011000010"; WHEN "0001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001010011101000101100010111000010101101001011110101"; WHEN "0001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001000111011000010001010101010001011100000010111010"; WHEN "0001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000111001110101100010011111100010101010110110110111"; WHEN "0001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000101011000000100100110110100010000001101000110010"; WHEN "0001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000011010111001011101111001010100111001000011000110"; WHEN "0001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000001001100000010011100101010111111111101111100110"; WHEN "0001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111110110110101001100010110011100110010010101101111"; WHEN "0010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111100010111000001111000110100110100110000010101111"; WHEN "0010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111001101101001100011001110000111100101111100011100"; WHEN "0010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110110111001001010000100011011101100011000000101111"; WHEN "0010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110011111010111011111011011001110010110110010111000"; WHEN "0010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110000110010100011000101000000100011000111000100110"; WHEN "0010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101101100000000000101011010101010100111001000011100"; WHEN "0010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101010000011010101111100001101000100000101011011110"; WHEN "0010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100110011100100100001001001011101110011110100001011"; WHEN "0011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100010101011101100100111100011101111110101100100111"; WHEN "0011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011110110000110000110000010101011100010111110000011"; WHEN "0011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011010101011110010000000001110011001100010100001001"; WHEN "0011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010110011100110001110111101000110101001111110010101"; WHEN "0011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010010000011110001111010101010111011011010001011111"; WHEN "0011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001101100000110011110001000110001001111001100110001"; WHEN "0011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001000110011111001000110010110100010111000011111111"; WHEN "0011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001000011111101000011101001100001111101100010010011001"; WHEN "0100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111110111100010101001101010111010101001011000110001"; WHEN "0100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111001110001101111101000001101110110110001001100100"; WHEN "0100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000110100011101010100110100000100001100111000110001110"; WHEN "0100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101110111111000110101110011111101010000010000111000"; WHEN "0100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101001010111000111011000101011010001011010101011100"; WHEN "0100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000100011100101011000110111010110111110001001101100111"; WHEN "0100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000011101101001111101010010110110101000111000011000010"; WHEN "0100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010111100100110110110111000001001011110110011001101"; WHEN "0101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010001010110000111110011001111100101011011000101100"; WHEN "0101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000001010111101110010011010011011111001000011101001111"; WHEN "0101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000000100011011111001000011000000001110101111000110101"; WHEN "0101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111111101110000011110000110110101110000111000001001000"; WHEN "0101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111110110111011100100000011010011101000101101101101111"; WHEN "0101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101111111101001101011001001101111001001010100111010"; WHEN "0101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101000110101011100101100110100011000001100101000111"; WHEN "0101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111100001100100010100100101110001100110101011111100110"; WHEN "0110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111011010001001110111101111001001100110110011000001101"; WHEN "0110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111010010100110001000110111011000110000110111110111111"; WHEN "0110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111001010111001001010110000010010100110110110111111101"; WHEN "0110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111000011000011000000001111000000100110010000101101101"; WHEN "0110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110111011000011101100001100000000111000101001011011010"; WHEN "0110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110110010111011010001100011000101000010101101011001001"; WHEN "0110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110101010101001110011010011010000110001111000101001011"; WHEN "0110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110100010001111010100011110111000101000100011101001111"; WHEN "0111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110011001101011111000001011100000101000110101010111101"; WHEN "0111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110010000111111100001100001111010111101111011010000110"; WHEN "0111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110001000001010010011101110000110100100001000000010111"; WHEN "0111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101111111001100010001111111001101101111011001101100100"; WHEN "0111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101110110000101011111100111100100110000100111011101101"; WHEN "0111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101101100110101111111111100101000011001011000100010101"; WHEN "0111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101100011011101110110010110111100011110100100000110011"; WHEN "0111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101011001111101000110010010001010011001011011010110110"; WHEN "1000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101010000010011110011001100111111100111011110011001101"; WHEN "1000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101000110100010000000101001001100001000111100100001001"; WHEN "1000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100111100100111110010001011100000111110000000101011101"; WHEN "1000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100110010100101001011011011101110100010101011000001110"; WHEN "1000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100101000011010010000000100100011001001010111111110011"; WHEN "1000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100011110000111000011110011101001010100010101110100101"; WHEN "1000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100010011101011101010011001100110001101101001100010111"; WHEN "1000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100001001001000000111101001110111111110000011100100111"; WHEN "1001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011111110011100011111011010110100000010100101010111001"; WHEN "1001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011110011101000110101100101100101100000111000011110001"; WHEN "1001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011101000101101001110000110001011011010011000000110010"; WHEN "1001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011011101101001101100111011010110111110001101101101010"; WHEN "1001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011010010011110010110000110101001111010000001101101100"; WHEN "1001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011000111001011001101101100010100101001100000111100110"; WHEN "1001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010111011110000010111110011010100100100110111110110011"; WHEN "1001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010110000001101111000100101010010001110000100000110101"; WHEN "1010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010100100100011110100001110011111011100111101101011110"; WHEN "1010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010011000110010001110111101110101101010011000000111111"; WHEN "1010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010001100111001001101000100110011111001111100111000001"; WHEN "1010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010000000111000110010110111011101000010111111101010001"; WHEN "1010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001110100110001000100101100010101111000001101101010100"; WHEN "1010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001101000100010000110111100100011001110011000100010010"; WHEN "1010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001011100001011111110000011101000000001111110000000000"; WHEN "1010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001001111101110101110011111100011011011101101000101110"; WHEN "1011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001000011001010011100110000101110110100001001110110000"; WHEN "1011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000110110011111001101011001111011110110010000011100000"; WHEN "1011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000101001101101000101000000010010100000111000101001110"; WHEN "1011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000011100110100001000001011001111000111011010101001101"; WHEN "1011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000001111110100011011100100100000010001010101111111000"; WHEN "1011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000000010101110000011111000000100111000111011110010110"; WHEN "1011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111110101100001000101110100001010001000111101001001101"; WHEN "1011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111101000001101100110001001001001011001011110100011010"; WHEN "1100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111011010110011101001101001100110001011110001011110000"; WHEN "1100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111001101010011010101001010001100000101010101000000111"; WHEN "1100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110111111101100101101100001101100101001111110101000001"; WHEN "1100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110110001111111110111101000111101010101001011110111000"; WHEN "1100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110100100001100111000011010110101010010011110001011110"; WHEN "1100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110010110010011110100110100001011010101000001111000001"; WHEN "1100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110001000010100110001110011110011101110100000111111001"; WHEN "1100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101111010001111110100011010011110000101000011010111010"; WHEN "1101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101101100000101000001101010110011001000011100110100101"; WHEN "1101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101011101110100011110101001010010100110101010011100110"; WHEN "1101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101001111011110010000011100010000111111100000000100011"; WHEN "1101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101000001000010011100001011110101010111100110111011100"; WHEN "1101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100110010100001000111000001110111001010101110101010001"; WHEN "1101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100100011111010010110001001111011111101010001100000100"; WHEN "1101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100010101001110001110110001010101001101001100111101111"; WHEN "1101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100000110011100110110000110111110000010001111110011101"; WHEN "1110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011110111100110010001011011011000111101011110100101010"; WHEN "1110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011101000101010100110000000101101101000001111101101101"; WHEN "1110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011011001101001111001001010100110100010100000001010111"; WHEN "1110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011001010100100010000001110001110110000100001110111001"; WHEN "1110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010111011011001110000100010001111101000000100110100000"; WHEN "1110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010101100001010011111011110101110011100111100001100101"; WHEN "1110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010011100110110100010011101001010001101000000010101011"; WHEN "1110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010001101011101111110111000011001001011101110101101100"; WHEN "1111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001111110000000111010001100100110101101001001001010110"; WHEN "1111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001101110011111011001110111010000110000010101010100001"; WHEN "1111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001011110111001100011010111000101101001011101010010011"; WHEN "1111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001001111001111011100001100000001101011010010111101001"; WHEN "1111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000111111100001001001110111001100110000010110101011110"; WHEN "1111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000101111101110110001111010111000000011100010110001010"; WHEN "1111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000011111111000011001111010011011101000011100101001111"; WHEN "1111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000001111111110000111011010010100000011001101000010011"; WHEN OTHERS => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid258_sinPiZPolyEval(CONSTANT,257) rndBit_uid258_sinPiZPolyEval_q <= "001"; --cIncludingRoundingBit_uid259_sinPiZPolyEval(BITJOIN,258)@33 cIncludingRoundingBit_uid259_sinPiZPolyEval_q <= memoryC0_uid226_sinPiZTableGenerator_q & rndBit_uid258_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0(REG,418)@33 reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid259_sinPiZPolyEval_q; END IF; END PROCESS; --ts5_uid260_sinPiZPolyEval(ADD,259)@34 ts5_uid260_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q); ts5_uid260_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((61 downto 54 => reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q(53)) & reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q); ts5_uid260_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid260_sinPiZPolyEval_a) + SIGNED(ts5_uid260_sinPiZPolyEval_b)); ts5_uid260_sinPiZPolyEval_q <= ts5_uid260_sinPiZPolyEval_o(61 downto 0); --s5_uid261_sinPiZPolyEval(BITSELECT,260)@34 s5_uid261_sinPiZPolyEval_in <= ts5_uid260_sinPiZPolyEval_q; s5_uid261_sinPiZPolyEval_b <= s5_uid261_sinPiZPolyEval_in(61 downto 1); --fxpSinRes_uid66_fpSinPiTest(BITSELECT,65)@34 fxpSinRes_uid66_fpSinPiTest_in <= s5_uid261_sinPiZPolyEval_b(58 downto 0); fxpSinRes_uid66_fpSinPiTest_b <= fxpSinRes_uid66_fpSinPiTest_in(58 downto 5); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor(LOGICAL,963) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q <= not (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a or ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top(CONSTANT,959) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q <= "011111"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp(LOGICAL,960) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q <= "1" when ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a = ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b else "0"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg(REG,961) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena(REG,964) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q = "1") THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd(LOGICAL,965) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a and ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt(COUNTER,955) -- every=1, low=0, high=31, step=1, init=1 ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ELSIF (clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg(REG,956) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux(MUX,957) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux: PROCESS (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem(DUALMEM,954) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia <= sinXIsX_uid30_fpSinPiTest_c; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 32, width_b => 1, widthad_b => 5, numwords_b => 32, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq, address_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa, data_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia ); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg(DELAY,953) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --multRightOp_uid68_fpSinPiTest(MUX,67)@34 multRightOp_uid68_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q; multRightOp_uid68_fpSinPiTest: PROCESS (multRightOp_uid68_fpSinPiTest_s, fxpSinRes_uid66_fpSinPiTest_b) BEGIN CASE multRightOp_uid68_fpSinPiTest_s IS WHEN "0" => multRightOp_uid68_fpSinPiTest_q <= fxpSinRes_uid66_fpSinPiTest_b; WHEN "1" => multRightOp_uid68_fpSinPiTest_q <= piwFP2_uid67_fpSinPiTest_q; WHEN OTHERS => multRightOp_uid68_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_b_1(BITSELECT,318)@34 mul2xSinRes_uid69_fpSinPiTest_b_1_in <= multRightOp_uid68_fpSinPiTest_q; mul2xSinRes_uid69_fpSinPiTest_b_1_b <= mul2xSinRes_uid69_fpSinPiTest_b_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1(REG,423)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor(LOGICAL,1129) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q <= not (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a or ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top(CONSTANT,1125) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q <= "010110"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp(LOGICAL,1126) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q <= "1" when ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a = ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b else "0"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg(REG,1127) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena(REG,1130) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q = "1") THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd(LOGICAL,1131) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a and ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor(LOGICAL,937) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a or ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top(CONSTANT,933) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q <= "0111"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp(LOGICAL,934) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a = ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b else "0"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg(REG,935) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena(REG,938) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q = "1") THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd(LOGICAL,939) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt(COUNTER,929) -- every=1, low=0, high=7, step=1, init=1 ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,3); ELSIF (clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i + 1; END IF; END PROCESS; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i,3)); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg(REG,930) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux(MUX,931) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q) BEGIN CASE ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s IS WHEN "0" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; WHEN "1" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; WHEN OTHERS => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem(DUALMEM,928) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 <= areset; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia <= oFracX_uid31_uid31_fpSinPiTest_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 3, numwords_a => 8, width_b => 53, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq, address_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa, data_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia ); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq(52 downto 0); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg(DELAY,927) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg : dspba_delay GENERIC MAP ( width => 53, depth => 1 ) PORT MAP ( xin => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q, xout => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q, clk => clk, aclr => areset ); --LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest(BITSELECT,220)@10 LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q(77 downto 0); LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in(77 downto 0); --leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest(BITJOIN,221)@10 leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b & GND_q; --LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest(BITSELECT,204)@9 LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(54 downto 0); LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in(54 downto 0); --leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest(BITJOIN,205)@9 leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest(BITSELECT,201)@9 LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(62 downto 0); LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in(62 downto 0); --leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest(BITJOIN,202)@9 leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest(BITSELECT,198)@9 LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(70 downto 0); LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in(70 downto 0); --leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest(BITJOIN,199)@9 leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --ozz_uid41_fpSinPiTest(CONSTANT,40) ozz_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor(LOGICAL,1040) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q <= not (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a or ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top(CONSTANT,1036) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q <= "011"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp(LOGICAL,1037) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q <= "1" when ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a = ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b else "0"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg(REG,1038) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena(REG,1041) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q = "1") THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd(LOGICAL,1042) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a and ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b; --vStage_uid149_lzcZ_uid51_fpSinPiTest(BITSELECT,148)@4 vStage_uid149_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(14 downto 0); vStage_uid149_lzcZ_uid51_fpSinPiTest_b <= vStage_uid149_lzcZ_uid51_fpSinPiTest_in(14 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt(COUNTER,1032) -- every=1, low=0, high=3, step=1, init=1 ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,2); ELSIF (clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i,2)); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg(REG,1033) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux(MUX,1034) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1043) ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= vStage_uid149_lzcZ_uid51_fpSinPiTest_b; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 2, numwords_a => 4, width_b => 15, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(14 downto 0); --leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest(BITJOIN,193)@9 leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X46dto0_uid190_alignedZ_uid52_fpSinPiTest(BITSELECT,189)@4 X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(46 downto 0); X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in(46 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1031) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 47, widthad_a => 2, numwords_a => 4, width_b => 47, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(46 downto 0); --leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest(BITJOIN,190)@9 leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor(LOGICAL,1065) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q <= not (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a or ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top(CONSTANT,1061) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q <= "010"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp(LOGICAL,1062) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q <= "1" when ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a = ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b else "0"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg(REG,1063) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena(REG,1066) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q = "1") THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd(LOGICAL,1067) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a and ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt(COUNTER,1057) -- every=1, low=0, high=2, step=1, init=1 ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i = 1 THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i - 2; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i,2)); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg(REG,1058) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux(MUX,1059) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux: PROCESS (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem(DUALMEM,1056) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia <= z_uid49_fpSinPiTest_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 79, widthad_a => 2, numwords_a => 3, width_b => 79, widthad_b => 2, numwords_b => 3, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq, address_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa, data_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia ); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq(78 downto 0); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg(DELAY,1055) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q, xout => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --rVStage_uid146_lzcZ_uid51_fpSinPiTest(BITSELECT,145)@4 rVStage_uid146_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; rVStage_uid146_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_in(78 downto 15); --reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0(REG,365)@4 reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid147_lzcZ_uid51_fpSinPiTest(LOGICAL,146)@5 vCount_uid147_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid147_lzcZ_uid51_fpSinPiTest_a = vCount_uid147_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g(DELAY,629)@5 ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => vCount_uid147_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q, clk => clk, aclr => areset ); --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b(DELAY,587)@4 ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => vStage_uid149_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q, clk => clk, aclr => areset ); --mO_uid148_lzcZ_uid51_fpSinPiTest(CONSTANT,147) mO_uid148_lzcZ_uid51_fpSinPiTest_q <= "1111111111111111111111111111111111111111111111111"; --cStage_uid150_lzcZ_uid51_fpSinPiTest(BITJOIN,149)@5 cStage_uid150_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q & mO_uid148_lzcZ_uid51_fpSinPiTest_q; --ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c(DELAY,589)@4 ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 64, depth => 1 ) PORT MAP ( xin => rVStage_uid146_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid152_lzcZ_uid51_fpSinPiTest(MUX,151)@5 vStagei_uid152_lzcZ_uid51_fpSinPiTest_s <= vCount_uid147_lzcZ_uid51_fpSinPiTest_q; vStagei_uid152_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid152_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, cStage_uid150_lzcZ_uid51_fpSinPiTest_q) BEGIN CASE vStagei_uid152_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= cStage_uid150_lzcZ_uid51_fpSinPiTest_q; WHEN OTHERS => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid154_lzcZ_uid51_fpSinPiTest(BITSELECT,153)@5 rVStage_uid154_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q; rVStage_uid154_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_in(63 downto 32); --reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0(REG,366)@5 reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= "00000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid155_lzcZ_uid51_fpSinPiTest(LOGICAL,154)@6 vCount_uid155_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid155_lzcZ_uid51_fpSinPiTest_a = vCount_uid155_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f(DELAY,628)@6 ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid155_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q, clk => clk, aclr => areset ); --vStage_uid156_lzcZ_uid51_fpSinPiTest(BITSELECT,155)@5 vStage_uid156_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q(31 downto 0); vStage_uid156_lzcZ_uid51_fpSinPiTest_b <= vStage_uid156_lzcZ_uid51_fpSinPiTest_in(31 downto 0); --ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d(DELAY,596)@5 ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => vStage_uid156_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c(DELAY,595)@5 ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => rVStage_uid154_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid158_lzcZ_uid51_fpSinPiTest(MUX,157)@6 vStagei_uid158_lzcZ_uid51_fpSinPiTest_s <= vCount_uid155_lzcZ_uid51_fpSinPiTest_q; vStagei_uid158_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid158_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid158_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid160_lzcZ_uid51_fpSinPiTest(BITSELECT,159)@6 rVStage_uid160_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q; rVStage_uid160_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_in(31 downto 16); --reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0(REG,367)@6 reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid161_lzcZ_uid51_fpSinPiTest(LOGICAL,160)@7 vCount_uid161_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid161_lzcZ_uid51_fpSinPiTest_a = vCount_uid161_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e(DELAY,627)@7 ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid161_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q, clk => clk, aclr => areset ); --vStage_uid162_lzcZ_uid51_fpSinPiTest(BITSELECT,161)@6 vStage_uid162_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q(15 downto 0); vStage_uid162_lzcZ_uid51_fpSinPiTest_b <= vStage_uid162_lzcZ_uid51_fpSinPiTest_in(15 downto 0); --ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d(DELAY,602)@6 ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => vStage_uid162_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c(DELAY,601)@6 ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => rVStage_uid160_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid164_lzcZ_uid51_fpSinPiTest(MUX,163)@7 vStagei_uid164_lzcZ_uid51_fpSinPiTest_s <= vCount_uid161_lzcZ_uid51_fpSinPiTest_q; vStagei_uid164_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid164_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid164_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid166_lzcZ_uid51_fpSinPiTest(BITSELECT,165)@7 rVStage_uid166_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q; rVStage_uid166_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_in(15 downto 8); --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0(REG,368)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid167_lzcZ_uid51_fpSinPiTest(LOGICAL,166)@8 vCount_uid167_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid167_lzcZ_uid51_fpSinPiTest_a = vCount_uid167_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid168_lzcZ_uid51_fpSinPiTest(BITSELECT,167)@7 vStage_uid168_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q(7 downto 0); vStage_uid168_lzcZ_uid51_fpSinPiTest_b <= vStage_uid168_lzcZ_uid51_fpSinPiTest_in(7 downto 0); --reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3(REG,369)@7 reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= vStage_uid168_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2(REG,370)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vStagei_uid170_lzcZ_uid51_fpSinPiTest(MUX,169)@8 vStagei_uid170_lzcZ_uid51_fpSinPiTest_s <= vCount_uid167_lzcZ_uid51_fpSinPiTest_q; vStagei_uid170_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid170_lzcZ_uid51_fpSinPiTest_s, reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q, reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q) BEGIN CASE vStagei_uid170_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q; WHEN "1" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q; WHEN OTHERS => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid172_lzcZ_uid51_fpSinPiTest(BITSELECT,171)@8 rVStage_uid172_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q; rVStage_uid172_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_in(7 downto 4); --vCount_uid173_lzcZ_uid51_fpSinPiTest(LOGICAL,172)@8 vCount_uid173_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; vCount_uid173_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; vCount_uid173_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid173_lzcZ_uid51_fpSinPiTest_a = vCount_uid173_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid174_lzcZ_uid51_fpSinPiTest(BITSELECT,173)@8 vStage_uid174_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q(3 downto 0); vStage_uid174_lzcZ_uid51_fpSinPiTest_b <= vStage_uid174_lzcZ_uid51_fpSinPiTest_in(3 downto 0); --vStagei_uid176_lzcZ_uid51_fpSinPiTest(MUX,175)@8 vStagei_uid176_lzcZ_uid51_fpSinPiTest_s <= vCount_uid173_lzcZ_uid51_fpSinPiTest_q; vStagei_uid176_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid176_lzcZ_uid51_fpSinPiTest_s, rVStage_uid172_lzcZ_uid51_fpSinPiTest_b, vStage_uid174_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid176_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= vStage_uid174_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid178_lzcZ_uid51_fpSinPiTest(BITSELECT,177)@8 rVStage_uid178_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q; rVStage_uid178_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_in(3 downto 2); --vCount_uid179_lzcZ_uid51_fpSinPiTest(LOGICAL,178)@8 vCount_uid179_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; vCount_uid179_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; vCount_uid179_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid179_lzcZ_uid51_fpSinPiTest_a = vCount_uid179_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid180_lzcZ_uid51_fpSinPiTest(BITSELECT,179)@8 vStage_uid180_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q(1 downto 0); vStage_uid180_lzcZ_uid51_fpSinPiTest_b <= vStage_uid180_lzcZ_uid51_fpSinPiTest_in(1 downto 0); --vStagei_uid182_lzcZ_uid51_fpSinPiTest(MUX,181)@8 vStagei_uid182_lzcZ_uid51_fpSinPiTest_s <= vCount_uid179_lzcZ_uid51_fpSinPiTest_q; vStagei_uid182_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid182_lzcZ_uid51_fpSinPiTest_s, rVStage_uid178_lzcZ_uid51_fpSinPiTest_b, vStage_uid180_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid182_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= vStage_uid180_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid184_lzcZ_uid51_fpSinPiTest(BITSELECT,183)@8 rVStage_uid184_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid51_fpSinPiTest_q; rVStage_uid184_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_in(1 downto 1); --vCount_uid185_lzcZ_uid51_fpSinPiTest(LOGICAL,184)@8 vCount_uid185_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_b; vCount_uid185_lzcZ_uid51_fpSinPiTest_b <= GND_q; vCount_uid185_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid185_lzcZ_uid51_fpSinPiTest_a = vCount_uid185_lzcZ_uid51_fpSinPiTest_b else "0"; --r_uid186_lzcZ_uid51_fpSinPiTest(BITJOIN,185)@8 r_uid186_lzcZ_uid51_fpSinPiTest_q <= ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q & ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q & ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q & vCount_uid167_lzcZ_uid51_fpSinPiTest_q & vCount_uid173_lzcZ_uid51_fpSinPiTest_q & vCount_uid179_lzcZ_uid51_fpSinPiTest_q & vCount_uid185_lzcZ_uid51_fpSinPiTest_q; --leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest(BITSELECT,195)@8 leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q; leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in(6 downto 5); --reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1(REG,371)@8 reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest(MUX,196)@9 leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q, leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q; WHEN "01" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ozz_uid41_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest(BITSELECT,206)@8 leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(4 downto 0); leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in(4 downto 3); --reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1(REG,372)@8 reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest(MUX,207)@9 leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s, leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest(BITSELECT,215)@9 LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(72 downto 0); LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in(72 downto 0); --leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest(BITJOIN,216)@9 leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5(REG,374)@9 reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest(BITSELECT,212)@9 LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest(BITJOIN,213)@9 leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4(REG,375)@9 reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest(BITSELECT,209)@9 LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest(BITJOIN,210)@9 leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3(REG,376)@9 reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2(REG,377)@9 reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest(BITSELECT,217)@8 leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(2 downto 0); leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in(2 downto 1); --reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1(REG,373)@8 reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b(DELAY,657)@9 ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest(MUX,218)@10 leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s, reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q, reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q, reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q, reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q) BEGIN CASE leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q; WHEN "01" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q; WHEN "10" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q; WHEN "11" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q; WHEN OTHERS => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest(BITSELECT,222)@8 leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(0 downto 0); leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in(0 downto 0); --reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1(REG,378)@8 reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b(DELAY,665)@9 ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest(MUX,223)@10 leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s, leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q, leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q; WHEN "1" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --alignedZLow_uid53_fpSinPiTest(BITSELECT,52)@10 alignedZLow_uid53_fpSinPiTest_in <= leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q; alignedZLow_uid53_fpSinPiTest_b <= alignedZLow_uid53_fpSinPiTest_in(78 downto 27); --pHardCase_uid54_fpSinPiTest(BITJOIN,53)@10 pHardCase_uid54_fpSinPiTest_q <= alignedZLow_uid53_fpSinPiTest_b & GND_q; --ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b(DELAY,474)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 10 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q, clk => clk, aclr => areset ); --p_uid55_fpSinPiTest(MUX,54)@10 p_uid55_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q; p_uid55_fpSinPiTest: PROCESS (p_uid55_fpSinPiTest_s, pHardCase_uid54_fpSinPiTest_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q) BEGIN CASE p_uid55_fpSinPiTest_s IS WHEN "0" => p_uid55_fpSinPiTest_q <= pHardCase_uid54_fpSinPiTest_q; WHEN "1" => p_uid55_fpSinPiTest_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q; WHEN OTHERS => p_uid55_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt(COUNTER,1121) -- every=1, low=0, high=22, step=1, init=1 ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i = 21 THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i - 22; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i,5)); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg(REG,1122) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux(MUX,1123) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux: PROCESS (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q) BEGIN CASE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s IS WHEN "0" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; WHEN "1" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem(DUALMEM,1120) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 <= areset; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia <= p_uid55_fpSinPiTest_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 5, numwords_a => 23, width_b => 53, widthad_b => 5, numwords_b => 23, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq, address_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa, data_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia ); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq(52 downto 0); --mul2xSinRes_uid69_fpSinPiTest_a_1(BITSELECT,316)@34 mul2xSinRes_uid69_fpSinPiTest_a_1_in <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q); mul2xSinRes_uid69_fpSinPiTest_a_1_b <= mul2xSinRes_uid69_fpSinPiTest_a_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0(REG,424)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b1(MULT,322)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_b); mul2xSinRes_uid69_fpSinPiTest_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1(BITSELECT,329)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1(REG,425)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a_0(BITSELECT,315)@34 mul2xSinRes_uid69_fpSinPiTest_a_0_in <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_a_0_b <= mul2xSinRes_uid69_fpSinPiTest_a_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0(REG,426)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b1(MULT,321)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_b); mul2xSinRes_uid69_fpSinPiTest_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1(BITSELECT,327)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_zero_36(CONSTANT,332) mul2xSinRes_uid69_fpSinPiTest_zero_36_q <= "000000000000000000000000000"; --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2(BITJOIN,336)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1(BITSELECT,328)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_b_0(BITSELECT,317)@34 mul2xSinRes_uid69_fpSinPiTest_b_0_in <= multRightOp_uid68_fpSinPiTest_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_b_0_b <= mul2xSinRes_uid69_fpSinPiTest_b_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1(REG,421)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0(REG,422)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b0(MULT,320)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_b); mul2xSinRes_uid69_fpSinPiTest_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0(BITSELECT,325)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1(BITJOIN,335)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC(LOGICAL,340)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b; --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1(BITSELECT,330)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0(BITSELECT,326)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1(REG,419)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0(REG,420)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b0(MULT,319)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_b); mul2xSinRes_uid69_fpSinPiTest_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0(BITSELECT,324)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0(BITSELECT,323)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0(BITJOIN,334)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC(LOGICAL,339)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB(LOGICAL,338)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne(LOGICAL,341)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c; --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS(BITSELECT,342)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q(106 downto 0); mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in(106 downto 0); --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ(BITJOIN,343)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b & GND_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b(BITJOIN,350)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b(BITSELECT,353)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne(LOGICAL,337)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a(BITJOIN,348)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a(BITSELECT,352)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2(ADD,354)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin <= GND_q; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b) & mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c(0) <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(90); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(89 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b(DELAY,822)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q, clk => clk, aclr => areset ); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a(DELAY,821)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2(ADD,355)@39 mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q) & mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o(20 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a(DELAY,824)@39 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a : dspba_delay GENERIC MAP ( width => 89, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q(BITJOIN,356)@40 mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q; --normBit_uid70_fpSinPiTest(BITSELECT,69)@40 normBit_uid70_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(106 downto 0); normBit_uid70_fpSinPiTest_b <= normBit_uid70_fpSinPiTest_in(106 downto 106); --ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c(DELAY,497)@40 ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => normBit_uid70_fpSinPiTest_b, xout => ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q, clk => clk, aclr => areset ); --rndExpUpdate_uid75_uid76_fpSinPiTest(BITJOIN,75)@41 rndExpUpdate_uid75_uid76_fpSinPiTest_q <= ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q & cstAllZWF_uid10_fpSinPiTest_q & VCC_q; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor(LOGICAL,976) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q <= not (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a or ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top(CONSTANT,972) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q <= "011100"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp(LOGICAL,973) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a = ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b else "0"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg(REG,974) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena(REG,977) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q = "1") THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd(LOGICAL,978) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a and ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem(DUALMEM,941) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 <= areset; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia <= expX_uid6_fpSinPiTest_b; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 3, numwords_a => 7, width_b => 11, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq, address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa, data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia ); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq(10 downto 0); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg(DELAY,940) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q, clk => clk, aclr => areset ); --expXP1_uid58_fpSinPiTest(ADD,57)@9 expXP1_uid58_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q); expXP1_uid58_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & VCC_q); expXP1_uid58_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid58_fpSinPiTest_a) + UNSIGNED(expXP1_uid58_fpSinPiTest_b)); expXP1_uid58_fpSinPiTest_q <= expXP1_uid58_fpSinPiTest_o(11 downto 0); --expXP1R_uid59_fpSinPiTest(BITSELECT,58)@9 expXP1R_uid59_fpSinPiTest_in <= expXP1_uid58_fpSinPiTest_q(10 downto 0); expXP1R_uid59_fpSinPiTest_b <= expXP1R_uid59_fpSinPiTest_in(10 downto 0); --reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1(REG,427)@8 reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= r_uid186_lzcZ_uid51_fpSinPiTest_q; END IF; END PROCESS; --expHardCase_uid57_fpSinPiTest(SUB,56)@9 expHardCase_uid57_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid27_fpSinPiTest_q); expHardCase_uid57_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000" & reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q); expHardCase_uid57_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid57_fpSinPiTest_a) - UNSIGNED(expHardCase_uid57_fpSinPiTest_b)); expHardCase_uid57_fpSinPiTest_q <= expHardCase_uid57_fpSinPiTest_o(11 downto 0); --expHardCaseR_uid60_fpSinPiTest(BITSELECT,59)@9 expHardCaseR_uid60_fpSinPiTest_in <= expHardCase_uid57_fpSinPiTest_q(10 downto 0); expHardCaseR_uid60_fpSinPiTest_b <= expHardCaseR_uid60_fpSinPiTest_in(10 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b(DELAY,481)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 9 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q, clk => clk, aclr => areset ); --expP_uid61_fpSinPiTest(MUX,60)@9 expP_uid61_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q; expP_uid61_fpSinPiTest: PROCESS (expP_uid61_fpSinPiTest_s, expHardCaseR_uid60_fpSinPiTest_b, expXP1R_uid59_fpSinPiTest_b) BEGIN CASE expP_uid61_fpSinPiTest_s IS WHEN "0" => expP_uid61_fpSinPiTest_q <= expHardCaseR_uid60_fpSinPiTest_b; WHEN "1" => expP_uid61_fpSinPiTest_q <= expXP1R_uid59_fpSinPiTest_b; WHEN OTHERS => expP_uid61_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt(COUNTER,968) -- every=1, low=0, high=28, step=1, init=1 ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i = 27 THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i - 28; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg(REG,969) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux(MUX,970) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem(DUALMEM,967) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia <= expP_uid61_fpSinPiTest_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 29, width_b => 11, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq, address_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa, data_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia ); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq(10 downto 0); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg(DELAY,966) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q, xout => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --highRes_uid71_fpSinPiTest(BITSELECT,70)@40 highRes_uid71_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(105 downto 0); highRes_uid71_fpSinPiTest_b <= highRes_uid71_fpSinPiTest_in(105 downto 53); --lowRes_uid72_fpSinPiTest(BITSELECT,71)@40 lowRes_uid72_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(104 downto 0); lowRes_uid72_fpSinPiTest_b <= lowRes_uid72_fpSinPiTest_in(104 downto 52); --fracRCompPreRnd_uid73_fpSinPiTest(MUX,72)@40 fracRCompPreRnd_uid73_fpSinPiTest_s <= normBit_uid70_fpSinPiTest_b; fracRCompPreRnd_uid73_fpSinPiTest: PROCESS (fracRCompPreRnd_uid73_fpSinPiTest_s, lowRes_uid72_fpSinPiTest_b, highRes_uid71_fpSinPiTest_b) BEGIN CASE fracRCompPreRnd_uid73_fpSinPiTest_s IS WHEN "0" => fracRCompPreRnd_uid73_fpSinPiTest_q <= lowRes_uid72_fpSinPiTest_b; WHEN "1" => fracRCompPreRnd_uid73_fpSinPiTest_q <= highRes_uid71_fpSinPiTest_b; WHEN OTHERS => fracRCompPreRnd_uid73_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracPreRnd_uid74_uid74_fpSinPiTest(BITJOIN,73)@40 expFracPreRnd_uid74_uid74_fpSinPiTest_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q & fracRCompPreRnd_uid73_fpSinPiTest_q; --reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0(REG,428)@40 reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= expFracPreRnd_uid74_uid74_fpSinPiTest_q; END IF; END PROCESS; --expFracComp_uid77_fpSinPiTest(ADD,76)@41 expFracComp_uid77_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q); expFracComp_uid77_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & rndExpUpdate_uid75_uid76_fpSinPiTest_q); expFracComp_uid77_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid77_fpSinPiTest_a) + UNSIGNED(expFracComp_uid77_fpSinPiTest_b)); expFracComp_uid77_fpSinPiTest_q <= expFracComp_uid77_fpSinPiTest_o(64 downto 0); --expRComp_uid79_fpSinPiTest(BITSELECT,78)@41 expRComp_uid79_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(63 downto 0); expRComp_uid79_fpSinPiTest_b <= expRComp_uid79_fpSinPiTest_in(63 downto 53); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor(LOGICAL,1015) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q <= not (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a or ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top(CONSTANT,1011) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q <= "0100010"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp(LOGICAL,1012) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q <= "1" when ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a = ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b else "0"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg(REG,1013) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena(REG,1016) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q = "1") THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd(LOGICAL,1017) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a and ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b; --reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1(REG,429)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c(DELAY,516)@0 ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q, xout => ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b(DELAY,515)@0 ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => expXIsZero_uid15_fpSinPiTest_q, xout => ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q, clk => clk, aclr => areset ); --reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0(REG,361)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --excRZero_uid87_fpSinPiTest(LOGICAL,86)@3 excRZero_uid87_fpSinPiTest_a <= reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q; excRZero_uid87_fpSinPiTest_b <= ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q; excRZero_uid87_fpSinPiTest_c <= ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q; excRZero_uid87_fpSinPiTest_q <= excRZero_uid87_fpSinPiTest_a or excRZero_uid87_fpSinPiTest_b or excRZero_uid87_fpSinPiTest_c; --Or2ExcRZeroXIsInt_uid92_fpSinPiTest(LOGICAL,91)@3 Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a <= excRZero_uid87_fpSinPiTest_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b <= reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a or Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt(COUNTER,1007) -- every=1, low=0, high=34, step=1, init=1 ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i = 33 THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i - 34; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg(REG,1008) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux(MUX,1009) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux: PROCESS (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem(DUALMEM,1006) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 35, width_b => 1, widthad_b => 6, numwords_b => 35, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq, address_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa, data_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia ); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg(DELAY,1005) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q, xout => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --expRPostExc1_uid95_fpSinPiTest(MUX,94)@41 expRPostExc1_uid95_fpSinPiTest_s <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q; expRPostExc1_uid95_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE expRPostExc1_uid95_fpSinPiTest_s IS WHEN "0" => expRPostExc1_uid95_fpSinPiTest_q <= expRComp_uid79_fpSinPiTest_b; WHEN "1" => expRPostExc1_uid95_fpSinPiTest_q <= cstAllZWE_uid11_fpSinPiTest_q; WHEN OTHERS => expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --InvXIntExp_uid84_fpSinPiTest(LOGICAL,83)@2 InvXIntExp_uid84_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; InvXIntExp_uid84_fpSinPiTest_q <= not InvXIntExp_uid84_fpSinPiTest_a; --join_uid42_fpSinPiTest(BITJOIN,41)@2 join_uid42_fpSinPiTest_q <= VCC_q & ozz_uid41_fpSinPiTest_q; --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0(REG,359)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid43_fpSinPiTest(LOGICAL,42)@2 yIsZero_uid43_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q; yIsZero_uid43_fpSinPiTest_b <= join_uid42_fpSinPiTest_q; yIsZero_uid43_fpSinPiTest_q <= "1" when yIsZero_uid43_fpSinPiTest_a = yIsZero_uid43_fpSinPiTest_b else "0"; --And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest(LOGICAL,85)@2 And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b <= yIsZero_uid43_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c <= InvSinXIsX_uid80_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d <= InvXIntExp_uid84_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d; --Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest(LOGICAL,95)@1 Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a <= GND_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q <= Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a or Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b; --ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a(DELAY,528)@1 ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q, xout => ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q, clk => clk, aclr => areset ); --join_uid97_fpSinPiTest(BITJOIN,96)@2 join_uid97_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q & ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q; --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg(DELAY,1195) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => join_uid97_fpSinPiTest_q, xout => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q, clk => clk, aclr => areset ); --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem(DUALMEM,1196) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 <= areset; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 6, numwords_a => 37, width_b => 2, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0, clock1 => clk, address_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq, address_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa, data_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia ); ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq(1 downto 0); --reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1(REG,430)@41 reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q; END IF; END PROCESS; --expRPostExc_uid98_fpSinPiTest(MUX,97)@42 expRPostExc_uid98_fpSinPiTest_s <= reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q; expRPostExc_uid98_fpSinPiTest: PROCESS (expRPostExc_uid98_fpSinPiTest_s, expRPostExc1_uid95_fpSinPiTest_q) BEGIN CASE expRPostExc_uid98_fpSinPiTest_s IS WHEN "00" => expRPostExc_uid98_fpSinPiTest_q <= expRPostExc1_uid95_fpSinPiTest_q; WHEN "01" => expRPostExc_uid98_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q; WHEN "10" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN "11" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN OTHERS => expRPostExc_uid98_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --oneFracRPostExc2_uid90_fpSinPiTest(CONSTANT,89) oneFracRPostExc2_uid90_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracRComp_uid78_fpSinPiTest(BITSELECT,77)@41 fracRComp_uid78_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(52 downto 0); fracRComp_uid78_fpSinPiTest_b <= fracRComp_uid78_fpSinPiTest_in(52 downto 1); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor(LOGICAL,989) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q <= not (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a or ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top(CONSTANT,985) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q <= "0100001"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp(LOGICAL,986) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q <= "1" when ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a = ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b else "0"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg(REG,987) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena(REG,990) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q = "1") THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd(LOGICAL,991) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a and ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b; --reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1(REG,362)@3 reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= excRZero_uid87_fpSinPiTest_q; END IF; END PROCESS; --ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a(DELAY,517)@2 ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q, xout => ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q, clk => clk, aclr => areset ); --or_uid88_fpSinPiTest(LOGICAL,87)@4 or_uid88_fpSinPiTest_a <= ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q; or_uid88_fpSinPiTest_b <= reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q; or_uid88_fpSinPiTest_c <= GND_q; or_uid88_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN or_uid88_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN or_uid88_fpSinPiTest_q <= or_uid88_fpSinPiTest_a or or_uid88_fpSinPiTest_b or or_uid88_fpSinPiTest_c; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt(COUNTER,981) -- every=1, low=0, high=33, step=1, init=1 ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i = 32 THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i - 33; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg(REG,982) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux(MUX,983) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux: PROCESS (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem(DUALMEM,980) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia <= or_uid88_fpSinPiTest_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 34, width_b => 1, widthad_b => 6, numwords_b => 34, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq, address_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa, data_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia ); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg(DELAY,979) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q, xout => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --fracRPostExc1_uid89_fpSinPiTest(MUX,88)@41 fracRPostExc1_uid89_fpSinPiTest_s <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q; fracRPostExc1_uid89_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE fracRPostExc1_uid89_fpSinPiTest_s IS WHEN "0" => fracRPostExc1_uid89_fpSinPiTest_q <= fracRComp_uid78_fpSinPiTest_b; WHEN "1" => fracRPostExc1_uid89_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q; WHEN OTHERS => fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor(LOGICAL,1002) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q <= not (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a or ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top(CONSTANT,998) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q <= "0100110"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp(LOGICAL,999) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q <= "1" when ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a = ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b else "0"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg(REG,1000) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena(REG,1003) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q = "1") THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd(LOGICAL,1004) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a and ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg(DELAY,992) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q, xout => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q, clk => clk, aclr => areset ); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt(COUNTER,994) -- every=1, low=0, high=38, step=1, init=1 ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i = 37 THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i - 38; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg(REG,995) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux(MUX,996) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux: PROCESS (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem(DUALMEM,993) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 39, width_b => 1, widthad_b => 6, numwords_b => 39, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq, address_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa, data_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia ); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq(0 downto 0); --fracRPostExc_uid91_fpSinPiTest(MUX,90)@42 fracRPostExc_uid91_fpSinPiTest_s <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q; fracRPostExc_uid91_fpSinPiTest: PROCESS (fracRPostExc_uid91_fpSinPiTest_s, fracRPostExc1_uid89_fpSinPiTest_q) BEGIN CASE fracRPostExc_uid91_fpSinPiTest_s IS WHEN "0" => fracRPostExc_uid91_fpSinPiTest_q <= fracRPostExc1_uid89_fpSinPiTest_q; WHEN "1" => fracRPostExc_uid91_fpSinPiTest_q <= oneFracRPostExc2_uid90_fpSinPiTest_q; WHEN OTHERS => fracRPostExc_uid91_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid105_fpSinPiTest(BITJOIN,104)@42 R_uid105_fpSinPiTest_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q & expRPostExc_uid98_fpSinPiTest_q & fracRPostExc_uid91_fpSinPiTest_q; --ld_xIn_v_to_xOut_v_nor(LOGICAL,910) ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b); --ld_xIn_v_to_xOut_v_mem_top(CONSTANT,906) ld_xIn_v_to_xOut_v_mem_top_q <= "0100111"; --ld_xIn_v_to_xOut_v_cmp(LOGICAL,907) ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q; ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q); ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0"; --ld_xIn_v_to_xOut_v_cmpReg(REG,908) ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_sticky_ena(REG,911) ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q; END IF; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,912) ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q; ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b; --ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,902) -- every=1, low=0, high=39, step=1, init=1 ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 38 THEN ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1'; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; END IF; IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 39; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,6)); --ld_xIn_v_to_xOut_v_replace_rdreg(REG,903) ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_replace_rdmux(MUX,904) ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q; ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q) BEGIN CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q; WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,914) ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset; ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c; ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 6, numwords_a => 40, width_b => 8, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_c_to_xOut_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_c_to_xOut_c_replace_mem_iq, address_a => ld_xIn_c_to_xOut_c_replace_mem_aa, data_a => ld_xIn_c_to_xOut_c_replace_mem_ia ); ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0); --ld_xIn_c_to_xOut_c_outputreg(DELAY,913) ld_xIn_c_to_xOut_c_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset ); --ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,901) ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset; ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v; ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 40, width_b => 1, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_v_to_xOut_v_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_v_to_xOut_v_replace_mem_iq, address_a => ld_xIn_v_to_xOut_v_replace_mem_aa, data_a => ld_xIn_v_to_xOut_v_replace_mem_ia ); ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0); --ld_xIn_v_to_xOut_v_outputreg(DELAY,900) ld_xIn_v_to_xOut_v_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset ); --xOut(PORTOUT,4)@42 xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q; xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q; xOut_0 <= R_uid105_fpSinPiTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Debug Version 12.0 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from SinPiDPStratixVf400 -- VHDL created on Wed Sep 05 17:55:57 2012 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; USE work.SinPiDPStratixVf400_safe_path.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; -- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240 entity SinPiDPStratixVf400 is port ( xIn_v : in std_logic_vector(0 downto 0); xIn_c : in std_logic_vector(7 downto 0); xIn_0 : in std_logic_vector(63 downto 0); xOut_v : out std_logic_vector(0 downto 0); xOut_c : out std_logic_vector(7 downto 0); xOut_0 : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic; bus_clk : in std_logic; h_areset : in std_logic ); end; architecture normal of SinPiDPStratixVf400 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBias_uid12_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBiasPwF_uid13_fpSinPiTest_q : std_logic_vector (10 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0); signal biasM1_uid27_fpSinPiTest_q : std_logic_vector (10 downto 0); signal biasMwShift_uid29_fpSinPiTest_q : std_logic_vector (10 downto 0); signal shiftBias_uid32_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cst01pWShift_uid34_fpSinPiTest_q : std_logic_vector (27 downto 0); signal ozz_uid41_fpSinPiTest_q : std_logic_vector (78 downto 0); signal cOne_uid44_fpSinPiTest_q : std_logic_vector (80 downto 0); signal oneMinusY_uid45_fpSinPiTest_a : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_b : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_o : std_logic_vector (81 downto 0); signal oneMinusY_uid45_fpSinPiTest_q : std_logic_vector (81 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_a : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_b : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_o : std_logic_vector (84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_c : std_logic_vector (0 downto 0); signal piwFP2_uid67_fpSinPiTest_q : std_logic_vector (53 downto 0); signal or_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_b : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_c : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_q : std_logic_vector (51 downto 0); signal oneFracRPostExc2_uid90_fpSinPiTest_q : std_logic_vector (51 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (10 downto 0); signal InvXIsInt_uid100_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIsInt_uid100_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (31 downto 0); signal leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (63 downto 0); signal leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (15 downto 0); signal leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (23 downto 0); signal leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (5 downto 0); signal mO_uid148_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (48 downto 0); signal memoryC3_uid229_sinPiZTableGenerator_q : std_logic_vector(34 downto 0); signal memoryC4_uid230_sinPiZTableGenerator_q : std_logic_vector(25 downto 0); signal memoryC5_uid231_sinPiZTableGenerator_q : std_logic_vector(16 downto 0); signal rndBit_uid246_sinPiZPolyEval_q : std_logic_vector (1 downto 0); signal rndBit_uid258_sinPiZPolyEval_q : std_logic_vector (2 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_a : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 : std_logic_vector (33 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr : SIGNED (34 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_q : std_logic_vector (33 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_a : std_logic_vector (25 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_zero_36_q : std_logic_vector (26 downto 0); type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type; signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q : std_logic_vector (36 downto 0); type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o : std_logic_vector (90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o : std_logic_vector (21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q : std_logic_vector (19 downto 0); signal reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q : std_logic_vector (80 downto 0); signal reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q : std_logic_vector (80 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q : std_logic_vector (0 downto 0); signal reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (31 downto 0); signal reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (15 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (7 downto 0); signal reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q : std_logic_vector (7 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q : std_logic_vector (7 downto 0); signal reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q : std_logic_vector (78 downto 0); signal reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q : std_logic_vector (16 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q : std_logic_vector (25 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q : std_logic_vector (16 downto 0); signal reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q : std_logic_vector (17 downto 0); signal reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q : std_logic_vector (36 downto 0); signal reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q : std_logic_vector (44 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q : std_logic_vector (45 downto 0); signal reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q : std_logic_vector (51 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q : std_logic_vector (53 downto 0); signal reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q : std_logic_vector (60 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q : std_logic_vector (26 downto 0); signal reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q : std_logic_vector (6 downto 0); signal reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q : std_logic_vector (78 downto 0); signal ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q : std_logic_vector (78 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q : std_logic_vector (78 downto 0); signal ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q : std_logic_vector (14 downto 0); signal ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (63 downto 0); signal ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (31 downto 0); signal ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (31 downto 0); signal ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (15 downto 0); signal ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (15 downto 0); signal ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q : std_logic_vector (0 downto 0); signal ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q : std_logic_vector (0 downto 0); signal ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (1 downto 0); signal ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (42 downto 0); signal ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q : std_logic_vector (88 downto 0); signal ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q : std_logic_vector (79 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic; signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic; signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic; signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 : std_logic; signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i : unsigned(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q : std_logic_vector (3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i : unsigned(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q : std_logic_vector (6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i : unsigned(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q : std_logic_vector (2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (14 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ir : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i : unsigned(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q : std_logic_vector (2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ir : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ir : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 : std_logic; signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ir : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0); signal yIsZero_uid40_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (18 downto 0); signal pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal z_uid49_fpSinPiTest_s : std_logic_vector (0 downto 0); signal z_uid49_fpSinPiTest_q : std_logic_vector (78 downto 0); signal expHardCase_uid57_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expHardCase_uid57_fpSinPiTest_q : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_q : std_logic_vector (11 downto 0); signal rndExpUpdate_uid75_uid76_fpSinPiTest_q : std_logic_vector (53 downto 0); signal expFracComp_uid77_fpSinPiTest_a : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_b : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_o : std_logic_vector (64 downto 0); signal expFracComp_uid77_fpSinPiTest_q : std_logic_vector (64 downto 0); signal fracRPostExc_uid91_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc_uid91_fpSinPiTest_q : std_logic_vector (51 downto 0); signal expRPostExc_uid98_fpSinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid98_fpSinPiTest_q : std_logic_vector (10 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal memoryC0_uid226_sinPiZTableGenerator_q : std_logic_vector(57 downto 0); signal memoryC1_uid227_sinPiZTableGenerator_q : std_logic_vector(49 downto 0); signal memoryC2_uid228_sinPiZTableGenerator_q : std_logic_vector(42 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_a : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_b : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_o : std_logic_vector (35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_q : std_logic_vector (35 downto 0); signal ts3_uid248_sinPiZPolyEval_a : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_b : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_o : std_logic_vector (45 downto 0); signal ts3_uid248_sinPiZPolyEval_q : std_logic_vector (45 downto 0); signal ts4_uid254_sinPiZPolyEval_a : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_b : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_o : std_logic_vector (52 downto 0); signal ts4_uid254_sinPiZPolyEval_q : std_logic_vector (52 downto 0); signal ts5_uid260_sinPiZPolyEval_a : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_b : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_o : std_logic_vector (61 downto 0); signal ts5_uid260_sinPiZPolyEval_q : std_logic_vector (61 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal join_uid42_fpSinPiTest_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal expX_uid6_fpSinPiTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSinPiTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSinPiTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSinPiTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0); signal expXIsMax_uid16_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSinPiTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid15_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_q : std_logic_vector(0 downto 0); signal xIntExp_uid26_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xIntExp_uid26_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xIntExp_uid26_fpSinPiTest_c : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xFrac_uid28_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_n : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_a : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_b : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_o : std_logic_vector (13 downto 0); signal sinXIsX_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0); signal shiftValue_uid33_fpSinPiTest_a : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_b : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_o : std_logic_vector (11 downto 0); signal shiftValue_uid33_fpSinPiTest_q : std_logic_vector (11 downto 0); signal oMyBottom_uid47_fpSinPiTest_in : std_logic_vector (78 downto 0); signal oMyBottom_uid47_fpSinPiTest_b : std_logic_vector (78 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid150_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal cIncludingRoundingBit_uid247_sinPiZPolyEval_q : std_logic_vector (44 downto 0); signal cIncludingRoundingBit_uid253_sinPiZPolyEval_q : std_logic_vector (51 downto 0); signal cIncludingRoundingBit_uid259_sinPiZPolyEval_q : std_logic_vector (60 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q : std_logic_vector (107 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (29 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (46 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q : std_logic_vector (108 downto 0); signal yIsZero_uid43_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zPPolyEval_uid64_fpSinPiTest_in : std_logic_vector (71 downto 0); signal zPPolyEval_uid64_fpSinPiTest_b : std_logic_vector (44 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_q : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_c : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (31 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (15 downto 0); signal s2_uid240_uid243_sinPiZPolyEval_q : std_logic_vector (36 downto 0); signal add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (55 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (42 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (72 downto 0); signal add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal R_uid105_fpSinPiTest_q : std_logic_vector (63 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal yT3_uid244_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT3_uid244_sinPiZPolyEval_b : std_logic_vector (34 downto 0); signal yT4_uid250_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT4_uid250_sinPiZPolyEval_b : std_logic_vector (42 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q : std_logic_vector(0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_b : std_logic_vector (26 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zAddr_uid63_fpSinPiTest_in : std_logic_vector (78 downto 0); signal zAddr_uid63_fpSinPiTest_b : std_logic_vector (6 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (78 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (63 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (14 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (14 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (46 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (46 downto 0); signal expHardCaseR_uid60_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expHardCaseR_uid60_fpSinPiTest_b : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracRComp_uid78_fpSinPiTest_in : std_logic_vector (52 downto 0); signal fracRComp_uid78_fpSinPiTest_b : std_logic_vector (51 downto 0); signal expRComp_uid79_fpSinPiTest_in : std_logic_vector (63 downto 0); signal expRComp_uid79_fpSinPiTest_b : std_logic_vector (10 downto 0); signal intXParity_uid38_fpSinPiTest_in : std_logic_vector (80 downto 0); signal intXParity_uid38_fpSinPiTest_b : std_logic_vector (0 downto 0); signal y_uid39_fpSinPiTest_in : std_logic_vector (79 downto 0); signal y_uid39_fpSinPiTest_b : std_logic_vector (79 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (77 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (77 downto 0); signal s3_uid249_sinPiZPolyEval_in : std_logic_vector (45 downto 0); signal s3_uid249_sinPiZPolyEval_b : std_logic_vector (44 downto 0); signal s4_uid255_sinPiZPolyEval_in : std_logic_vector (52 downto 0); signal s4_uid255_sinPiZPolyEval_b : std_logic_vector (51 downto 0); signal s5_uid261_sinPiZPolyEval_in : std_logic_vector (61 downto 0); signal s5_uid261_sinPiZPolyEval_b : std_logic_vector (60 downto 0); signal oFracX_uid31_uid31_fpSinPiTest_q : std_logic_vector (52 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_in : std_logic_vector (6 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_b : std_logic_vector (6 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid235_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal highBBits_uid235_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid241_sinPiZPolyEval_in : std_logic_vector (28 downto 0); signal highBBits_uid241_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q : std_logic_vector(107 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (29 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (46 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal normBit_uid70_fpSinPiTest_in : std_logic_vector (106 downto 0); signal normBit_uid70_fpSinPiTest_b : std_logic_vector (0 downto 0); signal highRes_uid71_fpSinPiTest_in : std_logic_vector (105 downto 0); signal highRes_uid71_fpSinPiTest_b : std_logic_vector (52 downto 0); signal lowRes_uid72_fpSinPiTest_in : std_logic_vector (104 downto 0); signal lowRes_uid72_fpSinPiTest_b : std_logic_vector (52 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (70 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (70 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (62 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (62 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (54 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (54 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q : std_logic_vector(0 downto 0); signal yT1_uid232_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT1_uid232_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal yT2_uid238_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT2_uid238_sinPiZPolyEval_b : std_logic_vector (25 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (63 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (9 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (9 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (36 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (71 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (45 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (78 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (7 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (7 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (15 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (15 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expP_uid61_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expP_uid61_fpSinPiTest_q : std_logic_vector (10 downto 0); signal yBottom_uid48_fpSinPiTest_in : std_logic_vector (78 downto 0); signal yBottom_uid48_fpSinPiTest_b : std_logic_vector (78 downto 0); signal leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (51 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal fxpSinRes_uid66_fpSinPiTest_in : std_logic_vector (58 downto 0); signal fxpSinRes_uid66_fpSinPiTest_b : std_logic_vector (53 downto 0); signal extendedFracX_uid35_fpSinPiTest_q : std_logic_vector (80 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (0 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_a : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_b : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_o : std_logic_vector (26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q : std_logic_vector(107 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_q : std_logic_vector (52 downto 0); signal join_uid97_fpSinPiTest_q : std_logic_vector (1 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal signR_uid104_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (10 downto 0); signal pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (16 downto 0); signal pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal xIsInt_uid83_fpSinPiTest_a : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_b : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal multRightOp_uid68_fpSinPiTest_s : std_logic_vector (0 downto 0); signal multRightOp_uid68_fpSinPiTest_q : std_logic_vector (53 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (48 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (48 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (16 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (16 downto 0); signal s1_uid234_uid237_sinPiZPolyEval_q : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c : std_logic_vector (19 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in : std_logic_vector (106 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b : std_logic_vector (106 downto 0); signal expFracPreRnd_uid74_uid74_fpSinPiTest_q : std_logic_vector (63 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (17 downto 0); signal alignedZLow_uid53_fpSinPiTest_in : std_logic_vector (78 downto 0); signal alignedZLow_uid53_fpSinPiTest_b : std_logic_vector (51 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_b : std_logic_vector (26 downto 0); signal leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q : std_logic_vector (107 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (1 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (74 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (72 downto 0); signal pHardCase_uid54_fpSinPiTest_q : std_logic_vector (52 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q : std_logic_vector (108 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (0 downto 0); signal leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal p_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0); signal p_uid55_fpSinPiTest_q : std_logic_vector (52 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (72 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (64 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (64 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (56 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (56 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c : std_logic_vector (19 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal r_uid186_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (6 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (0 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (78 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (78 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (74 downto 0); signal leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (79 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (79 downto 0); signal leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); begin --ld_xIn_v_to_xOut_v_notEnable(LOGICAL,909) ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q; ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor(LOGICAL,1028) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q <= not (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a or ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top(CONSTANT,1024) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q <= "0100100"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp(LOGICAL,1025) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q <= "1" when ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a = ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b else "0"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg(REG,1026) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena(REG,1029) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q = "1") THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd(LOGICAL,1030) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a and ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b; --LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest(BITSELECT,134)@0 LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest(CONSTANT,133) leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q <= "000000"; --leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest(BITJOIN,135)@0 leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest(BITSELECT,131)@0 LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest(CONSTANT,130) leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q <= "0000"; --leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest(BITJOIN,132)@0 leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest(BITSELECT,128)@0 LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(78 downto 0); LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in(78 downto 0); --leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest(CONSTANT,127) leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q <= "00"; --leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest(BITJOIN,129)@0 leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest(BITSELECT,123)@0 LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(56 downto 0); LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in(56 downto 0); --leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest(CONSTANT,122) leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000"; --leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest(BITJOIN,124)@0 leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest(BITSELECT,120)@0 LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(64 downto 0); LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in(64 downto 0); --leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest(CONSTANT,119) leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000"; --leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest(BITJOIN,121)@0 leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest(BITSELECT,117)@0 LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(72 downto 0); LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in(72 downto 0); --leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest(CONSTANT,116) leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q <= "00000000"; --leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest(BITJOIN,118)@0 leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest(CONSTANT,113) leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; --X16dto0_uid112_fixedPointX_uid37_fpSinPiTest(BITSELECT,111)@0 X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(16 downto 0); X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in(16 downto 0); --leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest(CONSTANT,110) leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000"; --leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest(BITJOIN,112)@0 leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X48dto0_uid109_fixedPointX_uid37_fpSinPiTest(BITSELECT,108)@0 X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(48 downto 0); X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in(48 downto 0); --leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest(CONSTANT,107) leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q <= "00000000000000000000000000000000"; --leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest(BITJOIN,109)@0 leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --cst01pWShift_uid34_fpSinPiTest(CONSTANT,33) cst01pWShift_uid34_fpSinPiTest_q <= "0000000000000000000000000000"; --xIn(PORTIN,3)@0 --fracX_uid7_fpSinPiTest(BITSELECT,6)@0 fracX_uid7_fpSinPiTest_in <= xIn_0(51 downto 0); fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(51 downto 0); --oFracX_uid31_uid31_fpSinPiTest(BITJOIN,30)@0 oFracX_uid31_uid31_fpSinPiTest_q <= VCC_q & fracX_uid7_fpSinPiTest_b; --extendedFracX_uid35_fpSinPiTest(BITJOIN,34)@0 extendedFracX_uid35_fpSinPiTest_q <= cst01pWShift_uid34_fpSinPiTest_q & oFracX_uid31_uid31_fpSinPiTest_q; --shiftBias_uid32_fpSinPiTest(CONSTANT,31) shiftBias_uid32_fpSinPiTest_q <= "01111100011"; --expX_uid6_fpSinPiTest(BITSELECT,5)@0 expX_uid6_fpSinPiTest_in <= xIn_0(62 downto 0); expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(62 downto 52); --shiftValue_uid33_fpSinPiTest(SUB,32)@0 shiftValue_uid33_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b); shiftValue_uid33_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid32_fpSinPiTest_q); shiftValue_uid33_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid33_fpSinPiTest_a) - UNSIGNED(shiftValue_uid33_fpSinPiTest_b)); shiftValue_uid33_fpSinPiTest_q <= shiftValue_uid33_fpSinPiTest_o(11 downto 0); --fxpShifterBits_uid36_fpSinPiTest(BITSELECT,35)@0 fxpShifterBits_uid36_fpSinPiTest_in <= shiftValue_uid33_fpSinPiTest_q(6 downto 0); fxpShifterBits_uid36_fpSinPiTest_b <= fxpShifterBits_uid36_fpSinPiTest_in(6 downto 0); --leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest(BITSELECT,114)@0 leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b; leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in(6 downto 5); --leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest(MUX,115)@0 leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s, extendedFracX_uid35_fpSinPiTest_q, leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= extendedFracX_uid35_fpSinPiTest_q; WHEN "01" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest(BITSELECT,125)@0 leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(4 downto 0); leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in(4 downto 3); --leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest(MUX,126)@0 leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest(BITSELECT,136)@0 leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(2 downto 0); leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in(2 downto 1); --leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest(MUX,137)@0 leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest(BITSELECT,139)@0 LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in(79 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest(BITJOIN,140)@0 leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b & GND_q; --reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3(REG,357)@0 reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2(REG,358)@0 reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest(BITSELECT,141)@0 leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(0 downto 0); leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in(0 downto 0); --ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b(DELAY,581)@0 ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest(MUX,142)@1 leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q; leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s, reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q, reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q) BEGIN CASE leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q; WHEN "1" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q; WHEN OTHERS => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --intXParity_uid38_fpSinPiTest(BITSELECT,37)@1 intXParity_uid38_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q; intXParity_uid38_fpSinPiTest_b <= intXParity_uid38_fpSinPiTest_in(80 downto 80); --ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c(DELAY,536)@1 ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => intXParity_uid38_fpSinPiTest_b, xout => ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q, clk => clk, aclr => areset ); --biasM1_uid27_fpSinPiTest(CONSTANT,26) biasM1_uid27_fpSinPiTest_q <= "01111111110"; --xFrac_uid28_fpSinPiTest(COMPARE,27)@0 xFrac_uid28_fpSinPiTest_cin <= GND_q; xFrac_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid27_fpSinPiTest_q) & '0'; xFrac_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid28_fpSinPiTest_cin(0); xFrac_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid28_fpSinPiTest_a) - UNSIGNED(xFrac_uid28_fpSinPiTest_b)); xFrac_uid28_fpSinPiTest_n(0) <= not xFrac_uid28_fpSinPiTest_o(13); --ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a(DELAY,532)@0 ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => xFrac_uid28_fpSinPiTest_n, xout => ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvXFrac_uid99_fpSinPiTest(LOGICAL,98)@3 InvXFrac_uid99_fpSinPiTest_a <= ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q; InvXFrac_uid99_fpSinPiTest_q <= not InvXFrac_uid99_fpSinPiTest_a; --biasMwShift_uid29_fpSinPiTest(CONSTANT,28) biasMwShift_uid29_fpSinPiTest_q <= "01111100100"; --sinXIsX_uid30_fpSinPiTest(COMPARE,29)@0 sinXIsX_uid30_fpSinPiTest_cin <= GND_q; sinXIsX_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0'; sinXIsX_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid29_fpSinPiTest_q) & sinXIsX_uid30_fpSinPiTest_cin(0); sinXIsX_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid30_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid30_fpSinPiTest_b)); sinXIsX_uid30_fpSinPiTest_c(0) <= sinXIsX_uid30_fpSinPiTest_o(13); --ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a(DELAY,502)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvSinXIsX_uid80_fpSinPiTest(LOGICAL,79)@2 InvSinXIsX_uid80_fpSinPiTest_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q; InvSinXIsX_uid80_fpSinPiTest_q <= not InvSinXIsX_uid80_fpSinPiTest_a; --y_uid39_fpSinPiTest(BITSELECT,38)@1 y_uid39_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); y_uid39_fpSinPiTest_b <= y_uid39_fpSinPiTest_in(79 downto 0); --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0(REG,360)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid40_fpSinPiTest(LOGICAL,39)@2 yIsZero_uid40_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q; yIsZero_uid40_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000000000000000000000000000000000000000000000000" & GND_q); yIsZero_uid40_fpSinPiTest_q <= "1" when yIsZero_uid40_fpSinPiTest_a = yIsZero_uid40_fpSinPiTest_b else "0"; --And2YIsZeroInvSinXIsX_uid81_fpSinPiTest(LOGICAL,80)@2 And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a <= yIsZero_uid40_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b <= InvSinXIsX_uid80_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a and And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b; --cstBiasPwF_uid13_fpSinPiTest(CONSTANT,12) cstBiasPwF_uid13_fpSinPiTest_q <= "10000110011"; --xIntExp_uid26_fpSinPiTest(COMPARE,25)@0 xIntExp_uid26_fpSinPiTest_cin <= GND_q; xIntExp_uid26_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid13_fpSinPiTest_q) & '0'; xIntExp_uid26_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid26_fpSinPiTest_cin(0); xIntExp_uid26_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid26_fpSinPiTest_a) - UNSIGNED(xIntExp_uid26_fpSinPiTest_b)); xIntExp_uid26_fpSinPiTest_c(0) <= xIntExp_uid26_fpSinPiTest_o(13); --ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a(DELAY,505)@0 ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => xIntExp_uid26_fpSinPiTest_c, xout => ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q, clk => clk, aclr => areset ); --Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest(LOGICAL,81)@2 Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a or Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b; --cstAllZWF_uid10_fpSinPiTest(CONSTANT,9) cstAllZWF_uid10_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracXIsZero_uid17_fpSinPiTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b; fracXIsZero_uid17_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q; fracXIsZero_uid17_fpSinPiTest_q <= "1" when fracXIsZero_uid17_fpSinPiTest_a = fracXIsZero_uid17_fpSinPiTest_b else "0"; --ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a(DELAY,442)@0 ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => fracXIsZero_uid17_fpSinPiTest_q, xout => ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvFracXIsZero_uid19_fpSinPiTest(LOGICAL,18)@1 InvFracXIsZero_uid19_fpSinPiTest_a <= ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q; InvFracXIsZero_uid19_fpSinPiTest_q <= not InvFracXIsZero_uid19_fpSinPiTest_a; --cstAllOWE_uid9_fpSinPiTest(CONSTANT,8) cstAllOWE_uid9_fpSinPiTest_q <= "11111111111"; --expXIsMax_uid16_fpSinPiTest(LOGICAL,15)@0 expXIsMax_uid16_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsMax_uid16_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q; expXIsMax_uid16_fpSinPiTest_q <= "1" when expXIsMax_uid16_fpSinPiTest_a = expXIsMax_uid16_fpSinPiTest_b else "0"; --ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a(DELAY,443)@0 ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsMax_uid16_fpSinPiTest_q, xout => ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest(LOGICAL,19)@1 And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a <= ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b <= InvFracXIsZero_uid19_fpSinPiTest_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a and And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b; --InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest(LOGICAL,20)@1 InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q <= not InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a; --And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0 And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a <= expXIsMax_uid16_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b <= fracXIsZero_uid17_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a and And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b; --InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0 InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q; InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q <= not InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a; --cstAllZWE_uid11_fpSinPiTest(CONSTANT,10) cstAllZWE_uid11_fpSinPiTest_q <= "00000000000"; --expXIsZero_uid15_fpSinPiTest(LOGICAL,14)@0 expXIsZero_uid15_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsZero_uid15_fpSinPiTest_b <= cstAllZWE_uid11_fpSinPiTest_q; expXIsZero_uid15_fpSinPiTest_q <= "1" when expXIsZero_uid15_fpSinPiTest_a = expXIsZero_uid15_fpSinPiTest_b else "0"; --InvExpXIsZero_uid23_fpSinPiTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSinPiTest_a <= expXIsZero_uid15_fpSinPiTest_q; InvExpXIsZero_uid23_fpSinPiTest_q <= not InvExpXIsZero_uid23_fpSinPiTest_a; --And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0 And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a <= InvExpXIsZero_uid23_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b <= InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a and And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b; --ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a(DELAY,450)@0 ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q, xout => ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest(LOGICAL,24)@1 And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a <= ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b <= InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a and And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b; END IF; END PROCESS; --xIsInt_uid83_fpSinPiTest(LOGICAL,82)@2 xIsInt_uid83_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_b <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_q <= xIsInt_uid83_fpSinPiTest_a and xIsInt_uid83_fpSinPiTest_b; --InvXIsInt_uid100_fpSinPiTest(LOGICAL,99)@2 InvXIsInt_uid100_fpSinPiTest_a <= xIsInt_uid83_fpSinPiTest_q; InvXIsInt_uid100_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= not InvXIsInt_uid100_fpSinPiTest_a; END IF; END PROCESS; --signComp_uid101_fpSinPiTest(LOGICAL,100)@3 signComp_uid101_fpSinPiTest_a <= InvXIsInt_uid100_fpSinPiTest_q; signComp_uid101_fpSinPiTest_b <= InvXFrac_uid99_fpSinPiTest_q; signComp_uid101_fpSinPiTest_c <= ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q; signComp_uid101_fpSinPiTest_q <= signComp_uid101_fpSinPiTest_a and signComp_uid101_fpSinPiTest_b and signComp_uid101_fpSinPiTest_c; --ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a(DELAY,537)@2 ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => yIsZero_uid40_fpSinPiTest_q, xout => ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvYIsZero_uid102_fpSinPiTest(LOGICAL,101)@3 InvYIsZero_uid102_fpSinPiTest_a <= ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q; InvYIsZero_uid102_fpSinPiTest_q <= not InvYIsZero_uid102_fpSinPiTest_a; --And2InvYIsZeroSignComp_uid103_fpSinPiTest(LOGICAL,102)@3 And2InvYIsZeroSignComp_uid103_fpSinPiTest_a <= InvYIsZero_uid102_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_b <= signComp_uid101_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_q <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_a and And2InvYIsZeroSignComp_uid103_fpSinPiTest_b; --signX_uid8_fpSinPiTest(BITSELECT,7)@0 signX_uid8_fpSinPiTest_in <= xIn_0; signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(63 downto 63); --ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a(DELAY,540)@0 ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q, clk => clk, aclr => areset ); --signR_uid104_fpSinPiTest(LOGICAL,103)@3 signR_uid104_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q; signR_uid104_fpSinPiTest_b <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_q; signR_uid104_fpSinPiTest_q <= signR_uid104_fpSinPiTest_a xor signR_uid104_fpSinPiTest_b; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt(COUNTER,1020) -- every=1, low=0, high=36, step=1, init=1 ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i = 35 THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i - 36; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i,6)); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg(REG,1021) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --VCC(CONSTANT,1) VCC_q <= "1"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux(MUX,1022) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux: PROCESS (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem(DUALMEM,1019) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia <= signR_uid104_fpSinPiTest_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 37, width_b => 1, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq, address_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa, data_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia ); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq(0 downto 0); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg(DELAY,1018) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q, xout => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --cstBias_uid12_fpSinPiTest(CONSTANT,11) cstBias_uid12_fpSinPiTest_q <= "01111111111"; --piwFP2_uid67_fpSinPiTest(CONSTANT,66) piwFP2_uid67_fpSinPiTest_q <= "110010010000111111011010101000100010000101101000110001"; --reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1(REG,363)@1 reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --cOne_uid44_fpSinPiTest(CONSTANT,43) cOne_uid44_fpSinPiTest_q <= "100000000000000000000000000000000000000000000000000000000000000000000000000000000"; --oneMinusY_uid45_fpSinPiTest(SUB,44)@2 oneMinusY_uid45_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid44_fpSinPiTest_q); oneMinusY_uid45_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q); oneMinusY_uid45_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid45_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid45_fpSinPiTest_b)); END IF; END PROCESS; oneMinusY_uid45_fpSinPiTest_q <= oneMinusY_uid45_fpSinPiTest_o(81 downto 0); --oMyBottom_uid47_fpSinPiTest(BITSELECT,46)@3 oMyBottom_uid47_fpSinPiTest_in <= oneMinusY_uid45_fpSinPiTest_q(78 downto 0); oMyBottom_uid47_fpSinPiTest_b <= oMyBottom_uid47_fpSinPiTest_in(78 downto 0); --ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d(DELAY,471)@3 ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => oMyBottom_uid47_fpSinPiTest_b, xout => ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q, clk => clk, aclr => areset ); --yBottom_uid48_fpSinPiTest(BITSELECT,47)@1 yBottom_uid48_fpSinPiTest_in <= y_uid39_fpSinPiTest_b(78 downto 0); yBottom_uid48_fpSinPiTest_b <= yBottom_uid48_fpSinPiTest_in(78 downto 0); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c(DELAY,470)@1 ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 79, depth => 2 ) PORT MAP ( xin => yBottom_uid48_fpSinPiTest_b, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg(DELAY,926) ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a(DELAY,833)@1 ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a : dspba_delay GENERIC MAP ( width => 80, depth => 1 ) PORT MAP ( xin => y_uid39_fpSinPiTest_b, xout => ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q, clk => clk, aclr => areset ); --reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1(REG,364)@2 reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q; END IF; END PROCESS; --cmpYToOneMinusY_uid46_fpSinPiTest(COMPARE,45)@3 cmpYToOneMinusY_uid46_fpSinPiTest_cin <= GND_q; cmpYToOneMinusY_uid46_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & oneMinusY_uid45_fpSinPiTest_q) & '0'; cmpYToOneMinusY_uid46_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q) & cmpYToOneMinusY_uid46_fpSinPiTest_cin(0); cmpYToOneMinusY_uid46_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_b)); END IF; END PROCESS; cmpYToOneMinusY_uid46_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid46_fpSinPiTest_o(84); --z_uid49_fpSinPiTest(MUX,48)@4 z_uid49_fpSinPiTest_s <= cmpYToOneMinusY_uid46_fpSinPiTest_c; z_uid49_fpSinPiTest: PROCESS (z_uid49_fpSinPiTest_s, ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q) BEGIN CASE z_uid49_fpSinPiTest_s IS WHEN "0" => z_uid49_fpSinPiTest_q <= ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q; WHEN "1" => z_uid49_fpSinPiTest_q <= ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q; WHEN OTHERS => z_uid49_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --zAddr_uid63_fpSinPiTest(BITSELECT,62)@4 zAddr_uid63_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; zAddr_uid63_fpSinPiTest_b <= zAddr_uid63_fpSinPiTest_in(78 downto 72); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0(REG,382)@4 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= zAddr_uid63_fpSinPiTest_b; END IF; END PROCESS; --memoryC5_uid231_sinPiZTableGenerator(LOOKUP,230)@5 memoryC5_uid231_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; WHEN "0000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111110101101000"; WHEN "0000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111101101011101"; WHEN "0000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100110001110"; WHEN "0000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100000000010"; WHEN "0000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111011000000000"; WHEN "0000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111010001101101"; WHEN "0000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111001010010111"; WHEN "0001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111000010110010"; WHEN "0001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110111100010100"; WHEN "0001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110110100011111"; WHEN "0001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110101100101101"; WHEN "0001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110100101101011"; WHEN "0001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110011111011101"; WHEN "0001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010111001010"; WHEN "0001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010001011011"; WHEN "0010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110001010101011"; WHEN "0010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110000011011001"; WHEN "0010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101111011000001"; WHEN "0010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101110101001010"; WHEN "0010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101101110100110"; WHEN "0010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101100111100011"; WHEN "0010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011111111111"; WHEN "0010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011001001010"; WHEN "0011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101010010100110"; WHEN "0011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101001010011011"; WHEN "0011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101000100011100"; WHEN "0011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100111101010110"; WHEN "0011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100110110111000"; WHEN "0011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100101111110010"; WHEN "0011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100111110010"; WHEN "0011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100001010101"; WHEN "0100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100011011011111"; WHEN "0100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100010011110111"; WHEN "0100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100001110001010"; WHEN "0100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100000111000100"; WHEN "0100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111111110101"; WHEN "0100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111001010110"; WHEN "0100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011110011000111"; WHEN "0100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011101101000000"; WHEN "0101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011100110000011"; WHEN "0101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011111111001"; WHEN "0101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011000100110"; WHEN "0101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011010010101100"; WHEN "0101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011001100010010"; WHEN "0101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011000101010111"; WHEN "0101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111111101010"; WHEN "0101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111001010000"; WHEN "0110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010110011010011"; WHEN "0110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010101100101011"; WHEN "0110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010100110111110"; WHEN "0110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011111111000"; WHEN "0110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011010110010"; WHEN "0110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010010101001110"; WHEN "0110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001110010011"; WHEN "0110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001000111011"; WHEN "0111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010000001111011"; WHEN "0111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001111011111110"; WHEN "0111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110111001010"; WHEN "0111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110001110111"; WHEN "0111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001101011000100"; WHEN "0111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100101010010"; WHEN "0111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100000011111"; WHEN "0111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001011010001010"; WHEN "1000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001010100111110"; WHEN "1000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001110110010"; WHEN "1000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001010111000"; WHEN "1000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001000100111111"; WHEN "1000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111111001100"; WHEN "1000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111010001001"; WHEN "1000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110101010110"; WHEN "1000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110000011101"; WHEN "1001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000101001110100"; WHEN "1001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000100101111001"; WHEN "1001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011111111010"; WHEN "1001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011011110110"; WHEN "1001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010110001100"; WHEN "1001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010001001000"; WHEN "1001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001101111001"; WHEN "1001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001000000111"; WHEN "1010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000000010111001"; WHEN "1010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111110110110"; WHEN "1010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111001111111"; WHEN "1010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110110010100"; WHEN "1010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110001011000"; WHEN "1010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101100010111"; WHEN "1010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101000010010"; WHEN "1010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100100010000"; WHEN "1011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100000111100"; WHEN "1011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111011011111111"; WHEN "1011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010111100000"; WHEN "1011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010011110100"; WHEN "1011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010000011100"; WHEN "1011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111001011011110"; WHEN "1011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000111111101"; WHEN "1011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000100101011"; WHEN "1100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000001100100"; WHEN "1100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111101101110"; WHEN "1100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111010011000"; WHEN "1100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110110110000"; WHEN "1100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110010011010"; WHEN "1100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110000011110"; WHEN "1100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101100101100"; WHEN "1100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101000101110"; WHEN "1101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100110100000"; WHEN "1101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100100010001"; WHEN "1101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100001000000"; WHEN "1101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011101101110"; WHEN "1101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011011011111"; WHEN "1101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010111000100"; WHEN "1101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010101110011"; WHEN "1101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010001111100"; WHEN "1110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010000001111"; WHEN "1110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001110011001"; WHEN "1110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001010100010"; WHEN "1110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000111111000"; WHEN "1110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101110110"; WHEN "1110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101000100"; WHEN "1110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000010100010"; WHEN "1110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111111110011"; WHEN "1111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111110010000"; WHEN "1111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111100110111"; WHEN "1111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111010111000"; WHEN "1111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111000101000"; WHEN "1111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110110110100"; WHEN "1111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110101011010"; WHEN "1111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110100000011"; WHEN "1111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110010001011"; WHEN OTHERS => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; END CASE; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a(DELAY,485)@4 ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => z_uid49_fpSinPiTest_q, xout => ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q, clk => clk, aclr => areset ); --zPPolyEval_uid64_fpSinPiTest(BITSELECT,63)@5 zPPolyEval_uid64_fpSinPiTest_in <= ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q(71 downto 0); zPPolyEval_uid64_fpSinPiTest_b <= zPPolyEval_uid64_fpSinPiTest_in(71 downto 27); --yT1_uid232_sinPiZPolyEval(BITSELECT,231)@5 yT1_uid232_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT1_uid232_sinPiZPolyEval_b <= yT1_uid232_sinPiZPolyEval_in(44 downto 28); --reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0(REG,383)@5 reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= yT1_uid232_sinPiZPolyEval_b; END IF; END PROCESS; --prodXY_uid263_pT1_uid233_sinPiZPolyEval(MULT,262)@6 prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_a),18)) * SIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_b); prodXY_uid263_pT1_uid233_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= memoryC5_uid231_sinPiZTableGenerator_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr,34)); END IF; END PROCESS; prodXY_uid263_pT1_uid233_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval(BITSELECT,263)@9 prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_q; prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in(33 downto 16); --highBBits_uid235_sinPiZPolyEval(BITSELECT,234)@9 highBBits_uid235_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b; highBBits_uid235_sinPiZPolyEval_b <= highBBits_uid235_sinPiZPolyEval_in(17 downto 1); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a(DELAY,853)@4 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a : dspba_delay GENERIC MAP ( width => 7, depth => 3 ) PORT MAP ( xin => zAddr_uid63_fpSinPiTest_b, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0(REG,384)@7 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q; END IF; END PROCESS; --memoryC4_uid230_sinPiZTableGenerator(LOOKUP,229)@8 memoryC4_uid230_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; WHEN "0000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110011111111100"; WHEN "0000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100101101100110011"; WHEN "0000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100100010011000101"; WHEN "0000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100010010010010110"; WHEN "0000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011111110011000100"; WHEN "0000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011100101011001100"; WHEN "0000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011001000001111000"; WHEN "0001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010100110101100100"; WHEN "0001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010000000010110001"; WHEN "0001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001001010101111100100"; WHEN "0001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001000100111000100010"; WHEN "0001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000111110011011110101"; WHEN "0001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000110111011001010101"; WHEN "0001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000101111111000110001"; WHEN "0001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000100111101101111110"; WHEN "0010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000011111000010010110"; WHEN "0010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000010101110100101111"; WHEN "0010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000001100000110110101"; WHEN "0010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000000001101111000000"; WHEN "0010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111110110110101110011"; WHEN "0010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111101011011010111001"; WHEN "0010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111011111011110000110"; WHEN "0010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111010010111100110100"; WHEN "0011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111000101110111111001"; WHEN "0011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110111000010100011101"; WHEN "0011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110101010001000110011"; WHEN "0011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110011011011101100111"; WHEN "0011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110001100001110001111"; WHEN "0011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101111100011110001010"; WHEN "0011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101101100001110100101"; WHEN "0011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101011011011000110110"; WHEN "0100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101001001111111101110"; WHEN "0100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100111000001001001111"; WHEN "0100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100100101101100011001"; WHEN "0100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100010010110001110000"; WHEN "0100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011111111010101110110"; WHEN "0100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011101011010111000111"; WHEN "0100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011010110110110011110"; WHEN "0100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011000001110100011110"; WHEN "0101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010101100010100010011"; WHEN "0101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010010110010001000111"; WHEN "0101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001111111110001000100"; WHEN "0101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001101000101100110110"; WHEN "0101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001010001001001111011"; WHEN "0101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000111001001000001110"; WHEN "0101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000100000100011110110"; WHEN "0101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000000111100001111001"; WHEN "0110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111101101111111011111"; WHEN "0110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111010011111111100110"; WHEN "0110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110111001011110100100"; WHEN "0110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110011110100010000111"; WHEN "0110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110000011000010001001"; WHEN "0110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101100111000101000011"; WHEN "0110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101001010101101011111"; WHEN "0110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100101101110011101110"; WHEN "0111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100010000100000111110"; WHEN "0111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011110010101101110100"; WHEN "0111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011010100011010011110"; WHEN "0111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010110101101011010111"; WHEN "0111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010010110100011011101"; WHEN "0111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001110110111100001001"; WHEN "0111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001010110110110010000"; WHEN "0111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000110110011000001101"; WHEN "1000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000010101011011011001"; WHEN "1000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111110100000101110010"; WHEN "1000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111010010001110101001"; WHEN "1000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110110000000001101011"; WHEN "1000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110001101011001110011"; WHEN "1000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101101010010101011101"; WHEN "1000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101000110110101111111"; WHEN "1000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111100100010111100111100"; WHEN "1001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011111110101110100100"; WHEN "1001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011011001111111110100"; WHEN "1001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010110100111101000111"; WHEN "1001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010001111011100101001"; WHEN "1001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001101001100111100001"; WHEN "1001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001000011011000101011"; WHEN "1001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111000011100101100110010"; WHEN "1001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111110101110000000011"; WHEN "1010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111001110011001111101"; WHEN "1010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110110100110101001110001"; WHEN "1010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101111110100101001011"; WHEN "1010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101010110000110010110"; WHEN "1010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100101101010100111010"; WHEN "1010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100000100001101101101"; WHEN "1010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110011011010101110011000"; WHEN "1010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010110000111001010011"; WHEN "1011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010000110101101010010"; WHEN "1011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110001011100010001000010"; WHEN "1011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000110001011111001110"; WHEN "1011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000000110010110110100"; WHEN "1011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101111011010111010001000"; WHEN "1011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110101111001110001011"; WHEN "1011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110000011001011001100"; WHEN "1011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101101010110110100111111"; WHEN "1100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101100101010001011011001"; WHEN "1100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011111101010010000000"; WHEN "1100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011010000000101001000"; WHEN "1100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101010100010100111110111"; WHEN "1100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001110100111011010110"; WHEN "1100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001000110110111101100"; WHEN "1100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101000011000101000001000"; WHEN "1100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100111101010001001010101"; WHEN "1101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110111011010110000011"; WHEN "1101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110001100010011011010"; WHEN "1101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100101011101000100011001"; WHEN "1101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100100101101100110100111"; WHEN "1101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011111101110111111010"; WHEN "1101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011001110000000101100"; WHEN "1101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100010011101110011110101"; WHEN "1101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100001101101100000010000"; WHEN "1110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000111100111010001011"; WHEN "1110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000001100000111111010"; WHEN "1110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011111011011001110101000"; WHEN "1110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011110101010000110010111"; WHEN "1110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101111000110001000001"; WHEN "1110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101000111001101001001"; WHEN "1110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011100010101100011001010"; WHEN "1110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011011100011101111010110"; WHEN "1111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011010110001101110011110"; WHEN "1111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001111111100011010111"; WHEN "1111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001001101010000100101"; WHEN "1111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011000011010110101101110"; WHEN "1111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010111101000010001000000"; WHEN "1111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110110101100011000101"; WHEN "1111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110000010101101010111"; WHEN "1111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010101001111110001011010"; WHEN OTHERS => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; END CASE; END IF; END PROCESS; --sumAHighB_uid236_sinPiZPolyEval(ADD,235)@9 sumAHighB_uid236_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((26 downto 26 => memoryC4_uid230_sinPiZTableGenerator_q(25)) & memoryC4_uid230_sinPiZTableGenerator_q); sumAHighB_uid236_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((26 downto 17 => highBBits_uid235_sinPiZPolyEval_b(16)) & highBBits_uid235_sinPiZPolyEval_b); sumAHighB_uid236_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid236_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid236_sinPiZPolyEval_b)); sumAHighB_uid236_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_o(26 downto 0); --lowRangeB_uid234_sinPiZPolyEval(BITSELECT,233)@9 lowRangeB_uid234_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid234_sinPiZPolyEval_b <= lowRangeB_uid234_sinPiZPolyEval_in(0 downto 0); --s1_uid234_uid237_sinPiZPolyEval(BITJOIN,236)@9 s1_uid234_uid237_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_q & lowRangeB_uid234_sinPiZPolyEval_b; --reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1(REG,385)@9 reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= s1_uid234_uid237_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor(LOGICAL,1179) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q <= not (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a or ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg(REG,1177) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= VCC_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena(REG,1180) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q = "1") THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd(LOGICAL,1181) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a and ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b; --yT2_uid238_sinPiZPolyEval(BITSELECT,237)@5 yT2_uid238_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT2_uid238_sinPiZPolyEval_b <= yT2_uid238_sinPiZPolyEval_in(44 downto 19); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt(COUNTER,1173) -- every=1, low=0, high=1, step=1, init=1 ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i + 1; END IF; END PROCESS; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i,1)); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg(REG,1174) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux(MUX,1175) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q) BEGIN CASE ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s IS WHEN "0" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; WHEN "1" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem(DUALMEM,1172) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia <= yT2_uid238_sinPiZPolyEval_b; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 26, widthad_a => 1, numwords_a => 2, width_b => 26, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq, address_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa, data_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia ); ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq(25 downto 0); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg(DELAY,1171) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q, xout => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0(REG,386)@9 reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q; END IF; END PROCESS; --prodXY_uid266_pT2_uid239_sinPiZPolyEval(MULT,265)@10 prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_a),27)) * SIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_b); prodXY_uid266_pT2_uid239_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr,54)); END IF; END PROCESS; prodXY_uid266_pT2_uid239_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval(BITSELECT,266)@13 prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_q; prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in(53 downto 25); --highBBits_uid241_sinPiZPolyEval(BITSELECT,240)@13 highBBits_uid241_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b; highBBits_uid241_sinPiZPolyEval_b <= highBBits_uid241_sinPiZPolyEval_in(28 downto 1); --reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1(REG,388)@13 reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= highBBits_uid241_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor(LOGICAL,1192) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1188) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q <= "0101"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp(LOGICAL,1189) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg(REG,1190) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena(REG,1193) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1194) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1184) -- every=1, low=0, high=5, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i = 4 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i - 5; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i,3)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg(REG,1185) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1186) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1183) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 3, numwords_a => 6, width_b => 7, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg(DELAY,1182) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0(REG,387)@12 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC3_uid229_sinPiZTableGenerator(LOOKUP,228)@13 memoryC3_uid229_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; WHEN "0000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000001010001100110101000111010101"; WHEN "0000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000010100011001100101101010110011"; WHEN "0000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000011110100110001101010100011011"; WHEN "0000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000101000110010100111100101110011"; WHEN "0000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000110010111110101111101101101000"; WHEN "0000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000111101001010100001100001001101"; WHEN "0000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001000111010101111000010100001000"; WHEN "0001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001010001100000101111101001011010"; WHEN "0001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001011011101011000011001000111110"; WHEN "0001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001100101110100101110001001110101"; WHEN "0001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001101111111101101100010100000001"; WHEN "0001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001111010000101111001001101010110"; WHEN "0001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010000100001101010000011000110101"; WHEN "0001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010001110010011101101001010101000"; WHEN "0001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010011000011001001011011101011111"; WHEN "0010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010100010011101100110100011101011"; WHEN "0010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010101100100000111010000011110001"; WHEN "0010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010110110100011000001011111010110"; WHEN "0010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011000000100011111000101110110101"; WHEN "0010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011001010100011011011001000001011"; WHEN "0010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011010100100001100100010010100101"; WHEN "0010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011011110011110001111110110101010"; WHEN "0010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011101000011001011001100000011011"; WHEN "0011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011110010010010111100111000010100"; WHEN "0011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011111100001010110101011110000110"; WHEN "0011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100000110000000111111001110100010"; WHEN "0011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100001111110101010101100100101101"; WHEN "0011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100011001100111110100010110001111"; WHEN "0011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100100011011000010111001001011111"; WHEN "0011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100101101000110111001101001101001"; WHEN "0011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100110110110011010111110011001100"; WHEN "0100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101000000011101101101010000100110"; WHEN "0100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101001010000101110101101000010110"; WHEN "0100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101010011101011101100111100100100"; WHEN "0100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101011101001111001110110000110010"; WHEN "0100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101100110110000010111000000110011"; WHEN "0100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101110000001111000001100011110100"; WHEN "0100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101111001101011001010010000000001"; WHEN "0100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110000011000100101100111100001110"; WHEN "0101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110001100011011100101011010100101"; WHEN "0101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110010101101111101111110000010101"; WHEN "0101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110011111000001000111101011101100"; WHEN "0101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110101000001111101001011001100010"; WHEN "0101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110110001011011010000101101010010"; WHEN "0101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110111010100011111001100111101100"; WHEN "0101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111000011101001100000010000100010"; WHEN "0101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111001100101100000000100001010000"; WHEN "0110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111010101101011010110100011101100"; WHEN "0110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111011110100111011110011000011110"; WHEN "0110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111100111100000010100001101010000"; WHEN "0110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111110000010101110100000001010000"; WHEN "0110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111111001000111111010001101010001"; WHEN "0110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000000001110110100010110001111010"; WHEN "0110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000001010100001101001110111110101"; WHEN "0110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000010011001001001011111110000001"; WHEN "0111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000011011101101000101000010101111"; WHEN "0111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000100100001101010001101000100100"; WHEN "0111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000101100101001101110000011010101"; WHEN "0111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000110101000010010110100001011010"; WHEN "0111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000111101010111000111010101011110"; WHEN "0111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001000101100111111101000110111000"; WHEN "0111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001001101110100110100001111001100"; WHEN "0111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001010101111101101001000001001010"; WHEN "1000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001011110000010011000001001000011"; WHEN "1000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001100110000010111101111101010011"; WHEN "1000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001101101111111010111010011001111"; WHEN "1000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001110101110111100000011010000110"; WHEN "1000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001111101101011010110000011010010"; WHEN "1000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010000101011010110100111100000101"; WHEN "1000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010001101000101111001101110100011"; WHEN "1000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010010100101100100001000101010010"; WHEN "1001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010011100001110100111101001010100"; WHEN "1001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010100011101100001010100001011100"; WHEN "1001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010101011000101000110001011100100"; WHEN "1001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010110010011001010111110000100100"; WHEN "1001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010111001101000111011111001000111"; WHEN "1001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000000110011101111101001011111"; WHEN "1001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000111111001110000000110011110"; WHEN "1001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011001110111010111001110111111110"; WHEN "1010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011010101110111001010010001110110"; WHEN "1010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011011100101110011110011000111101"; WHEN "1010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011100011100000110011001001001001"; WHEN "1010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011101010001110000101111000101100"; WHEN "1010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110000110110010011100011000111"; WHEN "1010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110111011001011001011101010011"; WHEN "1010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011111101110111010100111100011100"; WHEN "1010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100000100010000000011001111101101"; WHEN "1011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100001010100011100001101110011100"; WHEN "1011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010000110001101101100011100011"; WHEN "1011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010110111010100100010100000100"; WHEN "1011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100011100111110000011100000001010"; WHEN "1011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100100010111100001000100001101001"; WHEN "1011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101000110100110000110001111011"; WHEN "1011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101110100111111010000100111001"; WHEN "1011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100110100010101100001111010001101"; WHEN "1100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111001111101100101111101110000"; WHEN "1100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111111100000000011110011100101"; WHEN "1100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101000100111100111001010011110100"; WHEN "1100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001010010100000100001001001101"; WHEN "1100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001111100101100010000111001000"; WHEN "1100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101010100110001010001010100001101"; WHEN "1100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011001110111001111010101110101"; WHEN "1100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011110110111011010001101111010"; WHEN "1101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101100011110001110000000111001111"; WHEN "1101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101000100110001110111010010001"; WHEN "1101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101101010100110100100110101101"; WHEN "1101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110001111101011111011001010101"; WHEN "1101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110110100000001101100000100000"; WHEN "1101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111010111100111100111010111000"; WHEN "1101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111111010011101100010000110110"; WHEN "1101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000011100100011001011010100000"; WHEN "1110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000111101111000011000011110011"; WHEN "1110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001011110011100111011010000000"; WHEN "1110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001111110010000100101111100001"; WHEN "1110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010011101010011001110010000111"; WHEN "1110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010111011100100100111111111001"; WHEN "1110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011011001000100101000000101011"; WHEN "1110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011110101110011000001011101010"; WHEN "1110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100010001101111101010010100010"; WHEN "1111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100101100111010011001000110011"; WHEN "1111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101000111010011000011010000011"; WHEN "1111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101100000111001011110100010010"; WHEN "1111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101111001101101100001110011100"; WHEN "1111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110010001101111000100101110110"; WHEN "1111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110101000111101111110101001010"; WHEN "1111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110111111011010000111000110000"; WHEN "1111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110111010101000011010110000100000"; WHEN OTHERS => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; END CASE; END IF; END PROCESS; --sumAHighB_uid242_sinPiZPolyEval(ADD,241)@14 sumAHighB_uid242_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid229_sinPiZTableGenerator_q(34)) & memoryC3_uid229_sinPiZTableGenerator_q); sumAHighB_uid242_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((35 downto 28 => reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q(27)) & reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q); sumAHighB_uid242_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid242_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid242_sinPiZPolyEval_b)); sumAHighB_uid242_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_o(35 downto 0); --lowRangeB_uid240_sinPiZPolyEval(BITSELECT,239)@13 lowRangeB_uid240_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid240_sinPiZPolyEval_b <= lowRangeB_uid240_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a(DELAY,686)@13 ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid240_sinPiZPolyEval_b, xout => ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --s2_uid240_uid243_sinPiZPolyEval(BITJOIN,242)@14 s2_uid240_uid243_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_q & ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q; --yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval(BITSELECT,274)@14 yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in(36 downto 19); --reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9(REG,389)@14 reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor(LOGICAL,950) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top(CONSTANT,946) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q <= "0110"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp(LOGICAL,947) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b else "0"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg(REG,948) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena(REG,951) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q = "1") THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd(LOGICAL,952) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt(COUNTER,942) -- every=1, low=0, high=6, step=1, init=1 ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i = 5 THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i - 6; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i,3)); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg(REG,943) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux(MUX,944) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q) BEGIN CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s IS WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem(DUALMEM,1069) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 3, numwords_a => 7, width_b => 45, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg(DELAY,1068) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT3_uid244_sinPiZPolyEval(BITSELECT,243)@14 yT3_uid244_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q; yT3_uid244_sinPiZPolyEval_b <= yT3_uid244_sinPiZPolyEval_in(44 downto 10); --xBottomBits_uid274_pT3_uid245_sinPiZPolyEval(BITSELECT,273)@14 xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b(7 downto 0); xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in(7 downto 0); --pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval(BITJOIN,276)@14 pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7(REG,391)@14 reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid273_pT3_uid245_sinPiZPolyEval(BITSELECT,272)@14 yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q(9 downto 0); yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b <= yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in(9 downto 0); --spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval(BITJOIN,275)@14 spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q <= GND_q & yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b; --pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval(BITJOIN,277)@14 pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q <= spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6(REG,390)@14 reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval(BITSELECT,271)@14 xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in(34 downto 17); --reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4(REG,392)@14 reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma(CHAINMULTADD,345)@15 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1),38); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0); END IF; END PROCESS; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0),37)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval(BITSELECT,279)@18 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in(36 downto 7); --highBBits_uid282_pT3_uid245_sinPiZPolyEval(BITSELECT,281)@18 highBBits_uid282_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b; highBBits_uid282_pT3_uid245_sinPiZPolyEval_b <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_in(29 downto 1); --reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1(REG,395)@18 reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval(BITSELECT,269)@14 yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in(36 downto 10); --reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1(REG,393)@14 reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval(BITSELECT,268)@14 xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in(34 downto 8); --reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0(REG,394)@14 reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid271_pT3_uid245_sinPiZPolyEval(MULT,270)@15 topProd_uid271_pT3_uid245_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_b); topProd_uid271_pT3_uid245_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid271_pT3_uid245_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid271_pT3_uid245_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0(REG,396)@18 reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid283_pT3_uid245_sinPiZPolyEval(ADD,282)@19 sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q(53)) & reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b)); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid281_pT3_uid245_sinPiZPolyEval(BITSELECT,280)@18 lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b <= lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a(DELAY,724)@18 ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b, xout => ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid281_uid284_pT3_uid245_sinPiZPolyEval(BITJOIN,283)@19 add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q & ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q; --R_uid285_pT3_uid245_sinPiZPolyEval(BITSELECT,284)@19 R_uid285_pT3_uid245_sinPiZPolyEval_in <= add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q(54 downto 0); R_uid285_pT3_uid245_sinPiZPolyEval_b <= R_uid285_pT3_uid245_sinPiZPolyEval_in(54 downto 18); --reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1(REG,397)@19 reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= R_uid285_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor(LOGICAL,1168) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1164) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q <= "01011"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp(LOGICAL,1165) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg(REG,1166) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena(REG,1169) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1170) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1160) -- every=1, low=0, high=11, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i = 10 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i - 11; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i,4)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg(REG,1161) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1162) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1159) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 4, numwords_a => 12, width_b => 7, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg(DELAY,1158) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0(REG,381)@18 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC2_uid228_sinPiZTableGenerator(LOOKUP,227)@19 memoryC2_uid228_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; WHEN "0000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010010000000010011011110101101000"; WHEN "0000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010100110111111010000111001000101"; WHEN "0000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101011001101001111001000101101101011"; WHEN "0000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101100000010110001110010011100100110"; WHEN "0000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101101000111100110110110100100001100"; WHEN "0000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101110011011101101110110101011000001"; WHEN "0000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101111111111000110001101110000001000"; WHEN "0001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110001110001101111010000000001001001"; WHEN "0001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110011110011101000001010111100010011"; WHEN "0001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110110000100110000000101010101010010"; WHEN "0001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111000100101000101111111001111001110"; WHEN "0001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111011010100101000110010000000110000"; WHEN "0001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111110010011010111010000010100101101"; WHEN "0001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000001100001010000000110001101010110"; WHEN "0001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000100111110010001111000111001110001"; WHEN "0010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001000101010011011000111000110111111"; WHEN "0010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001100100101101010001000110100001110"; WHEN "0010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010000101111111101001111011000110110"; WHEN "0010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010101001001010010100101011111010000"; WHEN "0010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011001110001101000001111010001111100"; WHEN "0010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011110101000111100001010010001101000"; WHEN "0010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111100011101111001100001101011001010011"; WHEN "0010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101001000100010110001000111111011001"; WHEN "0011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101110101000010111100110110111011101"; WHEN "0011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111110100011011001110001010010101001001"; WHEN "0011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111111010011100110111010000000101010000"; WHEN "0011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000000101101010000001110011011110111"; WHEN "0011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000111001100010110010101001001001010"; WHEN "0011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000001101111010000110101101100011101100"; WHEN "0011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000010100110110011110011010100101011100"; WHEN "0011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000011100000001011010011000101010010101"; WHEN "0100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000100011011010110111011101111001100010"; WHEN "0100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000101011000010110010011010000011100100"; WHEN "0100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000110010111001000111110110011110000010"; WHEN "0100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000111010111101110100010110010000011111"; WHEN "0100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001000011010000110100010110001010111111"; WHEN "0100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001001011110010000100001100101110011011"; WHEN "0100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001010100100001100000001010001100011000"; WHEN "0100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001011101011111000100011000101001100001"; WHEN "0101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001100110101010101100111100000000011011"; WHEN "0101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001110000000100010101110001111101110010"; WHEN "0101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001111001101011111010110010001100011010"; WHEN "0101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010000011100001010111101110001010011110"; WHEN "0101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010001101100100101000010001011000100111"; WHEN "0101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010010111110101101000000001010011000010"; WHEN "0101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010100010010100010010011101010101101010"; WHEN "0101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010101101000000100010111111000010000011"; WHEN "0110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010110111111010010100111001111011100110"; WHEN "0110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011000011000001100011011011101110111001"; WHEN "0110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011001110010110001001101100001111110101"; WHEN "0110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011011001111000000010101101100000111100"; WHEN "0110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011100101100111001001011011101110011000"; WHEN "0110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011110001100011011000101101011001110101"; WHEN "0110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011111101101100101011010011010110110001"; WHEN "0110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100001010000010111011111000101001101100"; WHEN "0111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100010110100110000101000010110110110100"; WHEN "0111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100100011010110000001010001110101000110"; WHEN "0111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100110000010010101010111111111100101100"; WHEN "0111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100111101011011111100100010000110111111"; WHEN "0111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101001010110001110000000111101111100101"; WHEN "0111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101011000010011111111111010110011011100"; WHEN "0111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101100110000010100101111111111011010100"; WHEN "0111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101110011111101011100010110011100010110"; WHEN "1000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110000010000100011100111000010100111110"; WHEN "1000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110010000010111100001011010011001010101"; WHEN "1000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110011110110110100011101100001011001000"; WHEN "1000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110101101100001011101011000001011011001"; WHEN "1000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110111100011000001000000011101110001111"; WHEN "1000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111001011011010011101001111000101110001"; WHEN "1000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111011010101000010110010101100101000110"; WHEN "1000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111101010000001101100101101100010111111"; WHEN "1001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111111001100110011001101000011100111011"; WHEN "1001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000001001010110010110010010110100011100"; WHEN "1001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000011001010001011011110100100000011000"; WHEN "1001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000101001010111100011010000011111011101"; WHEN "1001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000111001101000100101100101001010011111"; WHEN "1001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001001010000100011011101100001100000010"; WHEN "1001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001011010101010111110011010101000110000"; WHEN "1001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001101011011100000110100001001001100100"; WHEN "1010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001111100010111101100101011101111001100"; WHEN "1010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010001101011101101001100010000010111010"; WHEN "1010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010011110101101110101100111011000000101"; WHEN "1010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010110000001000001001011010101000000100"; WHEN "1010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011000001101100011101010110100010000110"; WHEN "1010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011010011011010101001110001100010110011"; WHEN "1010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011100101010010100110111101111101101001"; WHEN "1010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011110111010100001101001010000001101110"; WHEN "1011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100001001011111010100011111111010110111"; WHEN "1011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100011011110011110101000101111001011001"; WHEN "1011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100101110010001100110111110001101101110"; WHEN "1011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101000000111000100010000111010010100101"; WHEN "1011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101010011101000011110011011110001111001"; WHEN "1011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101100110100001010011110010100110010101"; WHEN "1011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101111001100010111001111110111010001011"; WHEN "1011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110001100101101001000110000010101000001"; WHEN "1100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110011111111111110111110010111000010010"; WHEN "1100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110110011011010111110101111001000100111"; WHEN "1100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111000110111110010101001010001010011010"; WHEN "1100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111011010101001110010100101101110010111"; WHEN "1100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111101110011101001110100000001111101010"; WHEN "1100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000000010011000100000010100110110100000"; WHEN "1100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000010110011011011111011011100110110011"; WHEN "1100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000101010100110000011001001011000000001"; WHEN "1101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000111110111000000010101111111100010101"; WHEN "1101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001010011010001010101011110001011010100"; WHEN "1101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001100111110001110010100000000000010111"; WHEN "1101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001111100011001010000111110011101110000"; WHEN "1101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010010001000111100111111111110011011101"; WHEN "1101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010100101111100101110100111100110010101"; WHEN "1101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010111010111000011011110110101001010101"; WHEN "1101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011001111111010100110101011010011011011"; WHEN "1110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011100101000011000110000001010000000100"; WHEN "1110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011111010010001110000110001110011111011"; WHEN "1110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100001111100110011101110011111001111111"; WHEN "1110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100100101000001000011111100000011011011"; WHEN "1110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100111010100001011001111100100100101001"; WHEN "1110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101010000000111010110100101100100010111"; WHEN "1110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101100101110010110000100101000101101101"; WHEN "1110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101111011100011011110100111000011010111"; WHEN "1111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110010001011001010111010101011001010001"; WHEN "1111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110100111010100010001011000001010110100"; WHEN "1111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110111101010100000011010101100101100011"; WHEN "1111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111010011011000100011110010000011111011"; WHEN "1111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111101001100001101001010000010010001011"; WHEN "1111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111111111101111001010010001010101000011"; WHEN "1111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000010110000000111101010100101101001001"; WHEN "1111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000101100010110111000111000011010110101"; WHEN OTHERS => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid246_sinPiZPolyEval(CONSTANT,245) rndBit_uid246_sinPiZPolyEval_q <= "01"; --cIncludingRoundingBit_uid247_sinPiZPolyEval(BITJOIN,246)@19 cIncludingRoundingBit_uid247_sinPiZPolyEval_q <= memoryC2_uid228_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0(REG,398)@19 reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid247_sinPiZPolyEval_q; END IF; END PROCESS; --ts3_uid248_sinPiZPolyEval(ADD,247)@20 ts3_uid248_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q); ts3_uid248_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q(36)) & reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q); ts3_uid248_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid248_sinPiZPolyEval_a) + SIGNED(ts3_uid248_sinPiZPolyEval_b)); ts3_uid248_sinPiZPolyEval_q <= ts3_uid248_sinPiZPolyEval_o(45 downto 0); --s3_uid249_sinPiZPolyEval(BITSELECT,248)@20 s3_uid249_sinPiZPolyEval_in <= ts3_uid248_sinPiZPolyEval_q; s3_uid249_sinPiZPolyEval_b <= s3_uid249_sinPiZPolyEval_in(45 downto 1); --yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval(BITSELECT,286)@20 yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b; yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in(44 downto 18); --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9(REG,399)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor(LOGICAL,1091) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top(CONSTANT,1087) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q <= "01100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp(LOGICAL,1088) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg(REG,1089) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena(REG,1092) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd(LOGICAL,1093) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1083) -- every=1, low=0, high=12, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i = 11 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i - 12; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i,4)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg(REG,1084) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux(MUX,1085) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem(DUALMEM,1082) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 13, width_b => 45, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg(DELAY,1081) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT4_uid250_sinPiZPolyEval(BITSELECT,249)@20 yT4_uid250_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q; yT4_uid250_sinPiZPolyEval_b <= yT4_uid250_sinPiZPolyEval_in(44 downto 2); --xBottomBits_uid290_pT4_uid251_sinPiZPolyEval(BITSELECT,289)@20 xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in <= yT4_uid250_sinPiZPolyEval_b(15 downto 0); xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in(15 downto 0); --pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval(BITJOIN,291)@20 pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7(REG,401)@20 reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid289_pT4_uid251_sinPiZPolyEval(BITSELECT,288)@20 yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b(17 downto 0); yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b <= yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a(DELAY,733)@20 ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b, xout => ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval(BITJOIN,290)@21 spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q; --pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval(BITJOIN,292)@21 pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q <= spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6(REG,400)@21 reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a(DELAY,727)@20 ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 43, depth => 1 ) PORT MAP ( xin => yT4_uid250_sinPiZPolyEval_b, xout => ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval(BITSELECT,285)@21 xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in <= ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q; xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in(42 downto 16); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4(REG,402)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma(CHAINMULTADD,346)@22 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval(BITSELECT,294)@25 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in(54 downto 8); --highBBits_uid297_pT4_uid251_sinPiZPolyEval(BITSELECT,296)@25 highBBits_uid297_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b; highBBits_uid297_pT4_uid251_sinPiZPolyEval_b <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_in(46 downto 18); --reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1(REG,405)@25 reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1(REG,403)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b(DELAY,730)@21 ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0(REG,404)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid288_pT4_uid251_sinPiZPolyEval(MULT,287)@22 topProd_uid288_pT4_uid251_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_b); topProd_uid288_pT4_uid251_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid288_pT4_uid251_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid288_pT4_uid251_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0(REG,406)@25 reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid298_pT4_uid251_sinPiZPolyEval(ADD,297)@26 sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q(53)) & reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b)); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid296_pT4_uid251_sinPiZPolyEval(BITSELECT,295)@25 lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b(17 downto 0); lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b <= lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a(DELAY,741)@25 ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b, xout => ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid296_uid299_pT4_uid251_sinPiZPolyEval(BITJOIN,298)@26 add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q & ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q; --R_uid300_pT4_uid251_sinPiZPolyEval(BITSELECT,299)@26 R_uid300_pT4_uid251_sinPiZPolyEval_in <= add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q(71 downto 0); R_uid300_pT4_uid251_sinPiZPolyEval_b <= R_uid300_pT4_uid251_sinPiZPolyEval_in(71 downto 26); --reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1(REG,407)@26 reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= R_uid300_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor(LOGICAL,1155) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1151) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q <= "010010"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp(LOGICAL,1152) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg(REG,1153) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena(REG,1156) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1157) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1147) -- every=1, low=0, high=18, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i = 17 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i - 18; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg(REG,1148) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1149) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1146) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 19, width_b => 7, widthad_b => 5, numwords_b => 19, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg(DELAY,1145) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0(REG,380)@25 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC1_uid227_sinPiZTableGenerator(LOOKUP,226)@26 memoryC1_uid227_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; WHEN "0000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111110101101010100010101111000000010001111100011"; WHEN "0000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111101011010101001001010010110100010110001011110"; WHEN "0000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111100000111111110111100000001110010011010000110"; WHEN "0000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111010110101010110001001011111100110111111100011"; WHEN "0000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111001100010101111010001010101001101111010110100"; WHEN "0000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111000010000001010110010000110111110101011111000"; WHEN "0000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110110111101101001001010011000001101011000111010"; WHEN "0001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110101101011001010111000101010111101010010100111"; WHEN "0001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110100011000110000011011011111110011010111001110"; WHEN "0001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110011000110011010010001010101101000110101101101"; WHEN "0001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110001110100001000111000101001011101110011011101"; WHEN "0001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110000100001111100101111110110001011110001011001"; WHEN "0001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101111001111110110010101010100011000010010100110"; WHEN "0001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101101111101110110000111011010000111100011100100"; WHEN "0001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101100101011111100100100011010101111000101000111"; WHEN "0010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101011011010001010001010100110101000010011111000"; WHEN "0010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101010001000011111011000001011000011010110000100"; WHEN "0010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101000110110111100101011010001111001100111110010"; WHEN "0010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100111100101100010100010000001100000101010111010"; WHEN "0010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100110010100010001011010011100011100110101011100"; WHEN "0010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100101000011001001110010100001010100000101101100"; WHEN "0010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100011110010001100001000001010100000110110000000"; WHEN "0010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100010100001011000111001001110000100110010111000"; WHEN "0011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100001010000110000100011011101011011110011010110"; WHEN "0011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100000000000010011100100100101001110110011000010"; WHEN "0011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011110110000000010011010001101000110110000011100"; WHEN "0011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011101011111111101100001110111011111101010000000"; WHEN "0011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011100010000000101011001000001011011100001111010"; WHEN "0011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011011000000011010011101000010010101100000110110"; WHEN "0011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011001110000111101001011001011110100111101110010"; WHEN "0011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011000100001101110000000101001100000101000010010"; WHEN "0100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010111010010101101011010100000110001110011110001"; WHEN "0100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010110000011111011110101110000100111100111110101"; WHEN "0100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010100110101011001101111010001011010010011110011"; WHEN "0100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010011100111000111100011110100101110100010111000"; WHEN "0100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010010011001000101110000000101001000110111000111"; WHEN "0100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010001001011010100110000100110000001000100101001"; WHEN "0100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001111111101110101000001110011010101110010001110"; WHEN "0100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001110110000100111000000000001011111111100011001"; WHEN "0101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001101100011101011000111011101000110011100100000"; WHEN "0101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001100010111000001110100001010110001110100101001"; WHEN "0101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001011001010101011100010000110111111111100011001"; WHEN "0101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001001111110101000101101000101110111110101110110"; WHEN "0101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001000110010111001110000110010111101100001101110"; WHEN "0101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000111100111011111001000110001000101111011110000"; WHEN "0101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000110011100011001010000011010001010111001000100"; WHEN "0101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000101010001101000100010111110111111001010110011"; WHEN "0110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000100000111001101011011100111000010100110100100"; WHEN "0110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000010111101001000010101010000010110010001100101"; WHEN "0110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000001110011011001101010101111010000110001110001"; WHEN "0110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000000101010000001110110101110010010100010001010"; WHEN "0110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111111100001000001010011101101111010001101110100"; WHEN "0110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111110011000011000011100000100011001001100111111"; WHEN "0110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111101010000000111101001111101101000001001100111"; WHEN "0110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111100001000001111010111011010111011101000011000"; WHEN "0111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111011000000101111111110010010111000110100000100"; WHEN "0111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111001111001101001111000010001001010010011000111"; WHEN "0111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111000110010111101011110110110010100111101001111"; WHEN "0111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110111101100101011001011010111101100111001001111"; WHEN "0111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110110100110110011010110111111001010011111110011"; WHEN "0111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110101100001010110011010101010111111100100001011"; WHEN "0111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110100011100010100101111001101101100100000011010"; WHEN "0111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110011010111101110101101001101110101101001000101"; WHEN "1000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110010010011100100101101000101111000100111000101"; WHEN "1000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110001001111110111000111000100000001110100110010"; WHEN "1000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110000001100100110010011001010000010000100100001"; WHEN "1000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101111001001110010101001001101000100001000011111"; WHEN "1000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101110000111011100100000110101100010100101111011"; WHEN "1000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101101000101100100010001011110111101101010011001"; WHEN "1000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101100000100001010010010010111110001001000100100"; WHEN "1000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101011000011001110111010100001001010011011010001"; WHEN "1001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101010000010110010100000101110111110101110111011"; WHEN "1001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101001000010110101011011100111100001010010001010"; WHEN "1001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101000000011011000000001100011011001101001101101"; WHEN "1001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100111000100011010101000101101011010001111110100"; WHEN "1001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100110000101111101100111000010010110110101001010"; WHEN "1001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100101001000000001010010010000111011001100101001"; WHEN "1001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100100001010100101111111111001100001111011011000"; WHEN "1001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100011001101101100000101001110001011001110111100"; WHEN "1010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100010010001010011110111010010010011111110100100"; WHEN "1010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100001010101011101101010111010101100101110000010"; WHEN "1010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100000011010001001110100101101010000111010011101"; WHEN "1010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011111011111011000101001000000111110001110111111"; WHEN "1010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011110100101001010011011111101101011111101000010"; WHEN "1010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011101101011011111100001011100000010100000001101"; WHEN "1010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011100110010011000001101000101010011000110001101"; WHEN "1010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011111001110100110010010011001111011110111011"; WHEN "1011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011000001110101100100010000000001110100011101"; WHEN "1011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011010001010011010110101110110000100101001100010"; WHEN "1011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011001010011100100111001101111111011000001100001"; WHEN "1011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011000011101010100000010011000001000101101011001"; WHEN "1011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010111100111101000100001111001001010100001001100"; WHEN "1011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010110110010100010101010001101001110110001111011"; WHEN "1011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101111110000010101100111110001101111011011100"; WHEN "1011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101001010001000111011100101100011001011100101"; WHEN "1100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010100010110110101100111001100000101011000010000"; WHEN "1100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010011100100001001000000101001111111111010110011"; WHEN "1100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010110010000011011000100110101011110110000011"; WHEN "1100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010000000100100111111011000101001000001000001"; WHEN "1100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010001001111101110000101000101010111011100100101"; WHEN "1100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010000011111011110111001100001010000110000001000"; WHEN "1100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111101111110111101100001111100001101100011111"; WHEN "1100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111000000111000101100100010000011111010101010"; WHEN "1101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001110010010100010001001011001010111110000100010"; WHEN "1101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001101100100110100010001100100011110001100110110"; WHEN "1101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100110111101111010011100000110010111101110011"; WHEN "1101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100001011010011011101011010000110101111000110"; WHEN "1101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001011011111100000111101001010011001011111101101"; WHEN "1101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010110100011000000000011001110101000000001010"; WHEN "1101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010001001111000110100011110100111011011010110"; WHEN "1101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001001100000000011100110011100111110000011010110"; WHEN "1110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000110110111000100011000111000000001100101100"; WHEN "1110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000001110010111110110111100101010001100011100"; WHEN "1110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000111100110100001101110001011101000100010101000"; WHEN "1110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110111111010110010100101111010011001100111001"; WHEN "1110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110011000110101110110010000101000111111101001"; WHEN "1110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101110011000000011110000110001011001010001101"; WHEN "1110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101001101110110010111010011111001000001110011"; WHEN "1110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100101001010111101100101011001011110111111001"; WHEN "1111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100000101100100101000101010110010110110110011"; WHEN "1111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011100010011101010101011110101111000111101111"; WHEN "1111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011000000000001111101000000010000000010001101"; WHEN "1111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000010011110010010101000110101101111100100010110"; WHEN "1111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001111101001111100010010010101110110011110010"; WHEN "1111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001011100111000110010010111110010100110111110"; WHEN "1111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000111101001110100001110010100000011000001001"; WHEN "1111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000011110010000111000111101011011000001000111"; WHEN OTHERS => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; END CASE; -- End reserved scope level END PROCESS; --cIncludingRoundingBit_uid253_sinPiZPolyEval(BITJOIN,252)@26 cIncludingRoundingBit_uid253_sinPiZPolyEval_q <= memoryC1_uid227_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0(REG,408)@26 reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid253_sinPiZPolyEval_q; END IF; END PROCESS; --ts4_uid254_sinPiZPolyEval(ADD,253)@27 ts4_uid254_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((52 downto 52 => reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q(51)) & reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q); ts4_uid254_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((52 downto 46 => reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q(45)) & reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q); ts4_uid254_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid254_sinPiZPolyEval_a) + SIGNED(ts4_uid254_sinPiZPolyEval_b)); ts4_uid254_sinPiZPolyEval_q <= ts4_uid254_sinPiZPolyEval_o(52 downto 0); --s4_uid255_sinPiZPolyEval(BITSELECT,254)@27 s4_uid255_sinPiZPolyEval_in <= ts4_uid254_sinPiZPolyEval_q; s4_uid255_sinPiZPolyEval_b <= s4_uid255_sinPiZPolyEval_in(52 downto 1); --yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval(BITSELECT,301)@27 yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b; yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in(51 downto 25); --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9(REG,409)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor(LOGICAL,1117) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q <= not (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a or ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top(CONSTANT,1113) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q <= "010011"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp(LOGICAL,1114) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a = ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b else "0"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg(REG,1115) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena(REG,1118) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q = "1") THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd(LOGICAL,1119) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a and ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b; --xBottomBits_uid305_pT5_uid257_sinPiZPolyEval(BITSELECT,304)@5 xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b(17 downto 0); xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt(COUNTER,1109) -- every=1, low=0, high=19, step=1, init=1 ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i = 18 THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '1'; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i - 19; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i,5)); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg(REG,1110) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux(MUX,1111) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q) BEGIN CASE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s IS WHEN "0" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; WHEN "1" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; WHEN OTHERS => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem(DUALMEM,1108) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 <= areset; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 5, numwords_a => 20, width_b => 18, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0, clock1 => clk, address_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq, address_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa, data_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia ); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg(DELAY,1107) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q, xout => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q, clk => clk, aclr => areset ); --pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval(BITJOIN,306)@27 pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7(REG,411)@27 reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid304_pT5_uid257_sinPiZPolyEval(BITSELECT,303)@27 yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b(24 downto 0); yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b <= yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a(DELAY,750)@27 ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b, xout => ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval(BITJOIN,305)@28 spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q; --pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval(BITJOIN,307)@28 pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q <= spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q & GND_q; --reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6(REG,410)@28 reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor(LOGICAL,1104) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top(CONSTANT,1100) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q <= "010100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp(LOGICAL,1101) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg(REG,1102) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena(REG,1105) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd(LOGICAL,1106) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1096) -- every=1, low=0, high=20, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i = 19 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i - 20; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i,5)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg(REG,1097) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux(MUX,1098) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem(DUALMEM,1095) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 5, numwords_a => 21, width_b => 45, widthad_b => 5, numwords_b => 21, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg(DELAY,1094) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval(BITSELECT,300)@28 xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q; xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in(44 downto 18); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4(REG,412)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma(CHAINMULTADD,347)@29 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval(BITSELECT,309)@32 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in(54 downto 1); --highBBits_uid312_pT5_uid257_sinPiZPolyEval(BITSELECT,311)@32 highBBits_uid312_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b; highBBits_uid312_pT5_uid257_sinPiZPolyEval_b <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_in(53 downto 25); --reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1(REG,415)@32 reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1(REG,413)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b(DELAY,747)@28 ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0(REG,414)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid303_pT5_uid257_sinPiZPolyEval(MULT,302)@29 topProd_uid303_pT5_uid257_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_b); topProd_uid303_pT5_uid257_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid303_pT5_uid257_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid303_pT5_uid257_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0(REG,416)@32 reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid313_pT5_uid257_sinPiZPolyEval(ADD,312)@33 sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q(53)) & reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b)); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid311_pT5_uid257_sinPiZPolyEval(BITSELECT,310)@32 lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b(24 downto 0); lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b <= lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a(DELAY,758)@32 ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b, xout => ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid311_uid314_pT5_uid257_sinPiZPolyEval(BITJOIN,313)@33 add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q & ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q; --R_uid315_pT5_uid257_sinPiZPolyEval(BITSELECT,314)@33 R_uid315_pT5_uid257_sinPiZPolyEval_in <= add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q(78 downto 0); R_uid315_pT5_uid257_sinPiZPolyEval_b <= R_uid315_pT5_uid257_sinPiZPolyEval_in(78 downto 25); --reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1(REG,417)@33 reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= R_uid315_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor(LOGICAL,1142) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1138) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q <= "011001"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp(LOGICAL,1139) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg(REG,1140) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena(REG,1143) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1144) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1134) -- every=1, low=0, high=25, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i = 24 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i - 25; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg(REG,1135) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1136) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1133) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 26, width_b => 7, widthad_b => 5, numwords_b => 26, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg(DELAY,1132) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0(REG,379)@32 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC0_uid226_sinPiZTableGenerator(LOOKUP,225)@33 memoryC0_uid226_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; WHEN "0000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111010001111111001101111011000111100001001010"; WHEN "0000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000101010101111101111010001101100110011111100100"; WHEN "0000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000010000111010001110111000001110010011001110001"; WHEN "0000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001111101100101111100010000110111011000000101000010"; WHEN "0000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110111110001111110110010110011100111000110011101"; WHEN "0000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110000101011011011100110100000100010100111010101"; WHEN "0000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001101000010010010101010100001100000100101011101101"; WHEN "0001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001011110100110101111000010100110110100001011000010"; WHEN "0001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001010011101000101100010111000010101101001011110101"; WHEN "0001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001000111011000010001010101010001011100000010111010"; WHEN "0001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000111001110101100010011111100010101010110110110111"; WHEN "0001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000101011000000100100110110100010000001101000110010"; WHEN "0001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000011010111001011101111001010100111001000011000110"; WHEN "0001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000001001100000010011100101010111111111101111100110"; WHEN "0001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111110110110101001100010110011100110010010101101111"; WHEN "0010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111100010111000001111000110100110100110000010101111"; WHEN "0010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111001101101001100011001110000111100101111100011100"; WHEN "0010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110110111001001010000100011011101100011000000101111"; WHEN "0010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110011111010111011111011011001110010110110010111000"; WHEN "0010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110000110010100011000101000000100011000111000100110"; WHEN "0010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101101100000000000101011010101010100111001000011100"; WHEN "0010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101010000011010101111100001101000100000101011011110"; WHEN "0010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100110011100100100001001001011101110011110100001011"; WHEN "0011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100010101011101100100111100011101111110101100100111"; WHEN "0011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011110110000110000110000010101011100010111110000011"; WHEN "0011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011010101011110010000000001110011001100010100001001"; WHEN "0011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010110011100110001110111101000110101001111110010101"; WHEN "0011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010010000011110001111010101010111011011010001011111"; WHEN "0011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001101100000110011110001000110001001111001100110001"; WHEN "0011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001000110011111001000110010110100010111000011111111"; WHEN "0011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001000011111101000011101001100001111101100010010011001"; WHEN "0100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111110111100010101001101010111010101001011000110001"; WHEN "0100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111001110001101111101000001101110110110001001100100"; WHEN "0100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000110100011101010100110100000100001100111000110001110"; WHEN "0100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101110111111000110101110011111101010000010000111000"; WHEN "0100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101001010111000111011000101011010001011010101011100"; WHEN "0100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000100011100101011000110111010110111110001001101100111"; WHEN "0100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000011101101001111101010010110110101000111000011000010"; WHEN "0100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010111100100110110110111000001001011110110011001101"; WHEN "0101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010001010110000111110011001111100101011011000101100"; WHEN "0101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000001010111101110010011010011011111001000011101001111"; WHEN "0101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000000100011011111001000011000000001110101111000110101"; WHEN "0101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111111101110000011110000110110101110000111000001001000"; WHEN "0101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111110110111011100100000011010011101000101101101101111"; WHEN "0101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101111111101001101011001001101111001001010100111010"; WHEN "0101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101000110101011100101100110100011000001100101000111"; WHEN "0101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111100001100100010100100101110001100110101011111100110"; WHEN "0110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111011010001001110111101111001001100110110011000001101"; WHEN "0110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111010010100110001000110111011000110000110111110111111"; WHEN "0110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111001010111001001010110000010010100110110110111111101"; WHEN "0110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111000011000011000000001111000000100110010000101101101"; WHEN "0110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110111011000011101100001100000000111000101001011011010"; WHEN "0110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110110010111011010001100011000101000010101101011001001"; WHEN "0110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110101010101001110011010011010000110001111000101001011"; WHEN "0110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110100010001111010100011110111000101000100011101001111"; WHEN "0111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110011001101011111000001011100000101000110101010111101"; WHEN "0111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110010000111111100001100001111010111101111011010000110"; WHEN "0111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110001000001010010011101110000110100100001000000010111"; WHEN "0111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101111111001100010001111111001101101111011001101100100"; WHEN "0111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101110110000101011111100111100100110000100111011101101"; WHEN "0111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101101100110101111111111100101000011001011000100010101"; WHEN "0111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101100011011101110110010110111100011110100100000110011"; WHEN "0111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101011001111101000110010010001010011001011011010110110"; WHEN "1000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101010000010011110011001100111111100111011110011001101"; WHEN "1000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101000110100010000000101001001100001000111100100001001"; WHEN "1000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100111100100111110010001011100000111110000000101011101"; WHEN "1000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100110010100101001011011011101110100010101011000001110"; WHEN "1000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100101000011010010000000100100011001001010111111110011"; WHEN "1000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100011110000111000011110011101001010100010101110100101"; WHEN "1000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100010011101011101010011001100110001101101001100010111"; WHEN "1000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100001001001000000111101001110111111110000011100100111"; WHEN "1001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011111110011100011111011010110100000010100101010111001"; WHEN "1001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011110011101000110101100101100101100000111000011110001"; WHEN "1001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011101000101101001110000110001011011010011000000110010"; WHEN "1001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011011101101001101100111011010110111110001101101101010"; WHEN "1001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011010010011110010110000110101001111010000001101101100"; WHEN "1001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011000111001011001101101100010100101001100000111100110"; WHEN "1001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010111011110000010111110011010100100100110111110110011"; WHEN "1001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010110000001101111000100101010010001110000100000110101"; WHEN "1010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010100100100011110100001110011111011100111101101011110"; WHEN "1010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010011000110010001110111101110101101010011000000111111"; WHEN "1010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010001100111001001101000100110011111001111100111000001"; WHEN "1010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010000000111000110010110111011101000010111111101010001"; WHEN "1010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001110100110001000100101100010101111000001101101010100"; WHEN "1010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001101000100010000110111100100011001110011000100010010"; WHEN "1010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001011100001011111110000011101000000001111110000000000"; WHEN "1010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001001111101110101110011111100011011011101101000101110"; WHEN "1011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001000011001010011100110000101110110100001001110110000"; WHEN "1011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000110110011111001101011001111011110110010000011100000"; WHEN "1011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000101001101101000101000000010010100000111000101001110"; WHEN "1011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000011100110100001000001011001111000111011010101001101"; WHEN "1011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000001111110100011011100100100000010001010101111111000"; WHEN "1011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000000010101110000011111000000100111000111011110010110"; WHEN "1011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111110101100001000101110100001010001000111101001001101"; WHEN "1011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111101000001101100110001001001001011001011110100011010"; WHEN "1100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111011010110011101001101001100110001011110001011110000"; WHEN "1100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111001101010011010101001010001100000101010101000000111"; WHEN "1100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110111111101100101101100001101100101001111110101000001"; WHEN "1100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110110001111111110111101000111101010101001011110111000"; WHEN "1100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110100100001100111000011010110101010010011110001011110"; WHEN "1100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110010110010011110100110100001011010101000001111000001"; WHEN "1100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110001000010100110001110011110011101110100000111111001"; WHEN "1100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101111010001111110100011010011110000101000011010111010"; WHEN "1101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101101100000101000001101010110011001000011100110100101"; WHEN "1101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101011101110100011110101001010010100110101010011100110"; WHEN "1101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101001111011110010000011100010000111111100000000100011"; WHEN "1101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101000001000010011100001011110101010111100110111011100"; WHEN "1101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100110010100001000111000001110111001010101110101010001"; WHEN "1101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100100011111010010110001001111011111101010001100000100"; WHEN "1101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100010101001110001110110001010101001101001100111101111"; WHEN "1101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100000110011100110110000110111110000010001111110011101"; WHEN "1110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011110111100110010001011011011000111101011110100101010"; WHEN "1110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011101000101010100110000000101101101000001111101101101"; WHEN "1110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011011001101001111001001010100110100010100000001010111"; WHEN "1110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011001010100100010000001110001110110000100001110111001"; WHEN "1110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010111011011001110000100010001111101000000100110100000"; WHEN "1110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010101100001010011111011110101110011100111100001100101"; WHEN "1110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010011100110110100010011101001010001101000000010101011"; WHEN "1110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010001101011101111110111000011001001011101110101101100"; WHEN "1111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001111110000000111010001100100110101101001001001010110"; WHEN "1111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001101110011111011001110111010000110000010101010100001"; WHEN "1111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001011110111001100011010111000101101001011101010010011"; WHEN "1111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001001111001111011100001100000001101011010010111101001"; WHEN "1111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000111111100001001001110111001100110000010110101011110"; WHEN "1111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000101111101110110001111010111000000011100010110001010"; WHEN "1111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000011111111000011001111010011011101000011100101001111"; WHEN "1111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000001111111110000111011010010100000011001101000010011"; WHEN OTHERS => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid258_sinPiZPolyEval(CONSTANT,257) rndBit_uid258_sinPiZPolyEval_q <= "001"; --cIncludingRoundingBit_uid259_sinPiZPolyEval(BITJOIN,258)@33 cIncludingRoundingBit_uid259_sinPiZPolyEval_q <= memoryC0_uid226_sinPiZTableGenerator_q & rndBit_uid258_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0(REG,418)@33 reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid259_sinPiZPolyEval_q; END IF; END PROCESS; --ts5_uid260_sinPiZPolyEval(ADD,259)@34 ts5_uid260_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q); ts5_uid260_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((61 downto 54 => reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q(53)) & reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q); ts5_uid260_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid260_sinPiZPolyEval_a) + SIGNED(ts5_uid260_sinPiZPolyEval_b)); ts5_uid260_sinPiZPolyEval_q <= ts5_uid260_sinPiZPolyEval_o(61 downto 0); --s5_uid261_sinPiZPolyEval(BITSELECT,260)@34 s5_uid261_sinPiZPolyEval_in <= ts5_uid260_sinPiZPolyEval_q; s5_uid261_sinPiZPolyEval_b <= s5_uid261_sinPiZPolyEval_in(61 downto 1); --fxpSinRes_uid66_fpSinPiTest(BITSELECT,65)@34 fxpSinRes_uid66_fpSinPiTest_in <= s5_uid261_sinPiZPolyEval_b(58 downto 0); fxpSinRes_uid66_fpSinPiTest_b <= fxpSinRes_uid66_fpSinPiTest_in(58 downto 5); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor(LOGICAL,963) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q <= not (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a or ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top(CONSTANT,959) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q <= "011111"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp(LOGICAL,960) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q <= "1" when ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a = ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b else "0"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg(REG,961) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena(REG,964) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q = "1") THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd(LOGICAL,965) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a and ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt(COUNTER,955) -- every=1, low=0, high=31, step=1, init=1 ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ELSIF (clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg(REG,956) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux(MUX,957) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux: PROCESS (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem(DUALMEM,954) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia <= sinXIsX_uid30_fpSinPiTest_c; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 32, width_b => 1, widthad_b => 5, numwords_b => 32, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq, address_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa, data_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia ); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg(DELAY,953) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --multRightOp_uid68_fpSinPiTest(MUX,67)@34 multRightOp_uid68_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q; multRightOp_uid68_fpSinPiTest: PROCESS (multRightOp_uid68_fpSinPiTest_s, fxpSinRes_uid66_fpSinPiTest_b) BEGIN CASE multRightOp_uid68_fpSinPiTest_s IS WHEN "0" => multRightOp_uid68_fpSinPiTest_q <= fxpSinRes_uid66_fpSinPiTest_b; WHEN "1" => multRightOp_uid68_fpSinPiTest_q <= piwFP2_uid67_fpSinPiTest_q; WHEN OTHERS => multRightOp_uid68_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_b_1(BITSELECT,318)@34 mul2xSinRes_uid69_fpSinPiTest_b_1_in <= multRightOp_uid68_fpSinPiTest_q; mul2xSinRes_uid69_fpSinPiTest_b_1_b <= mul2xSinRes_uid69_fpSinPiTest_b_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1(REG,423)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor(LOGICAL,1129) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q <= not (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a or ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top(CONSTANT,1125) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q <= "010110"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp(LOGICAL,1126) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q <= "1" when ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a = ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b else "0"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg(REG,1127) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena(REG,1130) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q = "1") THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd(LOGICAL,1131) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a and ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor(LOGICAL,937) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a or ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top(CONSTANT,933) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q <= "0111"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp(LOGICAL,934) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a = ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b else "0"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg(REG,935) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena(REG,938) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q = "1") THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd(LOGICAL,939) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt(COUNTER,929) -- every=1, low=0, high=7, step=1, init=1 ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,3); ELSIF (clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i + 1; END IF; END PROCESS; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i,3)); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg(REG,930) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux(MUX,931) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q) BEGIN CASE ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s IS WHEN "0" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; WHEN "1" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; WHEN OTHERS => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem(DUALMEM,928) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 <= areset; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia <= oFracX_uid31_uid31_fpSinPiTest_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 3, numwords_a => 8, width_b => 53, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq, address_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa, data_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia ); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq(52 downto 0); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg(DELAY,927) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg : dspba_delay GENERIC MAP ( width => 53, depth => 1 ) PORT MAP ( xin => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q, xout => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q, clk => clk, aclr => areset ); --LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest(BITSELECT,220)@10 LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q(77 downto 0); LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in(77 downto 0); --leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest(BITJOIN,221)@10 leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b & GND_q; --LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest(BITSELECT,204)@9 LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(54 downto 0); LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in(54 downto 0); --leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest(BITJOIN,205)@9 leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest(BITSELECT,201)@9 LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(62 downto 0); LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in(62 downto 0); --leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest(BITJOIN,202)@9 leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest(BITSELECT,198)@9 LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(70 downto 0); LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in(70 downto 0); --leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest(BITJOIN,199)@9 leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --ozz_uid41_fpSinPiTest(CONSTANT,40) ozz_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor(LOGICAL,1040) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q <= not (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a or ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top(CONSTANT,1036) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q <= "011"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp(LOGICAL,1037) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q <= "1" when ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a = ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b else "0"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg(REG,1038) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena(REG,1041) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q = "1") THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd(LOGICAL,1042) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a and ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b; --vStage_uid149_lzcZ_uid51_fpSinPiTest(BITSELECT,148)@4 vStage_uid149_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(14 downto 0); vStage_uid149_lzcZ_uid51_fpSinPiTest_b <= vStage_uid149_lzcZ_uid51_fpSinPiTest_in(14 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt(COUNTER,1032) -- every=1, low=0, high=3, step=1, init=1 ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,2); ELSIF (clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i,2)); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg(REG,1033) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux(MUX,1034) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1043) ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= vStage_uid149_lzcZ_uid51_fpSinPiTest_b; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 2, numwords_a => 4, width_b => 15, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(14 downto 0); --leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest(BITJOIN,193)@9 leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X46dto0_uid190_alignedZ_uid52_fpSinPiTest(BITSELECT,189)@4 X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(46 downto 0); X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in(46 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1031) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 47, widthad_a => 2, numwords_a => 4, width_b => 47, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(46 downto 0); --leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest(BITJOIN,190)@9 leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor(LOGICAL,1065) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q <= not (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a or ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top(CONSTANT,1061) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q <= "010"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp(LOGICAL,1062) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q <= "1" when ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a = ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b else "0"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg(REG,1063) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena(REG,1066) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q = "1") THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd(LOGICAL,1067) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a and ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt(COUNTER,1057) -- every=1, low=0, high=2, step=1, init=1 ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i = 1 THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i - 2; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i,2)); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg(REG,1058) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux(MUX,1059) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux: PROCESS (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem(DUALMEM,1056) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia <= z_uid49_fpSinPiTest_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 79, widthad_a => 2, numwords_a => 3, width_b => 79, widthad_b => 2, numwords_b => 3, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq, address_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa, data_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia ); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq(78 downto 0); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg(DELAY,1055) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q, xout => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --rVStage_uid146_lzcZ_uid51_fpSinPiTest(BITSELECT,145)@4 rVStage_uid146_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; rVStage_uid146_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_in(78 downto 15); --reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0(REG,365)@4 reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid147_lzcZ_uid51_fpSinPiTest(LOGICAL,146)@5 vCount_uid147_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid147_lzcZ_uid51_fpSinPiTest_a = vCount_uid147_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g(DELAY,629)@5 ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => vCount_uid147_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q, clk => clk, aclr => areset ); --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b(DELAY,587)@4 ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => vStage_uid149_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q, clk => clk, aclr => areset ); --mO_uid148_lzcZ_uid51_fpSinPiTest(CONSTANT,147) mO_uid148_lzcZ_uid51_fpSinPiTest_q <= "1111111111111111111111111111111111111111111111111"; --cStage_uid150_lzcZ_uid51_fpSinPiTest(BITJOIN,149)@5 cStage_uid150_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q & mO_uid148_lzcZ_uid51_fpSinPiTest_q; --ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c(DELAY,589)@4 ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 64, depth => 1 ) PORT MAP ( xin => rVStage_uid146_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid152_lzcZ_uid51_fpSinPiTest(MUX,151)@5 vStagei_uid152_lzcZ_uid51_fpSinPiTest_s <= vCount_uid147_lzcZ_uid51_fpSinPiTest_q; vStagei_uid152_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid152_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, cStage_uid150_lzcZ_uid51_fpSinPiTest_q) BEGIN CASE vStagei_uid152_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= cStage_uid150_lzcZ_uid51_fpSinPiTest_q; WHEN OTHERS => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid154_lzcZ_uid51_fpSinPiTest(BITSELECT,153)@5 rVStage_uid154_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q; rVStage_uid154_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_in(63 downto 32); --reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0(REG,366)@5 reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= "00000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid155_lzcZ_uid51_fpSinPiTest(LOGICAL,154)@6 vCount_uid155_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid155_lzcZ_uid51_fpSinPiTest_a = vCount_uid155_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f(DELAY,628)@6 ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid155_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q, clk => clk, aclr => areset ); --vStage_uid156_lzcZ_uid51_fpSinPiTest(BITSELECT,155)@5 vStage_uid156_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q(31 downto 0); vStage_uid156_lzcZ_uid51_fpSinPiTest_b <= vStage_uid156_lzcZ_uid51_fpSinPiTest_in(31 downto 0); --ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d(DELAY,596)@5 ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => vStage_uid156_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c(DELAY,595)@5 ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => rVStage_uid154_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid158_lzcZ_uid51_fpSinPiTest(MUX,157)@6 vStagei_uid158_lzcZ_uid51_fpSinPiTest_s <= vCount_uid155_lzcZ_uid51_fpSinPiTest_q; vStagei_uid158_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid158_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid158_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid160_lzcZ_uid51_fpSinPiTest(BITSELECT,159)@6 rVStage_uid160_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q; rVStage_uid160_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_in(31 downto 16); --reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0(REG,367)@6 reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid161_lzcZ_uid51_fpSinPiTest(LOGICAL,160)@7 vCount_uid161_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid161_lzcZ_uid51_fpSinPiTest_a = vCount_uid161_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e(DELAY,627)@7 ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid161_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q, clk => clk, aclr => areset ); --vStage_uid162_lzcZ_uid51_fpSinPiTest(BITSELECT,161)@6 vStage_uid162_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q(15 downto 0); vStage_uid162_lzcZ_uid51_fpSinPiTest_b <= vStage_uid162_lzcZ_uid51_fpSinPiTest_in(15 downto 0); --ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d(DELAY,602)@6 ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => vStage_uid162_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c(DELAY,601)@6 ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => rVStage_uid160_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid164_lzcZ_uid51_fpSinPiTest(MUX,163)@7 vStagei_uid164_lzcZ_uid51_fpSinPiTest_s <= vCount_uid161_lzcZ_uid51_fpSinPiTest_q; vStagei_uid164_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid164_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid164_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid166_lzcZ_uid51_fpSinPiTest(BITSELECT,165)@7 rVStage_uid166_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q; rVStage_uid166_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_in(15 downto 8); --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0(REG,368)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid167_lzcZ_uid51_fpSinPiTest(LOGICAL,166)@8 vCount_uid167_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid167_lzcZ_uid51_fpSinPiTest_a = vCount_uid167_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid168_lzcZ_uid51_fpSinPiTest(BITSELECT,167)@7 vStage_uid168_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q(7 downto 0); vStage_uid168_lzcZ_uid51_fpSinPiTest_b <= vStage_uid168_lzcZ_uid51_fpSinPiTest_in(7 downto 0); --reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3(REG,369)@7 reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= vStage_uid168_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2(REG,370)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vStagei_uid170_lzcZ_uid51_fpSinPiTest(MUX,169)@8 vStagei_uid170_lzcZ_uid51_fpSinPiTest_s <= vCount_uid167_lzcZ_uid51_fpSinPiTest_q; vStagei_uid170_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid170_lzcZ_uid51_fpSinPiTest_s, reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q, reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q) BEGIN CASE vStagei_uid170_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q; WHEN "1" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q; WHEN OTHERS => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid172_lzcZ_uid51_fpSinPiTest(BITSELECT,171)@8 rVStage_uid172_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q; rVStage_uid172_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_in(7 downto 4); --vCount_uid173_lzcZ_uid51_fpSinPiTest(LOGICAL,172)@8 vCount_uid173_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; vCount_uid173_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; vCount_uid173_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid173_lzcZ_uid51_fpSinPiTest_a = vCount_uid173_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid174_lzcZ_uid51_fpSinPiTest(BITSELECT,173)@8 vStage_uid174_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q(3 downto 0); vStage_uid174_lzcZ_uid51_fpSinPiTest_b <= vStage_uid174_lzcZ_uid51_fpSinPiTest_in(3 downto 0); --vStagei_uid176_lzcZ_uid51_fpSinPiTest(MUX,175)@8 vStagei_uid176_lzcZ_uid51_fpSinPiTest_s <= vCount_uid173_lzcZ_uid51_fpSinPiTest_q; vStagei_uid176_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid176_lzcZ_uid51_fpSinPiTest_s, rVStage_uid172_lzcZ_uid51_fpSinPiTest_b, vStage_uid174_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid176_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= vStage_uid174_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid178_lzcZ_uid51_fpSinPiTest(BITSELECT,177)@8 rVStage_uid178_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q; rVStage_uid178_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_in(3 downto 2); --vCount_uid179_lzcZ_uid51_fpSinPiTest(LOGICAL,178)@8 vCount_uid179_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; vCount_uid179_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; vCount_uid179_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid179_lzcZ_uid51_fpSinPiTest_a = vCount_uid179_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid180_lzcZ_uid51_fpSinPiTest(BITSELECT,179)@8 vStage_uid180_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q(1 downto 0); vStage_uid180_lzcZ_uid51_fpSinPiTest_b <= vStage_uid180_lzcZ_uid51_fpSinPiTest_in(1 downto 0); --vStagei_uid182_lzcZ_uid51_fpSinPiTest(MUX,181)@8 vStagei_uid182_lzcZ_uid51_fpSinPiTest_s <= vCount_uid179_lzcZ_uid51_fpSinPiTest_q; vStagei_uid182_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid182_lzcZ_uid51_fpSinPiTest_s, rVStage_uid178_lzcZ_uid51_fpSinPiTest_b, vStage_uid180_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid182_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= vStage_uid180_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid184_lzcZ_uid51_fpSinPiTest(BITSELECT,183)@8 rVStage_uid184_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid51_fpSinPiTest_q; rVStage_uid184_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_in(1 downto 1); --vCount_uid185_lzcZ_uid51_fpSinPiTest(LOGICAL,184)@8 vCount_uid185_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_b; vCount_uid185_lzcZ_uid51_fpSinPiTest_b <= GND_q; vCount_uid185_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid185_lzcZ_uid51_fpSinPiTest_a = vCount_uid185_lzcZ_uid51_fpSinPiTest_b else "0"; --r_uid186_lzcZ_uid51_fpSinPiTest(BITJOIN,185)@8 r_uid186_lzcZ_uid51_fpSinPiTest_q <= ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q & ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q & ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q & vCount_uid167_lzcZ_uid51_fpSinPiTest_q & vCount_uid173_lzcZ_uid51_fpSinPiTest_q & vCount_uid179_lzcZ_uid51_fpSinPiTest_q & vCount_uid185_lzcZ_uid51_fpSinPiTest_q; --leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest(BITSELECT,195)@8 leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q; leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in(6 downto 5); --reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1(REG,371)@8 reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest(MUX,196)@9 leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q, leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q; WHEN "01" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ozz_uid41_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest(BITSELECT,206)@8 leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(4 downto 0); leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in(4 downto 3); --reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1(REG,372)@8 reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest(MUX,207)@9 leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s, leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest(BITSELECT,215)@9 LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(72 downto 0); LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in(72 downto 0); --leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest(BITJOIN,216)@9 leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5(REG,374)@9 reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest(BITSELECT,212)@9 LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest(BITJOIN,213)@9 leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4(REG,375)@9 reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest(BITSELECT,209)@9 LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest(BITJOIN,210)@9 leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3(REG,376)@9 reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2(REG,377)@9 reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest(BITSELECT,217)@8 leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(2 downto 0); leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in(2 downto 1); --reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1(REG,373)@8 reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b(DELAY,657)@9 ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest(MUX,218)@10 leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s, reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q, reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q, reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q, reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q) BEGIN CASE leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q; WHEN "01" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q; WHEN "10" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q; WHEN "11" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q; WHEN OTHERS => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest(BITSELECT,222)@8 leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(0 downto 0); leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in(0 downto 0); --reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1(REG,378)@8 reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b(DELAY,665)@9 ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest(MUX,223)@10 leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s, leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q, leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q; WHEN "1" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --alignedZLow_uid53_fpSinPiTest(BITSELECT,52)@10 alignedZLow_uid53_fpSinPiTest_in <= leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q; alignedZLow_uid53_fpSinPiTest_b <= alignedZLow_uid53_fpSinPiTest_in(78 downto 27); --pHardCase_uid54_fpSinPiTest(BITJOIN,53)@10 pHardCase_uid54_fpSinPiTest_q <= alignedZLow_uid53_fpSinPiTest_b & GND_q; --ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b(DELAY,474)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 10 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q, clk => clk, aclr => areset ); --p_uid55_fpSinPiTest(MUX,54)@10 p_uid55_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q; p_uid55_fpSinPiTest: PROCESS (p_uid55_fpSinPiTest_s, pHardCase_uid54_fpSinPiTest_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q) BEGIN CASE p_uid55_fpSinPiTest_s IS WHEN "0" => p_uid55_fpSinPiTest_q <= pHardCase_uid54_fpSinPiTest_q; WHEN "1" => p_uid55_fpSinPiTest_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q; WHEN OTHERS => p_uid55_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt(COUNTER,1121) -- every=1, low=0, high=22, step=1, init=1 ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i = 21 THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i - 22; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i,5)); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg(REG,1122) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux(MUX,1123) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux: PROCESS (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q) BEGIN CASE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s IS WHEN "0" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; WHEN "1" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem(DUALMEM,1120) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 <= areset; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia <= p_uid55_fpSinPiTest_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 5, numwords_a => 23, width_b => 53, widthad_b => 5, numwords_b => 23, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq, address_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa, data_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia ); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq(52 downto 0); --mul2xSinRes_uid69_fpSinPiTest_a_1(BITSELECT,316)@34 mul2xSinRes_uid69_fpSinPiTest_a_1_in <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q); mul2xSinRes_uid69_fpSinPiTest_a_1_b <= mul2xSinRes_uid69_fpSinPiTest_a_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0(REG,424)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b1(MULT,322)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_b); mul2xSinRes_uid69_fpSinPiTest_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1(BITSELECT,329)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1(REG,425)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a_0(BITSELECT,315)@34 mul2xSinRes_uid69_fpSinPiTest_a_0_in <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_a_0_b <= mul2xSinRes_uid69_fpSinPiTest_a_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0(REG,426)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b1(MULT,321)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_b); mul2xSinRes_uid69_fpSinPiTest_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1(BITSELECT,327)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_zero_36(CONSTANT,332) mul2xSinRes_uid69_fpSinPiTest_zero_36_q <= "000000000000000000000000000"; --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2(BITJOIN,336)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1(BITSELECT,328)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_b_0(BITSELECT,317)@34 mul2xSinRes_uid69_fpSinPiTest_b_0_in <= multRightOp_uid68_fpSinPiTest_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_b_0_b <= mul2xSinRes_uid69_fpSinPiTest_b_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1(REG,421)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0(REG,422)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b0(MULT,320)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_b); mul2xSinRes_uid69_fpSinPiTest_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0(BITSELECT,325)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1(BITJOIN,335)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC(LOGICAL,340)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b; --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1(BITSELECT,330)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0(BITSELECT,326)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1(REG,419)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0(REG,420)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b0(MULT,319)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_b); mul2xSinRes_uid69_fpSinPiTest_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0(BITSELECT,324)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0(BITSELECT,323)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0(BITJOIN,334)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC(LOGICAL,339)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB(LOGICAL,338)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne(LOGICAL,341)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c; --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS(BITSELECT,342)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q(106 downto 0); mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in(106 downto 0); --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ(BITJOIN,343)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b & GND_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b(BITJOIN,350)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b(BITSELECT,353)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne(LOGICAL,337)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a(BITJOIN,348)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a(BITSELECT,352)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2(ADD,354)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin <= GND_q; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b) & mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c(0) <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(90); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(89 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b(DELAY,822)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q, clk => clk, aclr => areset ); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a(DELAY,821)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2(ADD,355)@39 mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q) & mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o(20 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a(DELAY,824)@39 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a : dspba_delay GENERIC MAP ( width => 89, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q(BITJOIN,356)@40 mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q; --normBit_uid70_fpSinPiTest(BITSELECT,69)@40 normBit_uid70_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(106 downto 0); normBit_uid70_fpSinPiTest_b <= normBit_uid70_fpSinPiTest_in(106 downto 106); --ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c(DELAY,497)@40 ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => normBit_uid70_fpSinPiTest_b, xout => ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q, clk => clk, aclr => areset ); --rndExpUpdate_uid75_uid76_fpSinPiTest(BITJOIN,75)@41 rndExpUpdate_uid75_uid76_fpSinPiTest_q <= ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q & cstAllZWF_uid10_fpSinPiTest_q & VCC_q; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor(LOGICAL,976) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q <= not (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a or ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top(CONSTANT,972) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q <= "011100"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp(LOGICAL,973) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a = ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b else "0"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg(REG,974) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena(REG,977) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q = "1") THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd(LOGICAL,978) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a and ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem(DUALMEM,941) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 <= areset; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia <= expX_uid6_fpSinPiTest_b; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 3, numwords_a => 7, width_b => 11, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq, address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa, data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia ); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq(10 downto 0); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg(DELAY,940) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q, clk => clk, aclr => areset ); --expXP1_uid58_fpSinPiTest(ADD,57)@9 expXP1_uid58_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q); expXP1_uid58_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & VCC_q); expXP1_uid58_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid58_fpSinPiTest_a) + UNSIGNED(expXP1_uid58_fpSinPiTest_b)); expXP1_uid58_fpSinPiTest_q <= expXP1_uid58_fpSinPiTest_o(11 downto 0); --expXP1R_uid59_fpSinPiTest(BITSELECT,58)@9 expXP1R_uid59_fpSinPiTest_in <= expXP1_uid58_fpSinPiTest_q(10 downto 0); expXP1R_uid59_fpSinPiTest_b <= expXP1R_uid59_fpSinPiTest_in(10 downto 0); --reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1(REG,427)@8 reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= r_uid186_lzcZ_uid51_fpSinPiTest_q; END IF; END PROCESS; --expHardCase_uid57_fpSinPiTest(SUB,56)@9 expHardCase_uid57_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid27_fpSinPiTest_q); expHardCase_uid57_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000" & reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q); expHardCase_uid57_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid57_fpSinPiTest_a) - UNSIGNED(expHardCase_uid57_fpSinPiTest_b)); expHardCase_uid57_fpSinPiTest_q <= expHardCase_uid57_fpSinPiTest_o(11 downto 0); --expHardCaseR_uid60_fpSinPiTest(BITSELECT,59)@9 expHardCaseR_uid60_fpSinPiTest_in <= expHardCase_uid57_fpSinPiTest_q(10 downto 0); expHardCaseR_uid60_fpSinPiTest_b <= expHardCaseR_uid60_fpSinPiTest_in(10 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b(DELAY,481)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 9 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q, clk => clk, aclr => areset ); --expP_uid61_fpSinPiTest(MUX,60)@9 expP_uid61_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q; expP_uid61_fpSinPiTest: PROCESS (expP_uid61_fpSinPiTest_s, expHardCaseR_uid60_fpSinPiTest_b, expXP1R_uid59_fpSinPiTest_b) BEGIN CASE expP_uid61_fpSinPiTest_s IS WHEN "0" => expP_uid61_fpSinPiTest_q <= expHardCaseR_uid60_fpSinPiTest_b; WHEN "1" => expP_uid61_fpSinPiTest_q <= expXP1R_uid59_fpSinPiTest_b; WHEN OTHERS => expP_uid61_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt(COUNTER,968) -- every=1, low=0, high=28, step=1, init=1 ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i = 27 THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i - 28; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg(REG,969) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux(MUX,970) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem(DUALMEM,967) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia <= expP_uid61_fpSinPiTest_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 29, width_b => 11, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq, address_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa, data_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia ); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq(10 downto 0); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg(DELAY,966) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q, xout => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --highRes_uid71_fpSinPiTest(BITSELECT,70)@40 highRes_uid71_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(105 downto 0); highRes_uid71_fpSinPiTest_b <= highRes_uid71_fpSinPiTest_in(105 downto 53); --lowRes_uid72_fpSinPiTest(BITSELECT,71)@40 lowRes_uid72_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(104 downto 0); lowRes_uid72_fpSinPiTest_b <= lowRes_uid72_fpSinPiTest_in(104 downto 52); --fracRCompPreRnd_uid73_fpSinPiTest(MUX,72)@40 fracRCompPreRnd_uid73_fpSinPiTest_s <= normBit_uid70_fpSinPiTest_b; fracRCompPreRnd_uid73_fpSinPiTest: PROCESS (fracRCompPreRnd_uid73_fpSinPiTest_s, lowRes_uid72_fpSinPiTest_b, highRes_uid71_fpSinPiTest_b) BEGIN CASE fracRCompPreRnd_uid73_fpSinPiTest_s IS WHEN "0" => fracRCompPreRnd_uid73_fpSinPiTest_q <= lowRes_uid72_fpSinPiTest_b; WHEN "1" => fracRCompPreRnd_uid73_fpSinPiTest_q <= highRes_uid71_fpSinPiTest_b; WHEN OTHERS => fracRCompPreRnd_uid73_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracPreRnd_uid74_uid74_fpSinPiTest(BITJOIN,73)@40 expFracPreRnd_uid74_uid74_fpSinPiTest_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q & fracRCompPreRnd_uid73_fpSinPiTest_q; --reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0(REG,428)@40 reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= expFracPreRnd_uid74_uid74_fpSinPiTest_q; END IF; END PROCESS; --expFracComp_uid77_fpSinPiTest(ADD,76)@41 expFracComp_uid77_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q); expFracComp_uid77_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & rndExpUpdate_uid75_uid76_fpSinPiTest_q); expFracComp_uid77_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid77_fpSinPiTest_a) + UNSIGNED(expFracComp_uid77_fpSinPiTest_b)); expFracComp_uid77_fpSinPiTest_q <= expFracComp_uid77_fpSinPiTest_o(64 downto 0); --expRComp_uid79_fpSinPiTest(BITSELECT,78)@41 expRComp_uid79_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(63 downto 0); expRComp_uid79_fpSinPiTest_b <= expRComp_uid79_fpSinPiTest_in(63 downto 53); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor(LOGICAL,1015) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q <= not (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a or ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top(CONSTANT,1011) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q <= "0100010"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp(LOGICAL,1012) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q <= "1" when ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a = ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b else "0"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg(REG,1013) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena(REG,1016) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q = "1") THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd(LOGICAL,1017) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a and ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b; --reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1(REG,429)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c(DELAY,516)@0 ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q, xout => ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b(DELAY,515)@0 ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => expXIsZero_uid15_fpSinPiTest_q, xout => ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q, clk => clk, aclr => areset ); --reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0(REG,361)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --excRZero_uid87_fpSinPiTest(LOGICAL,86)@3 excRZero_uid87_fpSinPiTest_a <= reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q; excRZero_uid87_fpSinPiTest_b <= ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q; excRZero_uid87_fpSinPiTest_c <= ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q; excRZero_uid87_fpSinPiTest_q <= excRZero_uid87_fpSinPiTest_a or excRZero_uid87_fpSinPiTest_b or excRZero_uid87_fpSinPiTest_c; --Or2ExcRZeroXIsInt_uid92_fpSinPiTest(LOGICAL,91)@3 Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a <= excRZero_uid87_fpSinPiTest_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b <= reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a or Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt(COUNTER,1007) -- every=1, low=0, high=34, step=1, init=1 ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i = 33 THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i - 34; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg(REG,1008) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux(MUX,1009) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux: PROCESS (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem(DUALMEM,1006) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 35, width_b => 1, widthad_b => 6, numwords_b => 35, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq, address_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa, data_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia ); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg(DELAY,1005) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q, xout => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --expRPostExc1_uid95_fpSinPiTest(MUX,94)@41 expRPostExc1_uid95_fpSinPiTest_s <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q; expRPostExc1_uid95_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE expRPostExc1_uid95_fpSinPiTest_s IS WHEN "0" => expRPostExc1_uid95_fpSinPiTest_q <= expRComp_uid79_fpSinPiTest_b; WHEN "1" => expRPostExc1_uid95_fpSinPiTest_q <= cstAllZWE_uid11_fpSinPiTest_q; WHEN OTHERS => expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --InvXIntExp_uid84_fpSinPiTest(LOGICAL,83)@2 InvXIntExp_uid84_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; InvXIntExp_uid84_fpSinPiTest_q <= not InvXIntExp_uid84_fpSinPiTest_a; --join_uid42_fpSinPiTest(BITJOIN,41)@2 join_uid42_fpSinPiTest_q <= VCC_q & ozz_uid41_fpSinPiTest_q; --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0(REG,359)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid43_fpSinPiTest(LOGICAL,42)@2 yIsZero_uid43_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q; yIsZero_uid43_fpSinPiTest_b <= join_uid42_fpSinPiTest_q; yIsZero_uid43_fpSinPiTest_q <= "1" when yIsZero_uid43_fpSinPiTest_a = yIsZero_uid43_fpSinPiTest_b else "0"; --And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest(LOGICAL,85)@2 And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b <= yIsZero_uid43_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c <= InvSinXIsX_uid80_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d <= InvXIntExp_uid84_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d; --Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest(LOGICAL,95)@1 Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a <= GND_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q <= Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a or Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b; --ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a(DELAY,528)@1 ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q, xout => ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q, clk => clk, aclr => areset ); --join_uid97_fpSinPiTest(BITJOIN,96)@2 join_uid97_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q & ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q; --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg(DELAY,1195) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => join_uid97_fpSinPiTest_q, xout => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q, clk => clk, aclr => areset ); --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem(DUALMEM,1196) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 <= areset; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 6, numwords_a => 37, width_b => 2, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0, clock1 => clk, address_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq, address_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa, data_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia ); ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq(1 downto 0); --reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1(REG,430)@41 reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q; END IF; END PROCESS; --expRPostExc_uid98_fpSinPiTest(MUX,97)@42 expRPostExc_uid98_fpSinPiTest_s <= reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q; expRPostExc_uid98_fpSinPiTest: PROCESS (expRPostExc_uid98_fpSinPiTest_s, expRPostExc1_uid95_fpSinPiTest_q) BEGIN CASE expRPostExc_uid98_fpSinPiTest_s IS WHEN "00" => expRPostExc_uid98_fpSinPiTest_q <= expRPostExc1_uid95_fpSinPiTest_q; WHEN "01" => expRPostExc_uid98_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q; WHEN "10" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN "11" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN OTHERS => expRPostExc_uid98_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --oneFracRPostExc2_uid90_fpSinPiTest(CONSTANT,89) oneFracRPostExc2_uid90_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracRComp_uid78_fpSinPiTest(BITSELECT,77)@41 fracRComp_uid78_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(52 downto 0); fracRComp_uid78_fpSinPiTest_b <= fracRComp_uid78_fpSinPiTest_in(52 downto 1); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor(LOGICAL,989) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q <= not (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a or ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top(CONSTANT,985) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q <= "0100001"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp(LOGICAL,986) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q <= "1" when ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a = ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b else "0"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg(REG,987) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena(REG,990) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q = "1") THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd(LOGICAL,991) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a and ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b; --reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1(REG,362)@3 reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= excRZero_uid87_fpSinPiTest_q; END IF; END PROCESS; --ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a(DELAY,517)@2 ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q, xout => ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q, clk => clk, aclr => areset ); --or_uid88_fpSinPiTest(LOGICAL,87)@4 or_uid88_fpSinPiTest_a <= ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q; or_uid88_fpSinPiTest_b <= reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q; or_uid88_fpSinPiTest_c <= GND_q; or_uid88_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN or_uid88_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN or_uid88_fpSinPiTest_q <= or_uid88_fpSinPiTest_a or or_uid88_fpSinPiTest_b or or_uid88_fpSinPiTest_c; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt(COUNTER,981) -- every=1, low=0, high=33, step=1, init=1 ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i = 32 THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i - 33; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg(REG,982) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux(MUX,983) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux: PROCESS (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem(DUALMEM,980) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia <= or_uid88_fpSinPiTest_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 34, width_b => 1, widthad_b => 6, numwords_b => 34, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq, address_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa, data_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia ); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg(DELAY,979) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q, xout => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --fracRPostExc1_uid89_fpSinPiTest(MUX,88)@41 fracRPostExc1_uid89_fpSinPiTest_s <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q; fracRPostExc1_uid89_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE fracRPostExc1_uid89_fpSinPiTest_s IS WHEN "0" => fracRPostExc1_uid89_fpSinPiTest_q <= fracRComp_uid78_fpSinPiTest_b; WHEN "1" => fracRPostExc1_uid89_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q; WHEN OTHERS => fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor(LOGICAL,1002) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q <= not (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a or ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top(CONSTANT,998) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q <= "0100110"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp(LOGICAL,999) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q <= "1" when ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a = ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b else "0"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg(REG,1000) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena(REG,1003) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q = "1") THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd(LOGICAL,1004) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a and ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg(DELAY,992) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q, xout => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q, clk => clk, aclr => areset ); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt(COUNTER,994) -- every=1, low=0, high=38, step=1, init=1 ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i = 37 THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i - 38; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg(REG,995) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux(MUX,996) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux: PROCESS (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem(DUALMEM,993) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 39, width_b => 1, widthad_b => 6, numwords_b => 39, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq, address_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa, data_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia ); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq(0 downto 0); --fracRPostExc_uid91_fpSinPiTest(MUX,90)@42 fracRPostExc_uid91_fpSinPiTest_s <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q; fracRPostExc_uid91_fpSinPiTest: PROCESS (fracRPostExc_uid91_fpSinPiTest_s, fracRPostExc1_uid89_fpSinPiTest_q) BEGIN CASE fracRPostExc_uid91_fpSinPiTest_s IS WHEN "0" => fracRPostExc_uid91_fpSinPiTest_q <= fracRPostExc1_uid89_fpSinPiTest_q; WHEN "1" => fracRPostExc_uid91_fpSinPiTest_q <= oneFracRPostExc2_uid90_fpSinPiTest_q; WHEN OTHERS => fracRPostExc_uid91_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid105_fpSinPiTest(BITJOIN,104)@42 R_uid105_fpSinPiTest_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q & expRPostExc_uid98_fpSinPiTest_q & fracRPostExc_uid91_fpSinPiTest_q; --ld_xIn_v_to_xOut_v_nor(LOGICAL,910) ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b); --ld_xIn_v_to_xOut_v_mem_top(CONSTANT,906) ld_xIn_v_to_xOut_v_mem_top_q <= "0100111"; --ld_xIn_v_to_xOut_v_cmp(LOGICAL,907) ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q; ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q); ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0"; --ld_xIn_v_to_xOut_v_cmpReg(REG,908) ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_sticky_ena(REG,911) ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q; END IF; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,912) ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q; ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b; --ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,902) -- every=1, low=0, high=39, step=1, init=1 ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 38 THEN ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1'; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; END IF; IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 39; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,6)); --ld_xIn_v_to_xOut_v_replace_rdreg(REG,903) ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_replace_rdmux(MUX,904) ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q; ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q) BEGIN CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q; WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,914) ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset; ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c; ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 6, numwords_a => 40, width_b => 8, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_c_to_xOut_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_c_to_xOut_c_replace_mem_iq, address_a => ld_xIn_c_to_xOut_c_replace_mem_aa, data_a => ld_xIn_c_to_xOut_c_replace_mem_ia ); ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0); --ld_xIn_c_to_xOut_c_outputreg(DELAY,913) ld_xIn_c_to_xOut_c_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset ); --ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,901) ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset; ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v; ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 40, width_b => 1, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_v_to_xOut_v_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_v_to_xOut_v_replace_mem_iq, address_a => ld_xIn_v_to_xOut_v_replace_mem_aa, data_a => ld_xIn_v_to_xOut_v_replace_mem_ia ); ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0); --ld_xIn_v_to_xOut_v_outputreg(DELAY,900) ld_xIn_v_to_xOut_v_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset ); --xOut(PORTOUT,4)@42 xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q; xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q; xOut_0 <= R_uid105_fpSinPiTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Debug Version 12.0 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from SinPiDPStratixVf400 -- VHDL created on Wed Sep 05 17:55:57 2012 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; USE work.SinPiDPStratixVf400_safe_path.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; -- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240 entity SinPiDPStratixVf400 is port ( xIn_v : in std_logic_vector(0 downto 0); xIn_c : in std_logic_vector(7 downto 0); xIn_0 : in std_logic_vector(63 downto 0); xOut_v : out std_logic_vector(0 downto 0); xOut_c : out std_logic_vector(7 downto 0); xOut_0 : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic; bus_clk : in std_logic; h_areset : in std_logic ); end; architecture normal of SinPiDPStratixVf400 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBias_uid12_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBiasPwF_uid13_fpSinPiTest_q : std_logic_vector (10 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0); signal biasM1_uid27_fpSinPiTest_q : std_logic_vector (10 downto 0); signal biasMwShift_uid29_fpSinPiTest_q : std_logic_vector (10 downto 0); signal shiftBias_uid32_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cst01pWShift_uid34_fpSinPiTest_q : std_logic_vector (27 downto 0); signal ozz_uid41_fpSinPiTest_q : std_logic_vector (78 downto 0); signal cOne_uid44_fpSinPiTest_q : std_logic_vector (80 downto 0); signal oneMinusY_uid45_fpSinPiTest_a : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_b : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_o : std_logic_vector (81 downto 0); signal oneMinusY_uid45_fpSinPiTest_q : std_logic_vector (81 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_a : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_b : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_o : std_logic_vector (84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_c : std_logic_vector (0 downto 0); signal piwFP2_uid67_fpSinPiTest_q : std_logic_vector (53 downto 0); signal or_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_b : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_c : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_q : std_logic_vector (51 downto 0); signal oneFracRPostExc2_uid90_fpSinPiTest_q : std_logic_vector (51 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (10 downto 0); signal InvXIsInt_uid100_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIsInt_uid100_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (31 downto 0); signal leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (63 downto 0); signal leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (15 downto 0); signal leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (23 downto 0); signal leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (5 downto 0); signal mO_uid148_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (48 downto 0); signal memoryC3_uid229_sinPiZTableGenerator_q : std_logic_vector(34 downto 0); signal memoryC4_uid230_sinPiZTableGenerator_q : std_logic_vector(25 downto 0); signal memoryC5_uid231_sinPiZTableGenerator_q : std_logic_vector(16 downto 0); signal rndBit_uid246_sinPiZPolyEval_q : std_logic_vector (1 downto 0); signal rndBit_uid258_sinPiZPolyEval_q : std_logic_vector (2 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_a : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 : std_logic_vector (33 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr : SIGNED (34 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_q : std_logic_vector (33 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_a : std_logic_vector (25 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_zero_36_q : std_logic_vector (26 downto 0); type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type; signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q : std_logic_vector (36 downto 0); type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o : std_logic_vector (90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o : std_logic_vector (21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q : std_logic_vector (19 downto 0); signal reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q : std_logic_vector (80 downto 0); signal reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q : std_logic_vector (80 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q : std_logic_vector (0 downto 0); signal reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (31 downto 0); signal reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (15 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (7 downto 0); signal reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q : std_logic_vector (7 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q : std_logic_vector (7 downto 0); signal reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q : std_logic_vector (78 downto 0); signal reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q : std_logic_vector (16 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q : std_logic_vector (25 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q : std_logic_vector (16 downto 0); signal reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q : std_logic_vector (17 downto 0); signal reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q : std_logic_vector (36 downto 0); signal reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q : std_logic_vector (44 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q : std_logic_vector (45 downto 0); signal reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q : std_logic_vector (51 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q : std_logic_vector (53 downto 0); signal reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q : std_logic_vector (60 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q : std_logic_vector (26 downto 0); signal reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q : std_logic_vector (6 downto 0); signal reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q : std_logic_vector (78 downto 0); signal ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q : std_logic_vector (78 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q : std_logic_vector (78 downto 0); signal ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q : std_logic_vector (14 downto 0); signal ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (63 downto 0); signal ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (31 downto 0); signal ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (31 downto 0); signal ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (15 downto 0); signal ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (15 downto 0); signal ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q : std_logic_vector (0 downto 0); signal ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q : std_logic_vector (0 downto 0); signal ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (1 downto 0); signal ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (42 downto 0); signal ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q : std_logic_vector (88 downto 0); signal ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q : std_logic_vector (79 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic; signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic; signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic; signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 : std_logic; signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i : unsigned(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q : std_logic_vector (3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i : unsigned(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q : std_logic_vector (6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i : unsigned(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q : std_logic_vector (2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (14 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ir : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i : unsigned(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q : std_logic_vector (2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ir : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ir : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 : std_logic; signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ir : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0); signal yIsZero_uid40_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (18 downto 0); signal pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal z_uid49_fpSinPiTest_s : std_logic_vector (0 downto 0); signal z_uid49_fpSinPiTest_q : std_logic_vector (78 downto 0); signal expHardCase_uid57_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expHardCase_uid57_fpSinPiTest_q : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_q : std_logic_vector (11 downto 0); signal rndExpUpdate_uid75_uid76_fpSinPiTest_q : std_logic_vector (53 downto 0); signal expFracComp_uid77_fpSinPiTest_a : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_b : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_o : std_logic_vector (64 downto 0); signal expFracComp_uid77_fpSinPiTest_q : std_logic_vector (64 downto 0); signal fracRPostExc_uid91_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc_uid91_fpSinPiTest_q : std_logic_vector (51 downto 0); signal expRPostExc_uid98_fpSinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid98_fpSinPiTest_q : std_logic_vector (10 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal memoryC0_uid226_sinPiZTableGenerator_q : std_logic_vector(57 downto 0); signal memoryC1_uid227_sinPiZTableGenerator_q : std_logic_vector(49 downto 0); signal memoryC2_uid228_sinPiZTableGenerator_q : std_logic_vector(42 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_a : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_b : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_o : std_logic_vector (35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_q : std_logic_vector (35 downto 0); signal ts3_uid248_sinPiZPolyEval_a : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_b : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_o : std_logic_vector (45 downto 0); signal ts3_uid248_sinPiZPolyEval_q : std_logic_vector (45 downto 0); signal ts4_uid254_sinPiZPolyEval_a : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_b : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_o : std_logic_vector (52 downto 0); signal ts4_uid254_sinPiZPolyEval_q : std_logic_vector (52 downto 0); signal ts5_uid260_sinPiZPolyEval_a : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_b : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_o : std_logic_vector (61 downto 0); signal ts5_uid260_sinPiZPolyEval_q : std_logic_vector (61 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal join_uid42_fpSinPiTest_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal expX_uid6_fpSinPiTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSinPiTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSinPiTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSinPiTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0); signal expXIsMax_uid16_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSinPiTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid15_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_q : std_logic_vector(0 downto 0); signal xIntExp_uid26_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xIntExp_uid26_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xIntExp_uid26_fpSinPiTest_c : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xFrac_uid28_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_n : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_a : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_b : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_o : std_logic_vector (13 downto 0); signal sinXIsX_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0); signal shiftValue_uid33_fpSinPiTest_a : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_b : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_o : std_logic_vector (11 downto 0); signal shiftValue_uid33_fpSinPiTest_q : std_logic_vector (11 downto 0); signal oMyBottom_uid47_fpSinPiTest_in : std_logic_vector (78 downto 0); signal oMyBottom_uid47_fpSinPiTest_b : std_logic_vector (78 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid150_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal cIncludingRoundingBit_uid247_sinPiZPolyEval_q : std_logic_vector (44 downto 0); signal cIncludingRoundingBit_uid253_sinPiZPolyEval_q : std_logic_vector (51 downto 0); signal cIncludingRoundingBit_uid259_sinPiZPolyEval_q : std_logic_vector (60 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q : std_logic_vector (107 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (29 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (46 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q : std_logic_vector (108 downto 0); signal yIsZero_uid43_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zPPolyEval_uid64_fpSinPiTest_in : std_logic_vector (71 downto 0); signal zPPolyEval_uid64_fpSinPiTest_b : std_logic_vector (44 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_q : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_c : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (31 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (15 downto 0); signal s2_uid240_uid243_sinPiZPolyEval_q : std_logic_vector (36 downto 0); signal add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (55 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (42 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (72 downto 0); signal add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal R_uid105_fpSinPiTest_q : std_logic_vector (63 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal yT3_uid244_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT3_uid244_sinPiZPolyEval_b : std_logic_vector (34 downto 0); signal yT4_uid250_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT4_uid250_sinPiZPolyEval_b : std_logic_vector (42 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q : std_logic_vector(0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_b : std_logic_vector (26 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zAddr_uid63_fpSinPiTest_in : std_logic_vector (78 downto 0); signal zAddr_uid63_fpSinPiTest_b : std_logic_vector (6 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (78 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (63 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (14 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (14 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (46 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (46 downto 0); signal expHardCaseR_uid60_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expHardCaseR_uid60_fpSinPiTest_b : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracRComp_uid78_fpSinPiTest_in : std_logic_vector (52 downto 0); signal fracRComp_uid78_fpSinPiTest_b : std_logic_vector (51 downto 0); signal expRComp_uid79_fpSinPiTest_in : std_logic_vector (63 downto 0); signal expRComp_uid79_fpSinPiTest_b : std_logic_vector (10 downto 0); signal intXParity_uid38_fpSinPiTest_in : std_logic_vector (80 downto 0); signal intXParity_uid38_fpSinPiTest_b : std_logic_vector (0 downto 0); signal y_uid39_fpSinPiTest_in : std_logic_vector (79 downto 0); signal y_uid39_fpSinPiTest_b : std_logic_vector (79 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (77 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (77 downto 0); signal s3_uid249_sinPiZPolyEval_in : std_logic_vector (45 downto 0); signal s3_uid249_sinPiZPolyEval_b : std_logic_vector (44 downto 0); signal s4_uid255_sinPiZPolyEval_in : std_logic_vector (52 downto 0); signal s4_uid255_sinPiZPolyEval_b : std_logic_vector (51 downto 0); signal s5_uid261_sinPiZPolyEval_in : std_logic_vector (61 downto 0); signal s5_uid261_sinPiZPolyEval_b : std_logic_vector (60 downto 0); signal oFracX_uid31_uid31_fpSinPiTest_q : std_logic_vector (52 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_in : std_logic_vector (6 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_b : std_logic_vector (6 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid235_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal highBBits_uid235_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid241_sinPiZPolyEval_in : std_logic_vector (28 downto 0); signal highBBits_uid241_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q : std_logic_vector(107 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (29 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (46 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal normBit_uid70_fpSinPiTest_in : std_logic_vector (106 downto 0); signal normBit_uid70_fpSinPiTest_b : std_logic_vector (0 downto 0); signal highRes_uid71_fpSinPiTest_in : std_logic_vector (105 downto 0); signal highRes_uid71_fpSinPiTest_b : std_logic_vector (52 downto 0); signal lowRes_uid72_fpSinPiTest_in : std_logic_vector (104 downto 0); signal lowRes_uid72_fpSinPiTest_b : std_logic_vector (52 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (70 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (70 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (62 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (62 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (54 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (54 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q : std_logic_vector(0 downto 0); signal yT1_uid232_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT1_uid232_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal yT2_uid238_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT2_uid238_sinPiZPolyEval_b : std_logic_vector (25 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (63 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (9 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (9 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (36 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (71 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (45 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (78 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (7 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (7 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (15 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (15 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expP_uid61_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expP_uid61_fpSinPiTest_q : std_logic_vector (10 downto 0); signal yBottom_uid48_fpSinPiTest_in : std_logic_vector (78 downto 0); signal yBottom_uid48_fpSinPiTest_b : std_logic_vector (78 downto 0); signal leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (51 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal fxpSinRes_uid66_fpSinPiTest_in : std_logic_vector (58 downto 0); signal fxpSinRes_uid66_fpSinPiTest_b : std_logic_vector (53 downto 0); signal extendedFracX_uid35_fpSinPiTest_q : std_logic_vector (80 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (0 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_a : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_b : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_o : std_logic_vector (26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q : std_logic_vector(107 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_q : std_logic_vector (52 downto 0); signal join_uid97_fpSinPiTest_q : std_logic_vector (1 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal signR_uid104_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (10 downto 0); signal pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (16 downto 0); signal pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal xIsInt_uid83_fpSinPiTest_a : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_b : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal multRightOp_uid68_fpSinPiTest_s : std_logic_vector (0 downto 0); signal multRightOp_uid68_fpSinPiTest_q : std_logic_vector (53 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (48 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (48 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (16 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (16 downto 0); signal s1_uid234_uid237_sinPiZPolyEval_q : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c : std_logic_vector (19 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in : std_logic_vector (106 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b : std_logic_vector (106 downto 0); signal expFracPreRnd_uid74_uid74_fpSinPiTest_q : std_logic_vector (63 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (17 downto 0); signal alignedZLow_uid53_fpSinPiTest_in : std_logic_vector (78 downto 0); signal alignedZLow_uid53_fpSinPiTest_b : std_logic_vector (51 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_b : std_logic_vector (26 downto 0); signal leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q : std_logic_vector (107 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (1 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (74 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (72 downto 0); signal pHardCase_uid54_fpSinPiTest_q : std_logic_vector (52 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q : std_logic_vector (108 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (0 downto 0); signal leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal p_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0); signal p_uid55_fpSinPiTest_q : std_logic_vector (52 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (72 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (64 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (64 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (56 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (56 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c : std_logic_vector (19 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal r_uid186_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (6 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (0 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (78 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (78 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (74 downto 0); signal leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (79 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (79 downto 0); signal leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); begin --ld_xIn_v_to_xOut_v_notEnable(LOGICAL,909) ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q; ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor(LOGICAL,1028) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q <= not (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a or ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top(CONSTANT,1024) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q <= "0100100"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp(LOGICAL,1025) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q <= "1" when ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a = ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b else "0"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg(REG,1026) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena(REG,1029) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q = "1") THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd(LOGICAL,1030) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a and ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b; --LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest(BITSELECT,134)@0 LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest(CONSTANT,133) leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q <= "000000"; --leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest(BITJOIN,135)@0 leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest(BITSELECT,131)@0 LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest(CONSTANT,130) leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q <= "0000"; --leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest(BITJOIN,132)@0 leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest(BITSELECT,128)@0 LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(78 downto 0); LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in(78 downto 0); --leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest(CONSTANT,127) leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q <= "00"; --leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest(BITJOIN,129)@0 leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest(BITSELECT,123)@0 LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(56 downto 0); LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in(56 downto 0); --leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest(CONSTANT,122) leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000"; --leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest(BITJOIN,124)@0 leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest(BITSELECT,120)@0 LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(64 downto 0); LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in(64 downto 0); --leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest(CONSTANT,119) leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000"; --leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest(BITJOIN,121)@0 leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest(BITSELECT,117)@0 LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(72 downto 0); LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in(72 downto 0); --leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest(CONSTANT,116) leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q <= "00000000"; --leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest(BITJOIN,118)@0 leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest(CONSTANT,113) leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; --X16dto0_uid112_fixedPointX_uid37_fpSinPiTest(BITSELECT,111)@0 X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(16 downto 0); X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in(16 downto 0); --leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest(CONSTANT,110) leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000"; --leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest(BITJOIN,112)@0 leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X48dto0_uid109_fixedPointX_uid37_fpSinPiTest(BITSELECT,108)@0 X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(48 downto 0); X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in(48 downto 0); --leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest(CONSTANT,107) leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q <= "00000000000000000000000000000000"; --leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest(BITJOIN,109)@0 leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --cst01pWShift_uid34_fpSinPiTest(CONSTANT,33) cst01pWShift_uid34_fpSinPiTest_q <= "0000000000000000000000000000"; --xIn(PORTIN,3)@0 --fracX_uid7_fpSinPiTest(BITSELECT,6)@0 fracX_uid7_fpSinPiTest_in <= xIn_0(51 downto 0); fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(51 downto 0); --oFracX_uid31_uid31_fpSinPiTest(BITJOIN,30)@0 oFracX_uid31_uid31_fpSinPiTest_q <= VCC_q & fracX_uid7_fpSinPiTest_b; --extendedFracX_uid35_fpSinPiTest(BITJOIN,34)@0 extendedFracX_uid35_fpSinPiTest_q <= cst01pWShift_uid34_fpSinPiTest_q & oFracX_uid31_uid31_fpSinPiTest_q; --shiftBias_uid32_fpSinPiTest(CONSTANT,31) shiftBias_uid32_fpSinPiTest_q <= "01111100011"; --expX_uid6_fpSinPiTest(BITSELECT,5)@0 expX_uid6_fpSinPiTest_in <= xIn_0(62 downto 0); expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(62 downto 52); --shiftValue_uid33_fpSinPiTest(SUB,32)@0 shiftValue_uid33_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b); shiftValue_uid33_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid32_fpSinPiTest_q); shiftValue_uid33_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid33_fpSinPiTest_a) - UNSIGNED(shiftValue_uid33_fpSinPiTest_b)); shiftValue_uid33_fpSinPiTest_q <= shiftValue_uid33_fpSinPiTest_o(11 downto 0); --fxpShifterBits_uid36_fpSinPiTest(BITSELECT,35)@0 fxpShifterBits_uid36_fpSinPiTest_in <= shiftValue_uid33_fpSinPiTest_q(6 downto 0); fxpShifterBits_uid36_fpSinPiTest_b <= fxpShifterBits_uid36_fpSinPiTest_in(6 downto 0); --leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest(BITSELECT,114)@0 leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b; leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in(6 downto 5); --leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest(MUX,115)@0 leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s, extendedFracX_uid35_fpSinPiTest_q, leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= extendedFracX_uid35_fpSinPiTest_q; WHEN "01" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest(BITSELECT,125)@0 leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(4 downto 0); leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in(4 downto 3); --leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest(MUX,126)@0 leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest(BITSELECT,136)@0 leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(2 downto 0); leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in(2 downto 1); --leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest(MUX,137)@0 leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest(BITSELECT,139)@0 LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in(79 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest(BITJOIN,140)@0 leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b & GND_q; --reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3(REG,357)@0 reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2(REG,358)@0 reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest(BITSELECT,141)@0 leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(0 downto 0); leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in(0 downto 0); --ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b(DELAY,581)@0 ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest(MUX,142)@1 leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q; leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s, reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q, reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q) BEGIN CASE leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q; WHEN "1" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q; WHEN OTHERS => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --intXParity_uid38_fpSinPiTest(BITSELECT,37)@1 intXParity_uid38_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q; intXParity_uid38_fpSinPiTest_b <= intXParity_uid38_fpSinPiTest_in(80 downto 80); --ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c(DELAY,536)@1 ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => intXParity_uid38_fpSinPiTest_b, xout => ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q, clk => clk, aclr => areset ); --biasM1_uid27_fpSinPiTest(CONSTANT,26) biasM1_uid27_fpSinPiTest_q <= "01111111110"; --xFrac_uid28_fpSinPiTest(COMPARE,27)@0 xFrac_uid28_fpSinPiTest_cin <= GND_q; xFrac_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid27_fpSinPiTest_q) & '0'; xFrac_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid28_fpSinPiTest_cin(0); xFrac_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid28_fpSinPiTest_a) - UNSIGNED(xFrac_uid28_fpSinPiTest_b)); xFrac_uid28_fpSinPiTest_n(0) <= not xFrac_uid28_fpSinPiTest_o(13); --ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a(DELAY,532)@0 ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => xFrac_uid28_fpSinPiTest_n, xout => ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvXFrac_uid99_fpSinPiTest(LOGICAL,98)@3 InvXFrac_uid99_fpSinPiTest_a <= ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q; InvXFrac_uid99_fpSinPiTest_q <= not InvXFrac_uid99_fpSinPiTest_a; --biasMwShift_uid29_fpSinPiTest(CONSTANT,28) biasMwShift_uid29_fpSinPiTest_q <= "01111100100"; --sinXIsX_uid30_fpSinPiTest(COMPARE,29)@0 sinXIsX_uid30_fpSinPiTest_cin <= GND_q; sinXIsX_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0'; sinXIsX_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid29_fpSinPiTest_q) & sinXIsX_uid30_fpSinPiTest_cin(0); sinXIsX_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid30_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid30_fpSinPiTest_b)); sinXIsX_uid30_fpSinPiTest_c(0) <= sinXIsX_uid30_fpSinPiTest_o(13); --ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a(DELAY,502)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvSinXIsX_uid80_fpSinPiTest(LOGICAL,79)@2 InvSinXIsX_uid80_fpSinPiTest_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q; InvSinXIsX_uid80_fpSinPiTest_q <= not InvSinXIsX_uid80_fpSinPiTest_a; --y_uid39_fpSinPiTest(BITSELECT,38)@1 y_uid39_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); y_uid39_fpSinPiTest_b <= y_uid39_fpSinPiTest_in(79 downto 0); --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0(REG,360)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid40_fpSinPiTest(LOGICAL,39)@2 yIsZero_uid40_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q; yIsZero_uid40_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000000000000000000000000000000000000000000000000" & GND_q); yIsZero_uid40_fpSinPiTest_q <= "1" when yIsZero_uid40_fpSinPiTest_a = yIsZero_uid40_fpSinPiTest_b else "0"; --And2YIsZeroInvSinXIsX_uid81_fpSinPiTest(LOGICAL,80)@2 And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a <= yIsZero_uid40_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b <= InvSinXIsX_uid80_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a and And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b; --cstBiasPwF_uid13_fpSinPiTest(CONSTANT,12) cstBiasPwF_uid13_fpSinPiTest_q <= "10000110011"; --xIntExp_uid26_fpSinPiTest(COMPARE,25)@0 xIntExp_uid26_fpSinPiTest_cin <= GND_q; xIntExp_uid26_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid13_fpSinPiTest_q) & '0'; xIntExp_uid26_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid26_fpSinPiTest_cin(0); xIntExp_uid26_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid26_fpSinPiTest_a) - UNSIGNED(xIntExp_uid26_fpSinPiTest_b)); xIntExp_uid26_fpSinPiTest_c(0) <= xIntExp_uid26_fpSinPiTest_o(13); --ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a(DELAY,505)@0 ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => xIntExp_uid26_fpSinPiTest_c, xout => ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q, clk => clk, aclr => areset ); --Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest(LOGICAL,81)@2 Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a or Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b; --cstAllZWF_uid10_fpSinPiTest(CONSTANT,9) cstAllZWF_uid10_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracXIsZero_uid17_fpSinPiTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b; fracXIsZero_uid17_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q; fracXIsZero_uid17_fpSinPiTest_q <= "1" when fracXIsZero_uid17_fpSinPiTest_a = fracXIsZero_uid17_fpSinPiTest_b else "0"; --ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a(DELAY,442)@0 ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => fracXIsZero_uid17_fpSinPiTest_q, xout => ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvFracXIsZero_uid19_fpSinPiTest(LOGICAL,18)@1 InvFracXIsZero_uid19_fpSinPiTest_a <= ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q; InvFracXIsZero_uid19_fpSinPiTest_q <= not InvFracXIsZero_uid19_fpSinPiTest_a; --cstAllOWE_uid9_fpSinPiTest(CONSTANT,8) cstAllOWE_uid9_fpSinPiTest_q <= "11111111111"; --expXIsMax_uid16_fpSinPiTest(LOGICAL,15)@0 expXIsMax_uid16_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsMax_uid16_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q; expXIsMax_uid16_fpSinPiTest_q <= "1" when expXIsMax_uid16_fpSinPiTest_a = expXIsMax_uid16_fpSinPiTest_b else "0"; --ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a(DELAY,443)@0 ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsMax_uid16_fpSinPiTest_q, xout => ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest(LOGICAL,19)@1 And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a <= ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b <= InvFracXIsZero_uid19_fpSinPiTest_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a and And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b; --InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest(LOGICAL,20)@1 InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q <= not InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a; --And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0 And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a <= expXIsMax_uid16_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b <= fracXIsZero_uid17_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a and And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b; --InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0 InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q; InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q <= not InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a; --cstAllZWE_uid11_fpSinPiTest(CONSTANT,10) cstAllZWE_uid11_fpSinPiTest_q <= "00000000000"; --expXIsZero_uid15_fpSinPiTest(LOGICAL,14)@0 expXIsZero_uid15_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsZero_uid15_fpSinPiTest_b <= cstAllZWE_uid11_fpSinPiTest_q; expXIsZero_uid15_fpSinPiTest_q <= "1" when expXIsZero_uid15_fpSinPiTest_a = expXIsZero_uid15_fpSinPiTest_b else "0"; --InvExpXIsZero_uid23_fpSinPiTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSinPiTest_a <= expXIsZero_uid15_fpSinPiTest_q; InvExpXIsZero_uid23_fpSinPiTest_q <= not InvExpXIsZero_uid23_fpSinPiTest_a; --And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0 And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a <= InvExpXIsZero_uid23_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b <= InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a and And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b; --ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a(DELAY,450)@0 ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q, xout => ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest(LOGICAL,24)@1 And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a <= ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b <= InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a and And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b; END IF; END PROCESS; --xIsInt_uid83_fpSinPiTest(LOGICAL,82)@2 xIsInt_uid83_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_b <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_q <= xIsInt_uid83_fpSinPiTest_a and xIsInt_uid83_fpSinPiTest_b; --InvXIsInt_uid100_fpSinPiTest(LOGICAL,99)@2 InvXIsInt_uid100_fpSinPiTest_a <= xIsInt_uid83_fpSinPiTest_q; InvXIsInt_uid100_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= not InvXIsInt_uid100_fpSinPiTest_a; END IF; END PROCESS; --signComp_uid101_fpSinPiTest(LOGICAL,100)@3 signComp_uid101_fpSinPiTest_a <= InvXIsInt_uid100_fpSinPiTest_q; signComp_uid101_fpSinPiTest_b <= InvXFrac_uid99_fpSinPiTest_q; signComp_uid101_fpSinPiTest_c <= ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q; signComp_uid101_fpSinPiTest_q <= signComp_uid101_fpSinPiTest_a and signComp_uid101_fpSinPiTest_b and signComp_uid101_fpSinPiTest_c; --ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a(DELAY,537)@2 ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => yIsZero_uid40_fpSinPiTest_q, xout => ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvYIsZero_uid102_fpSinPiTest(LOGICAL,101)@3 InvYIsZero_uid102_fpSinPiTest_a <= ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q; InvYIsZero_uid102_fpSinPiTest_q <= not InvYIsZero_uid102_fpSinPiTest_a; --And2InvYIsZeroSignComp_uid103_fpSinPiTest(LOGICAL,102)@3 And2InvYIsZeroSignComp_uid103_fpSinPiTest_a <= InvYIsZero_uid102_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_b <= signComp_uid101_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_q <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_a and And2InvYIsZeroSignComp_uid103_fpSinPiTest_b; --signX_uid8_fpSinPiTest(BITSELECT,7)@0 signX_uid8_fpSinPiTest_in <= xIn_0; signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(63 downto 63); --ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a(DELAY,540)@0 ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q, clk => clk, aclr => areset ); --signR_uid104_fpSinPiTest(LOGICAL,103)@3 signR_uid104_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q; signR_uid104_fpSinPiTest_b <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_q; signR_uid104_fpSinPiTest_q <= signR_uid104_fpSinPiTest_a xor signR_uid104_fpSinPiTest_b; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt(COUNTER,1020) -- every=1, low=0, high=36, step=1, init=1 ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i = 35 THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i - 36; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i,6)); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg(REG,1021) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --VCC(CONSTANT,1) VCC_q <= "1"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux(MUX,1022) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux: PROCESS (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem(DUALMEM,1019) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia <= signR_uid104_fpSinPiTest_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 37, width_b => 1, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq, address_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa, data_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia ); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq(0 downto 0); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg(DELAY,1018) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q, xout => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --cstBias_uid12_fpSinPiTest(CONSTANT,11) cstBias_uid12_fpSinPiTest_q <= "01111111111"; --piwFP2_uid67_fpSinPiTest(CONSTANT,66) piwFP2_uid67_fpSinPiTest_q <= "110010010000111111011010101000100010000101101000110001"; --reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1(REG,363)@1 reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --cOne_uid44_fpSinPiTest(CONSTANT,43) cOne_uid44_fpSinPiTest_q <= "100000000000000000000000000000000000000000000000000000000000000000000000000000000"; --oneMinusY_uid45_fpSinPiTest(SUB,44)@2 oneMinusY_uid45_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid44_fpSinPiTest_q); oneMinusY_uid45_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q); oneMinusY_uid45_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid45_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid45_fpSinPiTest_b)); END IF; END PROCESS; oneMinusY_uid45_fpSinPiTest_q <= oneMinusY_uid45_fpSinPiTest_o(81 downto 0); --oMyBottom_uid47_fpSinPiTest(BITSELECT,46)@3 oMyBottom_uid47_fpSinPiTest_in <= oneMinusY_uid45_fpSinPiTest_q(78 downto 0); oMyBottom_uid47_fpSinPiTest_b <= oMyBottom_uid47_fpSinPiTest_in(78 downto 0); --ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d(DELAY,471)@3 ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => oMyBottom_uid47_fpSinPiTest_b, xout => ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q, clk => clk, aclr => areset ); --yBottom_uid48_fpSinPiTest(BITSELECT,47)@1 yBottom_uid48_fpSinPiTest_in <= y_uid39_fpSinPiTest_b(78 downto 0); yBottom_uid48_fpSinPiTest_b <= yBottom_uid48_fpSinPiTest_in(78 downto 0); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c(DELAY,470)@1 ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 79, depth => 2 ) PORT MAP ( xin => yBottom_uid48_fpSinPiTest_b, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg(DELAY,926) ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a(DELAY,833)@1 ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a : dspba_delay GENERIC MAP ( width => 80, depth => 1 ) PORT MAP ( xin => y_uid39_fpSinPiTest_b, xout => ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q, clk => clk, aclr => areset ); --reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1(REG,364)@2 reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q; END IF; END PROCESS; --cmpYToOneMinusY_uid46_fpSinPiTest(COMPARE,45)@3 cmpYToOneMinusY_uid46_fpSinPiTest_cin <= GND_q; cmpYToOneMinusY_uid46_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & oneMinusY_uid45_fpSinPiTest_q) & '0'; cmpYToOneMinusY_uid46_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q) & cmpYToOneMinusY_uid46_fpSinPiTest_cin(0); cmpYToOneMinusY_uid46_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_b)); END IF; END PROCESS; cmpYToOneMinusY_uid46_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid46_fpSinPiTest_o(84); --z_uid49_fpSinPiTest(MUX,48)@4 z_uid49_fpSinPiTest_s <= cmpYToOneMinusY_uid46_fpSinPiTest_c; z_uid49_fpSinPiTest: PROCESS (z_uid49_fpSinPiTest_s, ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q) BEGIN CASE z_uid49_fpSinPiTest_s IS WHEN "0" => z_uid49_fpSinPiTest_q <= ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q; WHEN "1" => z_uid49_fpSinPiTest_q <= ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q; WHEN OTHERS => z_uid49_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --zAddr_uid63_fpSinPiTest(BITSELECT,62)@4 zAddr_uid63_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; zAddr_uid63_fpSinPiTest_b <= zAddr_uid63_fpSinPiTest_in(78 downto 72); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0(REG,382)@4 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= zAddr_uid63_fpSinPiTest_b; END IF; END PROCESS; --memoryC5_uid231_sinPiZTableGenerator(LOOKUP,230)@5 memoryC5_uid231_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; WHEN "0000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111110101101000"; WHEN "0000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111101101011101"; WHEN "0000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100110001110"; WHEN "0000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100000000010"; WHEN "0000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111011000000000"; WHEN "0000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111010001101101"; WHEN "0000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111001010010111"; WHEN "0001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111000010110010"; WHEN "0001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110111100010100"; WHEN "0001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110110100011111"; WHEN "0001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110101100101101"; WHEN "0001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110100101101011"; WHEN "0001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110011111011101"; WHEN "0001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010111001010"; WHEN "0001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010001011011"; WHEN "0010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110001010101011"; WHEN "0010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110000011011001"; WHEN "0010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101111011000001"; WHEN "0010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101110101001010"; WHEN "0010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101101110100110"; WHEN "0010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101100111100011"; WHEN "0010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011111111111"; WHEN "0010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011001001010"; WHEN "0011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101010010100110"; WHEN "0011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101001010011011"; WHEN "0011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101000100011100"; WHEN "0011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100111101010110"; WHEN "0011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100110110111000"; WHEN "0011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100101111110010"; WHEN "0011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100111110010"; WHEN "0011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100001010101"; WHEN "0100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100011011011111"; WHEN "0100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100010011110111"; WHEN "0100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100001110001010"; WHEN "0100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100000111000100"; WHEN "0100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111111110101"; WHEN "0100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111001010110"; WHEN "0100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011110011000111"; WHEN "0100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011101101000000"; WHEN "0101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011100110000011"; WHEN "0101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011111111001"; WHEN "0101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011000100110"; WHEN "0101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011010010101100"; WHEN "0101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011001100010010"; WHEN "0101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011000101010111"; WHEN "0101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111111101010"; WHEN "0101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111001010000"; WHEN "0110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010110011010011"; WHEN "0110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010101100101011"; WHEN "0110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010100110111110"; WHEN "0110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011111111000"; WHEN "0110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011010110010"; WHEN "0110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010010101001110"; WHEN "0110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001110010011"; WHEN "0110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001000111011"; WHEN "0111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010000001111011"; WHEN "0111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001111011111110"; WHEN "0111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110111001010"; WHEN "0111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110001110111"; WHEN "0111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001101011000100"; WHEN "0111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100101010010"; WHEN "0111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100000011111"; WHEN "0111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001011010001010"; WHEN "1000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001010100111110"; WHEN "1000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001110110010"; WHEN "1000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001010111000"; WHEN "1000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001000100111111"; WHEN "1000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111111001100"; WHEN "1000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111010001001"; WHEN "1000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110101010110"; WHEN "1000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110000011101"; WHEN "1001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000101001110100"; WHEN "1001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000100101111001"; WHEN "1001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011111111010"; WHEN "1001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011011110110"; WHEN "1001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010110001100"; WHEN "1001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010001001000"; WHEN "1001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001101111001"; WHEN "1001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001000000111"; WHEN "1010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000000010111001"; WHEN "1010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111110110110"; WHEN "1010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111001111111"; WHEN "1010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110110010100"; WHEN "1010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110001011000"; WHEN "1010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101100010111"; WHEN "1010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101000010010"; WHEN "1010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100100010000"; WHEN "1011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100000111100"; WHEN "1011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111011011111111"; WHEN "1011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010111100000"; WHEN "1011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010011110100"; WHEN "1011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010000011100"; WHEN "1011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111001011011110"; WHEN "1011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000111111101"; WHEN "1011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000100101011"; WHEN "1100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000001100100"; WHEN "1100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111101101110"; WHEN "1100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111010011000"; WHEN "1100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110110110000"; WHEN "1100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110010011010"; WHEN "1100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110000011110"; WHEN "1100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101100101100"; WHEN "1100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101000101110"; WHEN "1101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100110100000"; WHEN "1101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100100010001"; WHEN "1101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100001000000"; WHEN "1101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011101101110"; WHEN "1101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011011011111"; WHEN "1101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010111000100"; WHEN "1101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010101110011"; WHEN "1101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010001111100"; WHEN "1110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010000001111"; WHEN "1110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001110011001"; WHEN "1110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001010100010"; WHEN "1110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000111111000"; WHEN "1110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101110110"; WHEN "1110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101000100"; WHEN "1110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000010100010"; WHEN "1110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111111110011"; WHEN "1111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111110010000"; WHEN "1111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111100110111"; WHEN "1111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111010111000"; WHEN "1111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111000101000"; WHEN "1111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110110110100"; WHEN "1111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110101011010"; WHEN "1111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110100000011"; WHEN "1111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110010001011"; WHEN OTHERS => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; END CASE; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a(DELAY,485)@4 ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => z_uid49_fpSinPiTest_q, xout => ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q, clk => clk, aclr => areset ); --zPPolyEval_uid64_fpSinPiTest(BITSELECT,63)@5 zPPolyEval_uid64_fpSinPiTest_in <= ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q(71 downto 0); zPPolyEval_uid64_fpSinPiTest_b <= zPPolyEval_uid64_fpSinPiTest_in(71 downto 27); --yT1_uid232_sinPiZPolyEval(BITSELECT,231)@5 yT1_uid232_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT1_uid232_sinPiZPolyEval_b <= yT1_uid232_sinPiZPolyEval_in(44 downto 28); --reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0(REG,383)@5 reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= yT1_uid232_sinPiZPolyEval_b; END IF; END PROCESS; --prodXY_uid263_pT1_uid233_sinPiZPolyEval(MULT,262)@6 prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_a),18)) * SIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_b); prodXY_uid263_pT1_uid233_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= memoryC5_uid231_sinPiZTableGenerator_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr,34)); END IF; END PROCESS; prodXY_uid263_pT1_uid233_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval(BITSELECT,263)@9 prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_q; prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in(33 downto 16); --highBBits_uid235_sinPiZPolyEval(BITSELECT,234)@9 highBBits_uid235_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b; highBBits_uid235_sinPiZPolyEval_b <= highBBits_uid235_sinPiZPolyEval_in(17 downto 1); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a(DELAY,853)@4 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a : dspba_delay GENERIC MAP ( width => 7, depth => 3 ) PORT MAP ( xin => zAddr_uid63_fpSinPiTest_b, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0(REG,384)@7 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q; END IF; END PROCESS; --memoryC4_uid230_sinPiZTableGenerator(LOOKUP,229)@8 memoryC4_uid230_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; WHEN "0000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110011111111100"; WHEN "0000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100101101100110011"; WHEN "0000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100100010011000101"; WHEN "0000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100010010010010110"; WHEN "0000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011111110011000100"; WHEN "0000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011100101011001100"; WHEN "0000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011001000001111000"; WHEN "0001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010100110101100100"; WHEN "0001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010000000010110001"; WHEN "0001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001001010101111100100"; WHEN "0001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001000100111000100010"; WHEN "0001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000111110011011110101"; WHEN "0001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000110111011001010101"; WHEN "0001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000101111111000110001"; WHEN "0001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000100111101101111110"; WHEN "0010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000011111000010010110"; WHEN "0010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000010101110100101111"; WHEN "0010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000001100000110110101"; WHEN "0010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000000001101111000000"; WHEN "0010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111110110110101110011"; WHEN "0010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111101011011010111001"; WHEN "0010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111011111011110000110"; WHEN "0010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111010010111100110100"; WHEN "0011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111000101110111111001"; WHEN "0011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110111000010100011101"; WHEN "0011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110101010001000110011"; WHEN "0011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110011011011101100111"; WHEN "0011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110001100001110001111"; WHEN "0011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101111100011110001010"; WHEN "0011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101101100001110100101"; WHEN "0011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101011011011000110110"; WHEN "0100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101001001111111101110"; WHEN "0100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100111000001001001111"; WHEN "0100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100100101101100011001"; WHEN "0100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100010010110001110000"; WHEN "0100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011111111010101110110"; WHEN "0100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011101011010111000111"; WHEN "0100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011010110110110011110"; WHEN "0100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011000001110100011110"; WHEN "0101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010101100010100010011"; WHEN "0101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010010110010001000111"; WHEN "0101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001111111110001000100"; WHEN "0101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001101000101100110110"; WHEN "0101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001010001001001111011"; WHEN "0101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000111001001000001110"; WHEN "0101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000100000100011110110"; WHEN "0101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000000111100001111001"; WHEN "0110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111101101111111011111"; WHEN "0110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111010011111111100110"; WHEN "0110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110111001011110100100"; WHEN "0110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110011110100010000111"; WHEN "0110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110000011000010001001"; WHEN "0110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101100111000101000011"; WHEN "0110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101001010101101011111"; WHEN "0110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100101101110011101110"; WHEN "0111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100010000100000111110"; WHEN "0111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011110010101101110100"; WHEN "0111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011010100011010011110"; WHEN "0111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010110101101011010111"; WHEN "0111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010010110100011011101"; WHEN "0111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001110110111100001001"; WHEN "0111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001010110110110010000"; WHEN "0111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000110110011000001101"; WHEN "1000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000010101011011011001"; WHEN "1000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111110100000101110010"; WHEN "1000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111010010001110101001"; WHEN "1000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110110000000001101011"; WHEN "1000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110001101011001110011"; WHEN "1000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101101010010101011101"; WHEN "1000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101000110110101111111"; WHEN "1000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111100100010111100111100"; WHEN "1001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011111110101110100100"; WHEN "1001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011011001111111110100"; WHEN "1001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010110100111101000111"; WHEN "1001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010001111011100101001"; WHEN "1001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001101001100111100001"; WHEN "1001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001000011011000101011"; WHEN "1001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111000011100101100110010"; WHEN "1001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111110101110000000011"; WHEN "1010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111001110011001111101"; WHEN "1010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110110100110101001110001"; WHEN "1010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101111110100101001011"; WHEN "1010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101010110000110010110"; WHEN "1010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100101101010100111010"; WHEN "1010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100000100001101101101"; WHEN "1010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110011011010101110011000"; WHEN "1010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010110000111001010011"; WHEN "1011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010000110101101010010"; WHEN "1011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110001011100010001000010"; WHEN "1011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000110001011111001110"; WHEN "1011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000000110010110110100"; WHEN "1011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101111011010111010001000"; WHEN "1011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110101111001110001011"; WHEN "1011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110000011001011001100"; WHEN "1011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101101010110110100111111"; WHEN "1100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101100101010001011011001"; WHEN "1100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011111101010010000000"; WHEN "1100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011010000000101001000"; WHEN "1100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101010100010100111110111"; WHEN "1100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001110100111011010110"; WHEN "1100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001000110110111101100"; WHEN "1100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101000011000101000001000"; WHEN "1100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100111101010001001010101"; WHEN "1101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110111011010110000011"; WHEN "1101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110001100010011011010"; WHEN "1101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100101011101000100011001"; WHEN "1101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100100101101100110100111"; WHEN "1101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011111101110111111010"; WHEN "1101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011001110000000101100"; WHEN "1101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100010011101110011110101"; WHEN "1101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100001101101100000010000"; WHEN "1110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000111100111010001011"; WHEN "1110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000001100000111111010"; WHEN "1110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011111011011001110101000"; WHEN "1110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011110101010000110010111"; WHEN "1110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101111000110001000001"; WHEN "1110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101000111001101001001"; WHEN "1110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011100010101100011001010"; WHEN "1110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011011100011101111010110"; WHEN "1111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011010110001101110011110"; WHEN "1111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001111111100011010111"; WHEN "1111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001001101010000100101"; WHEN "1111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011000011010110101101110"; WHEN "1111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010111101000010001000000"; WHEN "1111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110110101100011000101"; WHEN "1111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110000010101101010111"; WHEN "1111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010101001111110001011010"; WHEN OTHERS => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; END CASE; END IF; END PROCESS; --sumAHighB_uid236_sinPiZPolyEval(ADD,235)@9 sumAHighB_uid236_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((26 downto 26 => memoryC4_uid230_sinPiZTableGenerator_q(25)) & memoryC4_uid230_sinPiZTableGenerator_q); sumAHighB_uid236_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((26 downto 17 => highBBits_uid235_sinPiZPolyEval_b(16)) & highBBits_uid235_sinPiZPolyEval_b); sumAHighB_uid236_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid236_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid236_sinPiZPolyEval_b)); sumAHighB_uid236_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_o(26 downto 0); --lowRangeB_uid234_sinPiZPolyEval(BITSELECT,233)@9 lowRangeB_uid234_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid234_sinPiZPolyEval_b <= lowRangeB_uid234_sinPiZPolyEval_in(0 downto 0); --s1_uid234_uid237_sinPiZPolyEval(BITJOIN,236)@9 s1_uid234_uid237_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_q & lowRangeB_uid234_sinPiZPolyEval_b; --reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1(REG,385)@9 reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= s1_uid234_uid237_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor(LOGICAL,1179) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q <= not (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a or ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg(REG,1177) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= VCC_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena(REG,1180) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q = "1") THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd(LOGICAL,1181) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a and ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b; --yT2_uid238_sinPiZPolyEval(BITSELECT,237)@5 yT2_uid238_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT2_uid238_sinPiZPolyEval_b <= yT2_uid238_sinPiZPolyEval_in(44 downto 19); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt(COUNTER,1173) -- every=1, low=0, high=1, step=1, init=1 ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i + 1; END IF; END PROCESS; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i,1)); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg(REG,1174) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux(MUX,1175) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q) BEGIN CASE ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s IS WHEN "0" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; WHEN "1" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem(DUALMEM,1172) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia <= yT2_uid238_sinPiZPolyEval_b; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 26, widthad_a => 1, numwords_a => 2, width_b => 26, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq, address_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa, data_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia ); ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq(25 downto 0); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg(DELAY,1171) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q, xout => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0(REG,386)@9 reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q; END IF; END PROCESS; --prodXY_uid266_pT2_uid239_sinPiZPolyEval(MULT,265)@10 prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_a),27)) * SIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_b); prodXY_uid266_pT2_uid239_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr,54)); END IF; END PROCESS; prodXY_uid266_pT2_uid239_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval(BITSELECT,266)@13 prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_q; prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in(53 downto 25); --highBBits_uid241_sinPiZPolyEval(BITSELECT,240)@13 highBBits_uid241_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b; highBBits_uid241_sinPiZPolyEval_b <= highBBits_uid241_sinPiZPolyEval_in(28 downto 1); --reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1(REG,388)@13 reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= highBBits_uid241_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor(LOGICAL,1192) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1188) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q <= "0101"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp(LOGICAL,1189) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg(REG,1190) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena(REG,1193) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1194) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1184) -- every=1, low=0, high=5, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i = 4 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i - 5; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i,3)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg(REG,1185) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1186) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1183) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 3, numwords_a => 6, width_b => 7, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg(DELAY,1182) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0(REG,387)@12 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC3_uid229_sinPiZTableGenerator(LOOKUP,228)@13 memoryC3_uid229_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; WHEN "0000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000001010001100110101000111010101"; WHEN "0000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000010100011001100101101010110011"; WHEN "0000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000011110100110001101010100011011"; WHEN "0000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000101000110010100111100101110011"; WHEN "0000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000110010111110101111101101101000"; WHEN "0000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000111101001010100001100001001101"; WHEN "0000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001000111010101111000010100001000"; WHEN "0001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001010001100000101111101001011010"; WHEN "0001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001011011101011000011001000111110"; WHEN "0001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001100101110100101110001001110101"; WHEN "0001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001101111111101101100010100000001"; WHEN "0001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001111010000101111001001101010110"; WHEN "0001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010000100001101010000011000110101"; WHEN "0001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010001110010011101101001010101000"; WHEN "0001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010011000011001001011011101011111"; WHEN "0010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010100010011101100110100011101011"; WHEN "0010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010101100100000111010000011110001"; WHEN "0010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010110110100011000001011111010110"; WHEN "0010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011000000100011111000101110110101"; WHEN "0010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011001010100011011011001000001011"; WHEN "0010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011010100100001100100010010100101"; WHEN "0010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011011110011110001111110110101010"; WHEN "0010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011101000011001011001100000011011"; WHEN "0011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011110010010010111100111000010100"; WHEN "0011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011111100001010110101011110000110"; WHEN "0011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100000110000000111111001110100010"; WHEN "0011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100001111110101010101100100101101"; WHEN "0011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100011001100111110100010110001111"; WHEN "0011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100100011011000010111001001011111"; WHEN "0011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100101101000110111001101001101001"; WHEN "0011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100110110110011010111110011001100"; WHEN "0100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101000000011101101101010000100110"; WHEN "0100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101001010000101110101101000010110"; WHEN "0100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101010011101011101100111100100100"; WHEN "0100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101011101001111001110110000110010"; WHEN "0100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101100110110000010111000000110011"; WHEN "0100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101110000001111000001100011110100"; WHEN "0100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101111001101011001010010000000001"; WHEN "0100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110000011000100101100111100001110"; WHEN "0101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110001100011011100101011010100101"; WHEN "0101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110010101101111101111110000010101"; WHEN "0101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110011111000001000111101011101100"; WHEN "0101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110101000001111101001011001100010"; WHEN "0101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110110001011011010000101101010010"; WHEN "0101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110111010100011111001100111101100"; WHEN "0101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111000011101001100000010000100010"; WHEN "0101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111001100101100000000100001010000"; WHEN "0110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111010101101011010110100011101100"; WHEN "0110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111011110100111011110011000011110"; WHEN "0110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111100111100000010100001101010000"; WHEN "0110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111110000010101110100000001010000"; WHEN "0110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111111001000111111010001101010001"; WHEN "0110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000000001110110100010110001111010"; WHEN "0110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000001010100001101001110111110101"; WHEN "0110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000010011001001001011111110000001"; WHEN "0111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000011011101101000101000010101111"; WHEN "0111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000100100001101010001101000100100"; WHEN "0111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000101100101001101110000011010101"; WHEN "0111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000110101000010010110100001011010"; WHEN "0111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000111101010111000111010101011110"; WHEN "0111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001000101100111111101000110111000"; WHEN "0111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001001101110100110100001111001100"; WHEN "0111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001010101111101101001000001001010"; WHEN "1000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001011110000010011000001001000011"; WHEN "1000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001100110000010111101111101010011"; WHEN "1000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001101101111111010111010011001111"; WHEN "1000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001110101110111100000011010000110"; WHEN "1000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001111101101011010110000011010010"; WHEN "1000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010000101011010110100111100000101"; WHEN "1000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010001101000101111001101110100011"; WHEN "1000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010010100101100100001000101010010"; WHEN "1001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010011100001110100111101001010100"; WHEN "1001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010100011101100001010100001011100"; WHEN "1001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010101011000101000110001011100100"; WHEN "1001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010110010011001010111110000100100"; WHEN "1001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010111001101000111011111001000111"; WHEN "1001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000000110011101111101001011111"; WHEN "1001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000111111001110000000110011110"; WHEN "1001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011001110111010111001110111111110"; WHEN "1010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011010101110111001010010001110110"; WHEN "1010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011011100101110011110011000111101"; WHEN "1010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011100011100000110011001001001001"; WHEN "1010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011101010001110000101111000101100"; WHEN "1010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110000110110010011100011000111"; WHEN "1010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110111011001011001011101010011"; WHEN "1010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011111101110111010100111100011100"; WHEN "1010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100000100010000000011001111101101"; WHEN "1011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100001010100011100001101110011100"; WHEN "1011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010000110001101101100011100011"; WHEN "1011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010110111010100100010100000100"; WHEN "1011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100011100111110000011100000001010"; WHEN "1011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100100010111100001000100001101001"; WHEN "1011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101000110100110000110001111011"; WHEN "1011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101110100111111010000100111001"; WHEN "1011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100110100010101100001111010001101"; WHEN "1100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111001111101100101111101110000"; WHEN "1100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111111100000000011110011100101"; WHEN "1100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101000100111100111001010011110100"; WHEN "1100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001010010100000100001001001101"; WHEN "1100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001111100101100010000111001000"; WHEN "1100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101010100110001010001010100001101"; WHEN "1100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011001110111001111010101110101"; WHEN "1100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011110110111011010001101111010"; WHEN "1101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101100011110001110000000111001111"; WHEN "1101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101000100110001110111010010001"; WHEN "1101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101101010100110100100110101101"; WHEN "1101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110001111101011111011001010101"; WHEN "1101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110110100000001101100000100000"; WHEN "1101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111010111100111100111010111000"; WHEN "1101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111111010011101100010000110110"; WHEN "1101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000011100100011001011010100000"; WHEN "1110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000111101111000011000011110011"; WHEN "1110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001011110011100111011010000000"; WHEN "1110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001111110010000100101111100001"; WHEN "1110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010011101010011001110010000111"; WHEN "1110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010111011100100100111111111001"; WHEN "1110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011011001000100101000000101011"; WHEN "1110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011110101110011000001011101010"; WHEN "1110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100010001101111101010010100010"; WHEN "1111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100101100111010011001000110011"; WHEN "1111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101000111010011000011010000011"; WHEN "1111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101100000111001011110100010010"; WHEN "1111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101111001101101100001110011100"; WHEN "1111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110010001101111000100101110110"; WHEN "1111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110101000111101111110101001010"; WHEN "1111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110111111011010000111000110000"; WHEN "1111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110111010101000011010110000100000"; WHEN OTHERS => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; END CASE; END IF; END PROCESS; --sumAHighB_uid242_sinPiZPolyEval(ADD,241)@14 sumAHighB_uid242_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid229_sinPiZTableGenerator_q(34)) & memoryC3_uid229_sinPiZTableGenerator_q); sumAHighB_uid242_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((35 downto 28 => reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q(27)) & reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q); sumAHighB_uid242_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid242_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid242_sinPiZPolyEval_b)); sumAHighB_uid242_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_o(35 downto 0); --lowRangeB_uid240_sinPiZPolyEval(BITSELECT,239)@13 lowRangeB_uid240_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid240_sinPiZPolyEval_b <= lowRangeB_uid240_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a(DELAY,686)@13 ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid240_sinPiZPolyEval_b, xout => ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --s2_uid240_uid243_sinPiZPolyEval(BITJOIN,242)@14 s2_uid240_uid243_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_q & ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q; --yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval(BITSELECT,274)@14 yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in(36 downto 19); --reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9(REG,389)@14 reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor(LOGICAL,950) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top(CONSTANT,946) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q <= "0110"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp(LOGICAL,947) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b else "0"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg(REG,948) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena(REG,951) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q = "1") THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd(LOGICAL,952) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt(COUNTER,942) -- every=1, low=0, high=6, step=1, init=1 ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i = 5 THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i - 6; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i,3)); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg(REG,943) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux(MUX,944) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q) BEGIN CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s IS WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem(DUALMEM,1069) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 3, numwords_a => 7, width_b => 45, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg(DELAY,1068) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT3_uid244_sinPiZPolyEval(BITSELECT,243)@14 yT3_uid244_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q; yT3_uid244_sinPiZPolyEval_b <= yT3_uid244_sinPiZPolyEval_in(44 downto 10); --xBottomBits_uid274_pT3_uid245_sinPiZPolyEval(BITSELECT,273)@14 xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b(7 downto 0); xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in(7 downto 0); --pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval(BITJOIN,276)@14 pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7(REG,391)@14 reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid273_pT3_uid245_sinPiZPolyEval(BITSELECT,272)@14 yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q(9 downto 0); yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b <= yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in(9 downto 0); --spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval(BITJOIN,275)@14 spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q <= GND_q & yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b; --pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval(BITJOIN,277)@14 pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q <= spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6(REG,390)@14 reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval(BITSELECT,271)@14 xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in(34 downto 17); --reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4(REG,392)@14 reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma(CHAINMULTADD,345)@15 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1),38); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0); END IF; END PROCESS; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0),37)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval(BITSELECT,279)@18 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in(36 downto 7); --highBBits_uid282_pT3_uid245_sinPiZPolyEval(BITSELECT,281)@18 highBBits_uid282_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b; highBBits_uid282_pT3_uid245_sinPiZPolyEval_b <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_in(29 downto 1); --reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1(REG,395)@18 reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval(BITSELECT,269)@14 yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in(36 downto 10); --reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1(REG,393)@14 reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval(BITSELECT,268)@14 xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in(34 downto 8); --reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0(REG,394)@14 reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid271_pT3_uid245_sinPiZPolyEval(MULT,270)@15 topProd_uid271_pT3_uid245_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_b); topProd_uid271_pT3_uid245_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid271_pT3_uid245_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid271_pT3_uid245_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0(REG,396)@18 reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid283_pT3_uid245_sinPiZPolyEval(ADD,282)@19 sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q(53)) & reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b)); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid281_pT3_uid245_sinPiZPolyEval(BITSELECT,280)@18 lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b <= lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a(DELAY,724)@18 ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b, xout => ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid281_uid284_pT3_uid245_sinPiZPolyEval(BITJOIN,283)@19 add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q & ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q; --R_uid285_pT3_uid245_sinPiZPolyEval(BITSELECT,284)@19 R_uid285_pT3_uid245_sinPiZPolyEval_in <= add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q(54 downto 0); R_uid285_pT3_uid245_sinPiZPolyEval_b <= R_uid285_pT3_uid245_sinPiZPolyEval_in(54 downto 18); --reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1(REG,397)@19 reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= R_uid285_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor(LOGICAL,1168) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1164) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q <= "01011"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp(LOGICAL,1165) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg(REG,1166) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena(REG,1169) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1170) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1160) -- every=1, low=0, high=11, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i = 10 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i - 11; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i,4)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg(REG,1161) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1162) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1159) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 4, numwords_a => 12, width_b => 7, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg(DELAY,1158) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0(REG,381)@18 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC2_uid228_sinPiZTableGenerator(LOOKUP,227)@19 memoryC2_uid228_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; WHEN "0000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010010000000010011011110101101000"; WHEN "0000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010100110111111010000111001000101"; WHEN "0000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101011001101001111001000101101101011"; WHEN "0000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101100000010110001110010011100100110"; WHEN "0000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101101000111100110110110100100001100"; WHEN "0000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101110011011101101110110101011000001"; WHEN "0000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101111111111000110001101110000001000"; WHEN "0001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110001110001101111010000000001001001"; WHEN "0001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110011110011101000001010111100010011"; WHEN "0001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110110000100110000000101010101010010"; WHEN "0001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111000100101000101111111001111001110"; WHEN "0001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111011010100101000110010000000110000"; WHEN "0001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111110010011010111010000010100101101"; WHEN "0001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000001100001010000000110001101010110"; WHEN "0001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000100111110010001111000111001110001"; WHEN "0010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001000101010011011000111000110111111"; WHEN "0010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001100100101101010001000110100001110"; WHEN "0010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010000101111111101001111011000110110"; WHEN "0010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010101001001010010100101011111010000"; WHEN "0010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011001110001101000001111010001111100"; WHEN "0010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011110101000111100001010010001101000"; WHEN "0010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111100011101111001100001101011001010011"; WHEN "0010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101001000100010110001000111111011001"; WHEN "0011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101110101000010111100110110111011101"; WHEN "0011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111110100011011001110001010010101001001"; WHEN "0011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111111010011100110111010000000101010000"; WHEN "0011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000000101101010000001110011011110111"; WHEN "0011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000111001100010110010101001001001010"; WHEN "0011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000001101111010000110101101100011101100"; WHEN "0011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000010100110110011110011010100101011100"; WHEN "0011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000011100000001011010011000101010010101"; WHEN "0100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000100011011010110111011101111001100010"; WHEN "0100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000101011000010110010011010000011100100"; WHEN "0100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000110010111001000111110110011110000010"; WHEN "0100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000111010111101110100010110010000011111"; WHEN "0100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001000011010000110100010110001010111111"; WHEN "0100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001001011110010000100001100101110011011"; WHEN "0100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001010100100001100000001010001100011000"; WHEN "0100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001011101011111000100011000101001100001"; WHEN "0101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001100110101010101100111100000000011011"; WHEN "0101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001110000000100010101110001111101110010"; WHEN "0101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001111001101011111010110010001100011010"; WHEN "0101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010000011100001010111101110001010011110"; WHEN "0101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010001101100100101000010001011000100111"; WHEN "0101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010010111110101101000000001010011000010"; WHEN "0101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010100010010100010010011101010101101010"; WHEN "0101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010101101000000100010111111000010000011"; WHEN "0110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010110111111010010100111001111011100110"; WHEN "0110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011000011000001100011011011101110111001"; WHEN "0110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011001110010110001001101100001111110101"; WHEN "0110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011011001111000000010101101100000111100"; WHEN "0110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011100101100111001001011011101110011000"; WHEN "0110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011110001100011011000101101011001110101"; WHEN "0110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011111101101100101011010011010110110001"; WHEN "0110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100001010000010111011111000101001101100"; WHEN "0111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100010110100110000101000010110110110100"; WHEN "0111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100100011010110000001010001110101000110"; WHEN "0111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100110000010010101010111111111100101100"; WHEN "0111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100111101011011111100100010000110111111"; WHEN "0111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101001010110001110000000111101111100101"; WHEN "0111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101011000010011111111111010110011011100"; WHEN "0111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101100110000010100101111111111011010100"; WHEN "0111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101110011111101011100010110011100010110"; WHEN "1000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110000010000100011100111000010100111110"; WHEN "1000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110010000010111100001011010011001010101"; WHEN "1000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110011110110110100011101100001011001000"; WHEN "1000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110101101100001011101011000001011011001"; WHEN "1000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110111100011000001000000011101110001111"; WHEN "1000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111001011011010011101001111000101110001"; WHEN "1000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111011010101000010110010101100101000110"; WHEN "1000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111101010000001101100101101100010111111"; WHEN "1001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111111001100110011001101000011100111011"; WHEN "1001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000001001010110010110010010110100011100"; WHEN "1001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000011001010001011011110100100000011000"; WHEN "1001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000101001010111100011010000011111011101"; WHEN "1001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000111001101000100101100101001010011111"; WHEN "1001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001001010000100011011101100001100000010"; WHEN "1001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001011010101010111110011010101000110000"; WHEN "1001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001101011011100000110100001001001100100"; WHEN "1010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001111100010111101100101011101111001100"; WHEN "1010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010001101011101101001100010000010111010"; WHEN "1010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010011110101101110101100111011000000101"; WHEN "1010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010110000001000001001011010101000000100"; WHEN "1010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011000001101100011101010110100010000110"; WHEN "1010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011010011011010101001110001100010110011"; WHEN "1010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011100101010010100110111101111101101001"; WHEN "1010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011110111010100001101001010000001101110"; WHEN "1011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100001001011111010100011111111010110111"; WHEN "1011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100011011110011110101000101111001011001"; WHEN "1011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100101110010001100110111110001101101110"; WHEN "1011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101000000111000100010000111010010100101"; WHEN "1011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101010011101000011110011011110001111001"; WHEN "1011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101100110100001010011110010100110010101"; WHEN "1011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101111001100010111001111110111010001011"; WHEN "1011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110001100101101001000110000010101000001"; WHEN "1100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110011111111111110111110010111000010010"; WHEN "1100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110110011011010111110101111001000100111"; WHEN "1100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111000110111110010101001010001010011010"; WHEN "1100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111011010101001110010100101101110010111"; WHEN "1100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111101110011101001110100000001111101010"; WHEN "1100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000000010011000100000010100110110100000"; WHEN "1100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000010110011011011111011011100110110011"; WHEN "1100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000101010100110000011001001011000000001"; WHEN "1101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000111110111000000010101111111100010101"; WHEN "1101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001010011010001010101011110001011010100"; WHEN "1101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001100111110001110010100000000000010111"; WHEN "1101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001111100011001010000111110011101110000"; WHEN "1101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010010001000111100111111111110011011101"; WHEN "1101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010100101111100101110100111100110010101"; WHEN "1101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010111010111000011011110110101001010101"; WHEN "1101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011001111111010100110101011010011011011"; WHEN "1110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011100101000011000110000001010000000100"; WHEN "1110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011111010010001110000110001110011111011"; WHEN "1110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100001111100110011101110011111001111111"; WHEN "1110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100100101000001000011111100000011011011"; WHEN "1110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100111010100001011001111100100100101001"; WHEN "1110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101010000000111010110100101100100010111"; WHEN "1110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101100101110010110000100101000101101101"; WHEN "1110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101111011100011011110100111000011010111"; WHEN "1111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110010001011001010111010101011001010001"; WHEN "1111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110100111010100010001011000001010110100"; WHEN "1111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110111101010100000011010101100101100011"; WHEN "1111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111010011011000100011110010000011111011"; WHEN "1111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111101001100001101001010000010010001011"; WHEN "1111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111111111101111001010010001010101000011"; WHEN "1111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000010110000000111101010100101101001001"; WHEN "1111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000101100010110111000111000011010110101"; WHEN OTHERS => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid246_sinPiZPolyEval(CONSTANT,245) rndBit_uid246_sinPiZPolyEval_q <= "01"; --cIncludingRoundingBit_uid247_sinPiZPolyEval(BITJOIN,246)@19 cIncludingRoundingBit_uid247_sinPiZPolyEval_q <= memoryC2_uid228_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0(REG,398)@19 reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid247_sinPiZPolyEval_q; END IF; END PROCESS; --ts3_uid248_sinPiZPolyEval(ADD,247)@20 ts3_uid248_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q); ts3_uid248_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q(36)) & reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q); ts3_uid248_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid248_sinPiZPolyEval_a) + SIGNED(ts3_uid248_sinPiZPolyEval_b)); ts3_uid248_sinPiZPolyEval_q <= ts3_uid248_sinPiZPolyEval_o(45 downto 0); --s3_uid249_sinPiZPolyEval(BITSELECT,248)@20 s3_uid249_sinPiZPolyEval_in <= ts3_uid248_sinPiZPolyEval_q; s3_uid249_sinPiZPolyEval_b <= s3_uid249_sinPiZPolyEval_in(45 downto 1); --yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval(BITSELECT,286)@20 yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b; yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in(44 downto 18); --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9(REG,399)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor(LOGICAL,1091) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top(CONSTANT,1087) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q <= "01100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp(LOGICAL,1088) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg(REG,1089) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena(REG,1092) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd(LOGICAL,1093) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1083) -- every=1, low=0, high=12, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i = 11 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i - 12; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i,4)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg(REG,1084) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux(MUX,1085) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem(DUALMEM,1082) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 13, width_b => 45, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg(DELAY,1081) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT4_uid250_sinPiZPolyEval(BITSELECT,249)@20 yT4_uid250_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q; yT4_uid250_sinPiZPolyEval_b <= yT4_uid250_sinPiZPolyEval_in(44 downto 2); --xBottomBits_uid290_pT4_uid251_sinPiZPolyEval(BITSELECT,289)@20 xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in <= yT4_uid250_sinPiZPolyEval_b(15 downto 0); xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in(15 downto 0); --pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval(BITJOIN,291)@20 pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7(REG,401)@20 reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid289_pT4_uid251_sinPiZPolyEval(BITSELECT,288)@20 yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b(17 downto 0); yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b <= yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a(DELAY,733)@20 ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b, xout => ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval(BITJOIN,290)@21 spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q; --pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval(BITJOIN,292)@21 pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q <= spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6(REG,400)@21 reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a(DELAY,727)@20 ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 43, depth => 1 ) PORT MAP ( xin => yT4_uid250_sinPiZPolyEval_b, xout => ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval(BITSELECT,285)@21 xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in <= ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q; xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in(42 downto 16); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4(REG,402)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma(CHAINMULTADD,346)@22 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval(BITSELECT,294)@25 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in(54 downto 8); --highBBits_uid297_pT4_uid251_sinPiZPolyEval(BITSELECT,296)@25 highBBits_uid297_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b; highBBits_uid297_pT4_uid251_sinPiZPolyEval_b <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_in(46 downto 18); --reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1(REG,405)@25 reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1(REG,403)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b(DELAY,730)@21 ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0(REG,404)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid288_pT4_uid251_sinPiZPolyEval(MULT,287)@22 topProd_uid288_pT4_uid251_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_b); topProd_uid288_pT4_uid251_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid288_pT4_uid251_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid288_pT4_uid251_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0(REG,406)@25 reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid298_pT4_uid251_sinPiZPolyEval(ADD,297)@26 sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q(53)) & reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b)); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid296_pT4_uid251_sinPiZPolyEval(BITSELECT,295)@25 lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b(17 downto 0); lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b <= lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a(DELAY,741)@25 ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b, xout => ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid296_uid299_pT4_uid251_sinPiZPolyEval(BITJOIN,298)@26 add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q & ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q; --R_uid300_pT4_uid251_sinPiZPolyEval(BITSELECT,299)@26 R_uid300_pT4_uid251_sinPiZPolyEval_in <= add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q(71 downto 0); R_uid300_pT4_uid251_sinPiZPolyEval_b <= R_uid300_pT4_uid251_sinPiZPolyEval_in(71 downto 26); --reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1(REG,407)@26 reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= R_uid300_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor(LOGICAL,1155) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1151) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q <= "010010"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp(LOGICAL,1152) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg(REG,1153) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena(REG,1156) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1157) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1147) -- every=1, low=0, high=18, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i = 17 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i - 18; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg(REG,1148) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1149) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1146) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 19, width_b => 7, widthad_b => 5, numwords_b => 19, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg(DELAY,1145) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0(REG,380)@25 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC1_uid227_sinPiZTableGenerator(LOOKUP,226)@26 memoryC1_uid227_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; WHEN "0000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111110101101010100010101111000000010001111100011"; WHEN "0000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111101011010101001001010010110100010110001011110"; WHEN "0000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111100000111111110111100000001110010011010000110"; WHEN "0000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111010110101010110001001011111100110111111100011"; WHEN "0000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111001100010101111010001010101001101111010110100"; WHEN "0000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111000010000001010110010000110111110101011111000"; WHEN "0000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110110111101101001001010011000001101011000111010"; WHEN "0001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110101101011001010111000101010111101010010100111"; WHEN "0001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110100011000110000011011011111110011010111001110"; WHEN "0001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110011000110011010010001010101101000110101101101"; WHEN "0001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110001110100001000111000101001011101110011011101"; WHEN "0001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110000100001111100101111110110001011110001011001"; WHEN "0001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101111001111110110010101010100011000010010100110"; WHEN "0001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101101111101110110000111011010000111100011100100"; WHEN "0001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101100101011111100100100011010101111000101000111"; WHEN "0010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101011011010001010001010100110101000010011111000"; WHEN "0010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101010001000011111011000001011000011010110000100"; WHEN "0010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101000110110111100101011010001111001100111110010"; WHEN "0010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100111100101100010100010000001100000101010111010"; WHEN "0010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100110010100010001011010011100011100110101011100"; WHEN "0010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100101000011001001110010100001010100000101101100"; WHEN "0010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100011110010001100001000001010100000110110000000"; WHEN "0010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100010100001011000111001001110000100110010111000"; WHEN "0011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100001010000110000100011011101011011110011010110"; WHEN "0011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100000000000010011100100100101001110110011000010"; WHEN "0011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011110110000000010011010001101000110110000011100"; WHEN "0011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011101011111111101100001110111011111101010000000"; WHEN "0011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011100010000000101011001000001011011100001111010"; WHEN "0011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011011000000011010011101000010010101100000110110"; WHEN "0011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011001110000111101001011001011110100111101110010"; WHEN "0011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011000100001101110000000101001100000101000010010"; WHEN "0100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010111010010101101011010100000110001110011110001"; WHEN "0100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010110000011111011110101110000100111100111110101"; WHEN "0100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010100110101011001101111010001011010010011110011"; WHEN "0100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010011100111000111100011110100101110100010111000"; WHEN "0100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010010011001000101110000000101001000110111000111"; WHEN "0100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010001001011010100110000100110000001000100101001"; WHEN "0100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001111111101110101000001110011010101110010001110"; WHEN "0100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001110110000100111000000000001011111111100011001"; WHEN "0101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001101100011101011000111011101000110011100100000"; WHEN "0101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001100010111000001110100001010110001110100101001"; WHEN "0101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001011001010101011100010000110111111111100011001"; WHEN "0101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001001111110101000101101000101110111110101110110"; WHEN "0101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001000110010111001110000110010111101100001101110"; WHEN "0101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000111100111011111001000110001000101111011110000"; WHEN "0101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000110011100011001010000011010001010111001000100"; WHEN "0101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000101010001101000100010111110111111001010110011"; WHEN "0110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000100000111001101011011100111000010100110100100"; WHEN "0110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000010111101001000010101010000010110010001100101"; WHEN "0110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000001110011011001101010101111010000110001110001"; WHEN "0110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000000101010000001110110101110010010100010001010"; WHEN "0110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111111100001000001010011101101111010001101110100"; WHEN "0110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111110011000011000011100000100011001001100111111"; WHEN "0110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111101010000000111101001111101101000001001100111"; WHEN "0110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111100001000001111010111011010111011101000011000"; WHEN "0111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111011000000101111111110010010111000110100000100"; WHEN "0111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111001111001101001111000010001001010010011000111"; WHEN "0111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111000110010111101011110110110010100111101001111"; WHEN "0111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110111101100101011001011010111101100111001001111"; WHEN "0111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110110100110110011010110111111001010011111110011"; WHEN "0111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110101100001010110011010101010111111100100001011"; WHEN "0111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110100011100010100101111001101101100100000011010"; WHEN "0111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110011010111101110101101001101110101101001000101"; WHEN "1000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110010010011100100101101000101111000100111000101"; WHEN "1000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110001001111110111000111000100000001110100110010"; WHEN "1000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110000001100100110010011001010000010000100100001"; WHEN "1000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101111001001110010101001001101000100001000011111"; WHEN "1000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101110000111011100100000110101100010100101111011"; WHEN "1000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101101000101100100010001011110111101101010011001"; WHEN "1000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101100000100001010010010010111110001001000100100"; WHEN "1000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101011000011001110111010100001001010011011010001"; WHEN "1001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101010000010110010100000101110111110101110111011"; WHEN "1001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101001000010110101011011100111100001010010001010"; WHEN "1001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101000000011011000000001100011011001101001101101"; WHEN "1001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100111000100011010101000101101011010001111110100"; WHEN "1001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100110000101111101100111000010010110110101001010"; WHEN "1001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100101001000000001010010010000111011001100101001"; WHEN "1001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100100001010100101111111111001100001111011011000"; WHEN "1001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100011001101101100000101001110001011001110111100"; WHEN "1010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100010010001010011110111010010010011111110100100"; WHEN "1010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100001010101011101101010111010101100101110000010"; WHEN "1010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100000011010001001110100101101010000111010011101"; WHEN "1010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011111011111011000101001000000111110001110111111"; WHEN "1010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011110100101001010011011111101101011111101000010"; WHEN "1010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011101101011011111100001011100000010100000001101"; WHEN "1010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011100110010011000001101000101010011000110001101"; WHEN "1010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011111001110100110010010011001111011110111011"; WHEN "1011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011000001110101100100010000000001110100011101"; WHEN "1011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011010001010011010110101110110000100101001100010"; WHEN "1011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011001010011100100111001101111111011000001100001"; WHEN "1011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011000011101010100000010011000001000101101011001"; WHEN "1011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010111100111101000100001111001001010100001001100"; WHEN "1011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010110110010100010101010001101001110110001111011"; WHEN "1011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101111110000010101100111110001101111011011100"; WHEN "1011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101001010001000111011100101100011001011100101"; WHEN "1100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010100010110110101100111001100000101011000010000"; WHEN "1100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010011100100001001000000101001111111111010110011"; WHEN "1100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010110010000011011000100110101011110110000011"; WHEN "1100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010000000100100111111011000101001000001000001"; WHEN "1100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010001001111101110000101000101010111011100100101"; WHEN "1100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010000011111011110111001100001010000110000001000"; WHEN "1100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111101111110111101100001111100001101100011111"; WHEN "1100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111000000111000101100100010000011111010101010"; WHEN "1101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001110010010100010001001011001010111110000100010"; WHEN "1101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001101100100110100010001100100011110001100110110"; WHEN "1101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100110111101111010011100000110010111101110011"; WHEN "1101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100001011010011011101011010000110101111000110"; WHEN "1101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001011011111100000111101001010011001011111101101"; WHEN "1101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010110100011000000000011001110101000000001010"; WHEN "1101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010001001111000110100011110100111011011010110"; WHEN "1101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001001100000000011100110011100111110000011010110"; WHEN "1110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000110110111000100011000111000000001100101100"; WHEN "1110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000001110010111110110111100101010001100011100"; WHEN "1110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000111100110100001101110001011101000100010101000"; WHEN "1110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110111111010110010100101111010011001100111001"; WHEN "1110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110011000110101110110010000101000111111101001"; WHEN "1110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101110011000000011110000110001011001010001101"; WHEN "1110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101001101110110010111010011111001000001110011"; WHEN "1110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100101001010111101100101011001011110111111001"; WHEN "1111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100000101100100101000101010110010110110110011"; WHEN "1111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011100010011101010101011110101111000111101111"; WHEN "1111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011000000000001111101000000010000000010001101"; WHEN "1111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000010011110010010101000110101101111100100010110"; WHEN "1111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001111101001111100010010010101110110011110010"; WHEN "1111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001011100111000110010010111110010100110111110"; WHEN "1111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000111101001110100001110010100000011000001001"; WHEN "1111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000011110010000111000111101011011000001000111"; WHEN OTHERS => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; END CASE; -- End reserved scope level END PROCESS; --cIncludingRoundingBit_uid253_sinPiZPolyEval(BITJOIN,252)@26 cIncludingRoundingBit_uid253_sinPiZPolyEval_q <= memoryC1_uid227_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0(REG,408)@26 reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid253_sinPiZPolyEval_q; END IF; END PROCESS; --ts4_uid254_sinPiZPolyEval(ADD,253)@27 ts4_uid254_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((52 downto 52 => reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q(51)) & reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q); ts4_uid254_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((52 downto 46 => reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q(45)) & reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q); ts4_uid254_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid254_sinPiZPolyEval_a) + SIGNED(ts4_uid254_sinPiZPolyEval_b)); ts4_uid254_sinPiZPolyEval_q <= ts4_uid254_sinPiZPolyEval_o(52 downto 0); --s4_uid255_sinPiZPolyEval(BITSELECT,254)@27 s4_uid255_sinPiZPolyEval_in <= ts4_uid254_sinPiZPolyEval_q; s4_uid255_sinPiZPolyEval_b <= s4_uid255_sinPiZPolyEval_in(52 downto 1); --yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval(BITSELECT,301)@27 yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b; yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in(51 downto 25); --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9(REG,409)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor(LOGICAL,1117) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q <= not (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a or ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top(CONSTANT,1113) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q <= "010011"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp(LOGICAL,1114) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a = ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b else "0"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg(REG,1115) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena(REG,1118) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q = "1") THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd(LOGICAL,1119) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a and ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b; --xBottomBits_uid305_pT5_uid257_sinPiZPolyEval(BITSELECT,304)@5 xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b(17 downto 0); xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt(COUNTER,1109) -- every=1, low=0, high=19, step=1, init=1 ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i = 18 THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '1'; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i - 19; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i,5)); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg(REG,1110) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux(MUX,1111) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q) BEGIN CASE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s IS WHEN "0" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; WHEN "1" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; WHEN OTHERS => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem(DUALMEM,1108) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 <= areset; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 5, numwords_a => 20, width_b => 18, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0, clock1 => clk, address_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq, address_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa, data_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia ); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg(DELAY,1107) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q, xout => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q, clk => clk, aclr => areset ); --pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval(BITJOIN,306)@27 pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7(REG,411)@27 reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid304_pT5_uid257_sinPiZPolyEval(BITSELECT,303)@27 yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b(24 downto 0); yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b <= yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a(DELAY,750)@27 ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b, xout => ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval(BITJOIN,305)@28 spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q; --pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval(BITJOIN,307)@28 pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q <= spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q & GND_q; --reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6(REG,410)@28 reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor(LOGICAL,1104) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top(CONSTANT,1100) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q <= "010100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp(LOGICAL,1101) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg(REG,1102) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena(REG,1105) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd(LOGICAL,1106) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1096) -- every=1, low=0, high=20, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i = 19 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i - 20; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i,5)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg(REG,1097) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux(MUX,1098) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem(DUALMEM,1095) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 5, numwords_a => 21, width_b => 45, widthad_b => 5, numwords_b => 21, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg(DELAY,1094) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval(BITSELECT,300)@28 xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q; xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in(44 downto 18); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4(REG,412)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma(CHAINMULTADD,347)@29 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval(BITSELECT,309)@32 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in(54 downto 1); --highBBits_uid312_pT5_uid257_sinPiZPolyEval(BITSELECT,311)@32 highBBits_uid312_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b; highBBits_uid312_pT5_uid257_sinPiZPolyEval_b <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_in(53 downto 25); --reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1(REG,415)@32 reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1(REG,413)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b(DELAY,747)@28 ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0(REG,414)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid303_pT5_uid257_sinPiZPolyEval(MULT,302)@29 topProd_uid303_pT5_uid257_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_b); topProd_uid303_pT5_uid257_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid303_pT5_uid257_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid303_pT5_uid257_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0(REG,416)@32 reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid313_pT5_uid257_sinPiZPolyEval(ADD,312)@33 sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q(53)) & reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b)); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid311_pT5_uid257_sinPiZPolyEval(BITSELECT,310)@32 lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b(24 downto 0); lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b <= lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a(DELAY,758)@32 ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b, xout => ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid311_uid314_pT5_uid257_sinPiZPolyEval(BITJOIN,313)@33 add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q & ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q; --R_uid315_pT5_uid257_sinPiZPolyEval(BITSELECT,314)@33 R_uid315_pT5_uid257_sinPiZPolyEval_in <= add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q(78 downto 0); R_uid315_pT5_uid257_sinPiZPolyEval_b <= R_uid315_pT5_uid257_sinPiZPolyEval_in(78 downto 25); --reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1(REG,417)@33 reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= R_uid315_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor(LOGICAL,1142) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1138) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q <= "011001"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp(LOGICAL,1139) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg(REG,1140) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena(REG,1143) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1144) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1134) -- every=1, low=0, high=25, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i = 24 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i - 25; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg(REG,1135) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1136) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1133) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 26, width_b => 7, widthad_b => 5, numwords_b => 26, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg(DELAY,1132) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0(REG,379)@32 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC0_uid226_sinPiZTableGenerator(LOOKUP,225)@33 memoryC0_uid226_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; WHEN "0000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111010001111111001101111011000111100001001010"; WHEN "0000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000101010101111101111010001101100110011111100100"; WHEN "0000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000010000111010001110111000001110010011001110001"; WHEN "0000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001111101100101111100010000110111011000000101000010"; WHEN "0000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110111110001111110110010110011100111000110011101"; WHEN "0000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110000101011011011100110100000100010100111010101"; WHEN "0000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001101000010010010101010100001100000100101011101101"; WHEN "0001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001011110100110101111000010100110110100001011000010"; WHEN "0001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001010011101000101100010111000010101101001011110101"; WHEN "0001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001000111011000010001010101010001011100000010111010"; WHEN "0001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000111001110101100010011111100010101010110110110111"; WHEN "0001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000101011000000100100110110100010000001101000110010"; WHEN "0001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000011010111001011101111001010100111001000011000110"; WHEN "0001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000001001100000010011100101010111111111101111100110"; WHEN "0001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111110110110101001100010110011100110010010101101111"; WHEN "0010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111100010111000001111000110100110100110000010101111"; WHEN "0010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111001101101001100011001110000111100101111100011100"; WHEN "0010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110110111001001010000100011011101100011000000101111"; WHEN "0010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110011111010111011111011011001110010110110010111000"; WHEN "0010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110000110010100011000101000000100011000111000100110"; WHEN "0010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101101100000000000101011010101010100111001000011100"; WHEN "0010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101010000011010101111100001101000100000101011011110"; WHEN "0010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100110011100100100001001001011101110011110100001011"; WHEN "0011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100010101011101100100111100011101111110101100100111"; WHEN "0011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011110110000110000110000010101011100010111110000011"; WHEN "0011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011010101011110010000000001110011001100010100001001"; WHEN "0011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010110011100110001110111101000110101001111110010101"; WHEN "0011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010010000011110001111010101010111011011010001011111"; WHEN "0011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001101100000110011110001000110001001111001100110001"; WHEN "0011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001000110011111001000110010110100010111000011111111"; WHEN "0011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001000011111101000011101001100001111101100010010011001"; WHEN "0100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111110111100010101001101010111010101001011000110001"; WHEN "0100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111001110001101111101000001101110110110001001100100"; WHEN "0100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000110100011101010100110100000100001100111000110001110"; WHEN "0100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101110111111000110101110011111101010000010000111000"; WHEN "0100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101001010111000111011000101011010001011010101011100"; WHEN "0100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000100011100101011000110111010110111110001001101100111"; WHEN "0100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000011101101001111101010010110110101000111000011000010"; WHEN "0100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010111100100110110110111000001001011110110011001101"; WHEN "0101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010001010110000111110011001111100101011011000101100"; WHEN "0101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000001010111101110010011010011011111001000011101001111"; WHEN "0101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000000100011011111001000011000000001110101111000110101"; WHEN "0101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111111101110000011110000110110101110000111000001001000"; WHEN "0101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111110110111011100100000011010011101000101101101101111"; WHEN "0101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101111111101001101011001001101111001001010100111010"; WHEN "0101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101000110101011100101100110100011000001100101000111"; WHEN "0101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111100001100100010100100101110001100110101011111100110"; WHEN "0110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111011010001001110111101111001001100110110011000001101"; WHEN "0110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111010010100110001000110111011000110000110111110111111"; WHEN "0110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111001010111001001010110000010010100110110110111111101"; WHEN "0110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111000011000011000000001111000000100110010000101101101"; WHEN "0110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110111011000011101100001100000000111000101001011011010"; WHEN "0110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110110010111011010001100011000101000010101101011001001"; WHEN "0110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110101010101001110011010011010000110001111000101001011"; WHEN "0110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110100010001111010100011110111000101000100011101001111"; WHEN "0111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110011001101011111000001011100000101000110101010111101"; WHEN "0111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110010000111111100001100001111010111101111011010000110"; WHEN "0111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110001000001010010011101110000110100100001000000010111"; WHEN "0111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101111111001100010001111111001101101111011001101100100"; WHEN "0111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101110110000101011111100111100100110000100111011101101"; WHEN "0111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101101100110101111111111100101000011001011000100010101"; WHEN "0111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101100011011101110110010110111100011110100100000110011"; WHEN "0111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101011001111101000110010010001010011001011011010110110"; WHEN "1000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101010000010011110011001100111111100111011110011001101"; WHEN "1000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101000110100010000000101001001100001000111100100001001"; WHEN "1000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100111100100111110010001011100000111110000000101011101"; WHEN "1000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100110010100101001011011011101110100010101011000001110"; WHEN "1000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100101000011010010000000100100011001001010111111110011"; WHEN "1000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100011110000111000011110011101001010100010101110100101"; WHEN "1000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100010011101011101010011001100110001101101001100010111"; WHEN "1000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100001001001000000111101001110111111110000011100100111"; WHEN "1001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011111110011100011111011010110100000010100101010111001"; WHEN "1001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011110011101000110101100101100101100000111000011110001"; WHEN "1001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011101000101101001110000110001011011010011000000110010"; WHEN "1001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011011101101001101100111011010110111110001101101101010"; WHEN "1001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011010010011110010110000110101001111010000001101101100"; WHEN "1001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011000111001011001101101100010100101001100000111100110"; WHEN "1001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010111011110000010111110011010100100100110111110110011"; WHEN "1001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010110000001101111000100101010010001110000100000110101"; WHEN "1010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010100100100011110100001110011111011100111101101011110"; WHEN "1010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010011000110010001110111101110101101010011000000111111"; WHEN "1010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010001100111001001101000100110011111001111100111000001"; WHEN "1010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010000000111000110010110111011101000010111111101010001"; WHEN "1010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001110100110001000100101100010101111000001101101010100"; WHEN "1010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001101000100010000110111100100011001110011000100010010"; WHEN "1010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001011100001011111110000011101000000001111110000000000"; WHEN "1010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001001111101110101110011111100011011011101101000101110"; WHEN "1011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001000011001010011100110000101110110100001001110110000"; WHEN "1011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000110110011111001101011001111011110110010000011100000"; WHEN "1011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000101001101101000101000000010010100000111000101001110"; WHEN "1011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000011100110100001000001011001111000111011010101001101"; WHEN "1011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000001111110100011011100100100000010001010101111111000"; WHEN "1011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000000010101110000011111000000100111000111011110010110"; WHEN "1011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111110101100001000101110100001010001000111101001001101"; WHEN "1011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111101000001101100110001001001001011001011110100011010"; WHEN "1100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111011010110011101001101001100110001011110001011110000"; WHEN "1100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111001101010011010101001010001100000101010101000000111"; WHEN "1100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110111111101100101101100001101100101001111110101000001"; WHEN "1100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110110001111111110111101000111101010101001011110111000"; WHEN "1100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110100100001100111000011010110101010010011110001011110"; WHEN "1100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110010110010011110100110100001011010101000001111000001"; WHEN "1100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110001000010100110001110011110011101110100000111111001"; WHEN "1100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101111010001111110100011010011110000101000011010111010"; WHEN "1101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101101100000101000001101010110011001000011100110100101"; WHEN "1101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101011101110100011110101001010010100110101010011100110"; WHEN "1101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101001111011110010000011100010000111111100000000100011"; WHEN "1101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101000001000010011100001011110101010111100110111011100"; WHEN "1101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100110010100001000111000001110111001010101110101010001"; WHEN "1101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100100011111010010110001001111011111101010001100000100"; WHEN "1101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100010101001110001110110001010101001101001100111101111"; WHEN "1101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100000110011100110110000110111110000010001111110011101"; WHEN "1110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011110111100110010001011011011000111101011110100101010"; WHEN "1110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011101000101010100110000000101101101000001111101101101"; WHEN "1110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011011001101001111001001010100110100010100000001010111"; WHEN "1110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011001010100100010000001110001110110000100001110111001"; WHEN "1110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010111011011001110000100010001111101000000100110100000"; WHEN "1110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010101100001010011111011110101110011100111100001100101"; WHEN "1110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010011100110110100010011101001010001101000000010101011"; WHEN "1110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010001101011101111110111000011001001011101110101101100"; WHEN "1111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001111110000000111010001100100110101101001001001010110"; WHEN "1111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001101110011111011001110111010000110000010101010100001"; WHEN "1111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001011110111001100011010111000101101001011101010010011"; WHEN "1111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001001111001111011100001100000001101011010010111101001"; WHEN "1111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000111111100001001001110111001100110000010110101011110"; WHEN "1111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000101111101110110001111010111000000011100010110001010"; WHEN "1111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000011111111000011001111010011011101000011100101001111"; WHEN "1111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000001111111110000111011010010100000011001101000010011"; WHEN OTHERS => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid258_sinPiZPolyEval(CONSTANT,257) rndBit_uid258_sinPiZPolyEval_q <= "001"; --cIncludingRoundingBit_uid259_sinPiZPolyEval(BITJOIN,258)@33 cIncludingRoundingBit_uid259_sinPiZPolyEval_q <= memoryC0_uid226_sinPiZTableGenerator_q & rndBit_uid258_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0(REG,418)@33 reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid259_sinPiZPolyEval_q; END IF; END PROCESS; --ts5_uid260_sinPiZPolyEval(ADD,259)@34 ts5_uid260_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q); ts5_uid260_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((61 downto 54 => reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q(53)) & reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q); ts5_uid260_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid260_sinPiZPolyEval_a) + SIGNED(ts5_uid260_sinPiZPolyEval_b)); ts5_uid260_sinPiZPolyEval_q <= ts5_uid260_sinPiZPolyEval_o(61 downto 0); --s5_uid261_sinPiZPolyEval(BITSELECT,260)@34 s5_uid261_sinPiZPolyEval_in <= ts5_uid260_sinPiZPolyEval_q; s5_uid261_sinPiZPolyEval_b <= s5_uid261_sinPiZPolyEval_in(61 downto 1); --fxpSinRes_uid66_fpSinPiTest(BITSELECT,65)@34 fxpSinRes_uid66_fpSinPiTest_in <= s5_uid261_sinPiZPolyEval_b(58 downto 0); fxpSinRes_uid66_fpSinPiTest_b <= fxpSinRes_uid66_fpSinPiTest_in(58 downto 5); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor(LOGICAL,963) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q <= not (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a or ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top(CONSTANT,959) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q <= "011111"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp(LOGICAL,960) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q <= "1" when ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a = ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b else "0"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg(REG,961) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena(REG,964) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q = "1") THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd(LOGICAL,965) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a and ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt(COUNTER,955) -- every=1, low=0, high=31, step=1, init=1 ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ELSIF (clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg(REG,956) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux(MUX,957) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux: PROCESS (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem(DUALMEM,954) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia <= sinXIsX_uid30_fpSinPiTest_c; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 32, width_b => 1, widthad_b => 5, numwords_b => 32, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq, address_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa, data_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia ); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg(DELAY,953) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --multRightOp_uid68_fpSinPiTest(MUX,67)@34 multRightOp_uid68_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q; multRightOp_uid68_fpSinPiTest: PROCESS (multRightOp_uid68_fpSinPiTest_s, fxpSinRes_uid66_fpSinPiTest_b) BEGIN CASE multRightOp_uid68_fpSinPiTest_s IS WHEN "0" => multRightOp_uid68_fpSinPiTest_q <= fxpSinRes_uid66_fpSinPiTest_b; WHEN "1" => multRightOp_uid68_fpSinPiTest_q <= piwFP2_uid67_fpSinPiTest_q; WHEN OTHERS => multRightOp_uid68_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_b_1(BITSELECT,318)@34 mul2xSinRes_uid69_fpSinPiTest_b_1_in <= multRightOp_uid68_fpSinPiTest_q; mul2xSinRes_uid69_fpSinPiTest_b_1_b <= mul2xSinRes_uid69_fpSinPiTest_b_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1(REG,423)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor(LOGICAL,1129) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q <= not (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a or ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top(CONSTANT,1125) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q <= "010110"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp(LOGICAL,1126) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q <= "1" when ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a = ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b else "0"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg(REG,1127) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena(REG,1130) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q = "1") THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd(LOGICAL,1131) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a and ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor(LOGICAL,937) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a or ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top(CONSTANT,933) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q <= "0111"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp(LOGICAL,934) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a = ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b else "0"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg(REG,935) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena(REG,938) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q = "1") THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd(LOGICAL,939) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt(COUNTER,929) -- every=1, low=0, high=7, step=1, init=1 ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,3); ELSIF (clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i + 1; END IF; END PROCESS; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i,3)); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg(REG,930) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux(MUX,931) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q) BEGIN CASE ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s IS WHEN "0" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; WHEN "1" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; WHEN OTHERS => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem(DUALMEM,928) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 <= areset; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia <= oFracX_uid31_uid31_fpSinPiTest_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 3, numwords_a => 8, width_b => 53, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq, address_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa, data_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia ); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq(52 downto 0); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg(DELAY,927) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg : dspba_delay GENERIC MAP ( width => 53, depth => 1 ) PORT MAP ( xin => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q, xout => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q, clk => clk, aclr => areset ); --LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest(BITSELECT,220)@10 LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q(77 downto 0); LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in(77 downto 0); --leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest(BITJOIN,221)@10 leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b & GND_q; --LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest(BITSELECT,204)@9 LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(54 downto 0); LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in(54 downto 0); --leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest(BITJOIN,205)@9 leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest(BITSELECT,201)@9 LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(62 downto 0); LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in(62 downto 0); --leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest(BITJOIN,202)@9 leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest(BITSELECT,198)@9 LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(70 downto 0); LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in(70 downto 0); --leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest(BITJOIN,199)@9 leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --ozz_uid41_fpSinPiTest(CONSTANT,40) ozz_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor(LOGICAL,1040) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q <= not (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a or ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top(CONSTANT,1036) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q <= "011"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp(LOGICAL,1037) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q <= "1" when ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a = ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b else "0"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg(REG,1038) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena(REG,1041) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q = "1") THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd(LOGICAL,1042) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a and ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b; --vStage_uid149_lzcZ_uid51_fpSinPiTest(BITSELECT,148)@4 vStage_uid149_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(14 downto 0); vStage_uid149_lzcZ_uid51_fpSinPiTest_b <= vStage_uid149_lzcZ_uid51_fpSinPiTest_in(14 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt(COUNTER,1032) -- every=1, low=0, high=3, step=1, init=1 ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,2); ELSIF (clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i,2)); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg(REG,1033) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux(MUX,1034) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1043) ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= vStage_uid149_lzcZ_uid51_fpSinPiTest_b; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 2, numwords_a => 4, width_b => 15, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(14 downto 0); --leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest(BITJOIN,193)@9 leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X46dto0_uid190_alignedZ_uid52_fpSinPiTest(BITSELECT,189)@4 X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(46 downto 0); X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in(46 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1031) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 47, widthad_a => 2, numwords_a => 4, width_b => 47, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(46 downto 0); --leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest(BITJOIN,190)@9 leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor(LOGICAL,1065) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q <= not (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a or ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top(CONSTANT,1061) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q <= "010"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp(LOGICAL,1062) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q <= "1" when ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a = ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b else "0"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg(REG,1063) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena(REG,1066) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q = "1") THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd(LOGICAL,1067) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a and ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt(COUNTER,1057) -- every=1, low=0, high=2, step=1, init=1 ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i = 1 THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i - 2; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i,2)); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg(REG,1058) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux(MUX,1059) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux: PROCESS (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem(DUALMEM,1056) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia <= z_uid49_fpSinPiTest_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 79, widthad_a => 2, numwords_a => 3, width_b => 79, widthad_b => 2, numwords_b => 3, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq, address_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa, data_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia ); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq(78 downto 0); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg(DELAY,1055) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q, xout => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --rVStage_uid146_lzcZ_uid51_fpSinPiTest(BITSELECT,145)@4 rVStage_uid146_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; rVStage_uid146_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_in(78 downto 15); --reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0(REG,365)@4 reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid147_lzcZ_uid51_fpSinPiTest(LOGICAL,146)@5 vCount_uid147_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid147_lzcZ_uid51_fpSinPiTest_a = vCount_uid147_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g(DELAY,629)@5 ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => vCount_uid147_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q, clk => clk, aclr => areset ); --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b(DELAY,587)@4 ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => vStage_uid149_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q, clk => clk, aclr => areset ); --mO_uid148_lzcZ_uid51_fpSinPiTest(CONSTANT,147) mO_uid148_lzcZ_uid51_fpSinPiTest_q <= "1111111111111111111111111111111111111111111111111"; --cStage_uid150_lzcZ_uid51_fpSinPiTest(BITJOIN,149)@5 cStage_uid150_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q & mO_uid148_lzcZ_uid51_fpSinPiTest_q; --ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c(DELAY,589)@4 ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 64, depth => 1 ) PORT MAP ( xin => rVStage_uid146_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid152_lzcZ_uid51_fpSinPiTest(MUX,151)@5 vStagei_uid152_lzcZ_uid51_fpSinPiTest_s <= vCount_uid147_lzcZ_uid51_fpSinPiTest_q; vStagei_uid152_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid152_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, cStage_uid150_lzcZ_uid51_fpSinPiTest_q) BEGIN CASE vStagei_uid152_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= cStage_uid150_lzcZ_uid51_fpSinPiTest_q; WHEN OTHERS => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid154_lzcZ_uid51_fpSinPiTest(BITSELECT,153)@5 rVStage_uid154_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q; rVStage_uid154_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_in(63 downto 32); --reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0(REG,366)@5 reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= "00000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid155_lzcZ_uid51_fpSinPiTest(LOGICAL,154)@6 vCount_uid155_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid155_lzcZ_uid51_fpSinPiTest_a = vCount_uid155_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f(DELAY,628)@6 ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid155_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q, clk => clk, aclr => areset ); --vStage_uid156_lzcZ_uid51_fpSinPiTest(BITSELECT,155)@5 vStage_uid156_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q(31 downto 0); vStage_uid156_lzcZ_uid51_fpSinPiTest_b <= vStage_uid156_lzcZ_uid51_fpSinPiTest_in(31 downto 0); --ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d(DELAY,596)@5 ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => vStage_uid156_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c(DELAY,595)@5 ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => rVStage_uid154_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid158_lzcZ_uid51_fpSinPiTest(MUX,157)@6 vStagei_uid158_lzcZ_uid51_fpSinPiTest_s <= vCount_uid155_lzcZ_uid51_fpSinPiTest_q; vStagei_uid158_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid158_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid158_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid160_lzcZ_uid51_fpSinPiTest(BITSELECT,159)@6 rVStage_uid160_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q; rVStage_uid160_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_in(31 downto 16); --reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0(REG,367)@6 reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid161_lzcZ_uid51_fpSinPiTest(LOGICAL,160)@7 vCount_uid161_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid161_lzcZ_uid51_fpSinPiTest_a = vCount_uid161_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e(DELAY,627)@7 ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid161_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q, clk => clk, aclr => areset ); --vStage_uid162_lzcZ_uid51_fpSinPiTest(BITSELECT,161)@6 vStage_uid162_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q(15 downto 0); vStage_uid162_lzcZ_uid51_fpSinPiTest_b <= vStage_uid162_lzcZ_uid51_fpSinPiTest_in(15 downto 0); --ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d(DELAY,602)@6 ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => vStage_uid162_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c(DELAY,601)@6 ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => rVStage_uid160_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid164_lzcZ_uid51_fpSinPiTest(MUX,163)@7 vStagei_uid164_lzcZ_uid51_fpSinPiTest_s <= vCount_uid161_lzcZ_uid51_fpSinPiTest_q; vStagei_uid164_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid164_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid164_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid166_lzcZ_uid51_fpSinPiTest(BITSELECT,165)@7 rVStage_uid166_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q; rVStage_uid166_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_in(15 downto 8); --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0(REG,368)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid167_lzcZ_uid51_fpSinPiTest(LOGICAL,166)@8 vCount_uid167_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid167_lzcZ_uid51_fpSinPiTest_a = vCount_uid167_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid168_lzcZ_uid51_fpSinPiTest(BITSELECT,167)@7 vStage_uid168_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q(7 downto 0); vStage_uid168_lzcZ_uid51_fpSinPiTest_b <= vStage_uid168_lzcZ_uid51_fpSinPiTest_in(7 downto 0); --reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3(REG,369)@7 reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= vStage_uid168_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2(REG,370)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vStagei_uid170_lzcZ_uid51_fpSinPiTest(MUX,169)@8 vStagei_uid170_lzcZ_uid51_fpSinPiTest_s <= vCount_uid167_lzcZ_uid51_fpSinPiTest_q; vStagei_uid170_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid170_lzcZ_uid51_fpSinPiTest_s, reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q, reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q) BEGIN CASE vStagei_uid170_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q; WHEN "1" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q; WHEN OTHERS => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid172_lzcZ_uid51_fpSinPiTest(BITSELECT,171)@8 rVStage_uid172_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q; rVStage_uid172_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_in(7 downto 4); --vCount_uid173_lzcZ_uid51_fpSinPiTest(LOGICAL,172)@8 vCount_uid173_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; vCount_uid173_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; vCount_uid173_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid173_lzcZ_uid51_fpSinPiTest_a = vCount_uid173_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid174_lzcZ_uid51_fpSinPiTest(BITSELECT,173)@8 vStage_uid174_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q(3 downto 0); vStage_uid174_lzcZ_uid51_fpSinPiTest_b <= vStage_uid174_lzcZ_uid51_fpSinPiTest_in(3 downto 0); --vStagei_uid176_lzcZ_uid51_fpSinPiTest(MUX,175)@8 vStagei_uid176_lzcZ_uid51_fpSinPiTest_s <= vCount_uid173_lzcZ_uid51_fpSinPiTest_q; vStagei_uid176_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid176_lzcZ_uid51_fpSinPiTest_s, rVStage_uid172_lzcZ_uid51_fpSinPiTest_b, vStage_uid174_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid176_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= vStage_uid174_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid178_lzcZ_uid51_fpSinPiTest(BITSELECT,177)@8 rVStage_uid178_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q; rVStage_uid178_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_in(3 downto 2); --vCount_uid179_lzcZ_uid51_fpSinPiTest(LOGICAL,178)@8 vCount_uid179_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; vCount_uid179_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; vCount_uid179_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid179_lzcZ_uid51_fpSinPiTest_a = vCount_uid179_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid180_lzcZ_uid51_fpSinPiTest(BITSELECT,179)@8 vStage_uid180_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q(1 downto 0); vStage_uid180_lzcZ_uid51_fpSinPiTest_b <= vStage_uid180_lzcZ_uid51_fpSinPiTest_in(1 downto 0); --vStagei_uid182_lzcZ_uid51_fpSinPiTest(MUX,181)@8 vStagei_uid182_lzcZ_uid51_fpSinPiTest_s <= vCount_uid179_lzcZ_uid51_fpSinPiTest_q; vStagei_uid182_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid182_lzcZ_uid51_fpSinPiTest_s, rVStage_uid178_lzcZ_uid51_fpSinPiTest_b, vStage_uid180_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid182_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= vStage_uid180_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid184_lzcZ_uid51_fpSinPiTest(BITSELECT,183)@8 rVStage_uid184_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid51_fpSinPiTest_q; rVStage_uid184_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_in(1 downto 1); --vCount_uid185_lzcZ_uid51_fpSinPiTest(LOGICAL,184)@8 vCount_uid185_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_b; vCount_uid185_lzcZ_uid51_fpSinPiTest_b <= GND_q; vCount_uid185_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid185_lzcZ_uid51_fpSinPiTest_a = vCount_uid185_lzcZ_uid51_fpSinPiTest_b else "0"; --r_uid186_lzcZ_uid51_fpSinPiTest(BITJOIN,185)@8 r_uid186_lzcZ_uid51_fpSinPiTest_q <= ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q & ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q & ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q & vCount_uid167_lzcZ_uid51_fpSinPiTest_q & vCount_uid173_lzcZ_uid51_fpSinPiTest_q & vCount_uid179_lzcZ_uid51_fpSinPiTest_q & vCount_uid185_lzcZ_uid51_fpSinPiTest_q; --leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest(BITSELECT,195)@8 leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q; leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in(6 downto 5); --reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1(REG,371)@8 reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest(MUX,196)@9 leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q, leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q; WHEN "01" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ozz_uid41_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest(BITSELECT,206)@8 leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(4 downto 0); leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in(4 downto 3); --reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1(REG,372)@8 reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest(MUX,207)@9 leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s, leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest(BITSELECT,215)@9 LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(72 downto 0); LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in(72 downto 0); --leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest(BITJOIN,216)@9 leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5(REG,374)@9 reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest(BITSELECT,212)@9 LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest(BITJOIN,213)@9 leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4(REG,375)@9 reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest(BITSELECT,209)@9 LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest(BITJOIN,210)@9 leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3(REG,376)@9 reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2(REG,377)@9 reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest(BITSELECT,217)@8 leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(2 downto 0); leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in(2 downto 1); --reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1(REG,373)@8 reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b(DELAY,657)@9 ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest(MUX,218)@10 leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s, reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q, reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q, reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q, reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q) BEGIN CASE leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q; WHEN "01" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q; WHEN "10" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q; WHEN "11" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q; WHEN OTHERS => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest(BITSELECT,222)@8 leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(0 downto 0); leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in(0 downto 0); --reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1(REG,378)@8 reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b(DELAY,665)@9 ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest(MUX,223)@10 leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s, leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q, leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q; WHEN "1" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --alignedZLow_uid53_fpSinPiTest(BITSELECT,52)@10 alignedZLow_uid53_fpSinPiTest_in <= leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q; alignedZLow_uid53_fpSinPiTest_b <= alignedZLow_uid53_fpSinPiTest_in(78 downto 27); --pHardCase_uid54_fpSinPiTest(BITJOIN,53)@10 pHardCase_uid54_fpSinPiTest_q <= alignedZLow_uid53_fpSinPiTest_b & GND_q; --ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b(DELAY,474)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 10 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q, clk => clk, aclr => areset ); --p_uid55_fpSinPiTest(MUX,54)@10 p_uid55_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q; p_uid55_fpSinPiTest: PROCESS (p_uid55_fpSinPiTest_s, pHardCase_uid54_fpSinPiTest_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q) BEGIN CASE p_uid55_fpSinPiTest_s IS WHEN "0" => p_uid55_fpSinPiTest_q <= pHardCase_uid54_fpSinPiTest_q; WHEN "1" => p_uid55_fpSinPiTest_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q; WHEN OTHERS => p_uid55_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt(COUNTER,1121) -- every=1, low=0, high=22, step=1, init=1 ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i = 21 THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i - 22; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i,5)); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg(REG,1122) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux(MUX,1123) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux: PROCESS (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q) BEGIN CASE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s IS WHEN "0" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; WHEN "1" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem(DUALMEM,1120) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 <= areset; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia <= p_uid55_fpSinPiTest_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 5, numwords_a => 23, width_b => 53, widthad_b => 5, numwords_b => 23, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq, address_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa, data_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia ); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq(52 downto 0); --mul2xSinRes_uid69_fpSinPiTest_a_1(BITSELECT,316)@34 mul2xSinRes_uid69_fpSinPiTest_a_1_in <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q); mul2xSinRes_uid69_fpSinPiTest_a_1_b <= mul2xSinRes_uid69_fpSinPiTest_a_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0(REG,424)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b1(MULT,322)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_b); mul2xSinRes_uid69_fpSinPiTest_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1(BITSELECT,329)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1(REG,425)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a_0(BITSELECT,315)@34 mul2xSinRes_uid69_fpSinPiTest_a_0_in <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_a_0_b <= mul2xSinRes_uid69_fpSinPiTest_a_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0(REG,426)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b1(MULT,321)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_b); mul2xSinRes_uid69_fpSinPiTest_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1(BITSELECT,327)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_zero_36(CONSTANT,332) mul2xSinRes_uid69_fpSinPiTest_zero_36_q <= "000000000000000000000000000"; --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2(BITJOIN,336)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1(BITSELECT,328)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_b_0(BITSELECT,317)@34 mul2xSinRes_uid69_fpSinPiTest_b_0_in <= multRightOp_uid68_fpSinPiTest_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_b_0_b <= mul2xSinRes_uid69_fpSinPiTest_b_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1(REG,421)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0(REG,422)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b0(MULT,320)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_b); mul2xSinRes_uid69_fpSinPiTest_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0(BITSELECT,325)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1(BITJOIN,335)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC(LOGICAL,340)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b; --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1(BITSELECT,330)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0(BITSELECT,326)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1(REG,419)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0(REG,420)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b0(MULT,319)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_b); mul2xSinRes_uid69_fpSinPiTest_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0(BITSELECT,324)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0(BITSELECT,323)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0(BITJOIN,334)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC(LOGICAL,339)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB(LOGICAL,338)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne(LOGICAL,341)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c; --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS(BITSELECT,342)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q(106 downto 0); mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in(106 downto 0); --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ(BITJOIN,343)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b & GND_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b(BITJOIN,350)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b(BITSELECT,353)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne(LOGICAL,337)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a(BITJOIN,348)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a(BITSELECT,352)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2(ADD,354)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin <= GND_q; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b) & mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c(0) <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(90); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(89 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b(DELAY,822)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q, clk => clk, aclr => areset ); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a(DELAY,821)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2(ADD,355)@39 mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q) & mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o(20 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a(DELAY,824)@39 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a : dspba_delay GENERIC MAP ( width => 89, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q(BITJOIN,356)@40 mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q; --normBit_uid70_fpSinPiTest(BITSELECT,69)@40 normBit_uid70_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(106 downto 0); normBit_uid70_fpSinPiTest_b <= normBit_uid70_fpSinPiTest_in(106 downto 106); --ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c(DELAY,497)@40 ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => normBit_uid70_fpSinPiTest_b, xout => ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q, clk => clk, aclr => areset ); --rndExpUpdate_uid75_uid76_fpSinPiTest(BITJOIN,75)@41 rndExpUpdate_uid75_uid76_fpSinPiTest_q <= ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q & cstAllZWF_uid10_fpSinPiTest_q & VCC_q; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor(LOGICAL,976) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q <= not (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a or ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top(CONSTANT,972) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q <= "011100"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp(LOGICAL,973) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a = ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b else "0"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg(REG,974) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena(REG,977) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q = "1") THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd(LOGICAL,978) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a and ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem(DUALMEM,941) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 <= areset; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia <= expX_uid6_fpSinPiTest_b; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 3, numwords_a => 7, width_b => 11, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq, address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa, data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia ); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq(10 downto 0); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg(DELAY,940) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q, clk => clk, aclr => areset ); --expXP1_uid58_fpSinPiTest(ADD,57)@9 expXP1_uid58_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q); expXP1_uid58_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & VCC_q); expXP1_uid58_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid58_fpSinPiTest_a) + UNSIGNED(expXP1_uid58_fpSinPiTest_b)); expXP1_uid58_fpSinPiTest_q <= expXP1_uid58_fpSinPiTest_o(11 downto 0); --expXP1R_uid59_fpSinPiTest(BITSELECT,58)@9 expXP1R_uid59_fpSinPiTest_in <= expXP1_uid58_fpSinPiTest_q(10 downto 0); expXP1R_uid59_fpSinPiTest_b <= expXP1R_uid59_fpSinPiTest_in(10 downto 0); --reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1(REG,427)@8 reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= r_uid186_lzcZ_uid51_fpSinPiTest_q; END IF; END PROCESS; --expHardCase_uid57_fpSinPiTest(SUB,56)@9 expHardCase_uid57_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid27_fpSinPiTest_q); expHardCase_uid57_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000" & reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q); expHardCase_uid57_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid57_fpSinPiTest_a) - UNSIGNED(expHardCase_uid57_fpSinPiTest_b)); expHardCase_uid57_fpSinPiTest_q <= expHardCase_uid57_fpSinPiTest_o(11 downto 0); --expHardCaseR_uid60_fpSinPiTest(BITSELECT,59)@9 expHardCaseR_uid60_fpSinPiTest_in <= expHardCase_uid57_fpSinPiTest_q(10 downto 0); expHardCaseR_uid60_fpSinPiTest_b <= expHardCaseR_uid60_fpSinPiTest_in(10 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b(DELAY,481)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 9 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q, clk => clk, aclr => areset ); --expP_uid61_fpSinPiTest(MUX,60)@9 expP_uid61_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q; expP_uid61_fpSinPiTest: PROCESS (expP_uid61_fpSinPiTest_s, expHardCaseR_uid60_fpSinPiTest_b, expXP1R_uid59_fpSinPiTest_b) BEGIN CASE expP_uid61_fpSinPiTest_s IS WHEN "0" => expP_uid61_fpSinPiTest_q <= expHardCaseR_uid60_fpSinPiTest_b; WHEN "1" => expP_uid61_fpSinPiTest_q <= expXP1R_uid59_fpSinPiTest_b; WHEN OTHERS => expP_uid61_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt(COUNTER,968) -- every=1, low=0, high=28, step=1, init=1 ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i = 27 THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i - 28; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg(REG,969) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux(MUX,970) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem(DUALMEM,967) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia <= expP_uid61_fpSinPiTest_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 29, width_b => 11, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq, address_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa, data_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia ); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq(10 downto 0); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg(DELAY,966) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q, xout => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --highRes_uid71_fpSinPiTest(BITSELECT,70)@40 highRes_uid71_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(105 downto 0); highRes_uid71_fpSinPiTest_b <= highRes_uid71_fpSinPiTest_in(105 downto 53); --lowRes_uid72_fpSinPiTest(BITSELECT,71)@40 lowRes_uid72_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(104 downto 0); lowRes_uid72_fpSinPiTest_b <= lowRes_uid72_fpSinPiTest_in(104 downto 52); --fracRCompPreRnd_uid73_fpSinPiTest(MUX,72)@40 fracRCompPreRnd_uid73_fpSinPiTest_s <= normBit_uid70_fpSinPiTest_b; fracRCompPreRnd_uid73_fpSinPiTest: PROCESS (fracRCompPreRnd_uid73_fpSinPiTest_s, lowRes_uid72_fpSinPiTest_b, highRes_uid71_fpSinPiTest_b) BEGIN CASE fracRCompPreRnd_uid73_fpSinPiTest_s IS WHEN "0" => fracRCompPreRnd_uid73_fpSinPiTest_q <= lowRes_uid72_fpSinPiTest_b; WHEN "1" => fracRCompPreRnd_uid73_fpSinPiTest_q <= highRes_uid71_fpSinPiTest_b; WHEN OTHERS => fracRCompPreRnd_uid73_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracPreRnd_uid74_uid74_fpSinPiTest(BITJOIN,73)@40 expFracPreRnd_uid74_uid74_fpSinPiTest_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q & fracRCompPreRnd_uid73_fpSinPiTest_q; --reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0(REG,428)@40 reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= expFracPreRnd_uid74_uid74_fpSinPiTest_q; END IF; END PROCESS; --expFracComp_uid77_fpSinPiTest(ADD,76)@41 expFracComp_uid77_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q); expFracComp_uid77_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & rndExpUpdate_uid75_uid76_fpSinPiTest_q); expFracComp_uid77_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid77_fpSinPiTest_a) + UNSIGNED(expFracComp_uid77_fpSinPiTest_b)); expFracComp_uid77_fpSinPiTest_q <= expFracComp_uid77_fpSinPiTest_o(64 downto 0); --expRComp_uid79_fpSinPiTest(BITSELECT,78)@41 expRComp_uid79_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(63 downto 0); expRComp_uid79_fpSinPiTest_b <= expRComp_uid79_fpSinPiTest_in(63 downto 53); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor(LOGICAL,1015) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q <= not (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a or ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top(CONSTANT,1011) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q <= "0100010"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp(LOGICAL,1012) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q <= "1" when ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a = ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b else "0"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg(REG,1013) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena(REG,1016) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q = "1") THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd(LOGICAL,1017) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a and ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b; --reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1(REG,429)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c(DELAY,516)@0 ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q, xout => ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b(DELAY,515)@0 ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => expXIsZero_uid15_fpSinPiTest_q, xout => ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q, clk => clk, aclr => areset ); --reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0(REG,361)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --excRZero_uid87_fpSinPiTest(LOGICAL,86)@3 excRZero_uid87_fpSinPiTest_a <= reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q; excRZero_uid87_fpSinPiTest_b <= ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q; excRZero_uid87_fpSinPiTest_c <= ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q; excRZero_uid87_fpSinPiTest_q <= excRZero_uid87_fpSinPiTest_a or excRZero_uid87_fpSinPiTest_b or excRZero_uid87_fpSinPiTest_c; --Or2ExcRZeroXIsInt_uid92_fpSinPiTest(LOGICAL,91)@3 Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a <= excRZero_uid87_fpSinPiTest_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b <= reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a or Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt(COUNTER,1007) -- every=1, low=0, high=34, step=1, init=1 ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i = 33 THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i - 34; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg(REG,1008) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux(MUX,1009) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux: PROCESS (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem(DUALMEM,1006) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 35, width_b => 1, widthad_b => 6, numwords_b => 35, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq, address_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa, data_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia ); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg(DELAY,1005) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q, xout => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --expRPostExc1_uid95_fpSinPiTest(MUX,94)@41 expRPostExc1_uid95_fpSinPiTest_s <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q; expRPostExc1_uid95_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE expRPostExc1_uid95_fpSinPiTest_s IS WHEN "0" => expRPostExc1_uid95_fpSinPiTest_q <= expRComp_uid79_fpSinPiTest_b; WHEN "1" => expRPostExc1_uid95_fpSinPiTest_q <= cstAllZWE_uid11_fpSinPiTest_q; WHEN OTHERS => expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --InvXIntExp_uid84_fpSinPiTest(LOGICAL,83)@2 InvXIntExp_uid84_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; InvXIntExp_uid84_fpSinPiTest_q <= not InvXIntExp_uid84_fpSinPiTest_a; --join_uid42_fpSinPiTest(BITJOIN,41)@2 join_uid42_fpSinPiTest_q <= VCC_q & ozz_uid41_fpSinPiTest_q; --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0(REG,359)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid43_fpSinPiTest(LOGICAL,42)@2 yIsZero_uid43_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q; yIsZero_uid43_fpSinPiTest_b <= join_uid42_fpSinPiTest_q; yIsZero_uid43_fpSinPiTest_q <= "1" when yIsZero_uid43_fpSinPiTest_a = yIsZero_uid43_fpSinPiTest_b else "0"; --And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest(LOGICAL,85)@2 And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b <= yIsZero_uid43_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c <= InvSinXIsX_uid80_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d <= InvXIntExp_uid84_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d; --Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest(LOGICAL,95)@1 Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a <= GND_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q <= Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a or Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b; --ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a(DELAY,528)@1 ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q, xout => ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q, clk => clk, aclr => areset ); --join_uid97_fpSinPiTest(BITJOIN,96)@2 join_uid97_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q & ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q; --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg(DELAY,1195) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => join_uid97_fpSinPiTest_q, xout => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q, clk => clk, aclr => areset ); --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem(DUALMEM,1196) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 <= areset; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 6, numwords_a => 37, width_b => 2, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0, clock1 => clk, address_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq, address_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa, data_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia ); ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq(1 downto 0); --reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1(REG,430)@41 reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q; END IF; END PROCESS; --expRPostExc_uid98_fpSinPiTest(MUX,97)@42 expRPostExc_uid98_fpSinPiTest_s <= reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q; expRPostExc_uid98_fpSinPiTest: PROCESS (expRPostExc_uid98_fpSinPiTest_s, expRPostExc1_uid95_fpSinPiTest_q) BEGIN CASE expRPostExc_uid98_fpSinPiTest_s IS WHEN "00" => expRPostExc_uid98_fpSinPiTest_q <= expRPostExc1_uid95_fpSinPiTest_q; WHEN "01" => expRPostExc_uid98_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q; WHEN "10" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN "11" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN OTHERS => expRPostExc_uid98_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --oneFracRPostExc2_uid90_fpSinPiTest(CONSTANT,89) oneFracRPostExc2_uid90_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracRComp_uid78_fpSinPiTest(BITSELECT,77)@41 fracRComp_uid78_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(52 downto 0); fracRComp_uid78_fpSinPiTest_b <= fracRComp_uid78_fpSinPiTest_in(52 downto 1); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor(LOGICAL,989) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q <= not (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a or ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top(CONSTANT,985) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q <= "0100001"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp(LOGICAL,986) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q <= "1" when ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a = ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b else "0"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg(REG,987) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena(REG,990) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q = "1") THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd(LOGICAL,991) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a and ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b; --reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1(REG,362)@3 reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= excRZero_uid87_fpSinPiTest_q; END IF; END PROCESS; --ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a(DELAY,517)@2 ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q, xout => ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q, clk => clk, aclr => areset ); --or_uid88_fpSinPiTest(LOGICAL,87)@4 or_uid88_fpSinPiTest_a <= ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q; or_uid88_fpSinPiTest_b <= reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q; or_uid88_fpSinPiTest_c <= GND_q; or_uid88_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN or_uid88_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN or_uid88_fpSinPiTest_q <= or_uid88_fpSinPiTest_a or or_uid88_fpSinPiTest_b or or_uid88_fpSinPiTest_c; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt(COUNTER,981) -- every=1, low=0, high=33, step=1, init=1 ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i = 32 THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i - 33; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg(REG,982) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux(MUX,983) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux: PROCESS (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem(DUALMEM,980) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia <= or_uid88_fpSinPiTest_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 34, width_b => 1, widthad_b => 6, numwords_b => 34, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq, address_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa, data_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia ); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg(DELAY,979) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q, xout => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --fracRPostExc1_uid89_fpSinPiTest(MUX,88)@41 fracRPostExc1_uid89_fpSinPiTest_s <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q; fracRPostExc1_uid89_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE fracRPostExc1_uid89_fpSinPiTest_s IS WHEN "0" => fracRPostExc1_uid89_fpSinPiTest_q <= fracRComp_uid78_fpSinPiTest_b; WHEN "1" => fracRPostExc1_uid89_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q; WHEN OTHERS => fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor(LOGICAL,1002) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q <= not (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a or ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top(CONSTANT,998) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q <= "0100110"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp(LOGICAL,999) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q <= "1" when ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a = ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b else "0"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg(REG,1000) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena(REG,1003) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q = "1") THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd(LOGICAL,1004) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a and ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg(DELAY,992) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q, xout => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q, clk => clk, aclr => areset ); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt(COUNTER,994) -- every=1, low=0, high=38, step=1, init=1 ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i = 37 THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i - 38; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg(REG,995) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux(MUX,996) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux: PROCESS (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem(DUALMEM,993) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 39, width_b => 1, widthad_b => 6, numwords_b => 39, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq, address_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa, data_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia ); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq(0 downto 0); --fracRPostExc_uid91_fpSinPiTest(MUX,90)@42 fracRPostExc_uid91_fpSinPiTest_s <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q; fracRPostExc_uid91_fpSinPiTest: PROCESS (fracRPostExc_uid91_fpSinPiTest_s, fracRPostExc1_uid89_fpSinPiTest_q) BEGIN CASE fracRPostExc_uid91_fpSinPiTest_s IS WHEN "0" => fracRPostExc_uid91_fpSinPiTest_q <= fracRPostExc1_uid89_fpSinPiTest_q; WHEN "1" => fracRPostExc_uid91_fpSinPiTest_q <= oneFracRPostExc2_uid90_fpSinPiTest_q; WHEN OTHERS => fracRPostExc_uid91_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid105_fpSinPiTest(BITJOIN,104)@42 R_uid105_fpSinPiTest_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q & expRPostExc_uid98_fpSinPiTest_q & fracRPostExc_uid91_fpSinPiTest_q; --ld_xIn_v_to_xOut_v_nor(LOGICAL,910) ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b); --ld_xIn_v_to_xOut_v_mem_top(CONSTANT,906) ld_xIn_v_to_xOut_v_mem_top_q <= "0100111"; --ld_xIn_v_to_xOut_v_cmp(LOGICAL,907) ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q; ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q); ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0"; --ld_xIn_v_to_xOut_v_cmpReg(REG,908) ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_sticky_ena(REG,911) ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q; END IF; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,912) ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q; ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b; --ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,902) -- every=1, low=0, high=39, step=1, init=1 ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 38 THEN ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1'; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; END IF; IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 39; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,6)); --ld_xIn_v_to_xOut_v_replace_rdreg(REG,903) ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_replace_rdmux(MUX,904) ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q; ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q) BEGIN CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q; WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,914) ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset; ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c; ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 6, numwords_a => 40, width_b => 8, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_c_to_xOut_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_c_to_xOut_c_replace_mem_iq, address_a => ld_xIn_c_to_xOut_c_replace_mem_aa, data_a => ld_xIn_c_to_xOut_c_replace_mem_ia ); ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0); --ld_xIn_c_to_xOut_c_outputreg(DELAY,913) ld_xIn_c_to_xOut_c_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset ); --ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,901) ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset; ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v; ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 40, width_b => 1, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_v_to_xOut_v_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_v_to_xOut_v_replace_mem_iq, address_a => ld_xIn_v_to_xOut_v_replace_mem_aa, data_a => ld_xIn_v_to_xOut_v_replace_mem_ia ); ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0); --ld_xIn_v_to_xOut_v_outputreg(DELAY,900) ld_xIn_v_to_xOut_v_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset ); --xOut(PORTOUT,4)@42 xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q; xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q; xOut_0 <= R_uid105_fpSinPiTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Debug Version 12.0 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from SinPiDPStratixVf400 -- VHDL created on Wed Sep 05 17:55:57 2012 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; USE work.SinPiDPStratixVf400_safe_path.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; -- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240 entity SinPiDPStratixVf400 is port ( xIn_v : in std_logic_vector(0 downto 0); xIn_c : in std_logic_vector(7 downto 0); xIn_0 : in std_logic_vector(63 downto 0); xOut_v : out std_logic_vector(0 downto 0); xOut_c : out std_logic_vector(7 downto 0); xOut_0 : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic; bus_clk : in std_logic; h_areset : in std_logic ); end; architecture normal of SinPiDPStratixVf400 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBias_uid12_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBiasPwF_uid13_fpSinPiTest_q : std_logic_vector (10 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0); signal biasM1_uid27_fpSinPiTest_q : std_logic_vector (10 downto 0); signal biasMwShift_uid29_fpSinPiTest_q : std_logic_vector (10 downto 0); signal shiftBias_uid32_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cst01pWShift_uid34_fpSinPiTest_q : std_logic_vector (27 downto 0); signal ozz_uid41_fpSinPiTest_q : std_logic_vector (78 downto 0); signal cOne_uid44_fpSinPiTest_q : std_logic_vector (80 downto 0); signal oneMinusY_uid45_fpSinPiTest_a : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_b : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_o : std_logic_vector (81 downto 0); signal oneMinusY_uid45_fpSinPiTest_q : std_logic_vector (81 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_a : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_b : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_o : std_logic_vector (84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_c : std_logic_vector (0 downto 0); signal piwFP2_uid67_fpSinPiTest_q : std_logic_vector (53 downto 0); signal or_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_b : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_c : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_q : std_logic_vector (51 downto 0); signal oneFracRPostExc2_uid90_fpSinPiTest_q : std_logic_vector (51 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (10 downto 0); signal InvXIsInt_uid100_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIsInt_uid100_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (31 downto 0); signal leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (63 downto 0); signal leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (15 downto 0); signal leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (23 downto 0); signal leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (5 downto 0); signal mO_uid148_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (48 downto 0); signal memoryC3_uid229_sinPiZTableGenerator_q : std_logic_vector(34 downto 0); signal memoryC4_uid230_sinPiZTableGenerator_q : std_logic_vector(25 downto 0); signal memoryC5_uid231_sinPiZTableGenerator_q : std_logic_vector(16 downto 0); signal rndBit_uid246_sinPiZPolyEval_q : std_logic_vector (1 downto 0); signal rndBit_uid258_sinPiZPolyEval_q : std_logic_vector (2 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_a : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 : std_logic_vector (33 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr : SIGNED (34 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_q : std_logic_vector (33 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_a : std_logic_vector (25 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_zero_36_q : std_logic_vector (26 downto 0); type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type; signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q : std_logic_vector (36 downto 0); type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o : std_logic_vector (90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o : std_logic_vector (21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q : std_logic_vector (19 downto 0); signal reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q : std_logic_vector (80 downto 0); signal reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q : std_logic_vector (80 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q : std_logic_vector (0 downto 0); signal reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (31 downto 0); signal reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (15 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (7 downto 0); signal reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q : std_logic_vector (7 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q : std_logic_vector (7 downto 0); signal reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q : std_logic_vector (78 downto 0); signal reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q : std_logic_vector (16 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q : std_logic_vector (25 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q : std_logic_vector (16 downto 0); signal reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q : std_logic_vector (17 downto 0); signal reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q : std_logic_vector (36 downto 0); signal reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q : std_logic_vector (44 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q : std_logic_vector (45 downto 0); signal reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q : std_logic_vector (51 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q : std_logic_vector (53 downto 0); signal reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q : std_logic_vector (60 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q : std_logic_vector (26 downto 0); signal reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q : std_logic_vector (6 downto 0); signal reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q : std_logic_vector (78 downto 0); signal ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q : std_logic_vector (78 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q : std_logic_vector (78 downto 0); signal ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q : std_logic_vector (14 downto 0); signal ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (63 downto 0); signal ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (31 downto 0); signal ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (31 downto 0); signal ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (15 downto 0); signal ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (15 downto 0); signal ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q : std_logic_vector (0 downto 0); signal ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q : std_logic_vector (0 downto 0); signal ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (1 downto 0); signal ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (42 downto 0); signal ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q : std_logic_vector (88 downto 0); signal ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q : std_logic_vector (79 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic; signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic; signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic; signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 : std_logic; signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i : unsigned(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q : std_logic_vector (3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i : unsigned(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q : std_logic_vector (6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i : unsigned(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q : std_logic_vector (2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (14 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ir : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i : unsigned(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q : std_logic_vector (2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ir : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ir : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 : std_logic; signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ir : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0); signal yIsZero_uid40_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (18 downto 0); signal pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal z_uid49_fpSinPiTest_s : std_logic_vector (0 downto 0); signal z_uid49_fpSinPiTest_q : std_logic_vector (78 downto 0); signal expHardCase_uid57_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expHardCase_uid57_fpSinPiTest_q : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_q : std_logic_vector (11 downto 0); signal rndExpUpdate_uid75_uid76_fpSinPiTest_q : std_logic_vector (53 downto 0); signal expFracComp_uid77_fpSinPiTest_a : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_b : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_o : std_logic_vector (64 downto 0); signal expFracComp_uid77_fpSinPiTest_q : std_logic_vector (64 downto 0); signal fracRPostExc_uid91_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc_uid91_fpSinPiTest_q : std_logic_vector (51 downto 0); signal expRPostExc_uid98_fpSinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid98_fpSinPiTest_q : std_logic_vector (10 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal memoryC0_uid226_sinPiZTableGenerator_q : std_logic_vector(57 downto 0); signal memoryC1_uid227_sinPiZTableGenerator_q : std_logic_vector(49 downto 0); signal memoryC2_uid228_sinPiZTableGenerator_q : std_logic_vector(42 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_a : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_b : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_o : std_logic_vector (35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_q : std_logic_vector (35 downto 0); signal ts3_uid248_sinPiZPolyEval_a : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_b : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_o : std_logic_vector (45 downto 0); signal ts3_uid248_sinPiZPolyEval_q : std_logic_vector (45 downto 0); signal ts4_uid254_sinPiZPolyEval_a : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_b : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_o : std_logic_vector (52 downto 0); signal ts4_uid254_sinPiZPolyEval_q : std_logic_vector (52 downto 0); signal ts5_uid260_sinPiZPolyEval_a : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_b : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_o : std_logic_vector (61 downto 0); signal ts5_uid260_sinPiZPolyEval_q : std_logic_vector (61 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal join_uid42_fpSinPiTest_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal expX_uid6_fpSinPiTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSinPiTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSinPiTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSinPiTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0); signal expXIsMax_uid16_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSinPiTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid15_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_q : std_logic_vector(0 downto 0); signal xIntExp_uid26_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xIntExp_uid26_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xIntExp_uid26_fpSinPiTest_c : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xFrac_uid28_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_n : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_a : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_b : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_o : std_logic_vector (13 downto 0); signal sinXIsX_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0); signal shiftValue_uid33_fpSinPiTest_a : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_b : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_o : std_logic_vector (11 downto 0); signal shiftValue_uid33_fpSinPiTest_q : std_logic_vector (11 downto 0); signal oMyBottom_uid47_fpSinPiTest_in : std_logic_vector (78 downto 0); signal oMyBottom_uid47_fpSinPiTest_b : std_logic_vector (78 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid150_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal cIncludingRoundingBit_uid247_sinPiZPolyEval_q : std_logic_vector (44 downto 0); signal cIncludingRoundingBit_uid253_sinPiZPolyEval_q : std_logic_vector (51 downto 0); signal cIncludingRoundingBit_uid259_sinPiZPolyEval_q : std_logic_vector (60 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q : std_logic_vector (107 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (29 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (46 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q : std_logic_vector (108 downto 0); signal yIsZero_uid43_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zPPolyEval_uid64_fpSinPiTest_in : std_logic_vector (71 downto 0); signal zPPolyEval_uid64_fpSinPiTest_b : std_logic_vector (44 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_q : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_c : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (31 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (15 downto 0); signal s2_uid240_uid243_sinPiZPolyEval_q : std_logic_vector (36 downto 0); signal add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (55 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (42 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (72 downto 0); signal add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal R_uid105_fpSinPiTest_q : std_logic_vector (63 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal yT3_uid244_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT3_uid244_sinPiZPolyEval_b : std_logic_vector (34 downto 0); signal yT4_uid250_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT4_uid250_sinPiZPolyEval_b : std_logic_vector (42 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q : std_logic_vector(0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_b : std_logic_vector (26 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zAddr_uid63_fpSinPiTest_in : std_logic_vector (78 downto 0); signal zAddr_uid63_fpSinPiTest_b : std_logic_vector (6 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (78 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (63 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (14 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (14 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (46 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (46 downto 0); signal expHardCaseR_uid60_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expHardCaseR_uid60_fpSinPiTest_b : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracRComp_uid78_fpSinPiTest_in : std_logic_vector (52 downto 0); signal fracRComp_uid78_fpSinPiTest_b : std_logic_vector (51 downto 0); signal expRComp_uid79_fpSinPiTest_in : std_logic_vector (63 downto 0); signal expRComp_uid79_fpSinPiTest_b : std_logic_vector (10 downto 0); signal intXParity_uid38_fpSinPiTest_in : std_logic_vector (80 downto 0); signal intXParity_uid38_fpSinPiTest_b : std_logic_vector (0 downto 0); signal y_uid39_fpSinPiTest_in : std_logic_vector (79 downto 0); signal y_uid39_fpSinPiTest_b : std_logic_vector (79 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (77 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (77 downto 0); signal s3_uid249_sinPiZPolyEval_in : std_logic_vector (45 downto 0); signal s3_uid249_sinPiZPolyEval_b : std_logic_vector (44 downto 0); signal s4_uid255_sinPiZPolyEval_in : std_logic_vector (52 downto 0); signal s4_uid255_sinPiZPolyEval_b : std_logic_vector (51 downto 0); signal s5_uid261_sinPiZPolyEval_in : std_logic_vector (61 downto 0); signal s5_uid261_sinPiZPolyEval_b : std_logic_vector (60 downto 0); signal oFracX_uid31_uid31_fpSinPiTest_q : std_logic_vector (52 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_in : std_logic_vector (6 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_b : std_logic_vector (6 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid235_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal highBBits_uid235_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid241_sinPiZPolyEval_in : std_logic_vector (28 downto 0); signal highBBits_uid241_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q : std_logic_vector(107 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (29 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (46 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal normBit_uid70_fpSinPiTest_in : std_logic_vector (106 downto 0); signal normBit_uid70_fpSinPiTest_b : std_logic_vector (0 downto 0); signal highRes_uid71_fpSinPiTest_in : std_logic_vector (105 downto 0); signal highRes_uid71_fpSinPiTest_b : std_logic_vector (52 downto 0); signal lowRes_uid72_fpSinPiTest_in : std_logic_vector (104 downto 0); signal lowRes_uid72_fpSinPiTest_b : std_logic_vector (52 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (70 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (70 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (62 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (62 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (54 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (54 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q : std_logic_vector(0 downto 0); signal yT1_uid232_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT1_uid232_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal yT2_uid238_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT2_uid238_sinPiZPolyEval_b : std_logic_vector (25 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (63 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (9 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (9 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (36 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (71 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (45 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (78 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (7 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (7 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (15 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (15 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expP_uid61_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expP_uid61_fpSinPiTest_q : std_logic_vector (10 downto 0); signal yBottom_uid48_fpSinPiTest_in : std_logic_vector (78 downto 0); signal yBottom_uid48_fpSinPiTest_b : std_logic_vector (78 downto 0); signal leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (51 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal fxpSinRes_uid66_fpSinPiTest_in : std_logic_vector (58 downto 0); signal fxpSinRes_uid66_fpSinPiTest_b : std_logic_vector (53 downto 0); signal extendedFracX_uid35_fpSinPiTest_q : std_logic_vector (80 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (0 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_a : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_b : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_o : std_logic_vector (26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q : std_logic_vector(107 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_q : std_logic_vector (52 downto 0); signal join_uid97_fpSinPiTest_q : std_logic_vector (1 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal signR_uid104_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (10 downto 0); signal pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (16 downto 0); signal pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal xIsInt_uid83_fpSinPiTest_a : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_b : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal multRightOp_uid68_fpSinPiTest_s : std_logic_vector (0 downto 0); signal multRightOp_uid68_fpSinPiTest_q : std_logic_vector (53 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (48 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (48 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (16 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (16 downto 0); signal s1_uid234_uid237_sinPiZPolyEval_q : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c : std_logic_vector (19 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in : std_logic_vector (106 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b : std_logic_vector (106 downto 0); signal expFracPreRnd_uid74_uid74_fpSinPiTest_q : std_logic_vector (63 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (17 downto 0); signal alignedZLow_uid53_fpSinPiTest_in : std_logic_vector (78 downto 0); signal alignedZLow_uid53_fpSinPiTest_b : std_logic_vector (51 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_b : std_logic_vector (26 downto 0); signal leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q : std_logic_vector (107 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (1 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (74 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (72 downto 0); signal pHardCase_uid54_fpSinPiTest_q : std_logic_vector (52 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q : std_logic_vector (108 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (0 downto 0); signal leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal p_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0); signal p_uid55_fpSinPiTest_q : std_logic_vector (52 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (72 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (64 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (64 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (56 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (56 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c : std_logic_vector (19 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal r_uid186_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (6 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (0 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (78 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (78 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (74 downto 0); signal leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (79 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (79 downto 0); signal leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); begin --ld_xIn_v_to_xOut_v_notEnable(LOGICAL,909) ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q; ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor(LOGICAL,1028) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q <= not (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a or ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top(CONSTANT,1024) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q <= "0100100"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp(LOGICAL,1025) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q <= "1" when ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a = ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b else "0"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg(REG,1026) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena(REG,1029) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q = "1") THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd(LOGICAL,1030) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a and ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b; --LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest(BITSELECT,134)@0 LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest(CONSTANT,133) leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q <= "000000"; --leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest(BITJOIN,135)@0 leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest(BITSELECT,131)@0 LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest(CONSTANT,130) leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q <= "0000"; --leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest(BITJOIN,132)@0 leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest(BITSELECT,128)@0 LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(78 downto 0); LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in(78 downto 0); --leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest(CONSTANT,127) leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q <= "00"; --leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest(BITJOIN,129)@0 leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest(BITSELECT,123)@0 LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(56 downto 0); LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in(56 downto 0); --leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest(CONSTANT,122) leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000"; --leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest(BITJOIN,124)@0 leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest(BITSELECT,120)@0 LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(64 downto 0); LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in(64 downto 0); --leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest(CONSTANT,119) leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000"; --leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest(BITJOIN,121)@0 leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest(BITSELECT,117)@0 LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(72 downto 0); LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in(72 downto 0); --leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest(CONSTANT,116) leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q <= "00000000"; --leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest(BITJOIN,118)@0 leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest(CONSTANT,113) leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; --X16dto0_uid112_fixedPointX_uid37_fpSinPiTest(BITSELECT,111)@0 X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(16 downto 0); X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in(16 downto 0); --leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest(CONSTANT,110) leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000"; --leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest(BITJOIN,112)@0 leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X48dto0_uid109_fixedPointX_uid37_fpSinPiTest(BITSELECT,108)@0 X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(48 downto 0); X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in(48 downto 0); --leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest(CONSTANT,107) leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q <= "00000000000000000000000000000000"; --leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest(BITJOIN,109)@0 leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --cst01pWShift_uid34_fpSinPiTest(CONSTANT,33) cst01pWShift_uid34_fpSinPiTest_q <= "0000000000000000000000000000"; --xIn(PORTIN,3)@0 --fracX_uid7_fpSinPiTest(BITSELECT,6)@0 fracX_uid7_fpSinPiTest_in <= xIn_0(51 downto 0); fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(51 downto 0); --oFracX_uid31_uid31_fpSinPiTest(BITJOIN,30)@0 oFracX_uid31_uid31_fpSinPiTest_q <= VCC_q & fracX_uid7_fpSinPiTest_b; --extendedFracX_uid35_fpSinPiTest(BITJOIN,34)@0 extendedFracX_uid35_fpSinPiTest_q <= cst01pWShift_uid34_fpSinPiTest_q & oFracX_uid31_uid31_fpSinPiTest_q; --shiftBias_uid32_fpSinPiTest(CONSTANT,31) shiftBias_uid32_fpSinPiTest_q <= "01111100011"; --expX_uid6_fpSinPiTest(BITSELECT,5)@0 expX_uid6_fpSinPiTest_in <= xIn_0(62 downto 0); expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(62 downto 52); --shiftValue_uid33_fpSinPiTest(SUB,32)@0 shiftValue_uid33_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b); shiftValue_uid33_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid32_fpSinPiTest_q); shiftValue_uid33_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid33_fpSinPiTest_a) - UNSIGNED(shiftValue_uid33_fpSinPiTest_b)); shiftValue_uid33_fpSinPiTest_q <= shiftValue_uid33_fpSinPiTest_o(11 downto 0); --fxpShifterBits_uid36_fpSinPiTest(BITSELECT,35)@0 fxpShifterBits_uid36_fpSinPiTest_in <= shiftValue_uid33_fpSinPiTest_q(6 downto 0); fxpShifterBits_uid36_fpSinPiTest_b <= fxpShifterBits_uid36_fpSinPiTest_in(6 downto 0); --leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest(BITSELECT,114)@0 leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b; leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in(6 downto 5); --leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest(MUX,115)@0 leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s, extendedFracX_uid35_fpSinPiTest_q, leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= extendedFracX_uid35_fpSinPiTest_q; WHEN "01" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest(BITSELECT,125)@0 leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(4 downto 0); leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in(4 downto 3); --leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest(MUX,126)@0 leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest(BITSELECT,136)@0 leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(2 downto 0); leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in(2 downto 1); --leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest(MUX,137)@0 leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest(BITSELECT,139)@0 LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in(79 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest(BITJOIN,140)@0 leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b & GND_q; --reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3(REG,357)@0 reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2(REG,358)@0 reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest(BITSELECT,141)@0 leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(0 downto 0); leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in(0 downto 0); --ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b(DELAY,581)@0 ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest(MUX,142)@1 leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q; leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s, reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q, reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q) BEGIN CASE leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q; WHEN "1" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q; WHEN OTHERS => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --intXParity_uid38_fpSinPiTest(BITSELECT,37)@1 intXParity_uid38_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q; intXParity_uid38_fpSinPiTest_b <= intXParity_uid38_fpSinPiTest_in(80 downto 80); --ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c(DELAY,536)@1 ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => intXParity_uid38_fpSinPiTest_b, xout => ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q, clk => clk, aclr => areset ); --biasM1_uid27_fpSinPiTest(CONSTANT,26) biasM1_uid27_fpSinPiTest_q <= "01111111110"; --xFrac_uid28_fpSinPiTest(COMPARE,27)@0 xFrac_uid28_fpSinPiTest_cin <= GND_q; xFrac_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid27_fpSinPiTest_q) & '0'; xFrac_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid28_fpSinPiTest_cin(0); xFrac_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid28_fpSinPiTest_a) - UNSIGNED(xFrac_uid28_fpSinPiTest_b)); xFrac_uid28_fpSinPiTest_n(0) <= not xFrac_uid28_fpSinPiTest_o(13); --ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a(DELAY,532)@0 ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => xFrac_uid28_fpSinPiTest_n, xout => ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvXFrac_uid99_fpSinPiTest(LOGICAL,98)@3 InvXFrac_uid99_fpSinPiTest_a <= ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q; InvXFrac_uid99_fpSinPiTest_q <= not InvXFrac_uid99_fpSinPiTest_a; --biasMwShift_uid29_fpSinPiTest(CONSTANT,28) biasMwShift_uid29_fpSinPiTest_q <= "01111100100"; --sinXIsX_uid30_fpSinPiTest(COMPARE,29)@0 sinXIsX_uid30_fpSinPiTest_cin <= GND_q; sinXIsX_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0'; sinXIsX_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid29_fpSinPiTest_q) & sinXIsX_uid30_fpSinPiTest_cin(0); sinXIsX_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid30_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid30_fpSinPiTest_b)); sinXIsX_uid30_fpSinPiTest_c(0) <= sinXIsX_uid30_fpSinPiTest_o(13); --ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a(DELAY,502)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvSinXIsX_uid80_fpSinPiTest(LOGICAL,79)@2 InvSinXIsX_uid80_fpSinPiTest_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q; InvSinXIsX_uid80_fpSinPiTest_q <= not InvSinXIsX_uid80_fpSinPiTest_a; --y_uid39_fpSinPiTest(BITSELECT,38)@1 y_uid39_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); y_uid39_fpSinPiTest_b <= y_uid39_fpSinPiTest_in(79 downto 0); --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0(REG,360)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid40_fpSinPiTest(LOGICAL,39)@2 yIsZero_uid40_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q; yIsZero_uid40_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000000000000000000000000000000000000000000000000" & GND_q); yIsZero_uid40_fpSinPiTest_q <= "1" when yIsZero_uid40_fpSinPiTest_a = yIsZero_uid40_fpSinPiTest_b else "0"; --And2YIsZeroInvSinXIsX_uid81_fpSinPiTest(LOGICAL,80)@2 And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a <= yIsZero_uid40_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b <= InvSinXIsX_uid80_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a and And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b; --cstBiasPwF_uid13_fpSinPiTest(CONSTANT,12) cstBiasPwF_uid13_fpSinPiTest_q <= "10000110011"; --xIntExp_uid26_fpSinPiTest(COMPARE,25)@0 xIntExp_uid26_fpSinPiTest_cin <= GND_q; xIntExp_uid26_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid13_fpSinPiTest_q) & '0'; xIntExp_uid26_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid26_fpSinPiTest_cin(0); xIntExp_uid26_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid26_fpSinPiTest_a) - UNSIGNED(xIntExp_uid26_fpSinPiTest_b)); xIntExp_uid26_fpSinPiTest_c(0) <= xIntExp_uid26_fpSinPiTest_o(13); --ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a(DELAY,505)@0 ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => xIntExp_uid26_fpSinPiTest_c, xout => ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q, clk => clk, aclr => areset ); --Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest(LOGICAL,81)@2 Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a or Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b; --cstAllZWF_uid10_fpSinPiTest(CONSTANT,9) cstAllZWF_uid10_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracXIsZero_uid17_fpSinPiTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b; fracXIsZero_uid17_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q; fracXIsZero_uid17_fpSinPiTest_q <= "1" when fracXIsZero_uid17_fpSinPiTest_a = fracXIsZero_uid17_fpSinPiTest_b else "0"; --ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a(DELAY,442)@0 ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => fracXIsZero_uid17_fpSinPiTest_q, xout => ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvFracXIsZero_uid19_fpSinPiTest(LOGICAL,18)@1 InvFracXIsZero_uid19_fpSinPiTest_a <= ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q; InvFracXIsZero_uid19_fpSinPiTest_q <= not InvFracXIsZero_uid19_fpSinPiTest_a; --cstAllOWE_uid9_fpSinPiTest(CONSTANT,8) cstAllOWE_uid9_fpSinPiTest_q <= "11111111111"; --expXIsMax_uid16_fpSinPiTest(LOGICAL,15)@0 expXIsMax_uid16_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsMax_uid16_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q; expXIsMax_uid16_fpSinPiTest_q <= "1" when expXIsMax_uid16_fpSinPiTest_a = expXIsMax_uid16_fpSinPiTest_b else "0"; --ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a(DELAY,443)@0 ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsMax_uid16_fpSinPiTest_q, xout => ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest(LOGICAL,19)@1 And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a <= ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b <= InvFracXIsZero_uid19_fpSinPiTest_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a and And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b; --InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest(LOGICAL,20)@1 InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q <= not InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a; --And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0 And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a <= expXIsMax_uid16_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b <= fracXIsZero_uid17_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a and And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b; --InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0 InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q; InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q <= not InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a; --cstAllZWE_uid11_fpSinPiTest(CONSTANT,10) cstAllZWE_uid11_fpSinPiTest_q <= "00000000000"; --expXIsZero_uid15_fpSinPiTest(LOGICAL,14)@0 expXIsZero_uid15_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsZero_uid15_fpSinPiTest_b <= cstAllZWE_uid11_fpSinPiTest_q; expXIsZero_uid15_fpSinPiTest_q <= "1" when expXIsZero_uid15_fpSinPiTest_a = expXIsZero_uid15_fpSinPiTest_b else "0"; --InvExpXIsZero_uid23_fpSinPiTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSinPiTest_a <= expXIsZero_uid15_fpSinPiTest_q; InvExpXIsZero_uid23_fpSinPiTest_q <= not InvExpXIsZero_uid23_fpSinPiTest_a; --And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0 And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a <= InvExpXIsZero_uid23_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b <= InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a and And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b; --ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a(DELAY,450)@0 ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q, xout => ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest(LOGICAL,24)@1 And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a <= ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b <= InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a and And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b; END IF; END PROCESS; --xIsInt_uid83_fpSinPiTest(LOGICAL,82)@2 xIsInt_uid83_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_b <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_q <= xIsInt_uid83_fpSinPiTest_a and xIsInt_uid83_fpSinPiTest_b; --InvXIsInt_uid100_fpSinPiTest(LOGICAL,99)@2 InvXIsInt_uid100_fpSinPiTest_a <= xIsInt_uid83_fpSinPiTest_q; InvXIsInt_uid100_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= not InvXIsInt_uid100_fpSinPiTest_a; END IF; END PROCESS; --signComp_uid101_fpSinPiTest(LOGICAL,100)@3 signComp_uid101_fpSinPiTest_a <= InvXIsInt_uid100_fpSinPiTest_q; signComp_uid101_fpSinPiTest_b <= InvXFrac_uid99_fpSinPiTest_q; signComp_uid101_fpSinPiTest_c <= ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q; signComp_uid101_fpSinPiTest_q <= signComp_uid101_fpSinPiTest_a and signComp_uid101_fpSinPiTest_b and signComp_uid101_fpSinPiTest_c; --ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a(DELAY,537)@2 ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => yIsZero_uid40_fpSinPiTest_q, xout => ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvYIsZero_uid102_fpSinPiTest(LOGICAL,101)@3 InvYIsZero_uid102_fpSinPiTest_a <= ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q; InvYIsZero_uid102_fpSinPiTest_q <= not InvYIsZero_uid102_fpSinPiTest_a; --And2InvYIsZeroSignComp_uid103_fpSinPiTest(LOGICAL,102)@3 And2InvYIsZeroSignComp_uid103_fpSinPiTest_a <= InvYIsZero_uid102_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_b <= signComp_uid101_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_q <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_a and And2InvYIsZeroSignComp_uid103_fpSinPiTest_b; --signX_uid8_fpSinPiTest(BITSELECT,7)@0 signX_uid8_fpSinPiTest_in <= xIn_0; signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(63 downto 63); --ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a(DELAY,540)@0 ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q, clk => clk, aclr => areset ); --signR_uid104_fpSinPiTest(LOGICAL,103)@3 signR_uid104_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q; signR_uid104_fpSinPiTest_b <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_q; signR_uid104_fpSinPiTest_q <= signR_uid104_fpSinPiTest_a xor signR_uid104_fpSinPiTest_b; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt(COUNTER,1020) -- every=1, low=0, high=36, step=1, init=1 ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i = 35 THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i - 36; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i,6)); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg(REG,1021) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --VCC(CONSTANT,1) VCC_q <= "1"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux(MUX,1022) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux: PROCESS (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem(DUALMEM,1019) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia <= signR_uid104_fpSinPiTest_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 37, width_b => 1, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq, address_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa, data_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia ); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq(0 downto 0); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg(DELAY,1018) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q, xout => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --cstBias_uid12_fpSinPiTest(CONSTANT,11) cstBias_uid12_fpSinPiTest_q <= "01111111111"; --piwFP2_uid67_fpSinPiTest(CONSTANT,66) piwFP2_uid67_fpSinPiTest_q <= "110010010000111111011010101000100010000101101000110001"; --reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1(REG,363)@1 reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --cOne_uid44_fpSinPiTest(CONSTANT,43) cOne_uid44_fpSinPiTest_q <= "100000000000000000000000000000000000000000000000000000000000000000000000000000000"; --oneMinusY_uid45_fpSinPiTest(SUB,44)@2 oneMinusY_uid45_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid44_fpSinPiTest_q); oneMinusY_uid45_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q); oneMinusY_uid45_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid45_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid45_fpSinPiTest_b)); END IF; END PROCESS; oneMinusY_uid45_fpSinPiTest_q <= oneMinusY_uid45_fpSinPiTest_o(81 downto 0); --oMyBottom_uid47_fpSinPiTest(BITSELECT,46)@3 oMyBottom_uid47_fpSinPiTest_in <= oneMinusY_uid45_fpSinPiTest_q(78 downto 0); oMyBottom_uid47_fpSinPiTest_b <= oMyBottom_uid47_fpSinPiTest_in(78 downto 0); --ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d(DELAY,471)@3 ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => oMyBottom_uid47_fpSinPiTest_b, xout => ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q, clk => clk, aclr => areset ); --yBottom_uid48_fpSinPiTest(BITSELECT,47)@1 yBottom_uid48_fpSinPiTest_in <= y_uid39_fpSinPiTest_b(78 downto 0); yBottom_uid48_fpSinPiTest_b <= yBottom_uid48_fpSinPiTest_in(78 downto 0); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c(DELAY,470)@1 ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 79, depth => 2 ) PORT MAP ( xin => yBottom_uid48_fpSinPiTest_b, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg(DELAY,926) ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a(DELAY,833)@1 ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a : dspba_delay GENERIC MAP ( width => 80, depth => 1 ) PORT MAP ( xin => y_uid39_fpSinPiTest_b, xout => ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q, clk => clk, aclr => areset ); --reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1(REG,364)@2 reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q; END IF; END PROCESS; --cmpYToOneMinusY_uid46_fpSinPiTest(COMPARE,45)@3 cmpYToOneMinusY_uid46_fpSinPiTest_cin <= GND_q; cmpYToOneMinusY_uid46_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & oneMinusY_uid45_fpSinPiTest_q) & '0'; cmpYToOneMinusY_uid46_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q) & cmpYToOneMinusY_uid46_fpSinPiTest_cin(0); cmpYToOneMinusY_uid46_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_b)); END IF; END PROCESS; cmpYToOneMinusY_uid46_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid46_fpSinPiTest_o(84); --z_uid49_fpSinPiTest(MUX,48)@4 z_uid49_fpSinPiTest_s <= cmpYToOneMinusY_uid46_fpSinPiTest_c; z_uid49_fpSinPiTest: PROCESS (z_uid49_fpSinPiTest_s, ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q) BEGIN CASE z_uid49_fpSinPiTest_s IS WHEN "0" => z_uid49_fpSinPiTest_q <= ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q; WHEN "1" => z_uid49_fpSinPiTest_q <= ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q; WHEN OTHERS => z_uid49_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --zAddr_uid63_fpSinPiTest(BITSELECT,62)@4 zAddr_uid63_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; zAddr_uid63_fpSinPiTest_b <= zAddr_uid63_fpSinPiTest_in(78 downto 72); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0(REG,382)@4 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= zAddr_uid63_fpSinPiTest_b; END IF; END PROCESS; --memoryC5_uid231_sinPiZTableGenerator(LOOKUP,230)@5 memoryC5_uid231_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; WHEN "0000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111110101101000"; WHEN "0000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111101101011101"; WHEN "0000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100110001110"; WHEN "0000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100000000010"; WHEN "0000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111011000000000"; WHEN "0000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111010001101101"; WHEN "0000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111001010010111"; WHEN "0001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111000010110010"; WHEN "0001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110111100010100"; WHEN "0001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110110100011111"; WHEN "0001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110101100101101"; WHEN "0001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110100101101011"; WHEN "0001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110011111011101"; WHEN "0001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010111001010"; WHEN "0001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010001011011"; WHEN "0010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110001010101011"; WHEN "0010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110000011011001"; WHEN "0010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101111011000001"; WHEN "0010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101110101001010"; WHEN "0010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101101110100110"; WHEN "0010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101100111100011"; WHEN "0010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011111111111"; WHEN "0010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011001001010"; WHEN "0011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101010010100110"; WHEN "0011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101001010011011"; WHEN "0011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101000100011100"; WHEN "0011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100111101010110"; WHEN "0011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100110110111000"; WHEN "0011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100101111110010"; WHEN "0011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100111110010"; WHEN "0011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100001010101"; WHEN "0100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100011011011111"; WHEN "0100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100010011110111"; WHEN "0100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100001110001010"; WHEN "0100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100000111000100"; WHEN "0100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111111110101"; WHEN "0100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111001010110"; WHEN "0100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011110011000111"; WHEN "0100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011101101000000"; WHEN "0101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011100110000011"; WHEN "0101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011111111001"; WHEN "0101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011000100110"; WHEN "0101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011010010101100"; WHEN "0101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011001100010010"; WHEN "0101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011000101010111"; WHEN "0101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111111101010"; WHEN "0101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111001010000"; WHEN "0110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010110011010011"; WHEN "0110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010101100101011"; WHEN "0110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010100110111110"; WHEN "0110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011111111000"; WHEN "0110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011010110010"; WHEN "0110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010010101001110"; WHEN "0110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001110010011"; WHEN "0110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001000111011"; WHEN "0111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010000001111011"; WHEN "0111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001111011111110"; WHEN "0111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110111001010"; WHEN "0111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110001110111"; WHEN "0111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001101011000100"; WHEN "0111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100101010010"; WHEN "0111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100000011111"; WHEN "0111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001011010001010"; WHEN "1000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001010100111110"; WHEN "1000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001110110010"; WHEN "1000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001010111000"; WHEN "1000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001000100111111"; WHEN "1000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111111001100"; WHEN "1000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111010001001"; WHEN "1000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110101010110"; WHEN "1000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110000011101"; WHEN "1001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000101001110100"; WHEN "1001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000100101111001"; WHEN "1001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011111111010"; WHEN "1001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011011110110"; WHEN "1001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010110001100"; WHEN "1001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010001001000"; WHEN "1001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001101111001"; WHEN "1001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001000000111"; WHEN "1010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000000010111001"; WHEN "1010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111110110110"; WHEN "1010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111001111111"; WHEN "1010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110110010100"; WHEN "1010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110001011000"; WHEN "1010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101100010111"; WHEN "1010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101000010010"; WHEN "1010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100100010000"; WHEN "1011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100000111100"; WHEN "1011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111011011111111"; WHEN "1011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010111100000"; WHEN "1011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010011110100"; WHEN "1011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010000011100"; WHEN "1011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111001011011110"; WHEN "1011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000111111101"; WHEN "1011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000100101011"; WHEN "1100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000001100100"; WHEN "1100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111101101110"; WHEN "1100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111010011000"; WHEN "1100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110110110000"; WHEN "1100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110010011010"; WHEN "1100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110000011110"; WHEN "1100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101100101100"; WHEN "1100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101000101110"; WHEN "1101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100110100000"; WHEN "1101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100100010001"; WHEN "1101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100001000000"; WHEN "1101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011101101110"; WHEN "1101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011011011111"; WHEN "1101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010111000100"; WHEN "1101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010101110011"; WHEN "1101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010001111100"; WHEN "1110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010000001111"; WHEN "1110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001110011001"; WHEN "1110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001010100010"; WHEN "1110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000111111000"; WHEN "1110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101110110"; WHEN "1110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101000100"; WHEN "1110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000010100010"; WHEN "1110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111111110011"; WHEN "1111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111110010000"; WHEN "1111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111100110111"; WHEN "1111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111010111000"; WHEN "1111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111000101000"; WHEN "1111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110110110100"; WHEN "1111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110101011010"; WHEN "1111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110100000011"; WHEN "1111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110010001011"; WHEN OTHERS => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; END CASE; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a(DELAY,485)@4 ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => z_uid49_fpSinPiTest_q, xout => ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q, clk => clk, aclr => areset ); --zPPolyEval_uid64_fpSinPiTest(BITSELECT,63)@5 zPPolyEval_uid64_fpSinPiTest_in <= ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q(71 downto 0); zPPolyEval_uid64_fpSinPiTest_b <= zPPolyEval_uid64_fpSinPiTest_in(71 downto 27); --yT1_uid232_sinPiZPolyEval(BITSELECT,231)@5 yT1_uid232_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT1_uid232_sinPiZPolyEval_b <= yT1_uid232_sinPiZPolyEval_in(44 downto 28); --reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0(REG,383)@5 reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= yT1_uid232_sinPiZPolyEval_b; END IF; END PROCESS; --prodXY_uid263_pT1_uid233_sinPiZPolyEval(MULT,262)@6 prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_a),18)) * SIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_b); prodXY_uid263_pT1_uid233_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= memoryC5_uid231_sinPiZTableGenerator_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr,34)); END IF; END PROCESS; prodXY_uid263_pT1_uid233_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval(BITSELECT,263)@9 prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_q; prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in(33 downto 16); --highBBits_uid235_sinPiZPolyEval(BITSELECT,234)@9 highBBits_uid235_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b; highBBits_uid235_sinPiZPolyEval_b <= highBBits_uid235_sinPiZPolyEval_in(17 downto 1); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a(DELAY,853)@4 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a : dspba_delay GENERIC MAP ( width => 7, depth => 3 ) PORT MAP ( xin => zAddr_uid63_fpSinPiTest_b, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0(REG,384)@7 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q; END IF; END PROCESS; --memoryC4_uid230_sinPiZTableGenerator(LOOKUP,229)@8 memoryC4_uid230_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; WHEN "0000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110011111111100"; WHEN "0000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100101101100110011"; WHEN "0000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100100010011000101"; WHEN "0000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100010010010010110"; WHEN "0000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011111110011000100"; WHEN "0000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011100101011001100"; WHEN "0000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011001000001111000"; WHEN "0001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010100110101100100"; WHEN "0001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010000000010110001"; WHEN "0001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001001010101111100100"; WHEN "0001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001000100111000100010"; WHEN "0001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000111110011011110101"; WHEN "0001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000110111011001010101"; WHEN "0001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000101111111000110001"; WHEN "0001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000100111101101111110"; WHEN "0010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000011111000010010110"; WHEN "0010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000010101110100101111"; WHEN "0010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000001100000110110101"; WHEN "0010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000000001101111000000"; WHEN "0010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111110110110101110011"; WHEN "0010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111101011011010111001"; WHEN "0010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111011111011110000110"; WHEN "0010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111010010111100110100"; WHEN "0011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111000101110111111001"; WHEN "0011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110111000010100011101"; WHEN "0011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110101010001000110011"; WHEN "0011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110011011011101100111"; WHEN "0011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110001100001110001111"; WHEN "0011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101111100011110001010"; WHEN "0011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101101100001110100101"; WHEN "0011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101011011011000110110"; WHEN "0100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101001001111111101110"; WHEN "0100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100111000001001001111"; WHEN "0100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100100101101100011001"; WHEN "0100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100010010110001110000"; WHEN "0100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011111111010101110110"; WHEN "0100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011101011010111000111"; WHEN "0100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011010110110110011110"; WHEN "0100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011000001110100011110"; WHEN "0101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010101100010100010011"; WHEN "0101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010010110010001000111"; WHEN "0101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001111111110001000100"; WHEN "0101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001101000101100110110"; WHEN "0101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001010001001001111011"; WHEN "0101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000111001001000001110"; WHEN "0101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000100000100011110110"; WHEN "0101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000000111100001111001"; WHEN "0110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111101101111111011111"; WHEN "0110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111010011111111100110"; WHEN "0110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110111001011110100100"; WHEN "0110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110011110100010000111"; WHEN "0110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110000011000010001001"; WHEN "0110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101100111000101000011"; WHEN "0110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101001010101101011111"; WHEN "0110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100101101110011101110"; WHEN "0111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100010000100000111110"; WHEN "0111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011110010101101110100"; WHEN "0111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011010100011010011110"; WHEN "0111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010110101101011010111"; WHEN "0111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010010110100011011101"; WHEN "0111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001110110111100001001"; WHEN "0111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001010110110110010000"; WHEN "0111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000110110011000001101"; WHEN "1000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000010101011011011001"; WHEN "1000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111110100000101110010"; WHEN "1000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111010010001110101001"; WHEN "1000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110110000000001101011"; WHEN "1000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110001101011001110011"; WHEN "1000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101101010010101011101"; WHEN "1000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101000110110101111111"; WHEN "1000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111100100010111100111100"; WHEN "1001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011111110101110100100"; WHEN "1001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011011001111111110100"; WHEN "1001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010110100111101000111"; WHEN "1001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010001111011100101001"; WHEN "1001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001101001100111100001"; WHEN "1001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001000011011000101011"; WHEN "1001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111000011100101100110010"; WHEN "1001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111110101110000000011"; WHEN "1010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111001110011001111101"; WHEN "1010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110110100110101001110001"; WHEN "1010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101111110100101001011"; WHEN "1010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101010110000110010110"; WHEN "1010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100101101010100111010"; WHEN "1010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100000100001101101101"; WHEN "1010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110011011010101110011000"; WHEN "1010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010110000111001010011"; WHEN "1011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010000110101101010010"; WHEN "1011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110001011100010001000010"; WHEN "1011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000110001011111001110"; WHEN "1011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000000110010110110100"; WHEN "1011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101111011010111010001000"; WHEN "1011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110101111001110001011"; WHEN "1011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110000011001011001100"; WHEN "1011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101101010110110100111111"; WHEN "1100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101100101010001011011001"; WHEN "1100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011111101010010000000"; WHEN "1100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011010000000101001000"; WHEN "1100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101010100010100111110111"; WHEN "1100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001110100111011010110"; WHEN "1100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001000110110111101100"; WHEN "1100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101000011000101000001000"; WHEN "1100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100111101010001001010101"; WHEN "1101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110111011010110000011"; WHEN "1101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110001100010011011010"; WHEN "1101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100101011101000100011001"; WHEN "1101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100100101101100110100111"; WHEN "1101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011111101110111111010"; WHEN "1101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011001110000000101100"; WHEN "1101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100010011101110011110101"; WHEN "1101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100001101101100000010000"; WHEN "1110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000111100111010001011"; WHEN "1110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000001100000111111010"; WHEN "1110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011111011011001110101000"; WHEN "1110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011110101010000110010111"; WHEN "1110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101111000110001000001"; WHEN "1110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101000111001101001001"; WHEN "1110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011100010101100011001010"; WHEN "1110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011011100011101111010110"; WHEN "1111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011010110001101110011110"; WHEN "1111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001111111100011010111"; WHEN "1111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001001101010000100101"; WHEN "1111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011000011010110101101110"; WHEN "1111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010111101000010001000000"; WHEN "1111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110110101100011000101"; WHEN "1111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110000010101101010111"; WHEN "1111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010101001111110001011010"; WHEN OTHERS => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; END CASE; END IF; END PROCESS; --sumAHighB_uid236_sinPiZPolyEval(ADD,235)@9 sumAHighB_uid236_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((26 downto 26 => memoryC4_uid230_sinPiZTableGenerator_q(25)) & memoryC4_uid230_sinPiZTableGenerator_q); sumAHighB_uid236_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((26 downto 17 => highBBits_uid235_sinPiZPolyEval_b(16)) & highBBits_uid235_sinPiZPolyEval_b); sumAHighB_uid236_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid236_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid236_sinPiZPolyEval_b)); sumAHighB_uid236_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_o(26 downto 0); --lowRangeB_uid234_sinPiZPolyEval(BITSELECT,233)@9 lowRangeB_uid234_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid234_sinPiZPolyEval_b <= lowRangeB_uid234_sinPiZPolyEval_in(0 downto 0); --s1_uid234_uid237_sinPiZPolyEval(BITJOIN,236)@9 s1_uid234_uid237_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_q & lowRangeB_uid234_sinPiZPolyEval_b; --reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1(REG,385)@9 reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= s1_uid234_uid237_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor(LOGICAL,1179) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q <= not (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a or ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg(REG,1177) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= VCC_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena(REG,1180) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q = "1") THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd(LOGICAL,1181) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a and ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b; --yT2_uid238_sinPiZPolyEval(BITSELECT,237)@5 yT2_uid238_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT2_uid238_sinPiZPolyEval_b <= yT2_uid238_sinPiZPolyEval_in(44 downto 19); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt(COUNTER,1173) -- every=1, low=0, high=1, step=1, init=1 ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i + 1; END IF; END PROCESS; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i,1)); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg(REG,1174) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux(MUX,1175) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q) BEGIN CASE ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s IS WHEN "0" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; WHEN "1" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem(DUALMEM,1172) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia <= yT2_uid238_sinPiZPolyEval_b; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 26, widthad_a => 1, numwords_a => 2, width_b => 26, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq, address_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa, data_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia ); ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq(25 downto 0); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg(DELAY,1171) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q, xout => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0(REG,386)@9 reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q; END IF; END PROCESS; --prodXY_uid266_pT2_uid239_sinPiZPolyEval(MULT,265)@10 prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_a),27)) * SIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_b); prodXY_uid266_pT2_uid239_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr,54)); END IF; END PROCESS; prodXY_uid266_pT2_uid239_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval(BITSELECT,266)@13 prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_q; prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in(53 downto 25); --highBBits_uid241_sinPiZPolyEval(BITSELECT,240)@13 highBBits_uid241_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b; highBBits_uid241_sinPiZPolyEval_b <= highBBits_uid241_sinPiZPolyEval_in(28 downto 1); --reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1(REG,388)@13 reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= highBBits_uid241_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor(LOGICAL,1192) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1188) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q <= "0101"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp(LOGICAL,1189) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg(REG,1190) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena(REG,1193) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1194) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1184) -- every=1, low=0, high=5, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i = 4 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i - 5; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i,3)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg(REG,1185) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1186) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1183) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 3, numwords_a => 6, width_b => 7, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg(DELAY,1182) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0(REG,387)@12 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC3_uid229_sinPiZTableGenerator(LOOKUP,228)@13 memoryC3_uid229_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; WHEN "0000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000001010001100110101000111010101"; WHEN "0000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000010100011001100101101010110011"; WHEN "0000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000011110100110001101010100011011"; WHEN "0000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000101000110010100111100101110011"; WHEN "0000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000110010111110101111101101101000"; WHEN "0000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000111101001010100001100001001101"; WHEN "0000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001000111010101111000010100001000"; WHEN "0001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001010001100000101111101001011010"; WHEN "0001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001011011101011000011001000111110"; WHEN "0001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001100101110100101110001001110101"; WHEN "0001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001101111111101101100010100000001"; WHEN "0001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001111010000101111001001101010110"; WHEN "0001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010000100001101010000011000110101"; WHEN "0001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010001110010011101101001010101000"; WHEN "0001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010011000011001001011011101011111"; WHEN "0010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010100010011101100110100011101011"; WHEN "0010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010101100100000111010000011110001"; WHEN "0010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010110110100011000001011111010110"; WHEN "0010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011000000100011111000101110110101"; WHEN "0010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011001010100011011011001000001011"; WHEN "0010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011010100100001100100010010100101"; WHEN "0010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011011110011110001111110110101010"; WHEN "0010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011101000011001011001100000011011"; WHEN "0011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011110010010010111100111000010100"; WHEN "0011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011111100001010110101011110000110"; WHEN "0011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100000110000000111111001110100010"; WHEN "0011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100001111110101010101100100101101"; WHEN "0011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100011001100111110100010110001111"; WHEN "0011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100100011011000010111001001011111"; WHEN "0011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100101101000110111001101001101001"; WHEN "0011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100110110110011010111110011001100"; WHEN "0100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101000000011101101101010000100110"; WHEN "0100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101001010000101110101101000010110"; WHEN "0100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101010011101011101100111100100100"; WHEN "0100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101011101001111001110110000110010"; WHEN "0100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101100110110000010111000000110011"; WHEN "0100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101110000001111000001100011110100"; WHEN "0100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101111001101011001010010000000001"; WHEN "0100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110000011000100101100111100001110"; WHEN "0101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110001100011011100101011010100101"; WHEN "0101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110010101101111101111110000010101"; WHEN "0101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110011111000001000111101011101100"; WHEN "0101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110101000001111101001011001100010"; WHEN "0101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110110001011011010000101101010010"; WHEN "0101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110111010100011111001100111101100"; WHEN "0101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111000011101001100000010000100010"; WHEN "0101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111001100101100000000100001010000"; WHEN "0110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111010101101011010110100011101100"; WHEN "0110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111011110100111011110011000011110"; WHEN "0110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111100111100000010100001101010000"; WHEN "0110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111110000010101110100000001010000"; WHEN "0110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111111001000111111010001101010001"; WHEN "0110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000000001110110100010110001111010"; WHEN "0110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000001010100001101001110111110101"; WHEN "0110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000010011001001001011111110000001"; WHEN "0111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000011011101101000101000010101111"; WHEN "0111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000100100001101010001101000100100"; WHEN "0111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000101100101001101110000011010101"; WHEN "0111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000110101000010010110100001011010"; WHEN "0111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000111101010111000111010101011110"; WHEN "0111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001000101100111111101000110111000"; WHEN "0111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001001101110100110100001111001100"; WHEN "0111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001010101111101101001000001001010"; WHEN "1000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001011110000010011000001001000011"; WHEN "1000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001100110000010111101111101010011"; WHEN "1000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001101101111111010111010011001111"; WHEN "1000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001110101110111100000011010000110"; WHEN "1000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001111101101011010110000011010010"; WHEN "1000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010000101011010110100111100000101"; WHEN "1000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010001101000101111001101110100011"; WHEN "1000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010010100101100100001000101010010"; WHEN "1001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010011100001110100111101001010100"; WHEN "1001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010100011101100001010100001011100"; WHEN "1001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010101011000101000110001011100100"; WHEN "1001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010110010011001010111110000100100"; WHEN "1001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010111001101000111011111001000111"; WHEN "1001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000000110011101111101001011111"; WHEN "1001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000111111001110000000110011110"; WHEN "1001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011001110111010111001110111111110"; WHEN "1010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011010101110111001010010001110110"; WHEN "1010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011011100101110011110011000111101"; WHEN "1010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011100011100000110011001001001001"; WHEN "1010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011101010001110000101111000101100"; WHEN "1010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110000110110010011100011000111"; WHEN "1010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110111011001011001011101010011"; WHEN "1010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011111101110111010100111100011100"; WHEN "1010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100000100010000000011001111101101"; WHEN "1011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100001010100011100001101110011100"; WHEN "1011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010000110001101101100011100011"; WHEN "1011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010110111010100100010100000100"; WHEN "1011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100011100111110000011100000001010"; WHEN "1011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100100010111100001000100001101001"; WHEN "1011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101000110100110000110001111011"; WHEN "1011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101110100111111010000100111001"; WHEN "1011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100110100010101100001111010001101"; WHEN "1100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111001111101100101111101110000"; WHEN "1100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111111100000000011110011100101"; WHEN "1100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101000100111100111001010011110100"; WHEN "1100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001010010100000100001001001101"; WHEN "1100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001111100101100010000111001000"; WHEN "1100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101010100110001010001010100001101"; WHEN "1100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011001110111001111010101110101"; WHEN "1100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011110110111011010001101111010"; WHEN "1101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101100011110001110000000111001111"; WHEN "1101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101000100110001110111010010001"; WHEN "1101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101101010100110100100110101101"; WHEN "1101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110001111101011111011001010101"; WHEN "1101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110110100000001101100000100000"; WHEN "1101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111010111100111100111010111000"; WHEN "1101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111111010011101100010000110110"; WHEN "1101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000011100100011001011010100000"; WHEN "1110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000111101111000011000011110011"; WHEN "1110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001011110011100111011010000000"; WHEN "1110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001111110010000100101111100001"; WHEN "1110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010011101010011001110010000111"; WHEN "1110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010111011100100100111111111001"; WHEN "1110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011011001000100101000000101011"; WHEN "1110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011110101110011000001011101010"; WHEN "1110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100010001101111101010010100010"; WHEN "1111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100101100111010011001000110011"; WHEN "1111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101000111010011000011010000011"; WHEN "1111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101100000111001011110100010010"; WHEN "1111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101111001101101100001110011100"; WHEN "1111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110010001101111000100101110110"; WHEN "1111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110101000111101111110101001010"; WHEN "1111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110111111011010000111000110000"; WHEN "1111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110111010101000011010110000100000"; WHEN OTHERS => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; END CASE; END IF; END PROCESS; --sumAHighB_uid242_sinPiZPolyEval(ADD,241)@14 sumAHighB_uid242_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid229_sinPiZTableGenerator_q(34)) & memoryC3_uid229_sinPiZTableGenerator_q); sumAHighB_uid242_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((35 downto 28 => reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q(27)) & reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q); sumAHighB_uid242_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid242_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid242_sinPiZPolyEval_b)); sumAHighB_uid242_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_o(35 downto 0); --lowRangeB_uid240_sinPiZPolyEval(BITSELECT,239)@13 lowRangeB_uid240_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid240_sinPiZPolyEval_b <= lowRangeB_uid240_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a(DELAY,686)@13 ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid240_sinPiZPolyEval_b, xout => ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --s2_uid240_uid243_sinPiZPolyEval(BITJOIN,242)@14 s2_uid240_uid243_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_q & ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q; --yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval(BITSELECT,274)@14 yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in(36 downto 19); --reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9(REG,389)@14 reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor(LOGICAL,950) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top(CONSTANT,946) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q <= "0110"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp(LOGICAL,947) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b else "0"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg(REG,948) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena(REG,951) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q = "1") THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd(LOGICAL,952) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt(COUNTER,942) -- every=1, low=0, high=6, step=1, init=1 ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i = 5 THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i - 6; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i,3)); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg(REG,943) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux(MUX,944) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q) BEGIN CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s IS WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem(DUALMEM,1069) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 3, numwords_a => 7, width_b => 45, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg(DELAY,1068) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT3_uid244_sinPiZPolyEval(BITSELECT,243)@14 yT3_uid244_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q; yT3_uid244_sinPiZPolyEval_b <= yT3_uid244_sinPiZPolyEval_in(44 downto 10); --xBottomBits_uid274_pT3_uid245_sinPiZPolyEval(BITSELECT,273)@14 xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b(7 downto 0); xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in(7 downto 0); --pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval(BITJOIN,276)@14 pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7(REG,391)@14 reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid273_pT3_uid245_sinPiZPolyEval(BITSELECT,272)@14 yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q(9 downto 0); yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b <= yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in(9 downto 0); --spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval(BITJOIN,275)@14 spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q <= GND_q & yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b; --pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval(BITJOIN,277)@14 pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q <= spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6(REG,390)@14 reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval(BITSELECT,271)@14 xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in(34 downto 17); --reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4(REG,392)@14 reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma(CHAINMULTADD,345)@15 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1),38); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0); END IF; END PROCESS; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0),37)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval(BITSELECT,279)@18 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in(36 downto 7); --highBBits_uid282_pT3_uid245_sinPiZPolyEval(BITSELECT,281)@18 highBBits_uid282_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b; highBBits_uid282_pT3_uid245_sinPiZPolyEval_b <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_in(29 downto 1); --reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1(REG,395)@18 reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval(BITSELECT,269)@14 yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in(36 downto 10); --reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1(REG,393)@14 reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval(BITSELECT,268)@14 xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in(34 downto 8); --reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0(REG,394)@14 reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid271_pT3_uid245_sinPiZPolyEval(MULT,270)@15 topProd_uid271_pT3_uid245_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_b); topProd_uid271_pT3_uid245_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid271_pT3_uid245_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid271_pT3_uid245_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0(REG,396)@18 reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid283_pT3_uid245_sinPiZPolyEval(ADD,282)@19 sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q(53)) & reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b)); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid281_pT3_uid245_sinPiZPolyEval(BITSELECT,280)@18 lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b <= lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a(DELAY,724)@18 ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b, xout => ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid281_uid284_pT3_uid245_sinPiZPolyEval(BITJOIN,283)@19 add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q & ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q; --R_uid285_pT3_uid245_sinPiZPolyEval(BITSELECT,284)@19 R_uid285_pT3_uid245_sinPiZPolyEval_in <= add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q(54 downto 0); R_uid285_pT3_uid245_sinPiZPolyEval_b <= R_uid285_pT3_uid245_sinPiZPolyEval_in(54 downto 18); --reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1(REG,397)@19 reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= R_uid285_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor(LOGICAL,1168) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1164) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q <= "01011"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp(LOGICAL,1165) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg(REG,1166) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena(REG,1169) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1170) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1160) -- every=1, low=0, high=11, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i = 10 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i - 11; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i,4)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg(REG,1161) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1162) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1159) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 4, numwords_a => 12, width_b => 7, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg(DELAY,1158) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0(REG,381)@18 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC2_uid228_sinPiZTableGenerator(LOOKUP,227)@19 memoryC2_uid228_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; WHEN "0000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010010000000010011011110101101000"; WHEN "0000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010100110111111010000111001000101"; WHEN "0000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101011001101001111001000101101101011"; WHEN "0000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101100000010110001110010011100100110"; WHEN "0000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101101000111100110110110100100001100"; WHEN "0000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101110011011101101110110101011000001"; WHEN "0000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101111111111000110001101110000001000"; WHEN "0001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110001110001101111010000000001001001"; WHEN "0001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110011110011101000001010111100010011"; WHEN "0001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110110000100110000000101010101010010"; WHEN "0001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111000100101000101111111001111001110"; WHEN "0001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111011010100101000110010000000110000"; WHEN "0001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111110010011010111010000010100101101"; WHEN "0001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000001100001010000000110001101010110"; WHEN "0001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000100111110010001111000111001110001"; WHEN "0010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001000101010011011000111000110111111"; WHEN "0010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001100100101101010001000110100001110"; WHEN "0010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010000101111111101001111011000110110"; WHEN "0010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010101001001010010100101011111010000"; WHEN "0010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011001110001101000001111010001111100"; WHEN "0010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011110101000111100001010010001101000"; WHEN "0010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111100011101111001100001101011001010011"; WHEN "0010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101001000100010110001000111111011001"; WHEN "0011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101110101000010111100110110111011101"; WHEN "0011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111110100011011001110001010010101001001"; WHEN "0011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111111010011100110111010000000101010000"; WHEN "0011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000000101101010000001110011011110111"; WHEN "0011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000111001100010110010101001001001010"; WHEN "0011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000001101111010000110101101100011101100"; WHEN "0011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000010100110110011110011010100101011100"; WHEN "0011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000011100000001011010011000101010010101"; WHEN "0100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000100011011010110111011101111001100010"; WHEN "0100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000101011000010110010011010000011100100"; WHEN "0100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000110010111001000111110110011110000010"; WHEN "0100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000111010111101110100010110010000011111"; WHEN "0100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001000011010000110100010110001010111111"; WHEN "0100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001001011110010000100001100101110011011"; WHEN "0100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001010100100001100000001010001100011000"; WHEN "0100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001011101011111000100011000101001100001"; WHEN "0101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001100110101010101100111100000000011011"; WHEN "0101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001110000000100010101110001111101110010"; WHEN "0101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001111001101011111010110010001100011010"; WHEN "0101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010000011100001010111101110001010011110"; WHEN "0101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010001101100100101000010001011000100111"; WHEN "0101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010010111110101101000000001010011000010"; WHEN "0101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010100010010100010010011101010101101010"; WHEN "0101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010101101000000100010111111000010000011"; WHEN "0110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010110111111010010100111001111011100110"; WHEN "0110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011000011000001100011011011101110111001"; WHEN "0110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011001110010110001001101100001111110101"; WHEN "0110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011011001111000000010101101100000111100"; WHEN "0110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011100101100111001001011011101110011000"; WHEN "0110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011110001100011011000101101011001110101"; WHEN "0110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011111101101100101011010011010110110001"; WHEN "0110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100001010000010111011111000101001101100"; WHEN "0111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100010110100110000101000010110110110100"; WHEN "0111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100100011010110000001010001110101000110"; WHEN "0111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100110000010010101010111111111100101100"; WHEN "0111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100111101011011111100100010000110111111"; WHEN "0111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101001010110001110000000111101111100101"; WHEN "0111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101011000010011111111111010110011011100"; WHEN "0111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101100110000010100101111111111011010100"; WHEN "0111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101110011111101011100010110011100010110"; WHEN "1000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110000010000100011100111000010100111110"; WHEN "1000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110010000010111100001011010011001010101"; WHEN "1000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110011110110110100011101100001011001000"; WHEN "1000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110101101100001011101011000001011011001"; WHEN "1000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110111100011000001000000011101110001111"; WHEN "1000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111001011011010011101001111000101110001"; WHEN "1000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111011010101000010110010101100101000110"; WHEN "1000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111101010000001101100101101100010111111"; WHEN "1001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111111001100110011001101000011100111011"; WHEN "1001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000001001010110010110010010110100011100"; WHEN "1001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000011001010001011011110100100000011000"; WHEN "1001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000101001010111100011010000011111011101"; WHEN "1001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000111001101000100101100101001010011111"; WHEN "1001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001001010000100011011101100001100000010"; WHEN "1001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001011010101010111110011010101000110000"; WHEN "1001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001101011011100000110100001001001100100"; WHEN "1010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001111100010111101100101011101111001100"; WHEN "1010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010001101011101101001100010000010111010"; WHEN "1010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010011110101101110101100111011000000101"; WHEN "1010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010110000001000001001011010101000000100"; WHEN "1010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011000001101100011101010110100010000110"; WHEN "1010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011010011011010101001110001100010110011"; WHEN "1010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011100101010010100110111101111101101001"; WHEN "1010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011110111010100001101001010000001101110"; WHEN "1011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100001001011111010100011111111010110111"; WHEN "1011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100011011110011110101000101111001011001"; WHEN "1011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100101110010001100110111110001101101110"; WHEN "1011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101000000111000100010000111010010100101"; WHEN "1011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101010011101000011110011011110001111001"; WHEN "1011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101100110100001010011110010100110010101"; WHEN "1011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101111001100010111001111110111010001011"; WHEN "1011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110001100101101001000110000010101000001"; WHEN "1100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110011111111111110111110010111000010010"; WHEN "1100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110110011011010111110101111001000100111"; WHEN "1100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111000110111110010101001010001010011010"; WHEN "1100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111011010101001110010100101101110010111"; WHEN "1100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111101110011101001110100000001111101010"; WHEN "1100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000000010011000100000010100110110100000"; WHEN "1100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000010110011011011111011011100110110011"; WHEN "1100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000101010100110000011001001011000000001"; WHEN "1101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000111110111000000010101111111100010101"; WHEN "1101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001010011010001010101011110001011010100"; WHEN "1101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001100111110001110010100000000000010111"; WHEN "1101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001111100011001010000111110011101110000"; WHEN "1101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010010001000111100111111111110011011101"; WHEN "1101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010100101111100101110100111100110010101"; WHEN "1101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010111010111000011011110110101001010101"; WHEN "1101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011001111111010100110101011010011011011"; WHEN "1110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011100101000011000110000001010000000100"; WHEN "1110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011111010010001110000110001110011111011"; WHEN "1110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100001111100110011101110011111001111111"; WHEN "1110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100100101000001000011111100000011011011"; WHEN "1110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100111010100001011001111100100100101001"; WHEN "1110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101010000000111010110100101100100010111"; WHEN "1110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101100101110010110000100101000101101101"; WHEN "1110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101111011100011011110100111000011010111"; WHEN "1111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110010001011001010111010101011001010001"; WHEN "1111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110100111010100010001011000001010110100"; WHEN "1111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110111101010100000011010101100101100011"; WHEN "1111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111010011011000100011110010000011111011"; WHEN "1111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111101001100001101001010000010010001011"; WHEN "1111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111111111101111001010010001010101000011"; WHEN "1111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000010110000000111101010100101101001001"; WHEN "1111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000101100010110111000111000011010110101"; WHEN OTHERS => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid246_sinPiZPolyEval(CONSTANT,245) rndBit_uid246_sinPiZPolyEval_q <= "01"; --cIncludingRoundingBit_uid247_sinPiZPolyEval(BITJOIN,246)@19 cIncludingRoundingBit_uid247_sinPiZPolyEval_q <= memoryC2_uid228_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0(REG,398)@19 reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid247_sinPiZPolyEval_q; END IF; END PROCESS; --ts3_uid248_sinPiZPolyEval(ADD,247)@20 ts3_uid248_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q); ts3_uid248_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q(36)) & reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q); ts3_uid248_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid248_sinPiZPolyEval_a) + SIGNED(ts3_uid248_sinPiZPolyEval_b)); ts3_uid248_sinPiZPolyEval_q <= ts3_uid248_sinPiZPolyEval_o(45 downto 0); --s3_uid249_sinPiZPolyEval(BITSELECT,248)@20 s3_uid249_sinPiZPolyEval_in <= ts3_uid248_sinPiZPolyEval_q; s3_uid249_sinPiZPolyEval_b <= s3_uid249_sinPiZPolyEval_in(45 downto 1); --yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval(BITSELECT,286)@20 yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b; yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in(44 downto 18); --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9(REG,399)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor(LOGICAL,1091) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top(CONSTANT,1087) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q <= "01100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp(LOGICAL,1088) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg(REG,1089) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena(REG,1092) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd(LOGICAL,1093) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1083) -- every=1, low=0, high=12, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i = 11 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i - 12; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i,4)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg(REG,1084) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux(MUX,1085) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem(DUALMEM,1082) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 13, width_b => 45, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg(DELAY,1081) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT4_uid250_sinPiZPolyEval(BITSELECT,249)@20 yT4_uid250_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q; yT4_uid250_sinPiZPolyEval_b <= yT4_uid250_sinPiZPolyEval_in(44 downto 2); --xBottomBits_uid290_pT4_uid251_sinPiZPolyEval(BITSELECT,289)@20 xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in <= yT4_uid250_sinPiZPolyEval_b(15 downto 0); xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in(15 downto 0); --pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval(BITJOIN,291)@20 pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7(REG,401)@20 reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid289_pT4_uid251_sinPiZPolyEval(BITSELECT,288)@20 yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b(17 downto 0); yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b <= yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a(DELAY,733)@20 ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b, xout => ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval(BITJOIN,290)@21 spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q; --pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval(BITJOIN,292)@21 pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q <= spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6(REG,400)@21 reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a(DELAY,727)@20 ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 43, depth => 1 ) PORT MAP ( xin => yT4_uid250_sinPiZPolyEval_b, xout => ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval(BITSELECT,285)@21 xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in <= ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q; xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in(42 downto 16); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4(REG,402)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma(CHAINMULTADD,346)@22 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval(BITSELECT,294)@25 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in(54 downto 8); --highBBits_uid297_pT4_uid251_sinPiZPolyEval(BITSELECT,296)@25 highBBits_uid297_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b; highBBits_uid297_pT4_uid251_sinPiZPolyEval_b <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_in(46 downto 18); --reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1(REG,405)@25 reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1(REG,403)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b(DELAY,730)@21 ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0(REG,404)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid288_pT4_uid251_sinPiZPolyEval(MULT,287)@22 topProd_uid288_pT4_uid251_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_b); topProd_uid288_pT4_uid251_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid288_pT4_uid251_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid288_pT4_uid251_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0(REG,406)@25 reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid298_pT4_uid251_sinPiZPolyEval(ADD,297)@26 sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q(53)) & reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b)); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid296_pT4_uid251_sinPiZPolyEval(BITSELECT,295)@25 lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b(17 downto 0); lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b <= lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a(DELAY,741)@25 ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b, xout => ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid296_uid299_pT4_uid251_sinPiZPolyEval(BITJOIN,298)@26 add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q & ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q; --R_uid300_pT4_uid251_sinPiZPolyEval(BITSELECT,299)@26 R_uid300_pT4_uid251_sinPiZPolyEval_in <= add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q(71 downto 0); R_uid300_pT4_uid251_sinPiZPolyEval_b <= R_uid300_pT4_uid251_sinPiZPolyEval_in(71 downto 26); --reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1(REG,407)@26 reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= R_uid300_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor(LOGICAL,1155) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1151) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q <= "010010"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp(LOGICAL,1152) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg(REG,1153) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena(REG,1156) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1157) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1147) -- every=1, low=0, high=18, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i = 17 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i - 18; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg(REG,1148) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1149) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1146) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 19, width_b => 7, widthad_b => 5, numwords_b => 19, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg(DELAY,1145) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0(REG,380)@25 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC1_uid227_sinPiZTableGenerator(LOOKUP,226)@26 memoryC1_uid227_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; WHEN "0000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111110101101010100010101111000000010001111100011"; WHEN "0000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111101011010101001001010010110100010110001011110"; WHEN "0000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111100000111111110111100000001110010011010000110"; WHEN "0000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111010110101010110001001011111100110111111100011"; WHEN "0000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111001100010101111010001010101001101111010110100"; WHEN "0000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111000010000001010110010000110111110101011111000"; WHEN "0000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110110111101101001001010011000001101011000111010"; WHEN "0001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110101101011001010111000101010111101010010100111"; WHEN "0001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110100011000110000011011011111110011010111001110"; WHEN "0001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110011000110011010010001010101101000110101101101"; WHEN "0001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110001110100001000111000101001011101110011011101"; WHEN "0001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110000100001111100101111110110001011110001011001"; WHEN "0001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101111001111110110010101010100011000010010100110"; WHEN "0001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101101111101110110000111011010000111100011100100"; WHEN "0001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101100101011111100100100011010101111000101000111"; WHEN "0010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101011011010001010001010100110101000010011111000"; WHEN "0010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101010001000011111011000001011000011010110000100"; WHEN "0010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101000110110111100101011010001111001100111110010"; WHEN "0010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100111100101100010100010000001100000101010111010"; WHEN "0010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100110010100010001011010011100011100110101011100"; WHEN "0010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100101000011001001110010100001010100000101101100"; WHEN "0010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100011110010001100001000001010100000110110000000"; WHEN "0010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100010100001011000111001001110000100110010111000"; WHEN "0011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100001010000110000100011011101011011110011010110"; WHEN "0011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100000000000010011100100100101001110110011000010"; WHEN "0011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011110110000000010011010001101000110110000011100"; WHEN "0011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011101011111111101100001110111011111101010000000"; WHEN "0011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011100010000000101011001000001011011100001111010"; WHEN "0011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011011000000011010011101000010010101100000110110"; WHEN "0011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011001110000111101001011001011110100111101110010"; WHEN "0011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011000100001101110000000101001100000101000010010"; WHEN "0100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010111010010101101011010100000110001110011110001"; WHEN "0100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010110000011111011110101110000100111100111110101"; WHEN "0100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010100110101011001101111010001011010010011110011"; WHEN "0100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010011100111000111100011110100101110100010111000"; WHEN "0100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010010011001000101110000000101001000110111000111"; WHEN "0100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010001001011010100110000100110000001000100101001"; WHEN "0100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001111111101110101000001110011010101110010001110"; WHEN "0100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001110110000100111000000000001011111111100011001"; WHEN "0101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001101100011101011000111011101000110011100100000"; WHEN "0101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001100010111000001110100001010110001110100101001"; WHEN "0101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001011001010101011100010000110111111111100011001"; WHEN "0101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001001111110101000101101000101110111110101110110"; WHEN "0101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001000110010111001110000110010111101100001101110"; WHEN "0101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000111100111011111001000110001000101111011110000"; WHEN "0101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000110011100011001010000011010001010111001000100"; WHEN "0101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000101010001101000100010111110111111001010110011"; WHEN "0110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000100000111001101011011100111000010100110100100"; WHEN "0110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000010111101001000010101010000010110010001100101"; WHEN "0110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000001110011011001101010101111010000110001110001"; WHEN "0110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000000101010000001110110101110010010100010001010"; WHEN "0110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111111100001000001010011101101111010001101110100"; WHEN "0110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111110011000011000011100000100011001001100111111"; WHEN "0110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111101010000000111101001111101101000001001100111"; WHEN "0110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111100001000001111010111011010111011101000011000"; WHEN "0111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111011000000101111111110010010111000110100000100"; WHEN "0111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111001111001101001111000010001001010010011000111"; WHEN "0111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111000110010111101011110110110010100111101001111"; WHEN "0111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110111101100101011001011010111101100111001001111"; WHEN "0111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110110100110110011010110111111001010011111110011"; WHEN "0111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110101100001010110011010101010111111100100001011"; WHEN "0111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110100011100010100101111001101101100100000011010"; WHEN "0111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110011010111101110101101001101110101101001000101"; WHEN "1000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110010010011100100101101000101111000100111000101"; WHEN "1000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110001001111110111000111000100000001110100110010"; WHEN "1000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110000001100100110010011001010000010000100100001"; WHEN "1000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101111001001110010101001001101000100001000011111"; WHEN "1000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101110000111011100100000110101100010100101111011"; WHEN "1000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101101000101100100010001011110111101101010011001"; WHEN "1000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101100000100001010010010010111110001001000100100"; WHEN "1000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101011000011001110111010100001001010011011010001"; WHEN "1001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101010000010110010100000101110111110101110111011"; WHEN "1001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101001000010110101011011100111100001010010001010"; WHEN "1001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101000000011011000000001100011011001101001101101"; WHEN "1001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100111000100011010101000101101011010001111110100"; WHEN "1001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100110000101111101100111000010010110110101001010"; WHEN "1001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100101001000000001010010010000111011001100101001"; WHEN "1001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100100001010100101111111111001100001111011011000"; WHEN "1001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100011001101101100000101001110001011001110111100"; WHEN "1010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100010010001010011110111010010010011111110100100"; WHEN "1010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100001010101011101101010111010101100101110000010"; WHEN "1010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100000011010001001110100101101010000111010011101"; WHEN "1010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011111011111011000101001000000111110001110111111"; WHEN "1010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011110100101001010011011111101101011111101000010"; WHEN "1010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011101101011011111100001011100000010100000001101"; WHEN "1010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011100110010011000001101000101010011000110001101"; WHEN "1010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011111001110100110010010011001111011110111011"; WHEN "1011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011000001110101100100010000000001110100011101"; WHEN "1011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011010001010011010110101110110000100101001100010"; WHEN "1011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011001010011100100111001101111111011000001100001"; WHEN "1011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011000011101010100000010011000001000101101011001"; WHEN "1011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010111100111101000100001111001001010100001001100"; WHEN "1011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010110110010100010101010001101001110110001111011"; WHEN "1011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101111110000010101100111110001101111011011100"; WHEN "1011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101001010001000111011100101100011001011100101"; WHEN "1100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010100010110110101100111001100000101011000010000"; WHEN "1100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010011100100001001000000101001111111111010110011"; WHEN "1100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010110010000011011000100110101011110110000011"; WHEN "1100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010000000100100111111011000101001000001000001"; WHEN "1100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010001001111101110000101000101010111011100100101"; WHEN "1100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010000011111011110111001100001010000110000001000"; WHEN "1100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111101111110111101100001111100001101100011111"; WHEN "1100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111000000111000101100100010000011111010101010"; WHEN "1101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001110010010100010001001011001010111110000100010"; WHEN "1101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001101100100110100010001100100011110001100110110"; WHEN "1101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100110111101111010011100000110010111101110011"; WHEN "1101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100001011010011011101011010000110101111000110"; WHEN "1101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001011011111100000111101001010011001011111101101"; WHEN "1101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010110100011000000000011001110101000000001010"; WHEN "1101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010001001111000110100011110100111011011010110"; WHEN "1101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001001100000000011100110011100111110000011010110"; WHEN "1110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000110110111000100011000111000000001100101100"; WHEN "1110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000001110010111110110111100101010001100011100"; WHEN "1110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000111100110100001101110001011101000100010101000"; WHEN "1110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110111111010110010100101111010011001100111001"; WHEN "1110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110011000110101110110010000101000111111101001"; WHEN "1110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101110011000000011110000110001011001010001101"; WHEN "1110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101001101110110010111010011111001000001110011"; WHEN "1110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100101001010111101100101011001011110111111001"; WHEN "1111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100000101100100101000101010110010110110110011"; WHEN "1111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011100010011101010101011110101111000111101111"; WHEN "1111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011000000000001111101000000010000000010001101"; WHEN "1111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000010011110010010101000110101101111100100010110"; WHEN "1111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001111101001111100010010010101110110011110010"; WHEN "1111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001011100111000110010010111110010100110111110"; WHEN "1111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000111101001110100001110010100000011000001001"; WHEN "1111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000011110010000111000111101011011000001000111"; WHEN OTHERS => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; END CASE; -- End reserved scope level END PROCESS; --cIncludingRoundingBit_uid253_sinPiZPolyEval(BITJOIN,252)@26 cIncludingRoundingBit_uid253_sinPiZPolyEval_q <= memoryC1_uid227_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0(REG,408)@26 reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid253_sinPiZPolyEval_q; END IF; END PROCESS; --ts4_uid254_sinPiZPolyEval(ADD,253)@27 ts4_uid254_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((52 downto 52 => reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q(51)) & reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q); ts4_uid254_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((52 downto 46 => reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q(45)) & reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q); ts4_uid254_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid254_sinPiZPolyEval_a) + SIGNED(ts4_uid254_sinPiZPolyEval_b)); ts4_uid254_sinPiZPolyEval_q <= ts4_uid254_sinPiZPolyEval_o(52 downto 0); --s4_uid255_sinPiZPolyEval(BITSELECT,254)@27 s4_uid255_sinPiZPolyEval_in <= ts4_uid254_sinPiZPolyEval_q; s4_uid255_sinPiZPolyEval_b <= s4_uid255_sinPiZPolyEval_in(52 downto 1); --yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval(BITSELECT,301)@27 yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b; yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in(51 downto 25); --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9(REG,409)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor(LOGICAL,1117) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q <= not (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a or ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top(CONSTANT,1113) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q <= "010011"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp(LOGICAL,1114) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a = ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b else "0"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg(REG,1115) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena(REG,1118) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q = "1") THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd(LOGICAL,1119) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a and ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b; --xBottomBits_uid305_pT5_uid257_sinPiZPolyEval(BITSELECT,304)@5 xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b(17 downto 0); xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt(COUNTER,1109) -- every=1, low=0, high=19, step=1, init=1 ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i = 18 THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '1'; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i - 19; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i,5)); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg(REG,1110) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux(MUX,1111) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q) BEGIN CASE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s IS WHEN "0" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; WHEN "1" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; WHEN OTHERS => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem(DUALMEM,1108) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 <= areset; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 5, numwords_a => 20, width_b => 18, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0, clock1 => clk, address_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq, address_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa, data_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia ); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg(DELAY,1107) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q, xout => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q, clk => clk, aclr => areset ); --pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval(BITJOIN,306)@27 pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7(REG,411)@27 reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid304_pT5_uid257_sinPiZPolyEval(BITSELECT,303)@27 yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b(24 downto 0); yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b <= yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a(DELAY,750)@27 ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b, xout => ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval(BITJOIN,305)@28 spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q; --pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval(BITJOIN,307)@28 pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q <= spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q & GND_q; --reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6(REG,410)@28 reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor(LOGICAL,1104) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top(CONSTANT,1100) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q <= "010100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp(LOGICAL,1101) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg(REG,1102) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena(REG,1105) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd(LOGICAL,1106) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1096) -- every=1, low=0, high=20, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i = 19 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i - 20; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i,5)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg(REG,1097) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux(MUX,1098) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem(DUALMEM,1095) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 5, numwords_a => 21, width_b => 45, widthad_b => 5, numwords_b => 21, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg(DELAY,1094) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval(BITSELECT,300)@28 xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q; xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in(44 downto 18); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4(REG,412)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma(CHAINMULTADD,347)@29 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval(BITSELECT,309)@32 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in(54 downto 1); --highBBits_uid312_pT5_uid257_sinPiZPolyEval(BITSELECT,311)@32 highBBits_uid312_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b; highBBits_uid312_pT5_uid257_sinPiZPolyEval_b <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_in(53 downto 25); --reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1(REG,415)@32 reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1(REG,413)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b(DELAY,747)@28 ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0(REG,414)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid303_pT5_uid257_sinPiZPolyEval(MULT,302)@29 topProd_uid303_pT5_uid257_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_b); topProd_uid303_pT5_uid257_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid303_pT5_uid257_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid303_pT5_uid257_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0(REG,416)@32 reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid313_pT5_uid257_sinPiZPolyEval(ADD,312)@33 sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q(53)) & reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b)); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid311_pT5_uid257_sinPiZPolyEval(BITSELECT,310)@32 lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b(24 downto 0); lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b <= lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a(DELAY,758)@32 ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b, xout => ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid311_uid314_pT5_uid257_sinPiZPolyEval(BITJOIN,313)@33 add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q & ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q; --R_uid315_pT5_uid257_sinPiZPolyEval(BITSELECT,314)@33 R_uid315_pT5_uid257_sinPiZPolyEval_in <= add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q(78 downto 0); R_uid315_pT5_uid257_sinPiZPolyEval_b <= R_uid315_pT5_uid257_sinPiZPolyEval_in(78 downto 25); --reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1(REG,417)@33 reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= R_uid315_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor(LOGICAL,1142) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1138) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q <= "011001"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp(LOGICAL,1139) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg(REG,1140) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena(REG,1143) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1144) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1134) -- every=1, low=0, high=25, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i = 24 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i - 25; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg(REG,1135) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1136) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1133) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 26, width_b => 7, widthad_b => 5, numwords_b => 26, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg(DELAY,1132) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0(REG,379)@32 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC0_uid226_sinPiZTableGenerator(LOOKUP,225)@33 memoryC0_uid226_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; WHEN "0000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111010001111111001101111011000111100001001010"; WHEN "0000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000101010101111101111010001101100110011111100100"; WHEN "0000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000010000111010001110111000001110010011001110001"; WHEN "0000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001111101100101111100010000110111011000000101000010"; WHEN "0000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110111110001111110110010110011100111000110011101"; WHEN "0000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110000101011011011100110100000100010100111010101"; WHEN "0000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001101000010010010101010100001100000100101011101101"; WHEN "0001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001011110100110101111000010100110110100001011000010"; WHEN "0001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001010011101000101100010111000010101101001011110101"; WHEN "0001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001000111011000010001010101010001011100000010111010"; WHEN "0001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000111001110101100010011111100010101010110110110111"; WHEN "0001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000101011000000100100110110100010000001101000110010"; WHEN "0001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000011010111001011101111001010100111001000011000110"; WHEN "0001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000001001100000010011100101010111111111101111100110"; WHEN "0001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111110110110101001100010110011100110010010101101111"; WHEN "0010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111100010111000001111000110100110100110000010101111"; WHEN "0010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111001101101001100011001110000111100101111100011100"; WHEN "0010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110110111001001010000100011011101100011000000101111"; WHEN "0010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110011111010111011111011011001110010110110010111000"; WHEN "0010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110000110010100011000101000000100011000111000100110"; WHEN "0010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101101100000000000101011010101010100111001000011100"; WHEN "0010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101010000011010101111100001101000100000101011011110"; WHEN "0010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100110011100100100001001001011101110011110100001011"; WHEN "0011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100010101011101100100111100011101111110101100100111"; WHEN "0011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011110110000110000110000010101011100010111110000011"; WHEN "0011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011010101011110010000000001110011001100010100001001"; WHEN "0011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010110011100110001110111101000110101001111110010101"; WHEN "0011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010010000011110001111010101010111011011010001011111"; WHEN "0011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001101100000110011110001000110001001111001100110001"; WHEN "0011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001000110011111001000110010110100010111000011111111"; WHEN "0011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001000011111101000011101001100001111101100010010011001"; WHEN "0100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111110111100010101001101010111010101001011000110001"; WHEN "0100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111001110001101111101000001101110110110001001100100"; WHEN "0100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000110100011101010100110100000100001100111000110001110"; WHEN "0100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101110111111000110101110011111101010000010000111000"; WHEN "0100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101001010111000111011000101011010001011010101011100"; WHEN "0100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000100011100101011000110111010110111110001001101100111"; WHEN "0100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000011101101001111101010010110110101000111000011000010"; WHEN "0100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010111100100110110110111000001001011110110011001101"; WHEN "0101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010001010110000111110011001111100101011011000101100"; WHEN "0101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000001010111101110010011010011011111001000011101001111"; WHEN "0101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000000100011011111001000011000000001110101111000110101"; WHEN "0101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111111101110000011110000110110101110000111000001001000"; WHEN "0101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111110110111011100100000011010011101000101101101101111"; WHEN "0101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101111111101001101011001001101111001001010100111010"; WHEN "0101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101000110101011100101100110100011000001100101000111"; WHEN "0101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111100001100100010100100101110001100110101011111100110"; WHEN "0110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111011010001001110111101111001001100110110011000001101"; WHEN "0110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111010010100110001000110111011000110000110111110111111"; WHEN "0110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111001010111001001010110000010010100110110110111111101"; WHEN "0110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111000011000011000000001111000000100110010000101101101"; WHEN "0110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110111011000011101100001100000000111000101001011011010"; WHEN "0110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110110010111011010001100011000101000010101101011001001"; WHEN "0110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110101010101001110011010011010000110001111000101001011"; WHEN "0110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110100010001111010100011110111000101000100011101001111"; WHEN "0111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110011001101011111000001011100000101000110101010111101"; WHEN "0111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110010000111111100001100001111010111101111011010000110"; WHEN "0111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110001000001010010011101110000110100100001000000010111"; WHEN "0111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101111111001100010001111111001101101111011001101100100"; WHEN "0111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101110110000101011111100111100100110000100111011101101"; WHEN "0111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101101100110101111111111100101000011001011000100010101"; WHEN "0111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101100011011101110110010110111100011110100100000110011"; WHEN "0111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101011001111101000110010010001010011001011011010110110"; WHEN "1000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101010000010011110011001100111111100111011110011001101"; WHEN "1000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101000110100010000000101001001100001000111100100001001"; WHEN "1000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100111100100111110010001011100000111110000000101011101"; WHEN "1000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100110010100101001011011011101110100010101011000001110"; WHEN "1000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100101000011010010000000100100011001001010111111110011"; WHEN "1000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100011110000111000011110011101001010100010101110100101"; WHEN "1000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100010011101011101010011001100110001101101001100010111"; WHEN "1000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100001001001000000111101001110111111110000011100100111"; WHEN "1001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011111110011100011111011010110100000010100101010111001"; WHEN "1001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011110011101000110101100101100101100000111000011110001"; WHEN "1001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011101000101101001110000110001011011010011000000110010"; WHEN "1001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011011101101001101100111011010110111110001101101101010"; WHEN "1001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011010010011110010110000110101001111010000001101101100"; WHEN "1001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011000111001011001101101100010100101001100000111100110"; WHEN "1001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010111011110000010111110011010100100100110111110110011"; WHEN "1001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010110000001101111000100101010010001110000100000110101"; WHEN "1010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010100100100011110100001110011111011100111101101011110"; WHEN "1010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010011000110010001110111101110101101010011000000111111"; WHEN "1010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010001100111001001101000100110011111001111100111000001"; WHEN "1010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010000000111000110010110111011101000010111111101010001"; WHEN "1010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001110100110001000100101100010101111000001101101010100"; WHEN "1010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001101000100010000110111100100011001110011000100010010"; WHEN "1010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001011100001011111110000011101000000001111110000000000"; WHEN "1010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001001111101110101110011111100011011011101101000101110"; WHEN "1011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001000011001010011100110000101110110100001001110110000"; WHEN "1011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000110110011111001101011001111011110110010000011100000"; WHEN "1011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000101001101101000101000000010010100000111000101001110"; WHEN "1011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000011100110100001000001011001111000111011010101001101"; WHEN "1011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000001111110100011011100100100000010001010101111111000"; WHEN "1011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000000010101110000011111000000100111000111011110010110"; WHEN "1011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111110101100001000101110100001010001000111101001001101"; WHEN "1011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111101000001101100110001001001001011001011110100011010"; WHEN "1100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111011010110011101001101001100110001011110001011110000"; WHEN "1100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111001101010011010101001010001100000101010101000000111"; WHEN "1100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110111111101100101101100001101100101001111110101000001"; WHEN "1100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110110001111111110111101000111101010101001011110111000"; WHEN "1100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110100100001100111000011010110101010010011110001011110"; WHEN "1100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110010110010011110100110100001011010101000001111000001"; WHEN "1100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110001000010100110001110011110011101110100000111111001"; WHEN "1100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101111010001111110100011010011110000101000011010111010"; WHEN "1101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101101100000101000001101010110011001000011100110100101"; WHEN "1101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101011101110100011110101001010010100110101010011100110"; WHEN "1101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101001111011110010000011100010000111111100000000100011"; WHEN "1101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101000001000010011100001011110101010111100110111011100"; WHEN "1101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100110010100001000111000001110111001010101110101010001"; WHEN "1101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100100011111010010110001001111011111101010001100000100"; WHEN "1101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100010101001110001110110001010101001101001100111101111"; WHEN "1101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100000110011100110110000110111110000010001111110011101"; WHEN "1110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011110111100110010001011011011000111101011110100101010"; WHEN "1110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011101000101010100110000000101101101000001111101101101"; WHEN "1110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011011001101001111001001010100110100010100000001010111"; WHEN "1110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011001010100100010000001110001110110000100001110111001"; WHEN "1110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010111011011001110000100010001111101000000100110100000"; WHEN "1110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010101100001010011111011110101110011100111100001100101"; WHEN "1110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010011100110110100010011101001010001101000000010101011"; WHEN "1110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010001101011101111110111000011001001011101110101101100"; WHEN "1111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001111110000000111010001100100110101101001001001010110"; WHEN "1111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001101110011111011001110111010000110000010101010100001"; WHEN "1111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001011110111001100011010111000101101001011101010010011"; WHEN "1111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001001111001111011100001100000001101011010010111101001"; WHEN "1111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000111111100001001001110111001100110000010110101011110"; WHEN "1111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000101111101110110001111010111000000011100010110001010"; WHEN "1111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000011111111000011001111010011011101000011100101001111"; WHEN "1111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000001111111110000111011010010100000011001101000010011"; WHEN OTHERS => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid258_sinPiZPolyEval(CONSTANT,257) rndBit_uid258_sinPiZPolyEval_q <= "001"; --cIncludingRoundingBit_uid259_sinPiZPolyEval(BITJOIN,258)@33 cIncludingRoundingBit_uid259_sinPiZPolyEval_q <= memoryC0_uid226_sinPiZTableGenerator_q & rndBit_uid258_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0(REG,418)@33 reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid259_sinPiZPolyEval_q; END IF; END PROCESS; --ts5_uid260_sinPiZPolyEval(ADD,259)@34 ts5_uid260_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q); ts5_uid260_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((61 downto 54 => reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q(53)) & reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q); ts5_uid260_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid260_sinPiZPolyEval_a) + SIGNED(ts5_uid260_sinPiZPolyEval_b)); ts5_uid260_sinPiZPolyEval_q <= ts5_uid260_sinPiZPolyEval_o(61 downto 0); --s5_uid261_sinPiZPolyEval(BITSELECT,260)@34 s5_uid261_sinPiZPolyEval_in <= ts5_uid260_sinPiZPolyEval_q; s5_uid261_sinPiZPolyEval_b <= s5_uid261_sinPiZPolyEval_in(61 downto 1); --fxpSinRes_uid66_fpSinPiTest(BITSELECT,65)@34 fxpSinRes_uid66_fpSinPiTest_in <= s5_uid261_sinPiZPolyEval_b(58 downto 0); fxpSinRes_uid66_fpSinPiTest_b <= fxpSinRes_uid66_fpSinPiTest_in(58 downto 5); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor(LOGICAL,963) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q <= not (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a or ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top(CONSTANT,959) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q <= "011111"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp(LOGICAL,960) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q <= "1" when ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a = ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b else "0"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg(REG,961) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena(REG,964) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q = "1") THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd(LOGICAL,965) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a and ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt(COUNTER,955) -- every=1, low=0, high=31, step=1, init=1 ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ELSIF (clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg(REG,956) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux(MUX,957) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux: PROCESS (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem(DUALMEM,954) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia <= sinXIsX_uid30_fpSinPiTest_c; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 32, width_b => 1, widthad_b => 5, numwords_b => 32, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq, address_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa, data_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia ); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg(DELAY,953) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --multRightOp_uid68_fpSinPiTest(MUX,67)@34 multRightOp_uid68_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q; multRightOp_uid68_fpSinPiTest: PROCESS (multRightOp_uid68_fpSinPiTest_s, fxpSinRes_uid66_fpSinPiTest_b) BEGIN CASE multRightOp_uid68_fpSinPiTest_s IS WHEN "0" => multRightOp_uid68_fpSinPiTest_q <= fxpSinRes_uid66_fpSinPiTest_b; WHEN "1" => multRightOp_uid68_fpSinPiTest_q <= piwFP2_uid67_fpSinPiTest_q; WHEN OTHERS => multRightOp_uid68_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_b_1(BITSELECT,318)@34 mul2xSinRes_uid69_fpSinPiTest_b_1_in <= multRightOp_uid68_fpSinPiTest_q; mul2xSinRes_uid69_fpSinPiTest_b_1_b <= mul2xSinRes_uid69_fpSinPiTest_b_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1(REG,423)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor(LOGICAL,1129) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q <= not (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a or ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top(CONSTANT,1125) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q <= "010110"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp(LOGICAL,1126) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q <= "1" when ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a = ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b else "0"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg(REG,1127) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena(REG,1130) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q = "1") THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd(LOGICAL,1131) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a and ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor(LOGICAL,937) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a or ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top(CONSTANT,933) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q <= "0111"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp(LOGICAL,934) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a = ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b else "0"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg(REG,935) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena(REG,938) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q = "1") THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd(LOGICAL,939) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt(COUNTER,929) -- every=1, low=0, high=7, step=1, init=1 ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,3); ELSIF (clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i + 1; END IF; END PROCESS; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i,3)); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg(REG,930) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux(MUX,931) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q) BEGIN CASE ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s IS WHEN "0" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; WHEN "1" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; WHEN OTHERS => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem(DUALMEM,928) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 <= areset; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia <= oFracX_uid31_uid31_fpSinPiTest_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 3, numwords_a => 8, width_b => 53, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq, address_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa, data_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia ); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq(52 downto 0); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg(DELAY,927) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg : dspba_delay GENERIC MAP ( width => 53, depth => 1 ) PORT MAP ( xin => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q, xout => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q, clk => clk, aclr => areset ); --LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest(BITSELECT,220)@10 LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q(77 downto 0); LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in(77 downto 0); --leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest(BITJOIN,221)@10 leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b & GND_q; --LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest(BITSELECT,204)@9 LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(54 downto 0); LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in(54 downto 0); --leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest(BITJOIN,205)@9 leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest(BITSELECT,201)@9 LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(62 downto 0); LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in(62 downto 0); --leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest(BITJOIN,202)@9 leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest(BITSELECT,198)@9 LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(70 downto 0); LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in(70 downto 0); --leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest(BITJOIN,199)@9 leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --ozz_uid41_fpSinPiTest(CONSTANT,40) ozz_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor(LOGICAL,1040) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q <= not (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a or ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top(CONSTANT,1036) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q <= "011"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp(LOGICAL,1037) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q <= "1" when ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a = ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b else "0"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg(REG,1038) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena(REG,1041) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q = "1") THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd(LOGICAL,1042) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a and ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b; --vStage_uid149_lzcZ_uid51_fpSinPiTest(BITSELECT,148)@4 vStage_uid149_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(14 downto 0); vStage_uid149_lzcZ_uid51_fpSinPiTest_b <= vStage_uid149_lzcZ_uid51_fpSinPiTest_in(14 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt(COUNTER,1032) -- every=1, low=0, high=3, step=1, init=1 ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,2); ELSIF (clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i,2)); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg(REG,1033) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux(MUX,1034) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1043) ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= vStage_uid149_lzcZ_uid51_fpSinPiTest_b; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 2, numwords_a => 4, width_b => 15, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(14 downto 0); --leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest(BITJOIN,193)@9 leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X46dto0_uid190_alignedZ_uid52_fpSinPiTest(BITSELECT,189)@4 X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(46 downto 0); X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in(46 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1031) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 47, widthad_a => 2, numwords_a => 4, width_b => 47, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(46 downto 0); --leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest(BITJOIN,190)@9 leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor(LOGICAL,1065) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q <= not (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a or ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top(CONSTANT,1061) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q <= "010"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp(LOGICAL,1062) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q <= "1" when ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a = ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b else "0"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg(REG,1063) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena(REG,1066) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q = "1") THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd(LOGICAL,1067) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a and ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt(COUNTER,1057) -- every=1, low=0, high=2, step=1, init=1 ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i = 1 THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i - 2; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i,2)); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg(REG,1058) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux(MUX,1059) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux: PROCESS (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem(DUALMEM,1056) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia <= z_uid49_fpSinPiTest_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 79, widthad_a => 2, numwords_a => 3, width_b => 79, widthad_b => 2, numwords_b => 3, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq, address_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa, data_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia ); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq(78 downto 0); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg(DELAY,1055) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q, xout => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --rVStage_uid146_lzcZ_uid51_fpSinPiTest(BITSELECT,145)@4 rVStage_uid146_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; rVStage_uid146_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_in(78 downto 15); --reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0(REG,365)@4 reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid147_lzcZ_uid51_fpSinPiTest(LOGICAL,146)@5 vCount_uid147_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid147_lzcZ_uid51_fpSinPiTest_a = vCount_uid147_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g(DELAY,629)@5 ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => vCount_uid147_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q, clk => clk, aclr => areset ); --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b(DELAY,587)@4 ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => vStage_uid149_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q, clk => clk, aclr => areset ); --mO_uid148_lzcZ_uid51_fpSinPiTest(CONSTANT,147) mO_uid148_lzcZ_uid51_fpSinPiTest_q <= "1111111111111111111111111111111111111111111111111"; --cStage_uid150_lzcZ_uid51_fpSinPiTest(BITJOIN,149)@5 cStage_uid150_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q & mO_uid148_lzcZ_uid51_fpSinPiTest_q; --ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c(DELAY,589)@4 ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 64, depth => 1 ) PORT MAP ( xin => rVStage_uid146_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid152_lzcZ_uid51_fpSinPiTest(MUX,151)@5 vStagei_uid152_lzcZ_uid51_fpSinPiTest_s <= vCount_uid147_lzcZ_uid51_fpSinPiTest_q; vStagei_uid152_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid152_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, cStage_uid150_lzcZ_uid51_fpSinPiTest_q) BEGIN CASE vStagei_uid152_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= cStage_uid150_lzcZ_uid51_fpSinPiTest_q; WHEN OTHERS => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid154_lzcZ_uid51_fpSinPiTest(BITSELECT,153)@5 rVStage_uid154_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q; rVStage_uid154_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_in(63 downto 32); --reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0(REG,366)@5 reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= "00000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid155_lzcZ_uid51_fpSinPiTest(LOGICAL,154)@6 vCount_uid155_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid155_lzcZ_uid51_fpSinPiTest_a = vCount_uid155_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f(DELAY,628)@6 ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid155_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q, clk => clk, aclr => areset ); --vStage_uid156_lzcZ_uid51_fpSinPiTest(BITSELECT,155)@5 vStage_uid156_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q(31 downto 0); vStage_uid156_lzcZ_uid51_fpSinPiTest_b <= vStage_uid156_lzcZ_uid51_fpSinPiTest_in(31 downto 0); --ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d(DELAY,596)@5 ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => vStage_uid156_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c(DELAY,595)@5 ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => rVStage_uid154_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid158_lzcZ_uid51_fpSinPiTest(MUX,157)@6 vStagei_uid158_lzcZ_uid51_fpSinPiTest_s <= vCount_uid155_lzcZ_uid51_fpSinPiTest_q; vStagei_uid158_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid158_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid158_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid160_lzcZ_uid51_fpSinPiTest(BITSELECT,159)@6 rVStage_uid160_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q; rVStage_uid160_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_in(31 downto 16); --reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0(REG,367)@6 reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid161_lzcZ_uid51_fpSinPiTest(LOGICAL,160)@7 vCount_uid161_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid161_lzcZ_uid51_fpSinPiTest_a = vCount_uid161_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e(DELAY,627)@7 ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid161_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q, clk => clk, aclr => areset ); --vStage_uid162_lzcZ_uid51_fpSinPiTest(BITSELECT,161)@6 vStage_uid162_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q(15 downto 0); vStage_uid162_lzcZ_uid51_fpSinPiTest_b <= vStage_uid162_lzcZ_uid51_fpSinPiTest_in(15 downto 0); --ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d(DELAY,602)@6 ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => vStage_uid162_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c(DELAY,601)@6 ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => rVStage_uid160_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid164_lzcZ_uid51_fpSinPiTest(MUX,163)@7 vStagei_uid164_lzcZ_uid51_fpSinPiTest_s <= vCount_uid161_lzcZ_uid51_fpSinPiTest_q; vStagei_uid164_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid164_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid164_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid166_lzcZ_uid51_fpSinPiTest(BITSELECT,165)@7 rVStage_uid166_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q; rVStage_uid166_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_in(15 downto 8); --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0(REG,368)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid167_lzcZ_uid51_fpSinPiTest(LOGICAL,166)@8 vCount_uid167_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid167_lzcZ_uid51_fpSinPiTest_a = vCount_uid167_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid168_lzcZ_uid51_fpSinPiTest(BITSELECT,167)@7 vStage_uid168_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q(7 downto 0); vStage_uid168_lzcZ_uid51_fpSinPiTest_b <= vStage_uid168_lzcZ_uid51_fpSinPiTest_in(7 downto 0); --reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3(REG,369)@7 reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= vStage_uid168_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2(REG,370)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vStagei_uid170_lzcZ_uid51_fpSinPiTest(MUX,169)@8 vStagei_uid170_lzcZ_uid51_fpSinPiTest_s <= vCount_uid167_lzcZ_uid51_fpSinPiTest_q; vStagei_uid170_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid170_lzcZ_uid51_fpSinPiTest_s, reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q, reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q) BEGIN CASE vStagei_uid170_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q; WHEN "1" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q; WHEN OTHERS => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid172_lzcZ_uid51_fpSinPiTest(BITSELECT,171)@8 rVStage_uid172_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q; rVStage_uid172_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_in(7 downto 4); --vCount_uid173_lzcZ_uid51_fpSinPiTest(LOGICAL,172)@8 vCount_uid173_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; vCount_uid173_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; vCount_uid173_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid173_lzcZ_uid51_fpSinPiTest_a = vCount_uid173_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid174_lzcZ_uid51_fpSinPiTest(BITSELECT,173)@8 vStage_uid174_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q(3 downto 0); vStage_uid174_lzcZ_uid51_fpSinPiTest_b <= vStage_uid174_lzcZ_uid51_fpSinPiTest_in(3 downto 0); --vStagei_uid176_lzcZ_uid51_fpSinPiTest(MUX,175)@8 vStagei_uid176_lzcZ_uid51_fpSinPiTest_s <= vCount_uid173_lzcZ_uid51_fpSinPiTest_q; vStagei_uid176_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid176_lzcZ_uid51_fpSinPiTest_s, rVStage_uid172_lzcZ_uid51_fpSinPiTest_b, vStage_uid174_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid176_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= vStage_uid174_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid178_lzcZ_uid51_fpSinPiTest(BITSELECT,177)@8 rVStage_uid178_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q; rVStage_uid178_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_in(3 downto 2); --vCount_uid179_lzcZ_uid51_fpSinPiTest(LOGICAL,178)@8 vCount_uid179_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; vCount_uid179_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; vCount_uid179_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid179_lzcZ_uid51_fpSinPiTest_a = vCount_uid179_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid180_lzcZ_uid51_fpSinPiTest(BITSELECT,179)@8 vStage_uid180_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q(1 downto 0); vStage_uid180_lzcZ_uid51_fpSinPiTest_b <= vStage_uid180_lzcZ_uid51_fpSinPiTest_in(1 downto 0); --vStagei_uid182_lzcZ_uid51_fpSinPiTest(MUX,181)@8 vStagei_uid182_lzcZ_uid51_fpSinPiTest_s <= vCount_uid179_lzcZ_uid51_fpSinPiTest_q; vStagei_uid182_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid182_lzcZ_uid51_fpSinPiTest_s, rVStage_uid178_lzcZ_uid51_fpSinPiTest_b, vStage_uid180_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid182_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= vStage_uid180_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid184_lzcZ_uid51_fpSinPiTest(BITSELECT,183)@8 rVStage_uid184_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid51_fpSinPiTest_q; rVStage_uid184_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_in(1 downto 1); --vCount_uid185_lzcZ_uid51_fpSinPiTest(LOGICAL,184)@8 vCount_uid185_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_b; vCount_uid185_lzcZ_uid51_fpSinPiTest_b <= GND_q; vCount_uid185_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid185_lzcZ_uid51_fpSinPiTest_a = vCount_uid185_lzcZ_uid51_fpSinPiTest_b else "0"; --r_uid186_lzcZ_uid51_fpSinPiTest(BITJOIN,185)@8 r_uid186_lzcZ_uid51_fpSinPiTest_q <= ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q & ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q & ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q & vCount_uid167_lzcZ_uid51_fpSinPiTest_q & vCount_uid173_lzcZ_uid51_fpSinPiTest_q & vCount_uid179_lzcZ_uid51_fpSinPiTest_q & vCount_uid185_lzcZ_uid51_fpSinPiTest_q; --leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest(BITSELECT,195)@8 leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q; leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in(6 downto 5); --reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1(REG,371)@8 reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest(MUX,196)@9 leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q, leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q; WHEN "01" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ozz_uid41_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest(BITSELECT,206)@8 leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(4 downto 0); leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in(4 downto 3); --reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1(REG,372)@8 reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest(MUX,207)@9 leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s, leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest(BITSELECT,215)@9 LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(72 downto 0); LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in(72 downto 0); --leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest(BITJOIN,216)@9 leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5(REG,374)@9 reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest(BITSELECT,212)@9 LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest(BITJOIN,213)@9 leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4(REG,375)@9 reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest(BITSELECT,209)@9 LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest(BITJOIN,210)@9 leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3(REG,376)@9 reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2(REG,377)@9 reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest(BITSELECT,217)@8 leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(2 downto 0); leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in(2 downto 1); --reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1(REG,373)@8 reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b(DELAY,657)@9 ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest(MUX,218)@10 leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s, reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q, reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q, reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q, reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q) BEGIN CASE leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q; WHEN "01" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q; WHEN "10" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q; WHEN "11" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q; WHEN OTHERS => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest(BITSELECT,222)@8 leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(0 downto 0); leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in(0 downto 0); --reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1(REG,378)@8 reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b(DELAY,665)@9 ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest(MUX,223)@10 leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s, leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q, leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q; WHEN "1" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --alignedZLow_uid53_fpSinPiTest(BITSELECT,52)@10 alignedZLow_uid53_fpSinPiTest_in <= leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q; alignedZLow_uid53_fpSinPiTest_b <= alignedZLow_uid53_fpSinPiTest_in(78 downto 27); --pHardCase_uid54_fpSinPiTest(BITJOIN,53)@10 pHardCase_uid54_fpSinPiTest_q <= alignedZLow_uid53_fpSinPiTest_b & GND_q; --ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b(DELAY,474)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 10 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q, clk => clk, aclr => areset ); --p_uid55_fpSinPiTest(MUX,54)@10 p_uid55_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q; p_uid55_fpSinPiTest: PROCESS (p_uid55_fpSinPiTest_s, pHardCase_uid54_fpSinPiTest_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q) BEGIN CASE p_uid55_fpSinPiTest_s IS WHEN "0" => p_uid55_fpSinPiTest_q <= pHardCase_uid54_fpSinPiTest_q; WHEN "1" => p_uid55_fpSinPiTest_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q; WHEN OTHERS => p_uid55_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt(COUNTER,1121) -- every=1, low=0, high=22, step=1, init=1 ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i = 21 THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i - 22; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i,5)); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg(REG,1122) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux(MUX,1123) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux: PROCESS (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q) BEGIN CASE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s IS WHEN "0" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; WHEN "1" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem(DUALMEM,1120) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 <= areset; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia <= p_uid55_fpSinPiTest_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 5, numwords_a => 23, width_b => 53, widthad_b => 5, numwords_b => 23, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq, address_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa, data_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia ); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq(52 downto 0); --mul2xSinRes_uid69_fpSinPiTest_a_1(BITSELECT,316)@34 mul2xSinRes_uid69_fpSinPiTest_a_1_in <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q); mul2xSinRes_uid69_fpSinPiTest_a_1_b <= mul2xSinRes_uid69_fpSinPiTest_a_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0(REG,424)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b1(MULT,322)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_b); mul2xSinRes_uid69_fpSinPiTest_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1(BITSELECT,329)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1(REG,425)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a_0(BITSELECT,315)@34 mul2xSinRes_uid69_fpSinPiTest_a_0_in <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_a_0_b <= mul2xSinRes_uid69_fpSinPiTest_a_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0(REG,426)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b1(MULT,321)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_b); mul2xSinRes_uid69_fpSinPiTest_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1(BITSELECT,327)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_zero_36(CONSTANT,332) mul2xSinRes_uid69_fpSinPiTest_zero_36_q <= "000000000000000000000000000"; --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2(BITJOIN,336)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1(BITSELECT,328)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_b_0(BITSELECT,317)@34 mul2xSinRes_uid69_fpSinPiTest_b_0_in <= multRightOp_uid68_fpSinPiTest_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_b_0_b <= mul2xSinRes_uid69_fpSinPiTest_b_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1(REG,421)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0(REG,422)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b0(MULT,320)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_b); mul2xSinRes_uid69_fpSinPiTest_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0(BITSELECT,325)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1(BITJOIN,335)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC(LOGICAL,340)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b; --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1(BITSELECT,330)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0(BITSELECT,326)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1(REG,419)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0(REG,420)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b0(MULT,319)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_b); mul2xSinRes_uid69_fpSinPiTest_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0(BITSELECT,324)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0(BITSELECT,323)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0(BITJOIN,334)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC(LOGICAL,339)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB(LOGICAL,338)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne(LOGICAL,341)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c; --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS(BITSELECT,342)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q(106 downto 0); mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in(106 downto 0); --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ(BITJOIN,343)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b & GND_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b(BITJOIN,350)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b(BITSELECT,353)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne(LOGICAL,337)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a(BITJOIN,348)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a(BITSELECT,352)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2(ADD,354)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin <= GND_q; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b) & mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c(0) <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(90); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(89 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b(DELAY,822)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q, clk => clk, aclr => areset ); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a(DELAY,821)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2(ADD,355)@39 mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q) & mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o(20 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a(DELAY,824)@39 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a : dspba_delay GENERIC MAP ( width => 89, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q(BITJOIN,356)@40 mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q; --normBit_uid70_fpSinPiTest(BITSELECT,69)@40 normBit_uid70_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(106 downto 0); normBit_uid70_fpSinPiTest_b <= normBit_uid70_fpSinPiTest_in(106 downto 106); --ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c(DELAY,497)@40 ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => normBit_uid70_fpSinPiTest_b, xout => ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q, clk => clk, aclr => areset ); --rndExpUpdate_uid75_uid76_fpSinPiTest(BITJOIN,75)@41 rndExpUpdate_uid75_uid76_fpSinPiTest_q <= ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q & cstAllZWF_uid10_fpSinPiTest_q & VCC_q; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor(LOGICAL,976) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q <= not (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a or ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top(CONSTANT,972) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q <= "011100"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp(LOGICAL,973) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a = ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b else "0"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg(REG,974) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena(REG,977) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q = "1") THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd(LOGICAL,978) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a and ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem(DUALMEM,941) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 <= areset; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia <= expX_uid6_fpSinPiTest_b; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 3, numwords_a => 7, width_b => 11, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq, address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa, data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia ); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq(10 downto 0); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg(DELAY,940) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q, clk => clk, aclr => areset ); --expXP1_uid58_fpSinPiTest(ADD,57)@9 expXP1_uid58_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q); expXP1_uid58_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & VCC_q); expXP1_uid58_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid58_fpSinPiTest_a) + UNSIGNED(expXP1_uid58_fpSinPiTest_b)); expXP1_uid58_fpSinPiTest_q <= expXP1_uid58_fpSinPiTest_o(11 downto 0); --expXP1R_uid59_fpSinPiTest(BITSELECT,58)@9 expXP1R_uid59_fpSinPiTest_in <= expXP1_uid58_fpSinPiTest_q(10 downto 0); expXP1R_uid59_fpSinPiTest_b <= expXP1R_uid59_fpSinPiTest_in(10 downto 0); --reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1(REG,427)@8 reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= r_uid186_lzcZ_uid51_fpSinPiTest_q; END IF; END PROCESS; --expHardCase_uid57_fpSinPiTest(SUB,56)@9 expHardCase_uid57_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid27_fpSinPiTest_q); expHardCase_uid57_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000" & reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q); expHardCase_uid57_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid57_fpSinPiTest_a) - UNSIGNED(expHardCase_uid57_fpSinPiTest_b)); expHardCase_uid57_fpSinPiTest_q <= expHardCase_uid57_fpSinPiTest_o(11 downto 0); --expHardCaseR_uid60_fpSinPiTest(BITSELECT,59)@9 expHardCaseR_uid60_fpSinPiTest_in <= expHardCase_uid57_fpSinPiTest_q(10 downto 0); expHardCaseR_uid60_fpSinPiTest_b <= expHardCaseR_uid60_fpSinPiTest_in(10 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b(DELAY,481)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 9 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q, clk => clk, aclr => areset ); --expP_uid61_fpSinPiTest(MUX,60)@9 expP_uid61_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q; expP_uid61_fpSinPiTest: PROCESS (expP_uid61_fpSinPiTest_s, expHardCaseR_uid60_fpSinPiTest_b, expXP1R_uid59_fpSinPiTest_b) BEGIN CASE expP_uid61_fpSinPiTest_s IS WHEN "0" => expP_uid61_fpSinPiTest_q <= expHardCaseR_uid60_fpSinPiTest_b; WHEN "1" => expP_uid61_fpSinPiTest_q <= expXP1R_uid59_fpSinPiTest_b; WHEN OTHERS => expP_uid61_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt(COUNTER,968) -- every=1, low=0, high=28, step=1, init=1 ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i = 27 THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i - 28; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg(REG,969) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux(MUX,970) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem(DUALMEM,967) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia <= expP_uid61_fpSinPiTest_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 29, width_b => 11, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq, address_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa, data_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia ); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq(10 downto 0); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg(DELAY,966) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q, xout => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --highRes_uid71_fpSinPiTest(BITSELECT,70)@40 highRes_uid71_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(105 downto 0); highRes_uid71_fpSinPiTest_b <= highRes_uid71_fpSinPiTest_in(105 downto 53); --lowRes_uid72_fpSinPiTest(BITSELECT,71)@40 lowRes_uid72_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(104 downto 0); lowRes_uid72_fpSinPiTest_b <= lowRes_uid72_fpSinPiTest_in(104 downto 52); --fracRCompPreRnd_uid73_fpSinPiTest(MUX,72)@40 fracRCompPreRnd_uid73_fpSinPiTest_s <= normBit_uid70_fpSinPiTest_b; fracRCompPreRnd_uid73_fpSinPiTest: PROCESS (fracRCompPreRnd_uid73_fpSinPiTest_s, lowRes_uid72_fpSinPiTest_b, highRes_uid71_fpSinPiTest_b) BEGIN CASE fracRCompPreRnd_uid73_fpSinPiTest_s IS WHEN "0" => fracRCompPreRnd_uid73_fpSinPiTest_q <= lowRes_uid72_fpSinPiTest_b; WHEN "1" => fracRCompPreRnd_uid73_fpSinPiTest_q <= highRes_uid71_fpSinPiTest_b; WHEN OTHERS => fracRCompPreRnd_uid73_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracPreRnd_uid74_uid74_fpSinPiTest(BITJOIN,73)@40 expFracPreRnd_uid74_uid74_fpSinPiTest_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q & fracRCompPreRnd_uid73_fpSinPiTest_q; --reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0(REG,428)@40 reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= expFracPreRnd_uid74_uid74_fpSinPiTest_q; END IF; END PROCESS; --expFracComp_uid77_fpSinPiTest(ADD,76)@41 expFracComp_uid77_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q); expFracComp_uid77_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & rndExpUpdate_uid75_uid76_fpSinPiTest_q); expFracComp_uid77_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid77_fpSinPiTest_a) + UNSIGNED(expFracComp_uid77_fpSinPiTest_b)); expFracComp_uid77_fpSinPiTest_q <= expFracComp_uid77_fpSinPiTest_o(64 downto 0); --expRComp_uid79_fpSinPiTest(BITSELECT,78)@41 expRComp_uid79_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(63 downto 0); expRComp_uid79_fpSinPiTest_b <= expRComp_uid79_fpSinPiTest_in(63 downto 53); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor(LOGICAL,1015) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q <= not (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a or ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top(CONSTANT,1011) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q <= "0100010"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp(LOGICAL,1012) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q <= "1" when ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a = ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b else "0"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg(REG,1013) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena(REG,1016) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q = "1") THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd(LOGICAL,1017) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a and ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b; --reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1(REG,429)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c(DELAY,516)@0 ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q, xout => ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b(DELAY,515)@0 ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => expXIsZero_uid15_fpSinPiTest_q, xout => ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q, clk => clk, aclr => areset ); --reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0(REG,361)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --excRZero_uid87_fpSinPiTest(LOGICAL,86)@3 excRZero_uid87_fpSinPiTest_a <= reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q; excRZero_uid87_fpSinPiTest_b <= ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q; excRZero_uid87_fpSinPiTest_c <= ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q; excRZero_uid87_fpSinPiTest_q <= excRZero_uid87_fpSinPiTest_a or excRZero_uid87_fpSinPiTest_b or excRZero_uid87_fpSinPiTest_c; --Or2ExcRZeroXIsInt_uid92_fpSinPiTest(LOGICAL,91)@3 Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a <= excRZero_uid87_fpSinPiTest_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b <= reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a or Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt(COUNTER,1007) -- every=1, low=0, high=34, step=1, init=1 ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i = 33 THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i - 34; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg(REG,1008) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux(MUX,1009) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux: PROCESS (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem(DUALMEM,1006) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 35, width_b => 1, widthad_b => 6, numwords_b => 35, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq, address_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa, data_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia ); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg(DELAY,1005) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q, xout => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --expRPostExc1_uid95_fpSinPiTest(MUX,94)@41 expRPostExc1_uid95_fpSinPiTest_s <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q; expRPostExc1_uid95_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE expRPostExc1_uid95_fpSinPiTest_s IS WHEN "0" => expRPostExc1_uid95_fpSinPiTest_q <= expRComp_uid79_fpSinPiTest_b; WHEN "1" => expRPostExc1_uid95_fpSinPiTest_q <= cstAllZWE_uid11_fpSinPiTest_q; WHEN OTHERS => expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --InvXIntExp_uid84_fpSinPiTest(LOGICAL,83)@2 InvXIntExp_uid84_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; InvXIntExp_uid84_fpSinPiTest_q <= not InvXIntExp_uid84_fpSinPiTest_a; --join_uid42_fpSinPiTest(BITJOIN,41)@2 join_uid42_fpSinPiTest_q <= VCC_q & ozz_uid41_fpSinPiTest_q; --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0(REG,359)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid43_fpSinPiTest(LOGICAL,42)@2 yIsZero_uid43_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q; yIsZero_uid43_fpSinPiTest_b <= join_uid42_fpSinPiTest_q; yIsZero_uid43_fpSinPiTest_q <= "1" when yIsZero_uid43_fpSinPiTest_a = yIsZero_uid43_fpSinPiTest_b else "0"; --And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest(LOGICAL,85)@2 And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b <= yIsZero_uid43_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c <= InvSinXIsX_uid80_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d <= InvXIntExp_uid84_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d; --Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest(LOGICAL,95)@1 Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a <= GND_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q <= Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a or Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b; --ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a(DELAY,528)@1 ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q, xout => ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q, clk => clk, aclr => areset ); --join_uid97_fpSinPiTest(BITJOIN,96)@2 join_uid97_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q & ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q; --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg(DELAY,1195) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => join_uid97_fpSinPiTest_q, xout => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q, clk => clk, aclr => areset ); --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem(DUALMEM,1196) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 <= areset; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 6, numwords_a => 37, width_b => 2, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0, clock1 => clk, address_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq, address_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa, data_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia ); ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq(1 downto 0); --reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1(REG,430)@41 reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q; END IF; END PROCESS; --expRPostExc_uid98_fpSinPiTest(MUX,97)@42 expRPostExc_uid98_fpSinPiTest_s <= reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q; expRPostExc_uid98_fpSinPiTest: PROCESS (expRPostExc_uid98_fpSinPiTest_s, expRPostExc1_uid95_fpSinPiTest_q) BEGIN CASE expRPostExc_uid98_fpSinPiTest_s IS WHEN "00" => expRPostExc_uid98_fpSinPiTest_q <= expRPostExc1_uid95_fpSinPiTest_q; WHEN "01" => expRPostExc_uid98_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q; WHEN "10" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN "11" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN OTHERS => expRPostExc_uid98_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --oneFracRPostExc2_uid90_fpSinPiTest(CONSTANT,89) oneFracRPostExc2_uid90_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracRComp_uid78_fpSinPiTest(BITSELECT,77)@41 fracRComp_uid78_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(52 downto 0); fracRComp_uid78_fpSinPiTest_b <= fracRComp_uid78_fpSinPiTest_in(52 downto 1); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor(LOGICAL,989) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q <= not (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a or ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top(CONSTANT,985) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q <= "0100001"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp(LOGICAL,986) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q <= "1" when ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a = ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b else "0"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg(REG,987) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena(REG,990) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q = "1") THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd(LOGICAL,991) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a and ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b; --reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1(REG,362)@3 reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= excRZero_uid87_fpSinPiTest_q; END IF; END PROCESS; --ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a(DELAY,517)@2 ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q, xout => ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q, clk => clk, aclr => areset ); --or_uid88_fpSinPiTest(LOGICAL,87)@4 or_uid88_fpSinPiTest_a <= ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q; or_uid88_fpSinPiTest_b <= reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q; or_uid88_fpSinPiTest_c <= GND_q; or_uid88_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN or_uid88_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN or_uid88_fpSinPiTest_q <= or_uid88_fpSinPiTest_a or or_uid88_fpSinPiTest_b or or_uid88_fpSinPiTest_c; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt(COUNTER,981) -- every=1, low=0, high=33, step=1, init=1 ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i = 32 THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i - 33; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg(REG,982) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux(MUX,983) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux: PROCESS (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem(DUALMEM,980) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia <= or_uid88_fpSinPiTest_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 34, width_b => 1, widthad_b => 6, numwords_b => 34, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq, address_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa, data_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia ); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg(DELAY,979) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q, xout => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --fracRPostExc1_uid89_fpSinPiTest(MUX,88)@41 fracRPostExc1_uid89_fpSinPiTest_s <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q; fracRPostExc1_uid89_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE fracRPostExc1_uid89_fpSinPiTest_s IS WHEN "0" => fracRPostExc1_uid89_fpSinPiTest_q <= fracRComp_uid78_fpSinPiTest_b; WHEN "1" => fracRPostExc1_uid89_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q; WHEN OTHERS => fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor(LOGICAL,1002) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q <= not (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a or ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top(CONSTANT,998) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q <= "0100110"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp(LOGICAL,999) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q <= "1" when ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a = ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b else "0"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg(REG,1000) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena(REG,1003) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q = "1") THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd(LOGICAL,1004) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a and ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg(DELAY,992) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q, xout => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q, clk => clk, aclr => areset ); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt(COUNTER,994) -- every=1, low=0, high=38, step=1, init=1 ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i = 37 THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i - 38; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg(REG,995) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux(MUX,996) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux: PROCESS (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem(DUALMEM,993) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 39, width_b => 1, widthad_b => 6, numwords_b => 39, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq, address_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa, data_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia ); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq(0 downto 0); --fracRPostExc_uid91_fpSinPiTest(MUX,90)@42 fracRPostExc_uid91_fpSinPiTest_s <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q; fracRPostExc_uid91_fpSinPiTest: PROCESS (fracRPostExc_uid91_fpSinPiTest_s, fracRPostExc1_uid89_fpSinPiTest_q) BEGIN CASE fracRPostExc_uid91_fpSinPiTest_s IS WHEN "0" => fracRPostExc_uid91_fpSinPiTest_q <= fracRPostExc1_uid89_fpSinPiTest_q; WHEN "1" => fracRPostExc_uid91_fpSinPiTest_q <= oneFracRPostExc2_uid90_fpSinPiTest_q; WHEN OTHERS => fracRPostExc_uid91_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid105_fpSinPiTest(BITJOIN,104)@42 R_uid105_fpSinPiTest_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q & expRPostExc_uid98_fpSinPiTest_q & fracRPostExc_uid91_fpSinPiTest_q; --ld_xIn_v_to_xOut_v_nor(LOGICAL,910) ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b); --ld_xIn_v_to_xOut_v_mem_top(CONSTANT,906) ld_xIn_v_to_xOut_v_mem_top_q <= "0100111"; --ld_xIn_v_to_xOut_v_cmp(LOGICAL,907) ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q; ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q); ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0"; --ld_xIn_v_to_xOut_v_cmpReg(REG,908) ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_sticky_ena(REG,911) ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q; END IF; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,912) ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q; ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b; --ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,902) -- every=1, low=0, high=39, step=1, init=1 ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 38 THEN ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1'; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; END IF; IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 39; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,6)); --ld_xIn_v_to_xOut_v_replace_rdreg(REG,903) ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_replace_rdmux(MUX,904) ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q; ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q) BEGIN CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q; WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,914) ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset; ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c; ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 6, numwords_a => 40, width_b => 8, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_c_to_xOut_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_c_to_xOut_c_replace_mem_iq, address_a => ld_xIn_c_to_xOut_c_replace_mem_aa, data_a => ld_xIn_c_to_xOut_c_replace_mem_ia ); ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0); --ld_xIn_c_to_xOut_c_outputreg(DELAY,913) ld_xIn_c_to_xOut_c_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset ); --ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,901) ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset; ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v; ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 40, width_b => 1, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_v_to_xOut_v_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_v_to_xOut_v_replace_mem_iq, address_a => ld_xIn_v_to_xOut_v_replace_mem_aa, data_a => ld_xIn_v_to_xOut_v_replace_mem_ia ); ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0); --ld_xIn_v_to_xOut_v_outputreg(DELAY,900) ld_xIn_v_to_xOut_v_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset ); --xOut(PORTOUT,4)@42 xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q; xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q; xOut_0 <= R_uid105_fpSinPiTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Debug Version 12.0 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from SinPiDPStratixVf400 -- VHDL created on Wed Sep 05 17:55:57 2012 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; USE work.SinPiDPStratixVf400_safe_path.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; -- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240 entity SinPiDPStratixVf400 is port ( xIn_v : in std_logic_vector(0 downto 0); xIn_c : in std_logic_vector(7 downto 0); xIn_0 : in std_logic_vector(63 downto 0); xOut_v : out std_logic_vector(0 downto 0); xOut_c : out std_logic_vector(7 downto 0); xOut_0 : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic; bus_clk : in std_logic; h_areset : in std_logic ); end; architecture normal of SinPiDPStratixVf400 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBias_uid12_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBiasPwF_uid13_fpSinPiTest_q : std_logic_vector (10 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0); signal biasM1_uid27_fpSinPiTest_q : std_logic_vector (10 downto 0); signal biasMwShift_uid29_fpSinPiTest_q : std_logic_vector (10 downto 0); signal shiftBias_uid32_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cst01pWShift_uid34_fpSinPiTest_q : std_logic_vector (27 downto 0); signal ozz_uid41_fpSinPiTest_q : std_logic_vector (78 downto 0); signal cOne_uid44_fpSinPiTest_q : std_logic_vector (80 downto 0); signal oneMinusY_uid45_fpSinPiTest_a : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_b : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_o : std_logic_vector (81 downto 0); signal oneMinusY_uid45_fpSinPiTest_q : std_logic_vector (81 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_a : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_b : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_o : std_logic_vector (84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_c : std_logic_vector (0 downto 0); signal piwFP2_uid67_fpSinPiTest_q : std_logic_vector (53 downto 0); signal or_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_b : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_c : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_q : std_logic_vector (51 downto 0); signal oneFracRPostExc2_uid90_fpSinPiTest_q : std_logic_vector (51 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (10 downto 0); signal InvXIsInt_uid100_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIsInt_uid100_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (31 downto 0); signal leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (63 downto 0); signal leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (15 downto 0); signal leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (23 downto 0); signal leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (5 downto 0); signal mO_uid148_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (48 downto 0); signal memoryC3_uid229_sinPiZTableGenerator_q : std_logic_vector(34 downto 0); signal memoryC4_uid230_sinPiZTableGenerator_q : std_logic_vector(25 downto 0); signal memoryC5_uid231_sinPiZTableGenerator_q : std_logic_vector(16 downto 0); signal rndBit_uid246_sinPiZPolyEval_q : std_logic_vector (1 downto 0); signal rndBit_uid258_sinPiZPolyEval_q : std_logic_vector (2 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_a : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 : std_logic_vector (33 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr : SIGNED (34 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_q : std_logic_vector (33 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_a : std_logic_vector (25 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_zero_36_q : std_logic_vector (26 downto 0); type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type; signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q : std_logic_vector (36 downto 0); type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o : std_logic_vector (90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o : std_logic_vector (21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q : std_logic_vector (19 downto 0); signal reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q : std_logic_vector (80 downto 0); signal reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q : std_logic_vector (80 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q : std_logic_vector (0 downto 0); signal reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (31 downto 0); signal reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (15 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (7 downto 0); signal reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q : std_logic_vector (7 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q : std_logic_vector (7 downto 0); signal reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q : std_logic_vector (78 downto 0); signal reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q : std_logic_vector (16 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q : std_logic_vector (25 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q : std_logic_vector (16 downto 0); signal reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q : std_logic_vector (17 downto 0); signal reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q : std_logic_vector (36 downto 0); signal reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q : std_logic_vector (44 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q : std_logic_vector (45 downto 0); signal reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q : std_logic_vector (51 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q : std_logic_vector (53 downto 0); signal reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q : std_logic_vector (60 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q : std_logic_vector (26 downto 0); signal reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q : std_logic_vector (6 downto 0); signal reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q : std_logic_vector (78 downto 0); signal ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q : std_logic_vector (78 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q : std_logic_vector (78 downto 0); signal ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q : std_logic_vector (14 downto 0); signal ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (63 downto 0); signal ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (31 downto 0); signal ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (31 downto 0); signal ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (15 downto 0); signal ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (15 downto 0); signal ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q : std_logic_vector (0 downto 0); signal ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q : std_logic_vector (0 downto 0); signal ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (1 downto 0); signal ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (42 downto 0); signal ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q : std_logic_vector (88 downto 0); signal ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q : std_logic_vector (79 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic; signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic; signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic; signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 : std_logic; signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i : unsigned(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q : std_logic_vector (3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i : unsigned(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q : std_logic_vector (6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i : unsigned(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q : std_logic_vector (2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (14 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ir : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i : unsigned(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q : std_logic_vector (2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ir : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ir : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 : std_logic; signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ir : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0); signal yIsZero_uid40_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (18 downto 0); signal pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal z_uid49_fpSinPiTest_s : std_logic_vector (0 downto 0); signal z_uid49_fpSinPiTest_q : std_logic_vector (78 downto 0); signal expHardCase_uid57_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expHardCase_uid57_fpSinPiTest_q : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_q : std_logic_vector (11 downto 0); signal rndExpUpdate_uid75_uid76_fpSinPiTest_q : std_logic_vector (53 downto 0); signal expFracComp_uid77_fpSinPiTest_a : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_b : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_o : std_logic_vector (64 downto 0); signal expFracComp_uid77_fpSinPiTest_q : std_logic_vector (64 downto 0); signal fracRPostExc_uid91_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc_uid91_fpSinPiTest_q : std_logic_vector (51 downto 0); signal expRPostExc_uid98_fpSinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid98_fpSinPiTest_q : std_logic_vector (10 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal memoryC0_uid226_sinPiZTableGenerator_q : std_logic_vector(57 downto 0); signal memoryC1_uid227_sinPiZTableGenerator_q : std_logic_vector(49 downto 0); signal memoryC2_uid228_sinPiZTableGenerator_q : std_logic_vector(42 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_a : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_b : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_o : std_logic_vector (35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_q : std_logic_vector (35 downto 0); signal ts3_uid248_sinPiZPolyEval_a : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_b : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_o : std_logic_vector (45 downto 0); signal ts3_uid248_sinPiZPolyEval_q : std_logic_vector (45 downto 0); signal ts4_uid254_sinPiZPolyEval_a : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_b : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_o : std_logic_vector (52 downto 0); signal ts4_uid254_sinPiZPolyEval_q : std_logic_vector (52 downto 0); signal ts5_uid260_sinPiZPolyEval_a : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_b : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_o : std_logic_vector (61 downto 0); signal ts5_uid260_sinPiZPolyEval_q : std_logic_vector (61 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal join_uid42_fpSinPiTest_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal expX_uid6_fpSinPiTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSinPiTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSinPiTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSinPiTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0); signal expXIsMax_uid16_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSinPiTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid15_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_q : std_logic_vector(0 downto 0); signal xIntExp_uid26_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xIntExp_uid26_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xIntExp_uid26_fpSinPiTest_c : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xFrac_uid28_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_n : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_a : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_b : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_o : std_logic_vector (13 downto 0); signal sinXIsX_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0); signal shiftValue_uid33_fpSinPiTest_a : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_b : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_o : std_logic_vector (11 downto 0); signal shiftValue_uid33_fpSinPiTest_q : std_logic_vector (11 downto 0); signal oMyBottom_uid47_fpSinPiTest_in : std_logic_vector (78 downto 0); signal oMyBottom_uid47_fpSinPiTest_b : std_logic_vector (78 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid150_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal cIncludingRoundingBit_uid247_sinPiZPolyEval_q : std_logic_vector (44 downto 0); signal cIncludingRoundingBit_uid253_sinPiZPolyEval_q : std_logic_vector (51 downto 0); signal cIncludingRoundingBit_uid259_sinPiZPolyEval_q : std_logic_vector (60 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q : std_logic_vector (107 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (29 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (46 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q : std_logic_vector (108 downto 0); signal yIsZero_uid43_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zPPolyEval_uid64_fpSinPiTest_in : std_logic_vector (71 downto 0); signal zPPolyEval_uid64_fpSinPiTest_b : std_logic_vector (44 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_q : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_c : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (31 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (15 downto 0); signal s2_uid240_uid243_sinPiZPolyEval_q : std_logic_vector (36 downto 0); signal add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (55 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (42 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (72 downto 0); signal add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal R_uid105_fpSinPiTest_q : std_logic_vector (63 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal yT3_uid244_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT3_uid244_sinPiZPolyEval_b : std_logic_vector (34 downto 0); signal yT4_uid250_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT4_uid250_sinPiZPolyEval_b : std_logic_vector (42 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q : std_logic_vector(0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_b : std_logic_vector (26 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zAddr_uid63_fpSinPiTest_in : std_logic_vector (78 downto 0); signal zAddr_uid63_fpSinPiTest_b : std_logic_vector (6 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (78 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (63 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (14 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (14 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (46 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (46 downto 0); signal expHardCaseR_uid60_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expHardCaseR_uid60_fpSinPiTest_b : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracRComp_uid78_fpSinPiTest_in : std_logic_vector (52 downto 0); signal fracRComp_uid78_fpSinPiTest_b : std_logic_vector (51 downto 0); signal expRComp_uid79_fpSinPiTest_in : std_logic_vector (63 downto 0); signal expRComp_uid79_fpSinPiTest_b : std_logic_vector (10 downto 0); signal intXParity_uid38_fpSinPiTest_in : std_logic_vector (80 downto 0); signal intXParity_uid38_fpSinPiTest_b : std_logic_vector (0 downto 0); signal y_uid39_fpSinPiTest_in : std_logic_vector (79 downto 0); signal y_uid39_fpSinPiTest_b : std_logic_vector (79 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (77 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (77 downto 0); signal s3_uid249_sinPiZPolyEval_in : std_logic_vector (45 downto 0); signal s3_uid249_sinPiZPolyEval_b : std_logic_vector (44 downto 0); signal s4_uid255_sinPiZPolyEval_in : std_logic_vector (52 downto 0); signal s4_uid255_sinPiZPolyEval_b : std_logic_vector (51 downto 0); signal s5_uid261_sinPiZPolyEval_in : std_logic_vector (61 downto 0); signal s5_uid261_sinPiZPolyEval_b : std_logic_vector (60 downto 0); signal oFracX_uid31_uid31_fpSinPiTest_q : std_logic_vector (52 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_in : std_logic_vector (6 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_b : std_logic_vector (6 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid235_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal highBBits_uid235_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid241_sinPiZPolyEval_in : std_logic_vector (28 downto 0); signal highBBits_uid241_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q : std_logic_vector(107 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (29 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (46 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal normBit_uid70_fpSinPiTest_in : std_logic_vector (106 downto 0); signal normBit_uid70_fpSinPiTest_b : std_logic_vector (0 downto 0); signal highRes_uid71_fpSinPiTest_in : std_logic_vector (105 downto 0); signal highRes_uid71_fpSinPiTest_b : std_logic_vector (52 downto 0); signal lowRes_uid72_fpSinPiTest_in : std_logic_vector (104 downto 0); signal lowRes_uid72_fpSinPiTest_b : std_logic_vector (52 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (70 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (70 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (62 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (62 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (54 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (54 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q : std_logic_vector(0 downto 0); signal yT1_uid232_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT1_uid232_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal yT2_uid238_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT2_uid238_sinPiZPolyEval_b : std_logic_vector (25 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (63 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (9 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (9 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (36 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (71 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (45 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (78 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (7 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (7 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (15 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (15 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expP_uid61_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expP_uid61_fpSinPiTest_q : std_logic_vector (10 downto 0); signal yBottom_uid48_fpSinPiTest_in : std_logic_vector (78 downto 0); signal yBottom_uid48_fpSinPiTest_b : std_logic_vector (78 downto 0); signal leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (51 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal fxpSinRes_uid66_fpSinPiTest_in : std_logic_vector (58 downto 0); signal fxpSinRes_uid66_fpSinPiTest_b : std_logic_vector (53 downto 0); signal extendedFracX_uid35_fpSinPiTest_q : std_logic_vector (80 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (0 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_a : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_b : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_o : std_logic_vector (26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q : std_logic_vector(107 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_q : std_logic_vector (52 downto 0); signal join_uid97_fpSinPiTest_q : std_logic_vector (1 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal signR_uid104_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (10 downto 0); signal pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (16 downto 0); signal pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal xIsInt_uid83_fpSinPiTest_a : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_b : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal multRightOp_uid68_fpSinPiTest_s : std_logic_vector (0 downto 0); signal multRightOp_uid68_fpSinPiTest_q : std_logic_vector (53 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (48 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (48 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (16 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (16 downto 0); signal s1_uid234_uid237_sinPiZPolyEval_q : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c : std_logic_vector (19 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in : std_logic_vector (106 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b : std_logic_vector (106 downto 0); signal expFracPreRnd_uid74_uid74_fpSinPiTest_q : std_logic_vector (63 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (17 downto 0); signal alignedZLow_uid53_fpSinPiTest_in : std_logic_vector (78 downto 0); signal alignedZLow_uid53_fpSinPiTest_b : std_logic_vector (51 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_b : std_logic_vector (26 downto 0); signal leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q : std_logic_vector (107 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (1 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (74 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (72 downto 0); signal pHardCase_uid54_fpSinPiTest_q : std_logic_vector (52 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q : std_logic_vector (108 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (0 downto 0); signal leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal p_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0); signal p_uid55_fpSinPiTest_q : std_logic_vector (52 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (72 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (64 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (64 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (56 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (56 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c : std_logic_vector (19 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal r_uid186_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (6 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (0 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (78 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (78 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (74 downto 0); signal leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (79 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (79 downto 0); signal leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); begin --ld_xIn_v_to_xOut_v_notEnable(LOGICAL,909) ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q; ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor(LOGICAL,1028) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q <= not (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a or ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top(CONSTANT,1024) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q <= "0100100"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp(LOGICAL,1025) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q <= "1" when ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a = ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b else "0"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg(REG,1026) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena(REG,1029) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q = "1") THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd(LOGICAL,1030) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a and ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b; --LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest(BITSELECT,134)@0 LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest(CONSTANT,133) leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q <= "000000"; --leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest(BITJOIN,135)@0 leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest(BITSELECT,131)@0 LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest(CONSTANT,130) leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q <= "0000"; --leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest(BITJOIN,132)@0 leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest(BITSELECT,128)@0 LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(78 downto 0); LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in(78 downto 0); --leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest(CONSTANT,127) leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q <= "00"; --leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest(BITJOIN,129)@0 leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest(BITSELECT,123)@0 LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(56 downto 0); LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in(56 downto 0); --leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest(CONSTANT,122) leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000"; --leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest(BITJOIN,124)@0 leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest(BITSELECT,120)@0 LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(64 downto 0); LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in(64 downto 0); --leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest(CONSTANT,119) leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000"; --leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest(BITJOIN,121)@0 leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest(BITSELECT,117)@0 LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(72 downto 0); LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in(72 downto 0); --leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest(CONSTANT,116) leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q <= "00000000"; --leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest(BITJOIN,118)@0 leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest(CONSTANT,113) leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; --X16dto0_uid112_fixedPointX_uid37_fpSinPiTest(BITSELECT,111)@0 X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(16 downto 0); X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in(16 downto 0); --leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest(CONSTANT,110) leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000"; --leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest(BITJOIN,112)@0 leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X48dto0_uid109_fixedPointX_uid37_fpSinPiTest(BITSELECT,108)@0 X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(48 downto 0); X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in(48 downto 0); --leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest(CONSTANT,107) leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q <= "00000000000000000000000000000000"; --leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest(BITJOIN,109)@0 leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --cst01pWShift_uid34_fpSinPiTest(CONSTANT,33) cst01pWShift_uid34_fpSinPiTest_q <= "0000000000000000000000000000"; --xIn(PORTIN,3)@0 --fracX_uid7_fpSinPiTest(BITSELECT,6)@0 fracX_uid7_fpSinPiTest_in <= xIn_0(51 downto 0); fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(51 downto 0); --oFracX_uid31_uid31_fpSinPiTest(BITJOIN,30)@0 oFracX_uid31_uid31_fpSinPiTest_q <= VCC_q & fracX_uid7_fpSinPiTest_b; --extendedFracX_uid35_fpSinPiTest(BITJOIN,34)@0 extendedFracX_uid35_fpSinPiTest_q <= cst01pWShift_uid34_fpSinPiTest_q & oFracX_uid31_uid31_fpSinPiTest_q; --shiftBias_uid32_fpSinPiTest(CONSTANT,31) shiftBias_uid32_fpSinPiTest_q <= "01111100011"; --expX_uid6_fpSinPiTest(BITSELECT,5)@0 expX_uid6_fpSinPiTest_in <= xIn_0(62 downto 0); expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(62 downto 52); --shiftValue_uid33_fpSinPiTest(SUB,32)@0 shiftValue_uid33_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b); shiftValue_uid33_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid32_fpSinPiTest_q); shiftValue_uid33_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid33_fpSinPiTest_a) - UNSIGNED(shiftValue_uid33_fpSinPiTest_b)); shiftValue_uid33_fpSinPiTest_q <= shiftValue_uid33_fpSinPiTest_o(11 downto 0); --fxpShifterBits_uid36_fpSinPiTest(BITSELECT,35)@0 fxpShifterBits_uid36_fpSinPiTest_in <= shiftValue_uid33_fpSinPiTest_q(6 downto 0); fxpShifterBits_uid36_fpSinPiTest_b <= fxpShifterBits_uid36_fpSinPiTest_in(6 downto 0); --leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest(BITSELECT,114)@0 leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b; leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in(6 downto 5); --leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest(MUX,115)@0 leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s, extendedFracX_uid35_fpSinPiTest_q, leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= extendedFracX_uid35_fpSinPiTest_q; WHEN "01" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest(BITSELECT,125)@0 leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(4 downto 0); leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in(4 downto 3); --leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest(MUX,126)@0 leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest(BITSELECT,136)@0 leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(2 downto 0); leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in(2 downto 1); --leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest(MUX,137)@0 leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest(BITSELECT,139)@0 LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in(79 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest(BITJOIN,140)@0 leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b & GND_q; --reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3(REG,357)@0 reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2(REG,358)@0 reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest(BITSELECT,141)@0 leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(0 downto 0); leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in(0 downto 0); --ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b(DELAY,581)@0 ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest(MUX,142)@1 leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q; leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s, reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q, reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q) BEGIN CASE leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q; WHEN "1" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q; WHEN OTHERS => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --intXParity_uid38_fpSinPiTest(BITSELECT,37)@1 intXParity_uid38_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q; intXParity_uid38_fpSinPiTest_b <= intXParity_uid38_fpSinPiTest_in(80 downto 80); --ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c(DELAY,536)@1 ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => intXParity_uid38_fpSinPiTest_b, xout => ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q, clk => clk, aclr => areset ); --biasM1_uid27_fpSinPiTest(CONSTANT,26) biasM1_uid27_fpSinPiTest_q <= "01111111110"; --xFrac_uid28_fpSinPiTest(COMPARE,27)@0 xFrac_uid28_fpSinPiTest_cin <= GND_q; xFrac_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid27_fpSinPiTest_q) & '0'; xFrac_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid28_fpSinPiTest_cin(0); xFrac_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid28_fpSinPiTest_a) - UNSIGNED(xFrac_uid28_fpSinPiTest_b)); xFrac_uid28_fpSinPiTest_n(0) <= not xFrac_uid28_fpSinPiTest_o(13); --ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a(DELAY,532)@0 ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => xFrac_uid28_fpSinPiTest_n, xout => ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvXFrac_uid99_fpSinPiTest(LOGICAL,98)@3 InvXFrac_uid99_fpSinPiTest_a <= ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q; InvXFrac_uid99_fpSinPiTest_q <= not InvXFrac_uid99_fpSinPiTest_a; --biasMwShift_uid29_fpSinPiTest(CONSTANT,28) biasMwShift_uid29_fpSinPiTest_q <= "01111100100"; --sinXIsX_uid30_fpSinPiTest(COMPARE,29)@0 sinXIsX_uid30_fpSinPiTest_cin <= GND_q; sinXIsX_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0'; sinXIsX_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid29_fpSinPiTest_q) & sinXIsX_uid30_fpSinPiTest_cin(0); sinXIsX_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid30_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid30_fpSinPiTest_b)); sinXIsX_uid30_fpSinPiTest_c(0) <= sinXIsX_uid30_fpSinPiTest_o(13); --ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a(DELAY,502)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvSinXIsX_uid80_fpSinPiTest(LOGICAL,79)@2 InvSinXIsX_uid80_fpSinPiTest_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q; InvSinXIsX_uid80_fpSinPiTest_q <= not InvSinXIsX_uid80_fpSinPiTest_a; --y_uid39_fpSinPiTest(BITSELECT,38)@1 y_uid39_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); y_uid39_fpSinPiTest_b <= y_uid39_fpSinPiTest_in(79 downto 0); --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0(REG,360)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid40_fpSinPiTest(LOGICAL,39)@2 yIsZero_uid40_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q; yIsZero_uid40_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000000000000000000000000000000000000000000000000" & GND_q); yIsZero_uid40_fpSinPiTest_q <= "1" when yIsZero_uid40_fpSinPiTest_a = yIsZero_uid40_fpSinPiTest_b else "0"; --And2YIsZeroInvSinXIsX_uid81_fpSinPiTest(LOGICAL,80)@2 And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a <= yIsZero_uid40_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b <= InvSinXIsX_uid80_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a and And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b; --cstBiasPwF_uid13_fpSinPiTest(CONSTANT,12) cstBiasPwF_uid13_fpSinPiTest_q <= "10000110011"; --xIntExp_uid26_fpSinPiTest(COMPARE,25)@0 xIntExp_uid26_fpSinPiTest_cin <= GND_q; xIntExp_uid26_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid13_fpSinPiTest_q) & '0'; xIntExp_uid26_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid26_fpSinPiTest_cin(0); xIntExp_uid26_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid26_fpSinPiTest_a) - UNSIGNED(xIntExp_uid26_fpSinPiTest_b)); xIntExp_uid26_fpSinPiTest_c(0) <= xIntExp_uid26_fpSinPiTest_o(13); --ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a(DELAY,505)@0 ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => xIntExp_uid26_fpSinPiTest_c, xout => ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q, clk => clk, aclr => areset ); --Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest(LOGICAL,81)@2 Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a or Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b; --cstAllZWF_uid10_fpSinPiTest(CONSTANT,9) cstAllZWF_uid10_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracXIsZero_uid17_fpSinPiTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b; fracXIsZero_uid17_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q; fracXIsZero_uid17_fpSinPiTest_q <= "1" when fracXIsZero_uid17_fpSinPiTest_a = fracXIsZero_uid17_fpSinPiTest_b else "0"; --ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a(DELAY,442)@0 ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => fracXIsZero_uid17_fpSinPiTest_q, xout => ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvFracXIsZero_uid19_fpSinPiTest(LOGICAL,18)@1 InvFracXIsZero_uid19_fpSinPiTest_a <= ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q; InvFracXIsZero_uid19_fpSinPiTest_q <= not InvFracXIsZero_uid19_fpSinPiTest_a; --cstAllOWE_uid9_fpSinPiTest(CONSTANT,8) cstAllOWE_uid9_fpSinPiTest_q <= "11111111111"; --expXIsMax_uid16_fpSinPiTest(LOGICAL,15)@0 expXIsMax_uid16_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsMax_uid16_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q; expXIsMax_uid16_fpSinPiTest_q <= "1" when expXIsMax_uid16_fpSinPiTest_a = expXIsMax_uid16_fpSinPiTest_b else "0"; --ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a(DELAY,443)@0 ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsMax_uid16_fpSinPiTest_q, xout => ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest(LOGICAL,19)@1 And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a <= ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b <= InvFracXIsZero_uid19_fpSinPiTest_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a and And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b; --InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest(LOGICAL,20)@1 InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q <= not InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a; --And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0 And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a <= expXIsMax_uid16_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b <= fracXIsZero_uid17_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a and And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b; --InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0 InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q; InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q <= not InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a; --cstAllZWE_uid11_fpSinPiTest(CONSTANT,10) cstAllZWE_uid11_fpSinPiTest_q <= "00000000000"; --expXIsZero_uid15_fpSinPiTest(LOGICAL,14)@0 expXIsZero_uid15_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsZero_uid15_fpSinPiTest_b <= cstAllZWE_uid11_fpSinPiTest_q; expXIsZero_uid15_fpSinPiTest_q <= "1" when expXIsZero_uid15_fpSinPiTest_a = expXIsZero_uid15_fpSinPiTest_b else "0"; --InvExpXIsZero_uid23_fpSinPiTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSinPiTest_a <= expXIsZero_uid15_fpSinPiTest_q; InvExpXIsZero_uid23_fpSinPiTest_q <= not InvExpXIsZero_uid23_fpSinPiTest_a; --And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0 And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a <= InvExpXIsZero_uid23_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b <= InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a and And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b; --ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a(DELAY,450)@0 ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q, xout => ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest(LOGICAL,24)@1 And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a <= ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b <= InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a and And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b; END IF; END PROCESS; --xIsInt_uid83_fpSinPiTest(LOGICAL,82)@2 xIsInt_uid83_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_b <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_q <= xIsInt_uid83_fpSinPiTest_a and xIsInt_uid83_fpSinPiTest_b; --InvXIsInt_uid100_fpSinPiTest(LOGICAL,99)@2 InvXIsInt_uid100_fpSinPiTest_a <= xIsInt_uid83_fpSinPiTest_q; InvXIsInt_uid100_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= not InvXIsInt_uid100_fpSinPiTest_a; END IF; END PROCESS; --signComp_uid101_fpSinPiTest(LOGICAL,100)@3 signComp_uid101_fpSinPiTest_a <= InvXIsInt_uid100_fpSinPiTest_q; signComp_uid101_fpSinPiTest_b <= InvXFrac_uid99_fpSinPiTest_q; signComp_uid101_fpSinPiTest_c <= ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q; signComp_uid101_fpSinPiTest_q <= signComp_uid101_fpSinPiTest_a and signComp_uid101_fpSinPiTest_b and signComp_uid101_fpSinPiTest_c; --ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a(DELAY,537)@2 ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => yIsZero_uid40_fpSinPiTest_q, xout => ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvYIsZero_uid102_fpSinPiTest(LOGICAL,101)@3 InvYIsZero_uid102_fpSinPiTest_a <= ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q; InvYIsZero_uid102_fpSinPiTest_q <= not InvYIsZero_uid102_fpSinPiTest_a; --And2InvYIsZeroSignComp_uid103_fpSinPiTest(LOGICAL,102)@3 And2InvYIsZeroSignComp_uid103_fpSinPiTest_a <= InvYIsZero_uid102_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_b <= signComp_uid101_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_q <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_a and And2InvYIsZeroSignComp_uid103_fpSinPiTest_b; --signX_uid8_fpSinPiTest(BITSELECT,7)@0 signX_uid8_fpSinPiTest_in <= xIn_0; signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(63 downto 63); --ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a(DELAY,540)@0 ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q, clk => clk, aclr => areset ); --signR_uid104_fpSinPiTest(LOGICAL,103)@3 signR_uid104_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q; signR_uid104_fpSinPiTest_b <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_q; signR_uid104_fpSinPiTest_q <= signR_uid104_fpSinPiTest_a xor signR_uid104_fpSinPiTest_b; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt(COUNTER,1020) -- every=1, low=0, high=36, step=1, init=1 ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i = 35 THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i - 36; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i,6)); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg(REG,1021) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --VCC(CONSTANT,1) VCC_q <= "1"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux(MUX,1022) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux: PROCESS (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem(DUALMEM,1019) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia <= signR_uid104_fpSinPiTest_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 37, width_b => 1, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq, address_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa, data_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia ); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq(0 downto 0); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg(DELAY,1018) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q, xout => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --cstBias_uid12_fpSinPiTest(CONSTANT,11) cstBias_uid12_fpSinPiTest_q <= "01111111111"; --piwFP2_uid67_fpSinPiTest(CONSTANT,66) piwFP2_uid67_fpSinPiTest_q <= "110010010000111111011010101000100010000101101000110001"; --reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1(REG,363)@1 reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --cOne_uid44_fpSinPiTest(CONSTANT,43) cOne_uid44_fpSinPiTest_q <= "100000000000000000000000000000000000000000000000000000000000000000000000000000000"; --oneMinusY_uid45_fpSinPiTest(SUB,44)@2 oneMinusY_uid45_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid44_fpSinPiTest_q); oneMinusY_uid45_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q); oneMinusY_uid45_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid45_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid45_fpSinPiTest_b)); END IF; END PROCESS; oneMinusY_uid45_fpSinPiTest_q <= oneMinusY_uid45_fpSinPiTest_o(81 downto 0); --oMyBottom_uid47_fpSinPiTest(BITSELECT,46)@3 oMyBottom_uid47_fpSinPiTest_in <= oneMinusY_uid45_fpSinPiTest_q(78 downto 0); oMyBottom_uid47_fpSinPiTest_b <= oMyBottom_uid47_fpSinPiTest_in(78 downto 0); --ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d(DELAY,471)@3 ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => oMyBottom_uid47_fpSinPiTest_b, xout => ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q, clk => clk, aclr => areset ); --yBottom_uid48_fpSinPiTest(BITSELECT,47)@1 yBottom_uid48_fpSinPiTest_in <= y_uid39_fpSinPiTest_b(78 downto 0); yBottom_uid48_fpSinPiTest_b <= yBottom_uid48_fpSinPiTest_in(78 downto 0); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c(DELAY,470)@1 ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 79, depth => 2 ) PORT MAP ( xin => yBottom_uid48_fpSinPiTest_b, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg(DELAY,926) ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a(DELAY,833)@1 ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a : dspba_delay GENERIC MAP ( width => 80, depth => 1 ) PORT MAP ( xin => y_uid39_fpSinPiTest_b, xout => ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q, clk => clk, aclr => areset ); --reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1(REG,364)@2 reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q; END IF; END PROCESS; --cmpYToOneMinusY_uid46_fpSinPiTest(COMPARE,45)@3 cmpYToOneMinusY_uid46_fpSinPiTest_cin <= GND_q; cmpYToOneMinusY_uid46_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & oneMinusY_uid45_fpSinPiTest_q) & '0'; cmpYToOneMinusY_uid46_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q) & cmpYToOneMinusY_uid46_fpSinPiTest_cin(0); cmpYToOneMinusY_uid46_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_b)); END IF; END PROCESS; cmpYToOneMinusY_uid46_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid46_fpSinPiTest_o(84); --z_uid49_fpSinPiTest(MUX,48)@4 z_uid49_fpSinPiTest_s <= cmpYToOneMinusY_uid46_fpSinPiTest_c; z_uid49_fpSinPiTest: PROCESS (z_uid49_fpSinPiTest_s, ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q) BEGIN CASE z_uid49_fpSinPiTest_s IS WHEN "0" => z_uid49_fpSinPiTest_q <= ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q; WHEN "1" => z_uid49_fpSinPiTest_q <= ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q; WHEN OTHERS => z_uid49_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --zAddr_uid63_fpSinPiTest(BITSELECT,62)@4 zAddr_uid63_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; zAddr_uid63_fpSinPiTest_b <= zAddr_uid63_fpSinPiTest_in(78 downto 72); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0(REG,382)@4 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= zAddr_uid63_fpSinPiTest_b; END IF; END PROCESS; --memoryC5_uid231_sinPiZTableGenerator(LOOKUP,230)@5 memoryC5_uid231_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; WHEN "0000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111110101101000"; WHEN "0000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111101101011101"; WHEN "0000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100110001110"; WHEN "0000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100000000010"; WHEN "0000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111011000000000"; WHEN "0000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111010001101101"; WHEN "0000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111001010010111"; WHEN "0001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111000010110010"; WHEN "0001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110111100010100"; WHEN "0001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110110100011111"; WHEN "0001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110101100101101"; WHEN "0001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110100101101011"; WHEN "0001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110011111011101"; WHEN "0001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010111001010"; WHEN "0001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010001011011"; WHEN "0010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110001010101011"; WHEN "0010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110000011011001"; WHEN "0010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101111011000001"; WHEN "0010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101110101001010"; WHEN "0010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101101110100110"; WHEN "0010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101100111100011"; WHEN "0010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011111111111"; WHEN "0010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011001001010"; WHEN "0011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101010010100110"; WHEN "0011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101001010011011"; WHEN "0011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101000100011100"; WHEN "0011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100111101010110"; WHEN "0011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100110110111000"; WHEN "0011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100101111110010"; WHEN "0011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100111110010"; WHEN "0011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100001010101"; WHEN "0100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100011011011111"; WHEN "0100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100010011110111"; WHEN "0100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100001110001010"; WHEN "0100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100000111000100"; WHEN "0100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111111110101"; WHEN "0100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111001010110"; WHEN "0100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011110011000111"; WHEN "0100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011101101000000"; WHEN "0101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011100110000011"; WHEN "0101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011111111001"; WHEN "0101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011000100110"; WHEN "0101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011010010101100"; WHEN "0101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011001100010010"; WHEN "0101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011000101010111"; WHEN "0101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111111101010"; WHEN "0101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111001010000"; WHEN "0110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010110011010011"; WHEN "0110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010101100101011"; WHEN "0110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010100110111110"; WHEN "0110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011111111000"; WHEN "0110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011010110010"; WHEN "0110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010010101001110"; WHEN "0110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001110010011"; WHEN "0110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001000111011"; WHEN "0111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010000001111011"; WHEN "0111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001111011111110"; WHEN "0111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110111001010"; WHEN "0111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110001110111"; WHEN "0111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001101011000100"; WHEN "0111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100101010010"; WHEN "0111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100000011111"; WHEN "0111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001011010001010"; WHEN "1000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001010100111110"; WHEN "1000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001110110010"; WHEN "1000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001010111000"; WHEN "1000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001000100111111"; WHEN "1000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111111001100"; WHEN "1000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111010001001"; WHEN "1000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110101010110"; WHEN "1000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110000011101"; WHEN "1001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000101001110100"; WHEN "1001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000100101111001"; WHEN "1001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011111111010"; WHEN "1001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011011110110"; WHEN "1001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010110001100"; WHEN "1001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010001001000"; WHEN "1001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001101111001"; WHEN "1001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001000000111"; WHEN "1010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000000010111001"; WHEN "1010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111110110110"; WHEN "1010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111001111111"; WHEN "1010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110110010100"; WHEN "1010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110001011000"; WHEN "1010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101100010111"; WHEN "1010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101000010010"; WHEN "1010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100100010000"; WHEN "1011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100000111100"; WHEN "1011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111011011111111"; WHEN "1011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010111100000"; WHEN "1011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010011110100"; WHEN "1011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010000011100"; WHEN "1011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111001011011110"; WHEN "1011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000111111101"; WHEN "1011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000100101011"; WHEN "1100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000001100100"; WHEN "1100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111101101110"; WHEN "1100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111010011000"; WHEN "1100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110110110000"; WHEN "1100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110010011010"; WHEN "1100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110000011110"; WHEN "1100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101100101100"; WHEN "1100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101000101110"; WHEN "1101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100110100000"; WHEN "1101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100100010001"; WHEN "1101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100001000000"; WHEN "1101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011101101110"; WHEN "1101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011011011111"; WHEN "1101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010111000100"; WHEN "1101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010101110011"; WHEN "1101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010001111100"; WHEN "1110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010000001111"; WHEN "1110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001110011001"; WHEN "1110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001010100010"; WHEN "1110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000111111000"; WHEN "1110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101110110"; WHEN "1110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101000100"; WHEN "1110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000010100010"; WHEN "1110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111111110011"; WHEN "1111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111110010000"; WHEN "1111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111100110111"; WHEN "1111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111010111000"; WHEN "1111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111000101000"; WHEN "1111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110110110100"; WHEN "1111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110101011010"; WHEN "1111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110100000011"; WHEN "1111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110010001011"; WHEN OTHERS => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; END CASE; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a(DELAY,485)@4 ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => z_uid49_fpSinPiTest_q, xout => ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q, clk => clk, aclr => areset ); --zPPolyEval_uid64_fpSinPiTest(BITSELECT,63)@5 zPPolyEval_uid64_fpSinPiTest_in <= ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q(71 downto 0); zPPolyEval_uid64_fpSinPiTest_b <= zPPolyEval_uid64_fpSinPiTest_in(71 downto 27); --yT1_uid232_sinPiZPolyEval(BITSELECT,231)@5 yT1_uid232_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT1_uid232_sinPiZPolyEval_b <= yT1_uid232_sinPiZPolyEval_in(44 downto 28); --reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0(REG,383)@5 reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= yT1_uid232_sinPiZPolyEval_b; END IF; END PROCESS; --prodXY_uid263_pT1_uid233_sinPiZPolyEval(MULT,262)@6 prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_a),18)) * SIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_b); prodXY_uid263_pT1_uid233_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= memoryC5_uid231_sinPiZTableGenerator_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr,34)); END IF; END PROCESS; prodXY_uid263_pT1_uid233_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval(BITSELECT,263)@9 prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_q; prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in(33 downto 16); --highBBits_uid235_sinPiZPolyEval(BITSELECT,234)@9 highBBits_uid235_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b; highBBits_uid235_sinPiZPolyEval_b <= highBBits_uid235_sinPiZPolyEval_in(17 downto 1); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a(DELAY,853)@4 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a : dspba_delay GENERIC MAP ( width => 7, depth => 3 ) PORT MAP ( xin => zAddr_uid63_fpSinPiTest_b, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0(REG,384)@7 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q; END IF; END PROCESS; --memoryC4_uid230_sinPiZTableGenerator(LOOKUP,229)@8 memoryC4_uid230_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; WHEN "0000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110011111111100"; WHEN "0000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100101101100110011"; WHEN "0000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100100010011000101"; WHEN "0000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100010010010010110"; WHEN "0000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011111110011000100"; WHEN "0000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011100101011001100"; WHEN "0000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011001000001111000"; WHEN "0001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010100110101100100"; WHEN "0001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010000000010110001"; WHEN "0001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001001010101111100100"; WHEN "0001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001000100111000100010"; WHEN "0001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000111110011011110101"; WHEN "0001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000110111011001010101"; WHEN "0001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000101111111000110001"; WHEN "0001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000100111101101111110"; WHEN "0010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000011111000010010110"; WHEN "0010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000010101110100101111"; WHEN "0010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000001100000110110101"; WHEN "0010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000000001101111000000"; WHEN "0010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111110110110101110011"; WHEN "0010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111101011011010111001"; WHEN "0010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111011111011110000110"; WHEN "0010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111010010111100110100"; WHEN "0011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111000101110111111001"; WHEN "0011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110111000010100011101"; WHEN "0011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110101010001000110011"; WHEN "0011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110011011011101100111"; WHEN "0011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110001100001110001111"; WHEN "0011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101111100011110001010"; WHEN "0011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101101100001110100101"; WHEN "0011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101011011011000110110"; WHEN "0100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101001001111111101110"; WHEN "0100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100111000001001001111"; WHEN "0100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100100101101100011001"; WHEN "0100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100010010110001110000"; WHEN "0100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011111111010101110110"; WHEN "0100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011101011010111000111"; WHEN "0100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011010110110110011110"; WHEN "0100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011000001110100011110"; WHEN "0101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010101100010100010011"; WHEN "0101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010010110010001000111"; WHEN "0101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001111111110001000100"; WHEN "0101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001101000101100110110"; WHEN "0101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001010001001001111011"; WHEN "0101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000111001001000001110"; WHEN "0101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000100000100011110110"; WHEN "0101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000000111100001111001"; WHEN "0110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111101101111111011111"; WHEN "0110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111010011111111100110"; WHEN "0110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110111001011110100100"; WHEN "0110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110011110100010000111"; WHEN "0110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110000011000010001001"; WHEN "0110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101100111000101000011"; WHEN "0110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101001010101101011111"; WHEN "0110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100101101110011101110"; WHEN "0111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100010000100000111110"; WHEN "0111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011110010101101110100"; WHEN "0111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011010100011010011110"; WHEN "0111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010110101101011010111"; WHEN "0111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010010110100011011101"; WHEN "0111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001110110111100001001"; WHEN "0111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001010110110110010000"; WHEN "0111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000110110011000001101"; WHEN "1000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000010101011011011001"; WHEN "1000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111110100000101110010"; WHEN "1000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111010010001110101001"; WHEN "1000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110110000000001101011"; WHEN "1000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110001101011001110011"; WHEN "1000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101101010010101011101"; WHEN "1000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101000110110101111111"; WHEN "1000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111100100010111100111100"; WHEN "1001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011111110101110100100"; WHEN "1001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011011001111111110100"; WHEN "1001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010110100111101000111"; WHEN "1001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010001111011100101001"; WHEN "1001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001101001100111100001"; WHEN "1001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001000011011000101011"; WHEN "1001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111000011100101100110010"; WHEN "1001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111110101110000000011"; WHEN "1010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111001110011001111101"; WHEN "1010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110110100110101001110001"; WHEN "1010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101111110100101001011"; WHEN "1010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101010110000110010110"; WHEN "1010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100101101010100111010"; WHEN "1010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100000100001101101101"; WHEN "1010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110011011010101110011000"; WHEN "1010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010110000111001010011"; WHEN "1011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010000110101101010010"; WHEN "1011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110001011100010001000010"; WHEN "1011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000110001011111001110"; WHEN "1011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000000110010110110100"; WHEN "1011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101111011010111010001000"; WHEN "1011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110101111001110001011"; WHEN "1011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110000011001011001100"; WHEN "1011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101101010110110100111111"; WHEN "1100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101100101010001011011001"; WHEN "1100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011111101010010000000"; WHEN "1100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011010000000101001000"; WHEN "1100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101010100010100111110111"; WHEN "1100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001110100111011010110"; WHEN "1100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001000110110111101100"; WHEN "1100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101000011000101000001000"; WHEN "1100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100111101010001001010101"; WHEN "1101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110111011010110000011"; WHEN "1101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110001100010011011010"; WHEN "1101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100101011101000100011001"; WHEN "1101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100100101101100110100111"; WHEN "1101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011111101110111111010"; WHEN "1101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011001110000000101100"; WHEN "1101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100010011101110011110101"; WHEN "1101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100001101101100000010000"; WHEN "1110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000111100111010001011"; WHEN "1110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000001100000111111010"; WHEN "1110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011111011011001110101000"; WHEN "1110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011110101010000110010111"; WHEN "1110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101111000110001000001"; WHEN "1110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101000111001101001001"; WHEN "1110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011100010101100011001010"; WHEN "1110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011011100011101111010110"; WHEN "1111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011010110001101110011110"; WHEN "1111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001111111100011010111"; WHEN "1111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001001101010000100101"; WHEN "1111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011000011010110101101110"; WHEN "1111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010111101000010001000000"; WHEN "1111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110110101100011000101"; WHEN "1111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110000010101101010111"; WHEN "1111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010101001111110001011010"; WHEN OTHERS => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; END CASE; END IF; END PROCESS; --sumAHighB_uid236_sinPiZPolyEval(ADD,235)@9 sumAHighB_uid236_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((26 downto 26 => memoryC4_uid230_sinPiZTableGenerator_q(25)) & memoryC4_uid230_sinPiZTableGenerator_q); sumAHighB_uid236_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((26 downto 17 => highBBits_uid235_sinPiZPolyEval_b(16)) & highBBits_uid235_sinPiZPolyEval_b); sumAHighB_uid236_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid236_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid236_sinPiZPolyEval_b)); sumAHighB_uid236_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_o(26 downto 0); --lowRangeB_uid234_sinPiZPolyEval(BITSELECT,233)@9 lowRangeB_uid234_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid234_sinPiZPolyEval_b <= lowRangeB_uid234_sinPiZPolyEval_in(0 downto 0); --s1_uid234_uid237_sinPiZPolyEval(BITJOIN,236)@9 s1_uid234_uid237_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_q & lowRangeB_uid234_sinPiZPolyEval_b; --reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1(REG,385)@9 reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= s1_uid234_uid237_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor(LOGICAL,1179) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q <= not (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a or ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg(REG,1177) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= VCC_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena(REG,1180) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q = "1") THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd(LOGICAL,1181) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a and ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b; --yT2_uid238_sinPiZPolyEval(BITSELECT,237)@5 yT2_uid238_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT2_uid238_sinPiZPolyEval_b <= yT2_uid238_sinPiZPolyEval_in(44 downto 19); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt(COUNTER,1173) -- every=1, low=0, high=1, step=1, init=1 ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i + 1; END IF; END PROCESS; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i,1)); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg(REG,1174) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux(MUX,1175) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q) BEGIN CASE ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s IS WHEN "0" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; WHEN "1" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem(DUALMEM,1172) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia <= yT2_uid238_sinPiZPolyEval_b; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 26, widthad_a => 1, numwords_a => 2, width_b => 26, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq, address_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa, data_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia ); ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq(25 downto 0); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg(DELAY,1171) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q, xout => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0(REG,386)@9 reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q; END IF; END PROCESS; --prodXY_uid266_pT2_uid239_sinPiZPolyEval(MULT,265)@10 prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_a),27)) * SIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_b); prodXY_uid266_pT2_uid239_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr,54)); END IF; END PROCESS; prodXY_uid266_pT2_uid239_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval(BITSELECT,266)@13 prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_q; prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in(53 downto 25); --highBBits_uid241_sinPiZPolyEval(BITSELECT,240)@13 highBBits_uid241_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b; highBBits_uid241_sinPiZPolyEval_b <= highBBits_uid241_sinPiZPolyEval_in(28 downto 1); --reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1(REG,388)@13 reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= highBBits_uid241_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor(LOGICAL,1192) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1188) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q <= "0101"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp(LOGICAL,1189) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg(REG,1190) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena(REG,1193) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1194) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1184) -- every=1, low=0, high=5, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i = 4 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i - 5; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i,3)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg(REG,1185) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1186) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1183) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 3, numwords_a => 6, width_b => 7, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg(DELAY,1182) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0(REG,387)@12 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC3_uid229_sinPiZTableGenerator(LOOKUP,228)@13 memoryC3_uid229_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; WHEN "0000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000001010001100110101000111010101"; WHEN "0000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000010100011001100101101010110011"; WHEN "0000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000011110100110001101010100011011"; WHEN "0000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000101000110010100111100101110011"; WHEN "0000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000110010111110101111101101101000"; WHEN "0000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000111101001010100001100001001101"; WHEN "0000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001000111010101111000010100001000"; WHEN "0001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001010001100000101111101001011010"; WHEN "0001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001011011101011000011001000111110"; WHEN "0001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001100101110100101110001001110101"; WHEN "0001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001101111111101101100010100000001"; WHEN "0001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001111010000101111001001101010110"; WHEN "0001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010000100001101010000011000110101"; WHEN "0001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010001110010011101101001010101000"; WHEN "0001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010011000011001001011011101011111"; WHEN "0010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010100010011101100110100011101011"; WHEN "0010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010101100100000111010000011110001"; WHEN "0010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010110110100011000001011111010110"; WHEN "0010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011000000100011111000101110110101"; WHEN "0010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011001010100011011011001000001011"; WHEN "0010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011010100100001100100010010100101"; WHEN "0010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011011110011110001111110110101010"; WHEN "0010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011101000011001011001100000011011"; WHEN "0011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011110010010010111100111000010100"; WHEN "0011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011111100001010110101011110000110"; WHEN "0011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100000110000000111111001110100010"; WHEN "0011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100001111110101010101100100101101"; WHEN "0011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100011001100111110100010110001111"; WHEN "0011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100100011011000010111001001011111"; WHEN "0011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100101101000110111001101001101001"; WHEN "0011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100110110110011010111110011001100"; WHEN "0100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101000000011101101101010000100110"; WHEN "0100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101001010000101110101101000010110"; WHEN "0100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101010011101011101100111100100100"; WHEN "0100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101011101001111001110110000110010"; WHEN "0100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101100110110000010111000000110011"; WHEN "0100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101110000001111000001100011110100"; WHEN "0100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101111001101011001010010000000001"; WHEN "0100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110000011000100101100111100001110"; WHEN "0101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110001100011011100101011010100101"; WHEN "0101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110010101101111101111110000010101"; WHEN "0101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110011111000001000111101011101100"; WHEN "0101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110101000001111101001011001100010"; WHEN "0101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110110001011011010000101101010010"; WHEN "0101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110111010100011111001100111101100"; WHEN "0101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111000011101001100000010000100010"; WHEN "0101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111001100101100000000100001010000"; WHEN "0110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111010101101011010110100011101100"; WHEN "0110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111011110100111011110011000011110"; WHEN "0110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111100111100000010100001101010000"; WHEN "0110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111110000010101110100000001010000"; WHEN "0110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111111001000111111010001101010001"; WHEN "0110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000000001110110100010110001111010"; WHEN "0110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000001010100001101001110111110101"; WHEN "0110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000010011001001001011111110000001"; WHEN "0111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000011011101101000101000010101111"; WHEN "0111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000100100001101010001101000100100"; WHEN "0111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000101100101001101110000011010101"; WHEN "0111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000110101000010010110100001011010"; WHEN "0111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000111101010111000111010101011110"; WHEN "0111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001000101100111111101000110111000"; WHEN "0111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001001101110100110100001111001100"; WHEN "0111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001010101111101101001000001001010"; WHEN "1000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001011110000010011000001001000011"; WHEN "1000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001100110000010111101111101010011"; WHEN "1000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001101101111111010111010011001111"; WHEN "1000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001110101110111100000011010000110"; WHEN "1000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001111101101011010110000011010010"; WHEN "1000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010000101011010110100111100000101"; WHEN "1000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010001101000101111001101110100011"; WHEN "1000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010010100101100100001000101010010"; WHEN "1001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010011100001110100111101001010100"; WHEN "1001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010100011101100001010100001011100"; WHEN "1001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010101011000101000110001011100100"; WHEN "1001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010110010011001010111110000100100"; WHEN "1001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010111001101000111011111001000111"; WHEN "1001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000000110011101111101001011111"; WHEN "1001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000111111001110000000110011110"; WHEN "1001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011001110111010111001110111111110"; WHEN "1010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011010101110111001010010001110110"; WHEN "1010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011011100101110011110011000111101"; WHEN "1010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011100011100000110011001001001001"; WHEN "1010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011101010001110000101111000101100"; WHEN "1010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110000110110010011100011000111"; WHEN "1010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110111011001011001011101010011"; WHEN "1010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011111101110111010100111100011100"; WHEN "1010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100000100010000000011001111101101"; WHEN "1011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100001010100011100001101110011100"; WHEN "1011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010000110001101101100011100011"; WHEN "1011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010110111010100100010100000100"; WHEN "1011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100011100111110000011100000001010"; WHEN "1011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100100010111100001000100001101001"; WHEN "1011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101000110100110000110001111011"; WHEN "1011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101110100111111010000100111001"; WHEN "1011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100110100010101100001111010001101"; WHEN "1100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111001111101100101111101110000"; WHEN "1100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111111100000000011110011100101"; WHEN "1100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101000100111100111001010011110100"; WHEN "1100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001010010100000100001001001101"; WHEN "1100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001111100101100010000111001000"; WHEN "1100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101010100110001010001010100001101"; WHEN "1100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011001110111001111010101110101"; WHEN "1100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011110110111011010001101111010"; WHEN "1101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101100011110001110000000111001111"; WHEN "1101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101000100110001110111010010001"; WHEN "1101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101101010100110100100110101101"; WHEN "1101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110001111101011111011001010101"; WHEN "1101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110110100000001101100000100000"; WHEN "1101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111010111100111100111010111000"; WHEN "1101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111111010011101100010000110110"; WHEN "1101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000011100100011001011010100000"; WHEN "1110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000111101111000011000011110011"; WHEN "1110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001011110011100111011010000000"; WHEN "1110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001111110010000100101111100001"; WHEN "1110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010011101010011001110010000111"; WHEN "1110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010111011100100100111111111001"; WHEN "1110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011011001000100101000000101011"; WHEN "1110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011110101110011000001011101010"; WHEN "1110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100010001101111101010010100010"; WHEN "1111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100101100111010011001000110011"; WHEN "1111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101000111010011000011010000011"; WHEN "1111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101100000111001011110100010010"; WHEN "1111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101111001101101100001110011100"; WHEN "1111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110010001101111000100101110110"; WHEN "1111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110101000111101111110101001010"; WHEN "1111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110111111011010000111000110000"; WHEN "1111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110111010101000011010110000100000"; WHEN OTHERS => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; END CASE; END IF; END PROCESS; --sumAHighB_uid242_sinPiZPolyEval(ADD,241)@14 sumAHighB_uid242_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid229_sinPiZTableGenerator_q(34)) & memoryC3_uid229_sinPiZTableGenerator_q); sumAHighB_uid242_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((35 downto 28 => reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q(27)) & reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q); sumAHighB_uid242_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid242_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid242_sinPiZPolyEval_b)); sumAHighB_uid242_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_o(35 downto 0); --lowRangeB_uid240_sinPiZPolyEval(BITSELECT,239)@13 lowRangeB_uid240_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid240_sinPiZPolyEval_b <= lowRangeB_uid240_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a(DELAY,686)@13 ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid240_sinPiZPolyEval_b, xout => ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --s2_uid240_uid243_sinPiZPolyEval(BITJOIN,242)@14 s2_uid240_uid243_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_q & ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q; --yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval(BITSELECT,274)@14 yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in(36 downto 19); --reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9(REG,389)@14 reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor(LOGICAL,950) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top(CONSTANT,946) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q <= "0110"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp(LOGICAL,947) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b else "0"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg(REG,948) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena(REG,951) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q = "1") THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd(LOGICAL,952) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt(COUNTER,942) -- every=1, low=0, high=6, step=1, init=1 ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i = 5 THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i - 6; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i,3)); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg(REG,943) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux(MUX,944) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q) BEGIN CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s IS WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem(DUALMEM,1069) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 3, numwords_a => 7, width_b => 45, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg(DELAY,1068) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT3_uid244_sinPiZPolyEval(BITSELECT,243)@14 yT3_uid244_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q; yT3_uid244_sinPiZPolyEval_b <= yT3_uid244_sinPiZPolyEval_in(44 downto 10); --xBottomBits_uid274_pT3_uid245_sinPiZPolyEval(BITSELECT,273)@14 xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b(7 downto 0); xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in(7 downto 0); --pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval(BITJOIN,276)@14 pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7(REG,391)@14 reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid273_pT3_uid245_sinPiZPolyEval(BITSELECT,272)@14 yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q(9 downto 0); yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b <= yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in(9 downto 0); --spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval(BITJOIN,275)@14 spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q <= GND_q & yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b; --pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval(BITJOIN,277)@14 pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q <= spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6(REG,390)@14 reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval(BITSELECT,271)@14 xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in(34 downto 17); --reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4(REG,392)@14 reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma(CHAINMULTADD,345)@15 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1),38); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0); END IF; END PROCESS; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0),37)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval(BITSELECT,279)@18 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in(36 downto 7); --highBBits_uid282_pT3_uid245_sinPiZPolyEval(BITSELECT,281)@18 highBBits_uid282_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b; highBBits_uid282_pT3_uid245_sinPiZPolyEval_b <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_in(29 downto 1); --reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1(REG,395)@18 reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval(BITSELECT,269)@14 yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in(36 downto 10); --reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1(REG,393)@14 reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval(BITSELECT,268)@14 xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in(34 downto 8); --reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0(REG,394)@14 reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid271_pT3_uid245_sinPiZPolyEval(MULT,270)@15 topProd_uid271_pT3_uid245_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_b); topProd_uid271_pT3_uid245_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid271_pT3_uid245_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid271_pT3_uid245_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0(REG,396)@18 reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid283_pT3_uid245_sinPiZPolyEval(ADD,282)@19 sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q(53)) & reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b)); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid281_pT3_uid245_sinPiZPolyEval(BITSELECT,280)@18 lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b <= lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a(DELAY,724)@18 ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b, xout => ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid281_uid284_pT3_uid245_sinPiZPolyEval(BITJOIN,283)@19 add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q & ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q; --R_uid285_pT3_uid245_sinPiZPolyEval(BITSELECT,284)@19 R_uid285_pT3_uid245_sinPiZPolyEval_in <= add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q(54 downto 0); R_uid285_pT3_uid245_sinPiZPolyEval_b <= R_uid285_pT3_uid245_sinPiZPolyEval_in(54 downto 18); --reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1(REG,397)@19 reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= R_uid285_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor(LOGICAL,1168) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1164) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q <= "01011"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp(LOGICAL,1165) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg(REG,1166) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena(REG,1169) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1170) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1160) -- every=1, low=0, high=11, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i = 10 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i - 11; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i,4)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg(REG,1161) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1162) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1159) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 4, numwords_a => 12, width_b => 7, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg(DELAY,1158) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0(REG,381)@18 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC2_uid228_sinPiZTableGenerator(LOOKUP,227)@19 memoryC2_uid228_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; WHEN "0000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010010000000010011011110101101000"; WHEN "0000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010100110111111010000111001000101"; WHEN "0000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101011001101001111001000101101101011"; WHEN "0000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101100000010110001110010011100100110"; WHEN "0000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101101000111100110110110100100001100"; WHEN "0000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101110011011101101110110101011000001"; WHEN "0000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101111111111000110001101110000001000"; WHEN "0001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110001110001101111010000000001001001"; WHEN "0001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110011110011101000001010111100010011"; WHEN "0001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110110000100110000000101010101010010"; WHEN "0001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111000100101000101111111001111001110"; WHEN "0001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111011010100101000110010000000110000"; WHEN "0001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111110010011010111010000010100101101"; WHEN "0001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000001100001010000000110001101010110"; WHEN "0001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000100111110010001111000111001110001"; WHEN "0010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001000101010011011000111000110111111"; WHEN "0010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001100100101101010001000110100001110"; WHEN "0010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010000101111111101001111011000110110"; WHEN "0010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010101001001010010100101011111010000"; WHEN "0010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011001110001101000001111010001111100"; WHEN "0010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011110101000111100001010010001101000"; WHEN "0010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111100011101111001100001101011001010011"; WHEN "0010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101001000100010110001000111111011001"; WHEN "0011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101110101000010111100110110111011101"; WHEN "0011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111110100011011001110001010010101001001"; WHEN "0011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111111010011100110111010000000101010000"; WHEN "0011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000000101101010000001110011011110111"; WHEN "0011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000111001100010110010101001001001010"; WHEN "0011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000001101111010000110101101100011101100"; WHEN "0011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000010100110110011110011010100101011100"; WHEN "0011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000011100000001011010011000101010010101"; WHEN "0100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000100011011010110111011101111001100010"; WHEN "0100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000101011000010110010011010000011100100"; WHEN "0100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000110010111001000111110110011110000010"; WHEN "0100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000111010111101110100010110010000011111"; WHEN "0100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001000011010000110100010110001010111111"; WHEN "0100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001001011110010000100001100101110011011"; WHEN "0100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001010100100001100000001010001100011000"; WHEN "0100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001011101011111000100011000101001100001"; WHEN "0101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001100110101010101100111100000000011011"; WHEN "0101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001110000000100010101110001111101110010"; WHEN "0101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001111001101011111010110010001100011010"; WHEN "0101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010000011100001010111101110001010011110"; WHEN "0101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010001101100100101000010001011000100111"; WHEN "0101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010010111110101101000000001010011000010"; WHEN "0101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010100010010100010010011101010101101010"; WHEN "0101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010101101000000100010111111000010000011"; WHEN "0110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010110111111010010100111001111011100110"; WHEN "0110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011000011000001100011011011101110111001"; WHEN "0110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011001110010110001001101100001111110101"; WHEN "0110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011011001111000000010101101100000111100"; WHEN "0110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011100101100111001001011011101110011000"; WHEN "0110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011110001100011011000101101011001110101"; WHEN "0110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011111101101100101011010011010110110001"; WHEN "0110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100001010000010111011111000101001101100"; WHEN "0111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100010110100110000101000010110110110100"; WHEN "0111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100100011010110000001010001110101000110"; WHEN "0111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100110000010010101010111111111100101100"; WHEN "0111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100111101011011111100100010000110111111"; WHEN "0111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101001010110001110000000111101111100101"; WHEN "0111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101011000010011111111111010110011011100"; WHEN "0111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101100110000010100101111111111011010100"; WHEN "0111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101110011111101011100010110011100010110"; WHEN "1000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110000010000100011100111000010100111110"; WHEN "1000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110010000010111100001011010011001010101"; WHEN "1000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110011110110110100011101100001011001000"; WHEN "1000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110101101100001011101011000001011011001"; WHEN "1000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110111100011000001000000011101110001111"; WHEN "1000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111001011011010011101001111000101110001"; WHEN "1000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111011010101000010110010101100101000110"; WHEN "1000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111101010000001101100101101100010111111"; WHEN "1001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111111001100110011001101000011100111011"; WHEN "1001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000001001010110010110010010110100011100"; WHEN "1001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000011001010001011011110100100000011000"; WHEN "1001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000101001010111100011010000011111011101"; WHEN "1001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000111001101000100101100101001010011111"; WHEN "1001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001001010000100011011101100001100000010"; WHEN "1001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001011010101010111110011010101000110000"; WHEN "1001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001101011011100000110100001001001100100"; WHEN "1010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001111100010111101100101011101111001100"; WHEN "1010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010001101011101101001100010000010111010"; WHEN "1010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010011110101101110101100111011000000101"; WHEN "1010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010110000001000001001011010101000000100"; WHEN "1010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011000001101100011101010110100010000110"; WHEN "1010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011010011011010101001110001100010110011"; WHEN "1010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011100101010010100110111101111101101001"; WHEN "1010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011110111010100001101001010000001101110"; WHEN "1011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100001001011111010100011111111010110111"; WHEN "1011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100011011110011110101000101111001011001"; WHEN "1011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100101110010001100110111110001101101110"; WHEN "1011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101000000111000100010000111010010100101"; WHEN "1011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101010011101000011110011011110001111001"; WHEN "1011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101100110100001010011110010100110010101"; WHEN "1011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101111001100010111001111110111010001011"; WHEN "1011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110001100101101001000110000010101000001"; WHEN "1100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110011111111111110111110010111000010010"; WHEN "1100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110110011011010111110101111001000100111"; WHEN "1100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111000110111110010101001010001010011010"; WHEN "1100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111011010101001110010100101101110010111"; WHEN "1100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111101110011101001110100000001111101010"; WHEN "1100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000000010011000100000010100110110100000"; WHEN "1100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000010110011011011111011011100110110011"; WHEN "1100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000101010100110000011001001011000000001"; WHEN "1101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000111110111000000010101111111100010101"; WHEN "1101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001010011010001010101011110001011010100"; WHEN "1101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001100111110001110010100000000000010111"; WHEN "1101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001111100011001010000111110011101110000"; WHEN "1101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010010001000111100111111111110011011101"; WHEN "1101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010100101111100101110100111100110010101"; WHEN "1101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010111010111000011011110110101001010101"; WHEN "1101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011001111111010100110101011010011011011"; WHEN "1110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011100101000011000110000001010000000100"; WHEN "1110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011111010010001110000110001110011111011"; WHEN "1110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100001111100110011101110011111001111111"; WHEN "1110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100100101000001000011111100000011011011"; WHEN "1110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100111010100001011001111100100100101001"; WHEN "1110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101010000000111010110100101100100010111"; WHEN "1110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101100101110010110000100101000101101101"; WHEN "1110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101111011100011011110100111000011010111"; WHEN "1111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110010001011001010111010101011001010001"; WHEN "1111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110100111010100010001011000001010110100"; WHEN "1111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110111101010100000011010101100101100011"; WHEN "1111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111010011011000100011110010000011111011"; WHEN "1111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111101001100001101001010000010010001011"; WHEN "1111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111111111101111001010010001010101000011"; WHEN "1111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000010110000000111101010100101101001001"; WHEN "1111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000101100010110111000111000011010110101"; WHEN OTHERS => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid246_sinPiZPolyEval(CONSTANT,245) rndBit_uid246_sinPiZPolyEval_q <= "01"; --cIncludingRoundingBit_uid247_sinPiZPolyEval(BITJOIN,246)@19 cIncludingRoundingBit_uid247_sinPiZPolyEval_q <= memoryC2_uid228_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0(REG,398)@19 reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid247_sinPiZPolyEval_q; END IF; END PROCESS; --ts3_uid248_sinPiZPolyEval(ADD,247)@20 ts3_uid248_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q); ts3_uid248_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q(36)) & reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q); ts3_uid248_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid248_sinPiZPolyEval_a) + SIGNED(ts3_uid248_sinPiZPolyEval_b)); ts3_uid248_sinPiZPolyEval_q <= ts3_uid248_sinPiZPolyEval_o(45 downto 0); --s3_uid249_sinPiZPolyEval(BITSELECT,248)@20 s3_uid249_sinPiZPolyEval_in <= ts3_uid248_sinPiZPolyEval_q; s3_uid249_sinPiZPolyEval_b <= s3_uid249_sinPiZPolyEval_in(45 downto 1); --yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval(BITSELECT,286)@20 yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b; yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in(44 downto 18); --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9(REG,399)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor(LOGICAL,1091) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top(CONSTANT,1087) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q <= "01100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp(LOGICAL,1088) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg(REG,1089) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena(REG,1092) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd(LOGICAL,1093) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1083) -- every=1, low=0, high=12, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i = 11 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i - 12; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i,4)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg(REG,1084) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux(MUX,1085) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem(DUALMEM,1082) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 13, width_b => 45, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg(DELAY,1081) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT4_uid250_sinPiZPolyEval(BITSELECT,249)@20 yT4_uid250_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q; yT4_uid250_sinPiZPolyEval_b <= yT4_uid250_sinPiZPolyEval_in(44 downto 2); --xBottomBits_uid290_pT4_uid251_sinPiZPolyEval(BITSELECT,289)@20 xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in <= yT4_uid250_sinPiZPolyEval_b(15 downto 0); xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in(15 downto 0); --pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval(BITJOIN,291)@20 pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7(REG,401)@20 reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid289_pT4_uid251_sinPiZPolyEval(BITSELECT,288)@20 yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b(17 downto 0); yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b <= yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a(DELAY,733)@20 ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b, xout => ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval(BITJOIN,290)@21 spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q; --pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval(BITJOIN,292)@21 pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q <= spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6(REG,400)@21 reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a(DELAY,727)@20 ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 43, depth => 1 ) PORT MAP ( xin => yT4_uid250_sinPiZPolyEval_b, xout => ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval(BITSELECT,285)@21 xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in <= ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q; xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in(42 downto 16); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4(REG,402)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma(CHAINMULTADD,346)@22 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval(BITSELECT,294)@25 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in(54 downto 8); --highBBits_uid297_pT4_uid251_sinPiZPolyEval(BITSELECT,296)@25 highBBits_uid297_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b; highBBits_uid297_pT4_uid251_sinPiZPolyEval_b <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_in(46 downto 18); --reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1(REG,405)@25 reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1(REG,403)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b(DELAY,730)@21 ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0(REG,404)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid288_pT4_uid251_sinPiZPolyEval(MULT,287)@22 topProd_uid288_pT4_uid251_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_b); topProd_uid288_pT4_uid251_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid288_pT4_uid251_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid288_pT4_uid251_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0(REG,406)@25 reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid298_pT4_uid251_sinPiZPolyEval(ADD,297)@26 sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q(53)) & reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b)); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid296_pT4_uid251_sinPiZPolyEval(BITSELECT,295)@25 lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b(17 downto 0); lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b <= lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a(DELAY,741)@25 ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b, xout => ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid296_uid299_pT4_uid251_sinPiZPolyEval(BITJOIN,298)@26 add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q & ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q; --R_uid300_pT4_uid251_sinPiZPolyEval(BITSELECT,299)@26 R_uid300_pT4_uid251_sinPiZPolyEval_in <= add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q(71 downto 0); R_uid300_pT4_uid251_sinPiZPolyEval_b <= R_uid300_pT4_uid251_sinPiZPolyEval_in(71 downto 26); --reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1(REG,407)@26 reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= R_uid300_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor(LOGICAL,1155) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1151) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q <= "010010"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp(LOGICAL,1152) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg(REG,1153) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena(REG,1156) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1157) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1147) -- every=1, low=0, high=18, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i = 17 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i - 18; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg(REG,1148) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1149) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1146) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 19, width_b => 7, widthad_b => 5, numwords_b => 19, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg(DELAY,1145) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0(REG,380)@25 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC1_uid227_sinPiZTableGenerator(LOOKUP,226)@26 memoryC1_uid227_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; WHEN "0000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111110101101010100010101111000000010001111100011"; WHEN "0000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111101011010101001001010010110100010110001011110"; WHEN "0000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111100000111111110111100000001110010011010000110"; WHEN "0000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111010110101010110001001011111100110111111100011"; WHEN "0000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111001100010101111010001010101001101111010110100"; WHEN "0000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111000010000001010110010000110111110101011111000"; WHEN "0000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110110111101101001001010011000001101011000111010"; WHEN "0001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110101101011001010111000101010111101010010100111"; WHEN "0001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110100011000110000011011011111110011010111001110"; WHEN "0001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110011000110011010010001010101101000110101101101"; WHEN "0001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110001110100001000111000101001011101110011011101"; WHEN "0001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110000100001111100101111110110001011110001011001"; WHEN "0001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101111001111110110010101010100011000010010100110"; WHEN "0001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101101111101110110000111011010000111100011100100"; WHEN "0001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101100101011111100100100011010101111000101000111"; WHEN "0010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101011011010001010001010100110101000010011111000"; WHEN "0010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101010001000011111011000001011000011010110000100"; WHEN "0010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101000110110111100101011010001111001100111110010"; WHEN "0010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100111100101100010100010000001100000101010111010"; WHEN "0010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100110010100010001011010011100011100110101011100"; WHEN "0010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100101000011001001110010100001010100000101101100"; WHEN "0010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100011110010001100001000001010100000110110000000"; WHEN "0010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100010100001011000111001001110000100110010111000"; WHEN "0011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100001010000110000100011011101011011110011010110"; WHEN "0011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100000000000010011100100100101001110110011000010"; WHEN "0011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011110110000000010011010001101000110110000011100"; WHEN "0011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011101011111111101100001110111011111101010000000"; WHEN "0011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011100010000000101011001000001011011100001111010"; WHEN "0011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011011000000011010011101000010010101100000110110"; WHEN "0011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011001110000111101001011001011110100111101110010"; WHEN "0011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011000100001101110000000101001100000101000010010"; WHEN "0100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010111010010101101011010100000110001110011110001"; WHEN "0100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010110000011111011110101110000100111100111110101"; WHEN "0100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010100110101011001101111010001011010010011110011"; WHEN "0100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010011100111000111100011110100101110100010111000"; WHEN "0100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010010011001000101110000000101001000110111000111"; WHEN "0100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010001001011010100110000100110000001000100101001"; WHEN "0100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001111111101110101000001110011010101110010001110"; WHEN "0100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001110110000100111000000000001011111111100011001"; WHEN "0101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001101100011101011000111011101000110011100100000"; WHEN "0101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001100010111000001110100001010110001110100101001"; WHEN "0101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001011001010101011100010000110111111111100011001"; WHEN "0101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001001111110101000101101000101110111110101110110"; WHEN "0101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001000110010111001110000110010111101100001101110"; WHEN "0101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000111100111011111001000110001000101111011110000"; WHEN "0101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000110011100011001010000011010001010111001000100"; WHEN "0101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000101010001101000100010111110111111001010110011"; WHEN "0110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000100000111001101011011100111000010100110100100"; WHEN "0110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000010111101001000010101010000010110010001100101"; WHEN "0110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000001110011011001101010101111010000110001110001"; WHEN "0110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000000101010000001110110101110010010100010001010"; WHEN "0110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111111100001000001010011101101111010001101110100"; WHEN "0110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111110011000011000011100000100011001001100111111"; WHEN "0110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111101010000000111101001111101101000001001100111"; WHEN "0110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111100001000001111010111011010111011101000011000"; WHEN "0111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111011000000101111111110010010111000110100000100"; WHEN "0111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111001111001101001111000010001001010010011000111"; WHEN "0111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111000110010111101011110110110010100111101001111"; WHEN "0111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110111101100101011001011010111101100111001001111"; WHEN "0111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110110100110110011010110111111001010011111110011"; WHEN "0111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110101100001010110011010101010111111100100001011"; WHEN "0111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110100011100010100101111001101101100100000011010"; WHEN "0111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110011010111101110101101001101110101101001000101"; WHEN "1000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110010010011100100101101000101111000100111000101"; WHEN "1000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110001001111110111000111000100000001110100110010"; WHEN "1000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110000001100100110010011001010000010000100100001"; WHEN "1000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101111001001110010101001001101000100001000011111"; WHEN "1000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101110000111011100100000110101100010100101111011"; WHEN "1000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101101000101100100010001011110111101101010011001"; WHEN "1000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101100000100001010010010010111110001001000100100"; WHEN "1000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101011000011001110111010100001001010011011010001"; WHEN "1001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101010000010110010100000101110111110101110111011"; WHEN "1001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101001000010110101011011100111100001010010001010"; WHEN "1001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101000000011011000000001100011011001101001101101"; WHEN "1001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100111000100011010101000101101011010001111110100"; WHEN "1001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100110000101111101100111000010010110110101001010"; WHEN "1001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100101001000000001010010010000111011001100101001"; WHEN "1001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100100001010100101111111111001100001111011011000"; WHEN "1001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100011001101101100000101001110001011001110111100"; WHEN "1010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100010010001010011110111010010010011111110100100"; WHEN "1010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100001010101011101101010111010101100101110000010"; WHEN "1010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100000011010001001110100101101010000111010011101"; WHEN "1010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011111011111011000101001000000111110001110111111"; WHEN "1010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011110100101001010011011111101101011111101000010"; WHEN "1010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011101101011011111100001011100000010100000001101"; WHEN "1010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011100110010011000001101000101010011000110001101"; WHEN "1010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011111001110100110010010011001111011110111011"; WHEN "1011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011000001110101100100010000000001110100011101"; WHEN "1011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011010001010011010110101110110000100101001100010"; WHEN "1011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011001010011100100111001101111111011000001100001"; WHEN "1011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011000011101010100000010011000001000101101011001"; WHEN "1011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010111100111101000100001111001001010100001001100"; WHEN "1011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010110110010100010101010001101001110110001111011"; WHEN "1011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101111110000010101100111110001101111011011100"; WHEN "1011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101001010001000111011100101100011001011100101"; WHEN "1100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010100010110110101100111001100000101011000010000"; WHEN "1100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010011100100001001000000101001111111111010110011"; WHEN "1100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010110010000011011000100110101011110110000011"; WHEN "1100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010000000100100111111011000101001000001000001"; WHEN "1100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010001001111101110000101000101010111011100100101"; WHEN "1100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010000011111011110111001100001010000110000001000"; WHEN "1100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111101111110111101100001111100001101100011111"; WHEN "1100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111000000111000101100100010000011111010101010"; WHEN "1101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001110010010100010001001011001010111110000100010"; WHEN "1101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001101100100110100010001100100011110001100110110"; WHEN "1101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100110111101111010011100000110010111101110011"; WHEN "1101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100001011010011011101011010000110101111000110"; WHEN "1101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001011011111100000111101001010011001011111101101"; WHEN "1101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010110100011000000000011001110101000000001010"; WHEN "1101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010001001111000110100011110100111011011010110"; WHEN "1101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001001100000000011100110011100111110000011010110"; WHEN "1110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000110110111000100011000111000000001100101100"; WHEN "1110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000001110010111110110111100101010001100011100"; WHEN "1110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000111100110100001101110001011101000100010101000"; WHEN "1110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110111111010110010100101111010011001100111001"; WHEN "1110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110011000110101110110010000101000111111101001"; WHEN "1110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101110011000000011110000110001011001010001101"; WHEN "1110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101001101110110010111010011111001000001110011"; WHEN "1110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100101001010111101100101011001011110111111001"; WHEN "1111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100000101100100101000101010110010110110110011"; WHEN "1111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011100010011101010101011110101111000111101111"; WHEN "1111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011000000000001111101000000010000000010001101"; WHEN "1111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000010011110010010101000110101101111100100010110"; WHEN "1111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001111101001111100010010010101110110011110010"; WHEN "1111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001011100111000110010010111110010100110111110"; WHEN "1111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000111101001110100001110010100000011000001001"; WHEN "1111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000011110010000111000111101011011000001000111"; WHEN OTHERS => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; END CASE; -- End reserved scope level END PROCESS; --cIncludingRoundingBit_uid253_sinPiZPolyEval(BITJOIN,252)@26 cIncludingRoundingBit_uid253_sinPiZPolyEval_q <= memoryC1_uid227_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0(REG,408)@26 reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid253_sinPiZPolyEval_q; END IF; END PROCESS; --ts4_uid254_sinPiZPolyEval(ADD,253)@27 ts4_uid254_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((52 downto 52 => reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q(51)) & reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q); ts4_uid254_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((52 downto 46 => reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q(45)) & reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q); ts4_uid254_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid254_sinPiZPolyEval_a) + SIGNED(ts4_uid254_sinPiZPolyEval_b)); ts4_uid254_sinPiZPolyEval_q <= ts4_uid254_sinPiZPolyEval_o(52 downto 0); --s4_uid255_sinPiZPolyEval(BITSELECT,254)@27 s4_uid255_sinPiZPolyEval_in <= ts4_uid254_sinPiZPolyEval_q; s4_uid255_sinPiZPolyEval_b <= s4_uid255_sinPiZPolyEval_in(52 downto 1); --yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval(BITSELECT,301)@27 yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b; yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in(51 downto 25); --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9(REG,409)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor(LOGICAL,1117) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q <= not (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a or ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top(CONSTANT,1113) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q <= "010011"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp(LOGICAL,1114) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a = ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b else "0"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg(REG,1115) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena(REG,1118) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q = "1") THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd(LOGICAL,1119) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a and ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b; --xBottomBits_uid305_pT5_uid257_sinPiZPolyEval(BITSELECT,304)@5 xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b(17 downto 0); xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt(COUNTER,1109) -- every=1, low=0, high=19, step=1, init=1 ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i = 18 THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '1'; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i - 19; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i,5)); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg(REG,1110) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux(MUX,1111) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q) BEGIN CASE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s IS WHEN "0" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; WHEN "1" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; WHEN OTHERS => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem(DUALMEM,1108) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 <= areset; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 5, numwords_a => 20, width_b => 18, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0, clock1 => clk, address_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq, address_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa, data_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia ); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg(DELAY,1107) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q, xout => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q, clk => clk, aclr => areset ); --pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval(BITJOIN,306)@27 pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7(REG,411)@27 reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid304_pT5_uid257_sinPiZPolyEval(BITSELECT,303)@27 yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b(24 downto 0); yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b <= yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a(DELAY,750)@27 ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b, xout => ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval(BITJOIN,305)@28 spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q; --pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval(BITJOIN,307)@28 pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q <= spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q & GND_q; --reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6(REG,410)@28 reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor(LOGICAL,1104) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top(CONSTANT,1100) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q <= "010100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp(LOGICAL,1101) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg(REG,1102) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena(REG,1105) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd(LOGICAL,1106) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1096) -- every=1, low=0, high=20, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i = 19 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i - 20; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i,5)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg(REG,1097) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux(MUX,1098) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem(DUALMEM,1095) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 5, numwords_a => 21, width_b => 45, widthad_b => 5, numwords_b => 21, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg(DELAY,1094) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval(BITSELECT,300)@28 xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q; xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in(44 downto 18); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4(REG,412)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma(CHAINMULTADD,347)@29 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval(BITSELECT,309)@32 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in(54 downto 1); --highBBits_uid312_pT5_uid257_sinPiZPolyEval(BITSELECT,311)@32 highBBits_uid312_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b; highBBits_uid312_pT5_uid257_sinPiZPolyEval_b <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_in(53 downto 25); --reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1(REG,415)@32 reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1(REG,413)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b(DELAY,747)@28 ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0(REG,414)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid303_pT5_uid257_sinPiZPolyEval(MULT,302)@29 topProd_uid303_pT5_uid257_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_b); topProd_uid303_pT5_uid257_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid303_pT5_uid257_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid303_pT5_uid257_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0(REG,416)@32 reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid313_pT5_uid257_sinPiZPolyEval(ADD,312)@33 sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q(53)) & reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b)); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid311_pT5_uid257_sinPiZPolyEval(BITSELECT,310)@32 lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b(24 downto 0); lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b <= lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a(DELAY,758)@32 ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b, xout => ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid311_uid314_pT5_uid257_sinPiZPolyEval(BITJOIN,313)@33 add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q & ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q; --R_uid315_pT5_uid257_sinPiZPolyEval(BITSELECT,314)@33 R_uid315_pT5_uid257_sinPiZPolyEval_in <= add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q(78 downto 0); R_uid315_pT5_uid257_sinPiZPolyEval_b <= R_uid315_pT5_uid257_sinPiZPolyEval_in(78 downto 25); --reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1(REG,417)@33 reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= R_uid315_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor(LOGICAL,1142) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1138) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q <= "011001"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp(LOGICAL,1139) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg(REG,1140) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena(REG,1143) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1144) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1134) -- every=1, low=0, high=25, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i = 24 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i - 25; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg(REG,1135) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1136) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1133) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 26, width_b => 7, widthad_b => 5, numwords_b => 26, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg(DELAY,1132) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0(REG,379)@32 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC0_uid226_sinPiZTableGenerator(LOOKUP,225)@33 memoryC0_uid226_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; WHEN "0000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111010001111111001101111011000111100001001010"; WHEN "0000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000101010101111101111010001101100110011111100100"; WHEN "0000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000010000111010001110111000001110010011001110001"; WHEN "0000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001111101100101111100010000110111011000000101000010"; WHEN "0000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110111110001111110110010110011100111000110011101"; WHEN "0000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110000101011011011100110100000100010100111010101"; WHEN "0000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001101000010010010101010100001100000100101011101101"; WHEN "0001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001011110100110101111000010100110110100001011000010"; WHEN "0001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001010011101000101100010111000010101101001011110101"; WHEN "0001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001000111011000010001010101010001011100000010111010"; WHEN "0001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000111001110101100010011111100010101010110110110111"; WHEN "0001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000101011000000100100110110100010000001101000110010"; WHEN "0001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000011010111001011101111001010100111001000011000110"; WHEN "0001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000001001100000010011100101010111111111101111100110"; WHEN "0001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111110110110101001100010110011100110010010101101111"; WHEN "0010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111100010111000001111000110100110100110000010101111"; WHEN "0010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111001101101001100011001110000111100101111100011100"; WHEN "0010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110110111001001010000100011011101100011000000101111"; WHEN "0010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110011111010111011111011011001110010110110010111000"; WHEN "0010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110000110010100011000101000000100011000111000100110"; WHEN "0010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101101100000000000101011010101010100111001000011100"; WHEN "0010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101010000011010101111100001101000100000101011011110"; WHEN "0010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100110011100100100001001001011101110011110100001011"; WHEN "0011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100010101011101100100111100011101111110101100100111"; WHEN "0011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011110110000110000110000010101011100010111110000011"; WHEN "0011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011010101011110010000000001110011001100010100001001"; WHEN "0011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010110011100110001110111101000110101001111110010101"; WHEN "0011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010010000011110001111010101010111011011010001011111"; WHEN "0011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001101100000110011110001000110001001111001100110001"; WHEN "0011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001000110011111001000110010110100010111000011111111"; WHEN "0011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001000011111101000011101001100001111101100010010011001"; WHEN "0100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111110111100010101001101010111010101001011000110001"; WHEN "0100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111001110001101111101000001101110110110001001100100"; WHEN "0100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000110100011101010100110100000100001100111000110001110"; WHEN "0100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101110111111000110101110011111101010000010000111000"; WHEN "0100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101001010111000111011000101011010001011010101011100"; WHEN "0100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000100011100101011000110111010110111110001001101100111"; WHEN "0100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000011101101001111101010010110110101000111000011000010"; WHEN "0100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010111100100110110110111000001001011110110011001101"; WHEN "0101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010001010110000111110011001111100101011011000101100"; WHEN "0101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000001010111101110010011010011011111001000011101001111"; WHEN "0101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000000100011011111001000011000000001110101111000110101"; WHEN "0101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111111101110000011110000110110101110000111000001001000"; WHEN "0101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111110110111011100100000011010011101000101101101101111"; WHEN "0101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101111111101001101011001001101111001001010100111010"; WHEN "0101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101000110101011100101100110100011000001100101000111"; WHEN "0101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111100001100100010100100101110001100110101011111100110"; WHEN "0110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111011010001001110111101111001001100110110011000001101"; WHEN "0110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111010010100110001000110111011000110000110111110111111"; WHEN "0110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111001010111001001010110000010010100110110110111111101"; WHEN "0110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111000011000011000000001111000000100110010000101101101"; WHEN "0110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110111011000011101100001100000000111000101001011011010"; WHEN "0110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110110010111011010001100011000101000010101101011001001"; WHEN "0110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110101010101001110011010011010000110001111000101001011"; WHEN "0110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110100010001111010100011110111000101000100011101001111"; WHEN "0111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110011001101011111000001011100000101000110101010111101"; WHEN "0111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110010000111111100001100001111010111101111011010000110"; WHEN "0111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110001000001010010011101110000110100100001000000010111"; WHEN "0111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101111111001100010001111111001101101111011001101100100"; WHEN "0111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101110110000101011111100111100100110000100111011101101"; WHEN "0111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101101100110101111111111100101000011001011000100010101"; WHEN "0111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101100011011101110110010110111100011110100100000110011"; WHEN "0111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101011001111101000110010010001010011001011011010110110"; WHEN "1000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101010000010011110011001100111111100111011110011001101"; WHEN "1000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101000110100010000000101001001100001000111100100001001"; WHEN "1000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100111100100111110010001011100000111110000000101011101"; WHEN "1000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100110010100101001011011011101110100010101011000001110"; WHEN "1000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100101000011010010000000100100011001001010111111110011"; WHEN "1000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100011110000111000011110011101001010100010101110100101"; WHEN "1000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100010011101011101010011001100110001101101001100010111"; WHEN "1000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100001001001000000111101001110111111110000011100100111"; WHEN "1001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011111110011100011111011010110100000010100101010111001"; WHEN "1001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011110011101000110101100101100101100000111000011110001"; WHEN "1001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011101000101101001110000110001011011010011000000110010"; WHEN "1001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011011101101001101100111011010110111110001101101101010"; WHEN "1001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011010010011110010110000110101001111010000001101101100"; WHEN "1001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011000111001011001101101100010100101001100000111100110"; WHEN "1001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010111011110000010111110011010100100100110111110110011"; WHEN "1001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010110000001101111000100101010010001110000100000110101"; WHEN "1010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010100100100011110100001110011111011100111101101011110"; WHEN "1010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010011000110010001110111101110101101010011000000111111"; WHEN "1010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010001100111001001101000100110011111001111100111000001"; WHEN "1010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010000000111000110010110111011101000010111111101010001"; WHEN "1010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001110100110001000100101100010101111000001101101010100"; WHEN "1010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001101000100010000110111100100011001110011000100010010"; WHEN "1010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001011100001011111110000011101000000001111110000000000"; WHEN "1010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001001111101110101110011111100011011011101101000101110"; WHEN "1011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001000011001010011100110000101110110100001001110110000"; WHEN "1011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000110110011111001101011001111011110110010000011100000"; WHEN "1011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000101001101101000101000000010010100000111000101001110"; WHEN "1011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000011100110100001000001011001111000111011010101001101"; WHEN "1011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000001111110100011011100100100000010001010101111111000"; WHEN "1011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000000010101110000011111000000100111000111011110010110"; WHEN "1011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111110101100001000101110100001010001000111101001001101"; WHEN "1011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111101000001101100110001001001001011001011110100011010"; WHEN "1100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111011010110011101001101001100110001011110001011110000"; WHEN "1100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111001101010011010101001010001100000101010101000000111"; WHEN "1100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110111111101100101101100001101100101001111110101000001"; WHEN "1100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110110001111111110111101000111101010101001011110111000"; WHEN "1100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110100100001100111000011010110101010010011110001011110"; WHEN "1100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110010110010011110100110100001011010101000001111000001"; WHEN "1100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110001000010100110001110011110011101110100000111111001"; WHEN "1100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101111010001111110100011010011110000101000011010111010"; WHEN "1101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101101100000101000001101010110011001000011100110100101"; WHEN "1101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101011101110100011110101001010010100110101010011100110"; WHEN "1101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101001111011110010000011100010000111111100000000100011"; WHEN "1101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101000001000010011100001011110101010111100110111011100"; WHEN "1101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100110010100001000111000001110111001010101110101010001"; WHEN "1101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100100011111010010110001001111011111101010001100000100"; WHEN "1101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100010101001110001110110001010101001101001100111101111"; WHEN "1101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100000110011100110110000110111110000010001111110011101"; WHEN "1110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011110111100110010001011011011000111101011110100101010"; WHEN "1110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011101000101010100110000000101101101000001111101101101"; WHEN "1110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011011001101001111001001010100110100010100000001010111"; WHEN "1110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011001010100100010000001110001110110000100001110111001"; WHEN "1110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010111011011001110000100010001111101000000100110100000"; WHEN "1110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010101100001010011111011110101110011100111100001100101"; WHEN "1110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010011100110110100010011101001010001101000000010101011"; WHEN "1110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010001101011101111110111000011001001011101110101101100"; WHEN "1111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001111110000000111010001100100110101101001001001010110"; WHEN "1111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001101110011111011001110111010000110000010101010100001"; WHEN "1111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001011110111001100011010111000101101001011101010010011"; WHEN "1111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001001111001111011100001100000001101011010010111101001"; WHEN "1111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000111111100001001001110111001100110000010110101011110"; WHEN "1111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000101111101110110001111010111000000011100010110001010"; WHEN "1111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000011111111000011001111010011011101000011100101001111"; WHEN "1111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000001111111110000111011010010100000011001101000010011"; WHEN OTHERS => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid258_sinPiZPolyEval(CONSTANT,257) rndBit_uid258_sinPiZPolyEval_q <= "001"; --cIncludingRoundingBit_uid259_sinPiZPolyEval(BITJOIN,258)@33 cIncludingRoundingBit_uid259_sinPiZPolyEval_q <= memoryC0_uid226_sinPiZTableGenerator_q & rndBit_uid258_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0(REG,418)@33 reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid259_sinPiZPolyEval_q; END IF; END PROCESS; --ts5_uid260_sinPiZPolyEval(ADD,259)@34 ts5_uid260_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q); ts5_uid260_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((61 downto 54 => reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q(53)) & reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q); ts5_uid260_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid260_sinPiZPolyEval_a) + SIGNED(ts5_uid260_sinPiZPolyEval_b)); ts5_uid260_sinPiZPolyEval_q <= ts5_uid260_sinPiZPolyEval_o(61 downto 0); --s5_uid261_sinPiZPolyEval(BITSELECT,260)@34 s5_uid261_sinPiZPolyEval_in <= ts5_uid260_sinPiZPolyEval_q; s5_uid261_sinPiZPolyEval_b <= s5_uid261_sinPiZPolyEval_in(61 downto 1); --fxpSinRes_uid66_fpSinPiTest(BITSELECT,65)@34 fxpSinRes_uid66_fpSinPiTest_in <= s5_uid261_sinPiZPolyEval_b(58 downto 0); fxpSinRes_uid66_fpSinPiTest_b <= fxpSinRes_uid66_fpSinPiTest_in(58 downto 5); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor(LOGICAL,963) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q <= not (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a or ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top(CONSTANT,959) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q <= "011111"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp(LOGICAL,960) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q <= "1" when ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a = ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b else "0"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg(REG,961) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena(REG,964) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q = "1") THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd(LOGICAL,965) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a and ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt(COUNTER,955) -- every=1, low=0, high=31, step=1, init=1 ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ELSIF (clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg(REG,956) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux(MUX,957) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux: PROCESS (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem(DUALMEM,954) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia <= sinXIsX_uid30_fpSinPiTest_c; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 32, width_b => 1, widthad_b => 5, numwords_b => 32, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq, address_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa, data_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia ); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg(DELAY,953) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --multRightOp_uid68_fpSinPiTest(MUX,67)@34 multRightOp_uid68_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q; multRightOp_uid68_fpSinPiTest: PROCESS (multRightOp_uid68_fpSinPiTest_s, fxpSinRes_uid66_fpSinPiTest_b) BEGIN CASE multRightOp_uid68_fpSinPiTest_s IS WHEN "0" => multRightOp_uid68_fpSinPiTest_q <= fxpSinRes_uid66_fpSinPiTest_b; WHEN "1" => multRightOp_uid68_fpSinPiTest_q <= piwFP2_uid67_fpSinPiTest_q; WHEN OTHERS => multRightOp_uid68_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_b_1(BITSELECT,318)@34 mul2xSinRes_uid69_fpSinPiTest_b_1_in <= multRightOp_uid68_fpSinPiTest_q; mul2xSinRes_uid69_fpSinPiTest_b_1_b <= mul2xSinRes_uid69_fpSinPiTest_b_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1(REG,423)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor(LOGICAL,1129) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q <= not (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a or ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top(CONSTANT,1125) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q <= "010110"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp(LOGICAL,1126) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q <= "1" when ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a = ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b else "0"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg(REG,1127) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena(REG,1130) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q = "1") THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd(LOGICAL,1131) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a and ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor(LOGICAL,937) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a or ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top(CONSTANT,933) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q <= "0111"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp(LOGICAL,934) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a = ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b else "0"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg(REG,935) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena(REG,938) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q = "1") THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd(LOGICAL,939) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt(COUNTER,929) -- every=1, low=0, high=7, step=1, init=1 ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,3); ELSIF (clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i + 1; END IF; END PROCESS; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i,3)); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg(REG,930) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux(MUX,931) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q) BEGIN CASE ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s IS WHEN "0" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; WHEN "1" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; WHEN OTHERS => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem(DUALMEM,928) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 <= areset; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia <= oFracX_uid31_uid31_fpSinPiTest_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 3, numwords_a => 8, width_b => 53, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq, address_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa, data_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia ); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq(52 downto 0); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg(DELAY,927) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg : dspba_delay GENERIC MAP ( width => 53, depth => 1 ) PORT MAP ( xin => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q, xout => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q, clk => clk, aclr => areset ); --LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest(BITSELECT,220)@10 LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q(77 downto 0); LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in(77 downto 0); --leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest(BITJOIN,221)@10 leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b & GND_q; --LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest(BITSELECT,204)@9 LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(54 downto 0); LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in(54 downto 0); --leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest(BITJOIN,205)@9 leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest(BITSELECT,201)@9 LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(62 downto 0); LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in(62 downto 0); --leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest(BITJOIN,202)@9 leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest(BITSELECT,198)@9 LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(70 downto 0); LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in(70 downto 0); --leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest(BITJOIN,199)@9 leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --ozz_uid41_fpSinPiTest(CONSTANT,40) ozz_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor(LOGICAL,1040) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q <= not (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a or ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top(CONSTANT,1036) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q <= "011"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp(LOGICAL,1037) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q <= "1" when ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a = ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b else "0"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg(REG,1038) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena(REG,1041) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q = "1") THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd(LOGICAL,1042) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a and ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b; --vStage_uid149_lzcZ_uid51_fpSinPiTest(BITSELECT,148)@4 vStage_uid149_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(14 downto 0); vStage_uid149_lzcZ_uid51_fpSinPiTest_b <= vStage_uid149_lzcZ_uid51_fpSinPiTest_in(14 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt(COUNTER,1032) -- every=1, low=0, high=3, step=1, init=1 ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,2); ELSIF (clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i,2)); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg(REG,1033) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux(MUX,1034) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1043) ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= vStage_uid149_lzcZ_uid51_fpSinPiTest_b; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 2, numwords_a => 4, width_b => 15, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(14 downto 0); --leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest(BITJOIN,193)@9 leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X46dto0_uid190_alignedZ_uid52_fpSinPiTest(BITSELECT,189)@4 X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(46 downto 0); X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in(46 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1031) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 47, widthad_a => 2, numwords_a => 4, width_b => 47, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(46 downto 0); --leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest(BITJOIN,190)@9 leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor(LOGICAL,1065) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q <= not (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a or ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top(CONSTANT,1061) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q <= "010"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp(LOGICAL,1062) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q <= "1" when ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a = ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b else "0"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg(REG,1063) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena(REG,1066) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q = "1") THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd(LOGICAL,1067) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a and ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt(COUNTER,1057) -- every=1, low=0, high=2, step=1, init=1 ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i = 1 THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i - 2; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i,2)); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg(REG,1058) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux(MUX,1059) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux: PROCESS (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem(DUALMEM,1056) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia <= z_uid49_fpSinPiTest_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 79, widthad_a => 2, numwords_a => 3, width_b => 79, widthad_b => 2, numwords_b => 3, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq, address_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa, data_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia ); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq(78 downto 0); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg(DELAY,1055) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q, xout => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --rVStage_uid146_lzcZ_uid51_fpSinPiTest(BITSELECT,145)@4 rVStage_uid146_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; rVStage_uid146_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_in(78 downto 15); --reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0(REG,365)@4 reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid147_lzcZ_uid51_fpSinPiTest(LOGICAL,146)@5 vCount_uid147_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid147_lzcZ_uid51_fpSinPiTest_a = vCount_uid147_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g(DELAY,629)@5 ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => vCount_uid147_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q, clk => clk, aclr => areset ); --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b(DELAY,587)@4 ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => vStage_uid149_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q, clk => clk, aclr => areset ); --mO_uid148_lzcZ_uid51_fpSinPiTest(CONSTANT,147) mO_uid148_lzcZ_uid51_fpSinPiTest_q <= "1111111111111111111111111111111111111111111111111"; --cStage_uid150_lzcZ_uid51_fpSinPiTest(BITJOIN,149)@5 cStage_uid150_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q & mO_uid148_lzcZ_uid51_fpSinPiTest_q; --ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c(DELAY,589)@4 ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 64, depth => 1 ) PORT MAP ( xin => rVStage_uid146_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid152_lzcZ_uid51_fpSinPiTest(MUX,151)@5 vStagei_uid152_lzcZ_uid51_fpSinPiTest_s <= vCount_uid147_lzcZ_uid51_fpSinPiTest_q; vStagei_uid152_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid152_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, cStage_uid150_lzcZ_uid51_fpSinPiTest_q) BEGIN CASE vStagei_uid152_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= cStage_uid150_lzcZ_uid51_fpSinPiTest_q; WHEN OTHERS => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid154_lzcZ_uid51_fpSinPiTest(BITSELECT,153)@5 rVStage_uid154_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q; rVStage_uid154_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_in(63 downto 32); --reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0(REG,366)@5 reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= "00000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid155_lzcZ_uid51_fpSinPiTest(LOGICAL,154)@6 vCount_uid155_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid155_lzcZ_uid51_fpSinPiTest_a = vCount_uid155_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f(DELAY,628)@6 ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid155_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q, clk => clk, aclr => areset ); --vStage_uid156_lzcZ_uid51_fpSinPiTest(BITSELECT,155)@5 vStage_uid156_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q(31 downto 0); vStage_uid156_lzcZ_uid51_fpSinPiTest_b <= vStage_uid156_lzcZ_uid51_fpSinPiTest_in(31 downto 0); --ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d(DELAY,596)@5 ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => vStage_uid156_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c(DELAY,595)@5 ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => rVStage_uid154_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid158_lzcZ_uid51_fpSinPiTest(MUX,157)@6 vStagei_uid158_lzcZ_uid51_fpSinPiTest_s <= vCount_uid155_lzcZ_uid51_fpSinPiTest_q; vStagei_uid158_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid158_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid158_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid160_lzcZ_uid51_fpSinPiTest(BITSELECT,159)@6 rVStage_uid160_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q; rVStage_uid160_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_in(31 downto 16); --reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0(REG,367)@6 reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid161_lzcZ_uid51_fpSinPiTest(LOGICAL,160)@7 vCount_uid161_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid161_lzcZ_uid51_fpSinPiTest_a = vCount_uid161_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e(DELAY,627)@7 ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid161_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q, clk => clk, aclr => areset ); --vStage_uid162_lzcZ_uid51_fpSinPiTest(BITSELECT,161)@6 vStage_uid162_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q(15 downto 0); vStage_uid162_lzcZ_uid51_fpSinPiTest_b <= vStage_uid162_lzcZ_uid51_fpSinPiTest_in(15 downto 0); --ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d(DELAY,602)@6 ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => vStage_uid162_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c(DELAY,601)@6 ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => rVStage_uid160_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid164_lzcZ_uid51_fpSinPiTest(MUX,163)@7 vStagei_uid164_lzcZ_uid51_fpSinPiTest_s <= vCount_uid161_lzcZ_uid51_fpSinPiTest_q; vStagei_uid164_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid164_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid164_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid166_lzcZ_uid51_fpSinPiTest(BITSELECT,165)@7 rVStage_uid166_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q; rVStage_uid166_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_in(15 downto 8); --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0(REG,368)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid167_lzcZ_uid51_fpSinPiTest(LOGICAL,166)@8 vCount_uid167_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid167_lzcZ_uid51_fpSinPiTest_a = vCount_uid167_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid168_lzcZ_uid51_fpSinPiTest(BITSELECT,167)@7 vStage_uid168_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q(7 downto 0); vStage_uid168_lzcZ_uid51_fpSinPiTest_b <= vStage_uid168_lzcZ_uid51_fpSinPiTest_in(7 downto 0); --reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3(REG,369)@7 reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= vStage_uid168_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2(REG,370)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vStagei_uid170_lzcZ_uid51_fpSinPiTest(MUX,169)@8 vStagei_uid170_lzcZ_uid51_fpSinPiTest_s <= vCount_uid167_lzcZ_uid51_fpSinPiTest_q; vStagei_uid170_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid170_lzcZ_uid51_fpSinPiTest_s, reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q, reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q) BEGIN CASE vStagei_uid170_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q; WHEN "1" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q; WHEN OTHERS => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid172_lzcZ_uid51_fpSinPiTest(BITSELECT,171)@8 rVStage_uid172_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q; rVStage_uid172_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_in(7 downto 4); --vCount_uid173_lzcZ_uid51_fpSinPiTest(LOGICAL,172)@8 vCount_uid173_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; vCount_uid173_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; vCount_uid173_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid173_lzcZ_uid51_fpSinPiTest_a = vCount_uid173_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid174_lzcZ_uid51_fpSinPiTest(BITSELECT,173)@8 vStage_uid174_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q(3 downto 0); vStage_uid174_lzcZ_uid51_fpSinPiTest_b <= vStage_uid174_lzcZ_uid51_fpSinPiTest_in(3 downto 0); --vStagei_uid176_lzcZ_uid51_fpSinPiTest(MUX,175)@8 vStagei_uid176_lzcZ_uid51_fpSinPiTest_s <= vCount_uid173_lzcZ_uid51_fpSinPiTest_q; vStagei_uid176_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid176_lzcZ_uid51_fpSinPiTest_s, rVStage_uid172_lzcZ_uid51_fpSinPiTest_b, vStage_uid174_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid176_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= vStage_uid174_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid178_lzcZ_uid51_fpSinPiTest(BITSELECT,177)@8 rVStage_uid178_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q; rVStage_uid178_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_in(3 downto 2); --vCount_uid179_lzcZ_uid51_fpSinPiTest(LOGICAL,178)@8 vCount_uid179_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; vCount_uid179_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; vCount_uid179_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid179_lzcZ_uid51_fpSinPiTest_a = vCount_uid179_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid180_lzcZ_uid51_fpSinPiTest(BITSELECT,179)@8 vStage_uid180_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q(1 downto 0); vStage_uid180_lzcZ_uid51_fpSinPiTest_b <= vStage_uid180_lzcZ_uid51_fpSinPiTest_in(1 downto 0); --vStagei_uid182_lzcZ_uid51_fpSinPiTest(MUX,181)@8 vStagei_uid182_lzcZ_uid51_fpSinPiTest_s <= vCount_uid179_lzcZ_uid51_fpSinPiTest_q; vStagei_uid182_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid182_lzcZ_uid51_fpSinPiTest_s, rVStage_uid178_lzcZ_uid51_fpSinPiTest_b, vStage_uid180_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid182_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= vStage_uid180_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid184_lzcZ_uid51_fpSinPiTest(BITSELECT,183)@8 rVStage_uid184_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid51_fpSinPiTest_q; rVStage_uid184_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_in(1 downto 1); --vCount_uid185_lzcZ_uid51_fpSinPiTest(LOGICAL,184)@8 vCount_uid185_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_b; vCount_uid185_lzcZ_uid51_fpSinPiTest_b <= GND_q; vCount_uid185_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid185_lzcZ_uid51_fpSinPiTest_a = vCount_uid185_lzcZ_uid51_fpSinPiTest_b else "0"; --r_uid186_lzcZ_uid51_fpSinPiTest(BITJOIN,185)@8 r_uid186_lzcZ_uid51_fpSinPiTest_q <= ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q & ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q & ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q & vCount_uid167_lzcZ_uid51_fpSinPiTest_q & vCount_uid173_lzcZ_uid51_fpSinPiTest_q & vCount_uid179_lzcZ_uid51_fpSinPiTest_q & vCount_uid185_lzcZ_uid51_fpSinPiTest_q; --leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest(BITSELECT,195)@8 leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q; leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in(6 downto 5); --reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1(REG,371)@8 reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest(MUX,196)@9 leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q, leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q; WHEN "01" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ozz_uid41_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest(BITSELECT,206)@8 leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(4 downto 0); leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in(4 downto 3); --reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1(REG,372)@8 reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest(MUX,207)@9 leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s, leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest(BITSELECT,215)@9 LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(72 downto 0); LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in(72 downto 0); --leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest(BITJOIN,216)@9 leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5(REG,374)@9 reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest(BITSELECT,212)@9 LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest(BITJOIN,213)@9 leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4(REG,375)@9 reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest(BITSELECT,209)@9 LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest(BITJOIN,210)@9 leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3(REG,376)@9 reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2(REG,377)@9 reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest(BITSELECT,217)@8 leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(2 downto 0); leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in(2 downto 1); --reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1(REG,373)@8 reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b(DELAY,657)@9 ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest(MUX,218)@10 leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s, reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q, reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q, reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q, reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q) BEGIN CASE leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q; WHEN "01" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q; WHEN "10" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q; WHEN "11" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q; WHEN OTHERS => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest(BITSELECT,222)@8 leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(0 downto 0); leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in(0 downto 0); --reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1(REG,378)@8 reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b(DELAY,665)@9 ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest(MUX,223)@10 leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s, leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q, leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q; WHEN "1" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --alignedZLow_uid53_fpSinPiTest(BITSELECT,52)@10 alignedZLow_uid53_fpSinPiTest_in <= leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q; alignedZLow_uid53_fpSinPiTest_b <= alignedZLow_uid53_fpSinPiTest_in(78 downto 27); --pHardCase_uid54_fpSinPiTest(BITJOIN,53)@10 pHardCase_uid54_fpSinPiTest_q <= alignedZLow_uid53_fpSinPiTest_b & GND_q; --ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b(DELAY,474)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 10 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q, clk => clk, aclr => areset ); --p_uid55_fpSinPiTest(MUX,54)@10 p_uid55_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q; p_uid55_fpSinPiTest: PROCESS (p_uid55_fpSinPiTest_s, pHardCase_uid54_fpSinPiTest_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q) BEGIN CASE p_uid55_fpSinPiTest_s IS WHEN "0" => p_uid55_fpSinPiTest_q <= pHardCase_uid54_fpSinPiTest_q; WHEN "1" => p_uid55_fpSinPiTest_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q; WHEN OTHERS => p_uid55_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt(COUNTER,1121) -- every=1, low=0, high=22, step=1, init=1 ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i = 21 THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i - 22; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i,5)); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg(REG,1122) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux(MUX,1123) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux: PROCESS (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q) BEGIN CASE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s IS WHEN "0" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; WHEN "1" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem(DUALMEM,1120) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 <= areset; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia <= p_uid55_fpSinPiTest_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 5, numwords_a => 23, width_b => 53, widthad_b => 5, numwords_b => 23, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq, address_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa, data_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia ); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq(52 downto 0); --mul2xSinRes_uid69_fpSinPiTest_a_1(BITSELECT,316)@34 mul2xSinRes_uid69_fpSinPiTest_a_1_in <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q); mul2xSinRes_uid69_fpSinPiTest_a_1_b <= mul2xSinRes_uid69_fpSinPiTest_a_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0(REG,424)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b1(MULT,322)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_b); mul2xSinRes_uid69_fpSinPiTest_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1(BITSELECT,329)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1(REG,425)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a_0(BITSELECT,315)@34 mul2xSinRes_uid69_fpSinPiTest_a_0_in <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_a_0_b <= mul2xSinRes_uid69_fpSinPiTest_a_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0(REG,426)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b1(MULT,321)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_b); mul2xSinRes_uid69_fpSinPiTest_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1(BITSELECT,327)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_zero_36(CONSTANT,332) mul2xSinRes_uid69_fpSinPiTest_zero_36_q <= "000000000000000000000000000"; --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2(BITJOIN,336)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1(BITSELECT,328)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_b_0(BITSELECT,317)@34 mul2xSinRes_uid69_fpSinPiTest_b_0_in <= multRightOp_uid68_fpSinPiTest_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_b_0_b <= mul2xSinRes_uid69_fpSinPiTest_b_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1(REG,421)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0(REG,422)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b0(MULT,320)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_b); mul2xSinRes_uid69_fpSinPiTest_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0(BITSELECT,325)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1(BITJOIN,335)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC(LOGICAL,340)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b; --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1(BITSELECT,330)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0(BITSELECT,326)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1(REG,419)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0(REG,420)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b0(MULT,319)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_b); mul2xSinRes_uid69_fpSinPiTest_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0(BITSELECT,324)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0(BITSELECT,323)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0(BITJOIN,334)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC(LOGICAL,339)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB(LOGICAL,338)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne(LOGICAL,341)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c; --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS(BITSELECT,342)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q(106 downto 0); mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in(106 downto 0); --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ(BITJOIN,343)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b & GND_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b(BITJOIN,350)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b(BITSELECT,353)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne(LOGICAL,337)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a(BITJOIN,348)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a(BITSELECT,352)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2(ADD,354)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin <= GND_q; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b) & mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c(0) <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(90); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(89 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b(DELAY,822)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q, clk => clk, aclr => areset ); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a(DELAY,821)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2(ADD,355)@39 mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q) & mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o(20 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a(DELAY,824)@39 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a : dspba_delay GENERIC MAP ( width => 89, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q(BITJOIN,356)@40 mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q; --normBit_uid70_fpSinPiTest(BITSELECT,69)@40 normBit_uid70_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(106 downto 0); normBit_uid70_fpSinPiTest_b <= normBit_uid70_fpSinPiTest_in(106 downto 106); --ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c(DELAY,497)@40 ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => normBit_uid70_fpSinPiTest_b, xout => ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q, clk => clk, aclr => areset ); --rndExpUpdate_uid75_uid76_fpSinPiTest(BITJOIN,75)@41 rndExpUpdate_uid75_uid76_fpSinPiTest_q <= ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q & cstAllZWF_uid10_fpSinPiTest_q & VCC_q; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor(LOGICAL,976) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q <= not (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a or ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top(CONSTANT,972) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q <= "011100"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp(LOGICAL,973) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a = ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b else "0"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg(REG,974) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena(REG,977) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q = "1") THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd(LOGICAL,978) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a and ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem(DUALMEM,941) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 <= areset; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia <= expX_uid6_fpSinPiTest_b; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 3, numwords_a => 7, width_b => 11, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq, address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa, data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia ); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq(10 downto 0); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg(DELAY,940) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q, clk => clk, aclr => areset ); --expXP1_uid58_fpSinPiTest(ADD,57)@9 expXP1_uid58_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q); expXP1_uid58_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & VCC_q); expXP1_uid58_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid58_fpSinPiTest_a) + UNSIGNED(expXP1_uid58_fpSinPiTest_b)); expXP1_uid58_fpSinPiTest_q <= expXP1_uid58_fpSinPiTest_o(11 downto 0); --expXP1R_uid59_fpSinPiTest(BITSELECT,58)@9 expXP1R_uid59_fpSinPiTest_in <= expXP1_uid58_fpSinPiTest_q(10 downto 0); expXP1R_uid59_fpSinPiTest_b <= expXP1R_uid59_fpSinPiTest_in(10 downto 0); --reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1(REG,427)@8 reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= r_uid186_lzcZ_uid51_fpSinPiTest_q; END IF; END PROCESS; --expHardCase_uid57_fpSinPiTest(SUB,56)@9 expHardCase_uid57_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid27_fpSinPiTest_q); expHardCase_uid57_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000" & reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q); expHardCase_uid57_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid57_fpSinPiTest_a) - UNSIGNED(expHardCase_uid57_fpSinPiTest_b)); expHardCase_uid57_fpSinPiTest_q <= expHardCase_uid57_fpSinPiTest_o(11 downto 0); --expHardCaseR_uid60_fpSinPiTest(BITSELECT,59)@9 expHardCaseR_uid60_fpSinPiTest_in <= expHardCase_uid57_fpSinPiTest_q(10 downto 0); expHardCaseR_uid60_fpSinPiTest_b <= expHardCaseR_uid60_fpSinPiTest_in(10 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b(DELAY,481)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 9 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q, clk => clk, aclr => areset ); --expP_uid61_fpSinPiTest(MUX,60)@9 expP_uid61_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q; expP_uid61_fpSinPiTest: PROCESS (expP_uid61_fpSinPiTest_s, expHardCaseR_uid60_fpSinPiTest_b, expXP1R_uid59_fpSinPiTest_b) BEGIN CASE expP_uid61_fpSinPiTest_s IS WHEN "0" => expP_uid61_fpSinPiTest_q <= expHardCaseR_uid60_fpSinPiTest_b; WHEN "1" => expP_uid61_fpSinPiTest_q <= expXP1R_uid59_fpSinPiTest_b; WHEN OTHERS => expP_uid61_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt(COUNTER,968) -- every=1, low=0, high=28, step=1, init=1 ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i = 27 THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i - 28; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg(REG,969) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux(MUX,970) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem(DUALMEM,967) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia <= expP_uid61_fpSinPiTest_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 29, width_b => 11, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq, address_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa, data_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia ); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq(10 downto 0); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg(DELAY,966) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q, xout => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --highRes_uid71_fpSinPiTest(BITSELECT,70)@40 highRes_uid71_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(105 downto 0); highRes_uid71_fpSinPiTest_b <= highRes_uid71_fpSinPiTest_in(105 downto 53); --lowRes_uid72_fpSinPiTest(BITSELECT,71)@40 lowRes_uid72_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(104 downto 0); lowRes_uid72_fpSinPiTest_b <= lowRes_uid72_fpSinPiTest_in(104 downto 52); --fracRCompPreRnd_uid73_fpSinPiTest(MUX,72)@40 fracRCompPreRnd_uid73_fpSinPiTest_s <= normBit_uid70_fpSinPiTest_b; fracRCompPreRnd_uid73_fpSinPiTest: PROCESS (fracRCompPreRnd_uid73_fpSinPiTest_s, lowRes_uid72_fpSinPiTest_b, highRes_uid71_fpSinPiTest_b) BEGIN CASE fracRCompPreRnd_uid73_fpSinPiTest_s IS WHEN "0" => fracRCompPreRnd_uid73_fpSinPiTest_q <= lowRes_uid72_fpSinPiTest_b; WHEN "1" => fracRCompPreRnd_uid73_fpSinPiTest_q <= highRes_uid71_fpSinPiTest_b; WHEN OTHERS => fracRCompPreRnd_uid73_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracPreRnd_uid74_uid74_fpSinPiTest(BITJOIN,73)@40 expFracPreRnd_uid74_uid74_fpSinPiTest_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q & fracRCompPreRnd_uid73_fpSinPiTest_q; --reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0(REG,428)@40 reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= expFracPreRnd_uid74_uid74_fpSinPiTest_q; END IF; END PROCESS; --expFracComp_uid77_fpSinPiTest(ADD,76)@41 expFracComp_uid77_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q); expFracComp_uid77_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & rndExpUpdate_uid75_uid76_fpSinPiTest_q); expFracComp_uid77_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid77_fpSinPiTest_a) + UNSIGNED(expFracComp_uid77_fpSinPiTest_b)); expFracComp_uid77_fpSinPiTest_q <= expFracComp_uid77_fpSinPiTest_o(64 downto 0); --expRComp_uid79_fpSinPiTest(BITSELECT,78)@41 expRComp_uid79_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(63 downto 0); expRComp_uid79_fpSinPiTest_b <= expRComp_uid79_fpSinPiTest_in(63 downto 53); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor(LOGICAL,1015) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q <= not (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a or ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top(CONSTANT,1011) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q <= "0100010"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp(LOGICAL,1012) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q <= "1" when ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a = ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b else "0"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg(REG,1013) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena(REG,1016) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q = "1") THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd(LOGICAL,1017) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a and ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b; --reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1(REG,429)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c(DELAY,516)@0 ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q, xout => ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b(DELAY,515)@0 ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => expXIsZero_uid15_fpSinPiTest_q, xout => ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q, clk => clk, aclr => areset ); --reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0(REG,361)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --excRZero_uid87_fpSinPiTest(LOGICAL,86)@3 excRZero_uid87_fpSinPiTest_a <= reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q; excRZero_uid87_fpSinPiTest_b <= ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q; excRZero_uid87_fpSinPiTest_c <= ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q; excRZero_uid87_fpSinPiTest_q <= excRZero_uid87_fpSinPiTest_a or excRZero_uid87_fpSinPiTest_b or excRZero_uid87_fpSinPiTest_c; --Or2ExcRZeroXIsInt_uid92_fpSinPiTest(LOGICAL,91)@3 Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a <= excRZero_uid87_fpSinPiTest_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b <= reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a or Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt(COUNTER,1007) -- every=1, low=0, high=34, step=1, init=1 ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i = 33 THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i - 34; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg(REG,1008) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux(MUX,1009) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux: PROCESS (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem(DUALMEM,1006) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 35, width_b => 1, widthad_b => 6, numwords_b => 35, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq, address_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa, data_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia ); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg(DELAY,1005) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q, xout => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --expRPostExc1_uid95_fpSinPiTest(MUX,94)@41 expRPostExc1_uid95_fpSinPiTest_s <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q; expRPostExc1_uid95_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE expRPostExc1_uid95_fpSinPiTest_s IS WHEN "0" => expRPostExc1_uid95_fpSinPiTest_q <= expRComp_uid79_fpSinPiTest_b; WHEN "1" => expRPostExc1_uid95_fpSinPiTest_q <= cstAllZWE_uid11_fpSinPiTest_q; WHEN OTHERS => expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --InvXIntExp_uid84_fpSinPiTest(LOGICAL,83)@2 InvXIntExp_uid84_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; InvXIntExp_uid84_fpSinPiTest_q <= not InvXIntExp_uid84_fpSinPiTest_a; --join_uid42_fpSinPiTest(BITJOIN,41)@2 join_uid42_fpSinPiTest_q <= VCC_q & ozz_uid41_fpSinPiTest_q; --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0(REG,359)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid43_fpSinPiTest(LOGICAL,42)@2 yIsZero_uid43_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q; yIsZero_uid43_fpSinPiTest_b <= join_uid42_fpSinPiTest_q; yIsZero_uid43_fpSinPiTest_q <= "1" when yIsZero_uid43_fpSinPiTest_a = yIsZero_uid43_fpSinPiTest_b else "0"; --And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest(LOGICAL,85)@2 And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b <= yIsZero_uid43_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c <= InvSinXIsX_uid80_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d <= InvXIntExp_uid84_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d; --Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest(LOGICAL,95)@1 Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a <= GND_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q <= Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a or Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b; --ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a(DELAY,528)@1 ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q, xout => ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q, clk => clk, aclr => areset ); --join_uid97_fpSinPiTest(BITJOIN,96)@2 join_uid97_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q & ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q; --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg(DELAY,1195) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => join_uid97_fpSinPiTest_q, xout => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q, clk => clk, aclr => areset ); --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem(DUALMEM,1196) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 <= areset; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 6, numwords_a => 37, width_b => 2, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0, clock1 => clk, address_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq, address_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa, data_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia ); ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq(1 downto 0); --reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1(REG,430)@41 reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q; END IF; END PROCESS; --expRPostExc_uid98_fpSinPiTest(MUX,97)@42 expRPostExc_uid98_fpSinPiTest_s <= reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q; expRPostExc_uid98_fpSinPiTest: PROCESS (expRPostExc_uid98_fpSinPiTest_s, expRPostExc1_uid95_fpSinPiTest_q) BEGIN CASE expRPostExc_uid98_fpSinPiTest_s IS WHEN "00" => expRPostExc_uid98_fpSinPiTest_q <= expRPostExc1_uid95_fpSinPiTest_q; WHEN "01" => expRPostExc_uid98_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q; WHEN "10" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN "11" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN OTHERS => expRPostExc_uid98_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --oneFracRPostExc2_uid90_fpSinPiTest(CONSTANT,89) oneFracRPostExc2_uid90_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracRComp_uid78_fpSinPiTest(BITSELECT,77)@41 fracRComp_uid78_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(52 downto 0); fracRComp_uid78_fpSinPiTest_b <= fracRComp_uid78_fpSinPiTest_in(52 downto 1); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor(LOGICAL,989) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q <= not (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a or ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top(CONSTANT,985) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q <= "0100001"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp(LOGICAL,986) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q <= "1" when ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a = ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b else "0"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg(REG,987) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena(REG,990) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q = "1") THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd(LOGICAL,991) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a and ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b; --reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1(REG,362)@3 reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= excRZero_uid87_fpSinPiTest_q; END IF; END PROCESS; --ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a(DELAY,517)@2 ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q, xout => ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q, clk => clk, aclr => areset ); --or_uid88_fpSinPiTest(LOGICAL,87)@4 or_uid88_fpSinPiTest_a <= ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q; or_uid88_fpSinPiTest_b <= reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q; or_uid88_fpSinPiTest_c <= GND_q; or_uid88_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN or_uid88_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN or_uid88_fpSinPiTest_q <= or_uid88_fpSinPiTest_a or or_uid88_fpSinPiTest_b or or_uid88_fpSinPiTest_c; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt(COUNTER,981) -- every=1, low=0, high=33, step=1, init=1 ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i = 32 THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i - 33; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg(REG,982) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux(MUX,983) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux: PROCESS (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem(DUALMEM,980) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia <= or_uid88_fpSinPiTest_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 34, width_b => 1, widthad_b => 6, numwords_b => 34, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq, address_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa, data_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia ); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg(DELAY,979) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q, xout => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --fracRPostExc1_uid89_fpSinPiTest(MUX,88)@41 fracRPostExc1_uid89_fpSinPiTest_s <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q; fracRPostExc1_uid89_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE fracRPostExc1_uid89_fpSinPiTest_s IS WHEN "0" => fracRPostExc1_uid89_fpSinPiTest_q <= fracRComp_uid78_fpSinPiTest_b; WHEN "1" => fracRPostExc1_uid89_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q; WHEN OTHERS => fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor(LOGICAL,1002) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q <= not (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a or ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top(CONSTANT,998) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q <= "0100110"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp(LOGICAL,999) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q <= "1" when ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a = ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b else "0"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg(REG,1000) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena(REG,1003) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q = "1") THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd(LOGICAL,1004) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a and ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg(DELAY,992) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q, xout => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q, clk => clk, aclr => areset ); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt(COUNTER,994) -- every=1, low=0, high=38, step=1, init=1 ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i = 37 THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i - 38; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg(REG,995) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux(MUX,996) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux: PROCESS (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem(DUALMEM,993) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 39, width_b => 1, widthad_b => 6, numwords_b => 39, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq, address_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa, data_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia ); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq(0 downto 0); --fracRPostExc_uid91_fpSinPiTest(MUX,90)@42 fracRPostExc_uid91_fpSinPiTest_s <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q; fracRPostExc_uid91_fpSinPiTest: PROCESS (fracRPostExc_uid91_fpSinPiTest_s, fracRPostExc1_uid89_fpSinPiTest_q) BEGIN CASE fracRPostExc_uid91_fpSinPiTest_s IS WHEN "0" => fracRPostExc_uid91_fpSinPiTest_q <= fracRPostExc1_uid89_fpSinPiTest_q; WHEN "1" => fracRPostExc_uid91_fpSinPiTest_q <= oneFracRPostExc2_uid90_fpSinPiTest_q; WHEN OTHERS => fracRPostExc_uid91_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid105_fpSinPiTest(BITJOIN,104)@42 R_uid105_fpSinPiTest_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q & expRPostExc_uid98_fpSinPiTest_q & fracRPostExc_uid91_fpSinPiTest_q; --ld_xIn_v_to_xOut_v_nor(LOGICAL,910) ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b); --ld_xIn_v_to_xOut_v_mem_top(CONSTANT,906) ld_xIn_v_to_xOut_v_mem_top_q <= "0100111"; --ld_xIn_v_to_xOut_v_cmp(LOGICAL,907) ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q; ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q); ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0"; --ld_xIn_v_to_xOut_v_cmpReg(REG,908) ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_sticky_ena(REG,911) ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q; END IF; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,912) ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q; ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b; --ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,902) -- every=1, low=0, high=39, step=1, init=1 ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 38 THEN ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1'; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; END IF; IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 39; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,6)); --ld_xIn_v_to_xOut_v_replace_rdreg(REG,903) ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_replace_rdmux(MUX,904) ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q; ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q) BEGIN CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q; WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,914) ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset; ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c; ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 6, numwords_a => 40, width_b => 8, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_c_to_xOut_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_c_to_xOut_c_replace_mem_iq, address_a => ld_xIn_c_to_xOut_c_replace_mem_aa, data_a => ld_xIn_c_to_xOut_c_replace_mem_ia ); ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0); --ld_xIn_c_to_xOut_c_outputreg(DELAY,913) ld_xIn_c_to_xOut_c_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset ); --ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,901) ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset; ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v; ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 40, width_b => 1, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_v_to_xOut_v_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_v_to_xOut_v_replace_mem_iq, address_a => ld_xIn_v_to_xOut_v_replace_mem_aa, data_a => ld_xIn_v_to_xOut_v_replace_mem_ia ); ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0); --ld_xIn_v_to_xOut_v_outputreg(DELAY,900) ld_xIn_v_to_xOut_v_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset ); --xOut(PORTOUT,4)@42 xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q; xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q; xOut_0 <= R_uid105_fpSinPiTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Debug Version 12.0 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from SinPiDPStratixVf400 -- VHDL created on Wed Sep 05 17:55:57 2012 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; USE work.SinPiDPStratixVf400_safe_path.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; -- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240 entity SinPiDPStratixVf400 is port ( xIn_v : in std_logic_vector(0 downto 0); xIn_c : in std_logic_vector(7 downto 0); xIn_0 : in std_logic_vector(63 downto 0); xOut_v : out std_logic_vector(0 downto 0); xOut_c : out std_logic_vector(7 downto 0); xOut_0 : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic; bus_clk : in std_logic; h_areset : in std_logic ); end; architecture normal of SinPiDPStratixVf400 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBias_uid12_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBiasPwF_uid13_fpSinPiTest_q : std_logic_vector (10 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0); signal biasM1_uid27_fpSinPiTest_q : std_logic_vector (10 downto 0); signal biasMwShift_uid29_fpSinPiTest_q : std_logic_vector (10 downto 0); signal shiftBias_uid32_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cst01pWShift_uid34_fpSinPiTest_q : std_logic_vector (27 downto 0); signal ozz_uid41_fpSinPiTest_q : std_logic_vector (78 downto 0); signal cOne_uid44_fpSinPiTest_q : std_logic_vector (80 downto 0); signal oneMinusY_uid45_fpSinPiTest_a : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_b : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_o : std_logic_vector (81 downto 0); signal oneMinusY_uid45_fpSinPiTest_q : std_logic_vector (81 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_a : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_b : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_o : std_logic_vector (84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_c : std_logic_vector (0 downto 0); signal piwFP2_uid67_fpSinPiTest_q : std_logic_vector (53 downto 0); signal or_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_b : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_c : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_q : std_logic_vector (51 downto 0); signal oneFracRPostExc2_uid90_fpSinPiTest_q : std_logic_vector (51 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (10 downto 0); signal InvXIsInt_uid100_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIsInt_uid100_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (31 downto 0); signal leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (63 downto 0); signal leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (15 downto 0); signal leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (23 downto 0); signal leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (5 downto 0); signal mO_uid148_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (48 downto 0); signal memoryC3_uid229_sinPiZTableGenerator_q : std_logic_vector(34 downto 0); signal memoryC4_uid230_sinPiZTableGenerator_q : std_logic_vector(25 downto 0); signal memoryC5_uid231_sinPiZTableGenerator_q : std_logic_vector(16 downto 0); signal rndBit_uid246_sinPiZPolyEval_q : std_logic_vector (1 downto 0); signal rndBit_uid258_sinPiZPolyEval_q : std_logic_vector (2 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_a : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 : std_logic_vector (33 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr : SIGNED (34 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_q : std_logic_vector (33 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_a : std_logic_vector (25 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_zero_36_q : std_logic_vector (26 downto 0); type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type; signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q : std_logic_vector (36 downto 0); type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o : std_logic_vector (90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o : std_logic_vector (21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q : std_logic_vector (19 downto 0); signal reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q : std_logic_vector (80 downto 0); signal reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q : std_logic_vector (80 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q : std_logic_vector (0 downto 0); signal reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (31 downto 0); signal reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (15 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (7 downto 0); signal reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q : std_logic_vector (7 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q : std_logic_vector (7 downto 0); signal reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q : std_logic_vector (78 downto 0); signal reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q : std_logic_vector (16 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q : std_logic_vector (25 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q : std_logic_vector (16 downto 0); signal reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q : std_logic_vector (17 downto 0); signal reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q : std_logic_vector (36 downto 0); signal reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q : std_logic_vector (44 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q : std_logic_vector (45 downto 0); signal reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q : std_logic_vector (51 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q : std_logic_vector (53 downto 0); signal reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q : std_logic_vector (60 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q : std_logic_vector (26 downto 0); signal reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q : std_logic_vector (6 downto 0); signal reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q : std_logic_vector (78 downto 0); signal ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q : std_logic_vector (78 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q : std_logic_vector (78 downto 0); signal ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q : std_logic_vector (14 downto 0); signal ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (63 downto 0); signal ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (31 downto 0); signal ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (31 downto 0); signal ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (15 downto 0); signal ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (15 downto 0); signal ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q : std_logic_vector (0 downto 0); signal ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q : std_logic_vector (0 downto 0); signal ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (1 downto 0); signal ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (42 downto 0); signal ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q : std_logic_vector (88 downto 0); signal ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q : std_logic_vector (79 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic; signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic; signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic; signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 : std_logic; signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i : unsigned(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q : std_logic_vector (3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i : unsigned(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q : std_logic_vector (6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i : unsigned(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q : std_logic_vector (2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (14 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ir : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i : unsigned(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q : std_logic_vector (2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ir : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ir : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 : std_logic; signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ir : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0); signal yIsZero_uid40_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (18 downto 0); signal pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal z_uid49_fpSinPiTest_s : std_logic_vector (0 downto 0); signal z_uid49_fpSinPiTest_q : std_logic_vector (78 downto 0); signal expHardCase_uid57_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expHardCase_uid57_fpSinPiTest_q : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_q : std_logic_vector (11 downto 0); signal rndExpUpdate_uid75_uid76_fpSinPiTest_q : std_logic_vector (53 downto 0); signal expFracComp_uid77_fpSinPiTest_a : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_b : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_o : std_logic_vector (64 downto 0); signal expFracComp_uid77_fpSinPiTest_q : std_logic_vector (64 downto 0); signal fracRPostExc_uid91_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc_uid91_fpSinPiTest_q : std_logic_vector (51 downto 0); signal expRPostExc_uid98_fpSinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid98_fpSinPiTest_q : std_logic_vector (10 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal memoryC0_uid226_sinPiZTableGenerator_q : std_logic_vector(57 downto 0); signal memoryC1_uid227_sinPiZTableGenerator_q : std_logic_vector(49 downto 0); signal memoryC2_uid228_sinPiZTableGenerator_q : std_logic_vector(42 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_a : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_b : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_o : std_logic_vector (35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_q : std_logic_vector (35 downto 0); signal ts3_uid248_sinPiZPolyEval_a : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_b : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_o : std_logic_vector (45 downto 0); signal ts3_uid248_sinPiZPolyEval_q : std_logic_vector (45 downto 0); signal ts4_uid254_sinPiZPolyEval_a : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_b : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_o : std_logic_vector (52 downto 0); signal ts4_uid254_sinPiZPolyEval_q : std_logic_vector (52 downto 0); signal ts5_uid260_sinPiZPolyEval_a : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_b : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_o : std_logic_vector (61 downto 0); signal ts5_uid260_sinPiZPolyEval_q : std_logic_vector (61 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal join_uid42_fpSinPiTest_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal expX_uid6_fpSinPiTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSinPiTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSinPiTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSinPiTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0); signal expXIsMax_uid16_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSinPiTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid15_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_q : std_logic_vector(0 downto 0); signal xIntExp_uid26_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xIntExp_uid26_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xIntExp_uid26_fpSinPiTest_c : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xFrac_uid28_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_n : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_a : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_b : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_o : std_logic_vector (13 downto 0); signal sinXIsX_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0); signal shiftValue_uid33_fpSinPiTest_a : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_b : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_o : std_logic_vector (11 downto 0); signal shiftValue_uid33_fpSinPiTest_q : std_logic_vector (11 downto 0); signal oMyBottom_uid47_fpSinPiTest_in : std_logic_vector (78 downto 0); signal oMyBottom_uid47_fpSinPiTest_b : std_logic_vector (78 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid150_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal cIncludingRoundingBit_uid247_sinPiZPolyEval_q : std_logic_vector (44 downto 0); signal cIncludingRoundingBit_uid253_sinPiZPolyEval_q : std_logic_vector (51 downto 0); signal cIncludingRoundingBit_uid259_sinPiZPolyEval_q : std_logic_vector (60 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q : std_logic_vector (107 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (29 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (46 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q : std_logic_vector (108 downto 0); signal yIsZero_uid43_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zPPolyEval_uid64_fpSinPiTest_in : std_logic_vector (71 downto 0); signal zPPolyEval_uid64_fpSinPiTest_b : std_logic_vector (44 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_q : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_c : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (31 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (15 downto 0); signal s2_uid240_uid243_sinPiZPolyEval_q : std_logic_vector (36 downto 0); signal add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (55 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (42 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (72 downto 0); signal add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal R_uid105_fpSinPiTest_q : std_logic_vector (63 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal yT3_uid244_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT3_uid244_sinPiZPolyEval_b : std_logic_vector (34 downto 0); signal yT4_uid250_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT4_uid250_sinPiZPolyEval_b : std_logic_vector (42 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q : std_logic_vector(0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_b : std_logic_vector (26 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zAddr_uid63_fpSinPiTest_in : std_logic_vector (78 downto 0); signal zAddr_uid63_fpSinPiTest_b : std_logic_vector (6 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (78 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (63 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (14 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (14 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (46 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (46 downto 0); signal expHardCaseR_uid60_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expHardCaseR_uid60_fpSinPiTest_b : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracRComp_uid78_fpSinPiTest_in : std_logic_vector (52 downto 0); signal fracRComp_uid78_fpSinPiTest_b : std_logic_vector (51 downto 0); signal expRComp_uid79_fpSinPiTest_in : std_logic_vector (63 downto 0); signal expRComp_uid79_fpSinPiTest_b : std_logic_vector (10 downto 0); signal intXParity_uid38_fpSinPiTest_in : std_logic_vector (80 downto 0); signal intXParity_uid38_fpSinPiTest_b : std_logic_vector (0 downto 0); signal y_uid39_fpSinPiTest_in : std_logic_vector (79 downto 0); signal y_uid39_fpSinPiTest_b : std_logic_vector (79 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (77 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (77 downto 0); signal s3_uid249_sinPiZPolyEval_in : std_logic_vector (45 downto 0); signal s3_uid249_sinPiZPolyEval_b : std_logic_vector (44 downto 0); signal s4_uid255_sinPiZPolyEval_in : std_logic_vector (52 downto 0); signal s4_uid255_sinPiZPolyEval_b : std_logic_vector (51 downto 0); signal s5_uid261_sinPiZPolyEval_in : std_logic_vector (61 downto 0); signal s5_uid261_sinPiZPolyEval_b : std_logic_vector (60 downto 0); signal oFracX_uid31_uid31_fpSinPiTest_q : std_logic_vector (52 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_in : std_logic_vector (6 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_b : std_logic_vector (6 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid235_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal highBBits_uid235_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid241_sinPiZPolyEval_in : std_logic_vector (28 downto 0); signal highBBits_uid241_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q : std_logic_vector(107 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (29 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (46 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal normBit_uid70_fpSinPiTest_in : std_logic_vector (106 downto 0); signal normBit_uid70_fpSinPiTest_b : std_logic_vector (0 downto 0); signal highRes_uid71_fpSinPiTest_in : std_logic_vector (105 downto 0); signal highRes_uid71_fpSinPiTest_b : std_logic_vector (52 downto 0); signal lowRes_uid72_fpSinPiTest_in : std_logic_vector (104 downto 0); signal lowRes_uid72_fpSinPiTest_b : std_logic_vector (52 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (70 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (70 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (62 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (62 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (54 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (54 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q : std_logic_vector(0 downto 0); signal yT1_uid232_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT1_uid232_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal yT2_uid238_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT2_uid238_sinPiZPolyEval_b : std_logic_vector (25 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (63 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (9 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (9 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (36 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (71 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (45 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (78 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (7 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (7 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (15 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (15 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expP_uid61_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expP_uid61_fpSinPiTest_q : std_logic_vector (10 downto 0); signal yBottom_uid48_fpSinPiTest_in : std_logic_vector (78 downto 0); signal yBottom_uid48_fpSinPiTest_b : std_logic_vector (78 downto 0); signal leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (51 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal fxpSinRes_uid66_fpSinPiTest_in : std_logic_vector (58 downto 0); signal fxpSinRes_uid66_fpSinPiTest_b : std_logic_vector (53 downto 0); signal extendedFracX_uid35_fpSinPiTest_q : std_logic_vector (80 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (0 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_a : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_b : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_o : std_logic_vector (26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q : std_logic_vector(107 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_q : std_logic_vector (52 downto 0); signal join_uid97_fpSinPiTest_q : std_logic_vector (1 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal signR_uid104_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (10 downto 0); signal pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (16 downto 0); signal pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal xIsInt_uid83_fpSinPiTest_a : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_b : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal multRightOp_uid68_fpSinPiTest_s : std_logic_vector (0 downto 0); signal multRightOp_uid68_fpSinPiTest_q : std_logic_vector (53 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (48 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (48 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (16 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (16 downto 0); signal s1_uid234_uid237_sinPiZPolyEval_q : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c : std_logic_vector (19 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in : std_logic_vector (106 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b : std_logic_vector (106 downto 0); signal expFracPreRnd_uid74_uid74_fpSinPiTest_q : std_logic_vector (63 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (17 downto 0); signal alignedZLow_uid53_fpSinPiTest_in : std_logic_vector (78 downto 0); signal alignedZLow_uid53_fpSinPiTest_b : std_logic_vector (51 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_b : std_logic_vector (26 downto 0); signal leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q : std_logic_vector (107 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (1 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (74 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (72 downto 0); signal pHardCase_uid54_fpSinPiTest_q : std_logic_vector (52 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q : std_logic_vector (108 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (0 downto 0); signal leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal p_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0); signal p_uid55_fpSinPiTest_q : std_logic_vector (52 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (72 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (64 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (64 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (56 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (56 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c : std_logic_vector (19 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal r_uid186_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (6 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (0 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (78 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (78 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (74 downto 0); signal leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (79 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (79 downto 0); signal leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); begin --ld_xIn_v_to_xOut_v_notEnable(LOGICAL,909) ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q; ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor(LOGICAL,1028) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q <= not (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a or ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top(CONSTANT,1024) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q <= "0100100"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp(LOGICAL,1025) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q <= "1" when ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a = ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b else "0"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg(REG,1026) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena(REG,1029) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q = "1") THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd(LOGICAL,1030) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a and ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b; --LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest(BITSELECT,134)@0 LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest(CONSTANT,133) leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q <= "000000"; --leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest(BITJOIN,135)@0 leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest(BITSELECT,131)@0 LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest(CONSTANT,130) leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q <= "0000"; --leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest(BITJOIN,132)@0 leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest(BITSELECT,128)@0 LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(78 downto 0); LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in(78 downto 0); --leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest(CONSTANT,127) leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q <= "00"; --leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest(BITJOIN,129)@0 leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest(BITSELECT,123)@0 LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(56 downto 0); LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in(56 downto 0); --leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest(CONSTANT,122) leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000"; --leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest(BITJOIN,124)@0 leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest(BITSELECT,120)@0 LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(64 downto 0); LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in(64 downto 0); --leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest(CONSTANT,119) leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000"; --leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest(BITJOIN,121)@0 leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest(BITSELECT,117)@0 LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(72 downto 0); LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in(72 downto 0); --leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest(CONSTANT,116) leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q <= "00000000"; --leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest(BITJOIN,118)@0 leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest(CONSTANT,113) leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; --X16dto0_uid112_fixedPointX_uid37_fpSinPiTest(BITSELECT,111)@0 X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(16 downto 0); X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in(16 downto 0); --leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest(CONSTANT,110) leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000"; --leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest(BITJOIN,112)@0 leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X48dto0_uid109_fixedPointX_uid37_fpSinPiTest(BITSELECT,108)@0 X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(48 downto 0); X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in(48 downto 0); --leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest(CONSTANT,107) leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q <= "00000000000000000000000000000000"; --leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest(BITJOIN,109)@0 leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --cst01pWShift_uid34_fpSinPiTest(CONSTANT,33) cst01pWShift_uid34_fpSinPiTest_q <= "0000000000000000000000000000"; --xIn(PORTIN,3)@0 --fracX_uid7_fpSinPiTest(BITSELECT,6)@0 fracX_uid7_fpSinPiTest_in <= xIn_0(51 downto 0); fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(51 downto 0); --oFracX_uid31_uid31_fpSinPiTest(BITJOIN,30)@0 oFracX_uid31_uid31_fpSinPiTest_q <= VCC_q & fracX_uid7_fpSinPiTest_b; --extendedFracX_uid35_fpSinPiTest(BITJOIN,34)@0 extendedFracX_uid35_fpSinPiTest_q <= cst01pWShift_uid34_fpSinPiTest_q & oFracX_uid31_uid31_fpSinPiTest_q; --shiftBias_uid32_fpSinPiTest(CONSTANT,31) shiftBias_uid32_fpSinPiTest_q <= "01111100011"; --expX_uid6_fpSinPiTest(BITSELECT,5)@0 expX_uid6_fpSinPiTest_in <= xIn_0(62 downto 0); expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(62 downto 52); --shiftValue_uid33_fpSinPiTest(SUB,32)@0 shiftValue_uid33_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b); shiftValue_uid33_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid32_fpSinPiTest_q); shiftValue_uid33_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid33_fpSinPiTest_a) - UNSIGNED(shiftValue_uid33_fpSinPiTest_b)); shiftValue_uid33_fpSinPiTest_q <= shiftValue_uid33_fpSinPiTest_o(11 downto 0); --fxpShifterBits_uid36_fpSinPiTest(BITSELECT,35)@0 fxpShifterBits_uid36_fpSinPiTest_in <= shiftValue_uid33_fpSinPiTest_q(6 downto 0); fxpShifterBits_uid36_fpSinPiTest_b <= fxpShifterBits_uid36_fpSinPiTest_in(6 downto 0); --leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest(BITSELECT,114)@0 leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b; leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in(6 downto 5); --leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest(MUX,115)@0 leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s, extendedFracX_uid35_fpSinPiTest_q, leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= extendedFracX_uid35_fpSinPiTest_q; WHEN "01" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest(BITSELECT,125)@0 leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(4 downto 0); leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in(4 downto 3); --leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest(MUX,126)@0 leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest(BITSELECT,136)@0 leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(2 downto 0); leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in(2 downto 1); --leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest(MUX,137)@0 leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest(BITSELECT,139)@0 LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in(79 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest(BITJOIN,140)@0 leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b & GND_q; --reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3(REG,357)@0 reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2(REG,358)@0 reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest(BITSELECT,141)@0 leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(0 downto 0); leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in(0 downto 0); --ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b(DELAY,581)@0 ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest(MUX,142)@1 leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q; leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s, reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q, reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q) BEGIN CASE leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q; WHEN "1" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q; WHEN OTHERS => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --intXParity_uid38_fpSinPiTest(BITSELECT,37)@1 intXParity_uid38_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q; intXParity_uid38_fpSinPiTest_b <= intXParity_uid38_fpSinPiTest_in(80 downto 80); --ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c(DELAY,536)@1 ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => intXParity_uid38_fpSinPiTest_b, xout => ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q, clk => clk, aclr => areset ); --biasM1_uid27_fpSinPiTest(CONSTANT,26) biasM1_uid27_fpSinPiTest_q <= "01111111110"; --xFrac_uid28_fpSinPiTest(COMPARE,27)@0 xFrac_uid28_fpSinPiTest_cin <= GND_q; xFrac_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid27_fpSinPiTest_q) & '0'; xFrac_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid28_fpSinPiTest_cin(0); xFrac_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid28_fpSinPiTest_a) - UNSIGNED(xFrac_uid28_fpSinPiTest_b)); xFrac_uid28_fpSinPiTest_n(0) <= not xFrac_uid28_fpSinPiTest_o(13); --ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a(DELAY,532)@0 ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => xFrac_uid28_fpSinPiTest_n, xout => ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvXFrac_uid99_fpSinPiTest(LOGICAL,98)@3 InvXFrac_uid99_fpSinPiTest_a <= ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q; InvXFrac_uid99_fpSinPiTest_q <= not InvXFrac_uid99_fpSinPiTest_a; --biasMwShift_uid29_fpSinPiTest(CONSTANT,28) biasMwShift_uid29_fpSinPiTest_q <= "01111100100"; --sinXIsX_uid30_fpSinPiTest(COMPARE,29)@0 sinXIsX_uid30_fpSinPiTest_cin <= GND_q; sinXIsX_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0'; sinXIsX_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid29_fpSinPiTest_q) & sinXIsX_uid30_fpSinPiTest_cin(0); sinXIsX_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid30_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid30_fpSinPiTest_b)); sinXIsX_uid30_fpSinPiTest_c(0) <= sinXIsX_uid30_fpSinPiTest_o(13); --ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a(DELAY,502)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvSinXIsX_uid80_fpSinPiTest(LOGICAL,79)@2 InvSinXIsX_uid80_fpSinPiTest_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q; InvSinXIsX_uid80_fpSinPiTest_q <= not InvSinXIsX_uid80_fpSinPiTest_a; --y_uid39_fpSinPiTest(BITSELECT,38)@1 y_uid39_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); y_uid39_fpSinPiTest_b <= y_uid39_fpSinPiTest_in(79 downto 0); --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0(REG,360)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid40_fpSinPiTest(LOGICAL,39)@2 yIsZero_uid40_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q; yIsZero_uid40_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000000000000000000000000000000000000000000000000" & GND_q); yIsZero_uid40_fpSinPiTest_q <= "1" when yIsZero_uid40_fpSinPiTest_a = yIsZero_uid40_fpSinPiTest_b else "0"; --And2YIsZeroInvSinXIsX_uid81_fpSinPiTest(LOGICAL,80)@2 And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a <= yIsZero_uid40_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b <= InvSinXIsX_uid80_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a and And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b; --cstBiasPwF_uid13_fpSinPiTest(CONSTANT,12) cstBiasPwF_uid13_fpSinPiTest_q <= "10000110011"; --xIntExp_uid26_fpSinPiTest(COMPARE,25)@0 xIntExp_uid26_fpSinPiTest_cin <= GND_q; xIntExp_uid26_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid13_fpSinPiTest_q) & '0'; xIntExp_uid26_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid26_fpSinPiTest_cin(0); xIntExp_uid26_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid26_fpSinPiTest_a) - UNSIGNED(xIntExp_uid26_fpSinPiTest_b)); xIntExp_uid26_fpSinPiTest_c(0) <= xIntExp_uid26_fpSinPiTest_o(13); --ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a(DELAY,505)@0 ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => xIntExp_uid26_fpSinPiTest_c, xout => ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q, clk => clk, aclr => areset ); --Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest(LOGICAL,81)@2 Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a or Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b; --cstAllZWF_uid10_fpSinPiTest(CONSTANT,9) cstAllZWF_uid10_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracXIsZero_uid17_fpSinPiTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b; fracXIsZero_uid17_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q; fracXIsZero_uid17_fpSinPiTest_q <= "1" when fracXIsZero_uid17_fpSinPiTest_a = fracXIsZero_uid17_fpSinPiTest_b else "0"; --ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a(DELAY,442)@0 ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => fracXIsZero_uid17_fpSinPiTest_q, xout => ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvFracXIsZero_uid19_fpSinPiTest(LOGICAL,18)@1 InvFracXIsZero_uid19_fpSinPiTest_a <= ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q; InvFracXIsZero_uid19_fpSinPiTest_q <= not InvFracXIsZero_uid19_fpSinPiTest_a; --cstAllOWE_uid9_fpSinPiTest(CONSTANT,8) cstAllOWE_uid9_fpSinPiTest_q <= "11111111111"; --expXIsMax_uid16_fpSinPiTest(LOGICAL,15)@0 expXIsMax_uid16_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsMax_uid16_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q; expXIsMax_uid16_fpSinPiTest_q <= "1" when expXIsMax_uid16_fpSinPiTest_a = expXIsMax_uid16_fpSinPiTest_b else "0"; --ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a(DELAY,443)@0 ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsMax_uid16_fpSinPiTest_q, xout => ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest(LOGICAL,19)@1 And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a <= ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b <= InvFracXIsZero_uid19_fpSinPiTest_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a and And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b; --InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest(LOGICAL,20)@1 InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q <= not InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a; --And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0 And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a <= expXIsMax_uid16_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b <= fracXIsZero_uid17_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a and And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b; --InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0 InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q; InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q <= not InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a; --cstAllZWE_uid11_fpSinPiTest(CONSTANT,10) cstAllZWE_uid11_fpSinPiTest_q <= "00000000000"; --expXIsZero_uid15_fpSinPiTest(LOGICAL,14)@0 expXIsZero_uid15_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsZero_uid15_fpSinPiTest_b <= cstAllZWE_uid11_fpSinPiTest_q; expXIsZero_uid15_fpSinPiTest_q <= "1" when expXIsZero_uid15_fpSinPiTest_a = expXIsZero_uid15_fpSinPiTest_b else "0"; --InvExpXIsZero_uid23_fpSinPiTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSinPiTest_a <= expXIsZero_uid15_fpSinPiTest_q; InvExpXIsZero_uid23_fpSinPiTest_q <= not InvExpXIsZero_uid23_fpSinPiTest_a; --And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0 And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a <= InvExpXIsZero_uid23_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b <= InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a and And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b; --ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a(DELAY,450)@0 ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q, xout => ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest(LOGICAL,24)@1 And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a <= ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b <= InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a and And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b; END IF; END PROCESS; --xIsInt_uid83_fpSinPiTest(LOGICAL,82)@2 xIsInt_uid83_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_b <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_q <= xIsInt_uid83_fpSinPiTest_a and xIsInt_uid83_fpSinPiTest_b; --InvXIsInt_uid100_fpSinPiTest(LOGICAL,99)@2 InvXIsInt_uid100_fpSinPiTest_a <= xIsInt_uid83_fpSinPiTest_q; InvXIsInt_uid100_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= not InvXIsInt_uid100_fpSinPiTest_a; END IF; END PROCESS; --signComp_uid101_fpSinPiTest(LOGICAL,100)@3 signComp_uid101_fpSinPiTest_a <= InvXIsInt_uid100_fpSinPiTest_q; signComp_uid101_fpSinPiTest_b <= InvXFrac_uid99_fpSinPiTest_q; signComp_uid101_fpSinPiTest_c <= ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q; signComp_uid101_fpSinPiTest_q <= signComp_uid101_fpSinPiTest_a and signComp_uid101_fpSinPiTest_b and signComp_uid101_fpSinPiTest_c; --ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a(DELAY,537)@2 ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => yIsZero_uid40_fpSinPiTest_q, xout => ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvYIsZero_uid102_fpSinPiTest(LOGICAL,101)@3 InvYIsZero_uid102_fpSinPiTest_a <= ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q; InvYIsZero_uid102_fpSinPiTest_q <= not InvYIsZero_uid102_fpSinPiTest_a; --And2InvYIsZeroSignComp_uid103_fpSinPiTest(LOGICAL,102)@3 And2InvYIsZeroSignComp_uid103_fpSinPiTest_a <= InvYIsZero_uid102_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_b <= signComp_uid101_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_q <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_a and And2InvYIsZeroSignComp_uid103_fpSinPiTest_b; --signX_uid8_fpSinPiTest(BITSELECT,7)@0 signX_uid8_fpSinPiTest_in <= xIn_0; signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(63 downto 63); --ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a(DELAY,540)@0 ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q, clk => clk, aclr => areset ); --signR_uid104_fpSinPiTest(LOGICAL,103)@3 signR_uid104_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q; signR_uid104_fpSinPiTest_b <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_q; signR_uid104_fpSinPiTest_q <= signR_uid104_fpSinPiTest_a xor signR_uid104_fpSinPiTest_b; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt(COUNTER,1020) -- every=1, low=0, high=36, step=1, init=1 ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i = 35 THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i - 36; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i,6)); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg(REG,1021) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --VCC(CONSTANT,1) VCC_q <= "1"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux(MUX,1022) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux: PROCESS (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem(DUALMEM,1019) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia <= signR_uid104_fpSinPiTest_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 37, width_b => 1, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq, address_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa, data_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia ); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq(0 downto 0); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg(DELAY,1018) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q, xout => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --cstBias_uid12_fpSinPiTest(CONSTANT,11) cstBias_uid12_fpSinPiTest_q <= "01111111111"; --piwFP2_uid67_fpSinPiTest(CONSTANT,66) piwFP2_uid67_fpSinPiTest_q <= "110010010000111111011010101000100010000101101000110001"; --reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1(REG,363)@1 reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --cOne_uid44_fpSinPiTest(CONSTANT,43) cOne_uid44_fpSinPiTest_q <= "100000000000000000000000000000000000000000000000000000000000000000000000000000000"; --oneMinusY_uid45_fpSinPiTest(SUB,44)@2 oneMinusY_uid45_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid44_fpSinPiTest_q); oneMinusY_uid45_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q); oneMinusY_uid45_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid45_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid45_fpSinPiTest_b)); END IF; END PROCESS; oneMinusY_uid45_fpSinPiTest_q <= oneMinusY_uid45_fpSinPiTest_o(81 downto 0); --oMyBottom_uid47_fpSinPiTest(BITSELECT,46)@3 oMyBottom_uid47_fpSinPiTest_in <= oneMinusY_uid45_fpSinPiTest_q(78 downto 0); oMyBottom_uid47_fpSinPiTest_b <= oMyBottom_uid47_fpSinPiTest_in(78 downto 0); --ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d(DELAY,471)@3 ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => oMyBottom_uid47_fpSinPiTest_b, xout => ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q, clk => clk, aclr => areset ); --yBottom_uid48_fpSinPiTest(BITSELECT,47)@1 yBottom_uid48_fpSinPiTest_in <= y_uid39_fpSinPiTest_b(78 downto 0); yBottom_uid48_fpSinPiTest_b <= yBottom_uid48_fpSinPiTest_in(78 downto 0); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c(DELAY,470)@1 ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 79, depth => 2 ) PORT MAP ( xin => yBottom_uid48_fpSinPiTest_b, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg(DELAY,926) ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a(DELAY,833)@1 ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a : dspba_delay GENERIC MAP ( width => 80, depth => 1 ) PORT MAP ( xin => y_uid39_fpSinPiTest_b, xout => ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q, clk => clk, aclr => areset ); --reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1(REG,364)@2 reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q; END IF; END PROCESS; --cmpYToOneMinusY_uid46_fpSinPiTest(COMPARE,45)@3 cmpYToOneMinusY_uid46_fpSinPiTest_cin <= GND_q; cmpYToOneMinusY_uid46_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & oneMinusY_uid45_fpSinPiTest_q) & '0'; cmpYToOneMinusY_uid46_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q) & cmpYToOneMinusY_uid46_fpSinPiTest_cin(0); cmpYToOneMinusY_uid46_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_b)); END IF; END PROCESS; cmpYToOneMinusY_uid46_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid46_fpSinPiTest_o(84); --z_uid49_fpSinPiTest(MUX,48)@4 z_uid49_fpSinPiTest_s <= cmpYToOneMinusY_uid46_fpSinPiTest_c; z_uid49_fpSinPiTest: PROCESS (z_uid49_fpSinPiTest_s, ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q) BEGIN CASE z_uid49_fpSinPiTest_s IS WHEN "0" => z_uid49_fpSinPiTest_q <= ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q; WHEN "1" => z_uid49_fpSinPiTest_q <= ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q; WHEN OTHERS => z_uid49_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --zAddr_uid63_fpSinPiTest(BITSELECT,62)@4 zAddr_uid63_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; zAddr_uid63_fpSinPiTest_b <= zAddr_uid63_fpSinPiTest_in(78 downto 72); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0(REG,382)@4 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= zAddr_uid63_fpSinPiTest_b; END IF; END PROCESS; --memoryC5_uid231_sinPiZTableGenerator(LOOKUP,230)@5 memoryC5_uid231_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; WHEN "0000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111110101101000"; WHEN "0000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111101101011101"; WHEN "0000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100110001110"; WHEN "0000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100000000010"; WHEN "0000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111011000000000"; WHEN "0000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111010001101101"; WHEN "0000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111001010010111"; WHEN "0001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111000010110010"; WHEN "0001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110111100010100"; WHEN "0001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110110100011111"; WHEN "0001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110101100101101"; WHEN "0001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110100101101011"; WHEN "0001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110011111011101"; WHEN "0001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010111001010"; WHEN "0001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010001011011"; WHEN "0010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110001010101011"; WHEN "0010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110000011011001"; WHEN "0010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101111011000001"; WHEN "0010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101110101001010"; WHEN "0010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101101110100110"; WHEN "0010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101100111100011"; WHEN "0010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011111111111"; WHEN "0010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011001001010"; WHEN "0011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101010010100110"; WHEN "0011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101001010011011"; WHEN "0011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101000100011100"; WHEN "0011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100111101010110"; WHEN "0011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100110110111000"; WHEN "0011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100101111110010"; WHEN "0011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100111110010"; WHEN "0011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100001010101"; WHEN "0100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100011011011111"; WHEN "0100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100010011110111"; WHEN "0100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100001110001010"; WHEN "0100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100000111000100"; WHEN "0100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111111110101"; WHEN "0100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111001010110"; WHEN "0100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011110011000111"; WHEN "0100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011101101000000"; WHEN "0101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011100110000011"; WHEN "0101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011111111001"; WHEN "0101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011000100110"; WHEN "0101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011010010101100"; WHEN "0101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011001100010010"; WHEN "0101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011000101010111"; WHEN "0101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111111101010"; WHEN "0101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111001010000"; WHEN "0110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010110011010011"; WHEN "0110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010101100101011"; WHEN "0110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010100110111110"; WHEN "0110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011111111000"; WHEN "0110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011010110010"; WHEN "0110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010010101001110"; WHEN "0110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001110010011"; WHEN "0110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001000111011"; WHEN "0111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010000001111011"; WHEN "0111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001111011111110"; WHEN "0111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110111001010"; WHEN "0111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110001110111"; WHEN "0111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001101011000100"; WHEN "0111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100101010010"; WHEN "0111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100000011111"; WHEN "0111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001011010001010"; WHEN "1000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001010100111110"; WHEN "1000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001110110010"; WHEN "1000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001010111000"; WHEN "1000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001000100111111"; WHEN "1000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111111001100"; WHEN "1000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111010001001"; WHEN "1000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110101010110"; WHEN "1000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110000011101"; WHEN "1001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000101001110100"; WHEN "1001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000100101111001"; WHEN "1001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011111111010"; WHEN "1001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011011110110"; WHEN "1001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010110001100"; WHEN "1001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010001001000"; WHEN "1001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001101111001"; WHEN "1001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001000000111"; WHEN "1010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000000010111001"; WHEN "1010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111110110110"; WHEN "1010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111001111111"; WHEN "1010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110110010100"; WHEN "1010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110001011000"; WHEN "1010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101100010111"; WHEN "1010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101000010010"; WHEN "1010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100100010000"; WHEN "1011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100000111100"; WHEN "1011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111011011111111"; WHEN "1011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010111100000"; WHEN "1011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010011110100"; WHEN "1011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010000011100"; WHEN "1011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111001011011110"; WHEN "1011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000111111101"; WHEN "1011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000100101011"; WHEN "1100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000001100100"; WHEN "1100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111101101110"; WHEN "1100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111010011000"; WHEN "1100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110110110000"; WHEN "1100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110010011010"; WHEN "1100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110000011110"; WHEN "1100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101100101100"; WHEN "1100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101000101110"; WHEN "1101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100110100000"; WHEN "1101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100100010001"; WHEN "1101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100001000000"; WHEN "1101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011101101110"; WHEN "1101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011011011111"; WHEN "1101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010111000100"; WHEN "1101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010101110011"; WHEN "1101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010001111100"; WHEN "1110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010000001111"; WHEN "1110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001110011001"; WHEN "1110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001010100010"; WHEN "1110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000111111000"; WHEN "1110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101110110"; WHEN "1110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101000100"; WHEN "1110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000010100010"; WHEN "1110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111111110011"; WHEN "1111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111110010000"; WHEN "1111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111100110111"; WHEN "1111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111010111000"; WHEN "1111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111000101000"; WHEN "1111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110110110100"; WHEN "1111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110101011010"; WHEN "1111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110100000011"; WHEN "1111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110010001011"; WHEN OTHERS => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; END CASE; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a(DELAY,485)@4 ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => z_uid49_fpSinPiTest_q, xout => ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q, clk => clk, aclr => areset ); --zPPolyEval_uid64_fpSinPiTest(BITSELECT,63)@5 zPPolyEval_uid64_fpSinPiTest_in <= ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q(71 downto 0); zPPolyEval_uid64_fpSinPiTest_b <= zPPolyEval_uid64_fpSinPiTest_in(71 downto 27); --yT1_uid232_sinPiZPolyEval(BITSELECT,231)@5 yT1_uid232_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT1_uid232_sinPiZPolyEval_b <= yT1_uid232_sinPiZPolyEval_in(44 downto 28); --reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0(REG,383)@5 reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= yT1_uid232_sinPiZPolyEval_b; END IF; END PROCESS; --prodXY_uid263_pT1_uid233_sinPiZPolyEval(MULT,262)@6 prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_a),18)) * SIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_b); prodXY_uid263_pT1_uid233_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= memoryC5_uid231_sinPiZTableGenerator_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr,34)); END IF; END PROCESS; prodXY_uid263_pT1_uid233_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval(BITSELECT,263)@9 prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_q; prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in(33 downto 16); --highBBits_uid235_sinPiZPolyEval(BITSELECT,234)@9 highBBits_uid235_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b; highBBits_uid235_sinPiZPolyEval_b <= highBBits_uid235_sinPiZPolyEval_in(17 downto 1); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a(DELAY,853)@4 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a : dspba_delay GENERIC MAP ( width => 7, depth => 3 ) PORT MAP ( xin => zAddr_uid63_fpSinPiTest_b, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0(REG,384)@7 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q; END IF; END PROCESS; --memoryC4_uid230_sinPiZTableGenerator(LOOKUP,229)@8 memoryC4_uid230_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; WHEN "0000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110011111111100"; WHEN "0000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100101101100110011"; WHEN "0000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100100010011000101"; WHEN "0000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100010010010010110"; WHEN "0000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011111110011000100"; WHEN "0000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011100101011001100"; WHEN "0000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011001000001111000"; WHEN "0001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010100110101100100"; WHEN "0001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010000000010110001"; WHEN "0001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001001010101111100100"; WHEN "0001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001000100111000100010"; WHEN "0001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000111110011011110101"; WHEN "0001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000110111011001010101"; WHEN "0001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000101111111000110001"; WHEN "0001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000100111101101111110"; WHEN "0010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000011111000010010110"; WHEN "0010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000010101110100101111"; WHEN "0010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000001100000110110101"; WHEN "0010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000000001101111000000"; WHEN "0010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111110110110101110011"; WHEN "0010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111101011011010111001"; WHEN "0010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111011111011110000110"; WHEN "0010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111010010111100110100"; WHEN "0011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111000101110111111001"; WHEN "0011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110111000010100011101"; WHEN "0011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110101010001000110011"; WHEN "0011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110011011011101100111"; WHEN "0011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110001100001110001111"; WHEN "0011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101111100011110001010"; WHEN "0011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101101100001110100101"; WHEN "0011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101011011011000110110"; WHEN "0100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101001001111111101110"; WHEN "0100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100111000001001001111"; WHEN "0100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100100101101100011001"; WHEN "0100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100010010110001110000"; WHEN "0100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011111111010101110110"; WHEN "0100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011101011010111000111"; WHEN "0100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011010110110110011110"; WHEN "0100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011000001110100011110"; WHEN "0101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010101100010100010011"; WHEN "0101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010010110010001000111"; WHEN "0101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001111111110001000100"; WHEN "0101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001101000101100110110"; WHEN "0101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001010001001001111011"; WHEN "0101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000111001001000001110"; WHEN "0101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000100000100011110110"; WHEN "0101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000000111100001111001"; WHEN "0110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111101101111111011111"; WHEN "0110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111010011111111100110"; WHEN "0110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110111001011110100100"; WHEN "0110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110011110100010000111"; WHEN "0110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110000011000010001001"; WHEN "0110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101100111000101000011"; WHEN "0110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101001010101101011111"; WHEN "0110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100101101110011101110"; WHEN "0111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100010000100000111110"; WHEN "0111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011110010101101110100"; WHEN "0111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011010100011010011110"; WHEN "0111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010110101101011010111"; WHEN "0111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010010110100011011101"; WHEN "0111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001110110111100001001"; WHEN "0111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001010110110110010000"; WHEN "0111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000110110011000001101"; WHEN "1000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000010101011011011001"; WHEN "1000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111110100000101110010"; WHEN "1000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111010010001110101001"; WHEN "1000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110110000000001101011"; WHEN "1000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110001101011001110011"; WHEN "1000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101101010010101011101"; WHEN "1000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101000110110101111111"; WHEN "1000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111100100010111100111100"; WHEN "1001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011111110101110100100"; WHEN "1001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011011001111111110100"; WHEN "1001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010110100111101000111"; WHEN "1001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010001111011100101001"; WHEN "1001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001101001100111100001"; WHEN "1001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001000011011000101011"; WHEN "1001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111000011100101100110010"; WHEN "1001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111110101110000000011"; WHEN "1010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111001110011001111101"; WHEN "1010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110110100110101001110001"; WHEN "1010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101111110100101001011"; WHEN "1010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101010110000110010110"; WHEN "1010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100101101010100111010"; WHEN "1010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100000100001101101101"; WHEN "1010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110011011010101110011000"; WHEN "1010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010110000111001010011"; WHEN "1011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010000110101101010010"; WHEN "1011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110001011100010001000010"; WHEN "1011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000110001011111001110"; WHEN "1011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000000110010110110100"; WHEN "1011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101111011010111010001000"; WHEN "1011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110101111001110001011"; WHEN "1011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110000011001011001100"; WHEN "1011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101101010110110100111111"; WHEN "1100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101100101010001011011001"; WHEN "1100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011111101010010000000"; WHEN "1100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011010000000101001000"; WHEN "1100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101010100010100111110111"; WHEN "1100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001110100111011010110"; WHEN "1100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001000110110111101100"; WHEN "1100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101000011000101000001000"; WHEN "1100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100111101010001001010101"; WHEN "1101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110111011010110000011"; WHEN "1101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110001100010011011010"; WHEN "1101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100101011101000100011001"; WHEN "1101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100100101101100110100111"; WHEN "1101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011111101110111111010"; WHEN "1101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011001110000000101100"; WHEN "1101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100010011101110011110101"; WHEN "1101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100001101101100000010000"; WHEN "1110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000111100111010001011"; WHEN "1110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000001100000111111010"; WHEN "1110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011111011011001110101000"; WHEN "1110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011110101010000110010111"; WHEN "1110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101111000110001000001"; WHEN "1110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101000111001101001001"; WHEN "1110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011100010101100011001010"; WHEN "1110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011011100011101111010110"; WHEN "1111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011010110001101110011110"; WHEN "1111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001111111100011010111"; WHEN "1111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001001101010000100101"; WHEN "1111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011000011010110101101110"; WHEN "1111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010111101000010001000000"; WHEN "1111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110110101100011000101"; WHEN "1111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110000010101101010111"; WHEN "1111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010101001111110001011010"; WHEN OTHERS => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; END CASE; END IF; END PROCESS; --sumAHighB_uid236_sinPiZPolyEval(ADD,235)@9 sumAHighB_uid236_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((26 downto 26 => memoryC4_uid230_sinPiZTableGenerator_q(25)) & memoryC4_uid230_sinPiZTableGenerator_q); sumAHighB_uid236_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((26 downto 17 => highBBits_uid235_sinPiZPolyEval_b(16)) & highBBits_uid235_sinPiZPolyEval_b); sumAHighB_uid236_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid236_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid236_sinPiZPolyEval_b)); sumAHighB_uid236_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_o(26 downto 0); --lowRangeB_uid234_sinPiZPolyEval(BITSELECT,233)@9 lowRangeB_uid234_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid234_sinPiZPolyEval_b <= lowRangeB_uid234_sinPiZPolyEval_in(0 downto 0); --s1_uid234_uid237_sinPiZPolyEval(BITJOIN,236)@9 s1_uid234_uid237_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_q & lowRangeB_uid234_sinPiZPolyEval_b; --reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1(REG,385)@9 reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= s1_uid234_uid237_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor(LOGICAL,1179) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q <= not (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a or ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg(REG,1177) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= VCC_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena(REG,1180) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q = "1") THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd(LOGICAL,1181) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a and ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b; --yT2_uid238_sinPiZPolyEval(BITSELECT,237)@5 yT2_uid238_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT2_uid238_sinPiZPolyEval_b <= yT2_uid238_sinPiZPolyEval_in(44 downto 19); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt(COUNTER,1173) -- every=1, low=0, high=1, step=1, init=1 ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i + 1; END IF; END PROCESS; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i,1)); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg(REG,1174) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux(MUX,1175) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q) BEGIN CASE ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s IS WHEN "0" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; WHEN "1" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem(DUALMEM,1172) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia <= yT2_uid238_sinPiZPolyEval_b; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 26, widthad_a => 1, numwords_a => 2, width_b => 26, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq, address_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa, data_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia ); ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq(25 downto 0); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg(DELAY,1171) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q, xout => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0(REG,386)@9 reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q; END IF; END PROCESS; --prodXY_uid266_pT2_uid239_sinPiZPolyEval(MULT,265)@10 prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_a),27)) * SIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_b); prodXY_uid266_pT2_uid239_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr,54)); END IF; END PROCESS; prodXY_uid266_pT2_uid239_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval(BITSELECT,266)@13 prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_q; prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in(53 downto 25); --highBBits_uid241_sinPiZPolyEval(BITSELECT,240)@13 highBBits_uid241_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b; highBBits_uid241_sinPiZPolyEval_b <= highBBits_uid241_sinPiZPolyEval_in(28 downto 1); --reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1(REG,388)@13 reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= highBBits_uid241_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor(LOGICAL,1192) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1188) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q <= "0101"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp(LOGICAL,1189) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg(REG,1190) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena(REG,1193) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1194) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1184) -- every=1, low=0, high=5, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i = 4 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i - 5; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i,3)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg(REG,1185) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1186) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1183) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 3, numwords_a => 6, width_b => 7, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg(DELAY,1182) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0(REG,387)@12 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC3_uid229_sinPiZTableGenerator(LOOKUP,228)@13 memoryC3_uid229_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; WHEN "0000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000001010001100110101000111010101"; WHEN "0000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000010100011001100101101010110011"; WHEN "0000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000011110100110001101010100011011"; WHEN "0000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000101000110010100111100101110011"; WHEN "0000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000110010111110101111101101101000"; WHEN "0000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000111101001010100001100001001101"; WHEN "0000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001000111010101111000010100001000"; WHEN "0001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001010001100000101111101001011010"; WHEN "0001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001011011101011000011001000111110"; WHEN "0001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001100101110100101110001001110101"; WHEN "0001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001101111111101101100010100000001"; WHEN "0001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001111010000101111001001101010110"; WHEN "0001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010000100001101010000011000110101"; WHEN "0001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010001110010011101101001010101000"; WHEN "0001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010011000011001001011011101011111"; WHEN "0010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010100010011101100110100011101011"; WHEN "0010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010101100100000111010000011110001"; WHEN "0010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010110110100011000001011111010110"; WHEN "0010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011000000100011111000101110110101"; WHEN "0010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011001010100011011011001000001011"; WHEN "0010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011010100100001100100010010100101"; WHEN "0010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011011110011110001111110110101010"; WHEN "0010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011101000011001011001100000011011"; WHEN "0011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011110010010010111100111000010100"; WHEN "0011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011111100001010110101011110000110"; WHEN "0011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100000110000000111111001110100010"; WHEN "0011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100001111110101010101100100101101"; WHEN "0011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100011001100111110100010110001111"; WHEN "0011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100100011011000010111001001011111"; WHEN "0011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100101101000110111001101001101001"; WHEN "0011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100110110110011010111110011001100"; WHEN "0100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101000000011101101101010000100110"; WHEN "0100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101001010000101110101101000010110"; WHEN "0100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101010011101011101100111100100100"; WHEN "0100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101011101001111001110110000110010"; WHEN "0100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101100110110000010111000000110011"; WHEN "0100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101110000001111000001100011110100"; WHEN "0100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101111001101011001010010000000001"; WHEN "0100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110000011000100101100111100001110"; WHEN "0101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110001100011011100101011010100101"; WHEN "0101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110010101101111101111110000010101"; WHEN "0101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110011111000001000111101011101100"; WHEN "0101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110101000001111101001011001100010"; WHEN "0101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110110001011011010000101101010010"; WHEN "0101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110111010100011111001100111101100"; WHEN "0101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111000011101001100000010000100010"; WHEN "0101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111001100101100000000100001010000"; WHEN "0110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111010101101011010110100011101100"; WHEN "0110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111011110100111011110011000011110"; WHEN "0110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111100111100000010100001101010000"; WHEN "0110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111110000010101110100000001010000"; WHEN "0110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111111001000111111010001101010001"; WHEN "0110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000000001110110100010110001111010"; WHEN "0110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000001010100001101001110111110101"; WHEN "0110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000010011001001001011111110000001"; WHEN "0111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000011011101101000101000010101111"; WHEN "0111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000100100001101010001101000100100"; WHEN "0111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000101100101001101110000011010101"; WHEN "0111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000110101000010010110100001011010"; WHEN "0111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000111101010111000111010101011110"; WHEN "0111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001000101100111111101000110111000"; WHEN "0111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001001101110100110100001111001100"; WHEN "0111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001010101111101101001000001001010"; WHEN "1000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001011110000010011000001001000011"; WHEN "1000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001100110000010111101111101010011"; WHEN "1000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001101101111111010111010011001111"; WHEN "1000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001110101110111100000011010000110"; WHEN "1000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001111101101011010110000011010010"; WHEN "1000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010000101011010110100111100000101"; WHEN "1000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010001101000101111001101110100011"; WHEN "1000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010010100101100100001000101010010"; WHEN "1001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010011100001110100111101001010100"; WHEN "1001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010100011101100001010100001011100"; WHEN "1001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010101011000101000110001011100100"; WHEN "1001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010110010011001010111110000100100"; WHEN "1001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010111001101000111011111001000111"; WHEN "1001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000000110011101111101001011111"; WHEN "1001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000111111001110000000110011110"; WHEN "1001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011001110111010111001110111111110"; WHEN "1010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011010101110111001010010001110110"; WHEN "1010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011011100101110011110011000111101"; WHEN "1010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011100011100000110011001001001001"; WHEN "1010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011101010001110000101111000101100"; WHEN "1010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110000110110010011100011000111"; WHEN "1010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110111011001011001011101010011"; WHEN "1010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011111101110111010100111100011100"; WHEN "1010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100000100010000000011001111101101"; WHEN "1011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100001010100011100001101110011100"; WHEN "1011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010000110001101101100011100011"; WHEN "1011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010110111010100100010100000100"; WHEN "1011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100011100111110000011100000001010"; WHEN "1011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100100010111100001000100001101001"; WHEN "1011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101000110100110000110001111011"; WHEN "1011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101110100111111010000100111001"; WHEN "1011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100110100010101100001111010001101"; WHEN "1100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111001111101100101111101110000"; WHEN "1100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111111100000000011110011100101"; WHEN "1100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101000100111100111001010011110100"; WHEN "1100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001010010100000100001001001101"; WHEN "1100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001111100101100010000111001000"; WHEN "1100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101010100110001010001010100001101"; WHEN "1100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011001110111001111010101110101"; WHEN "1100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011110110111011010001101111010"; WHEN "1101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101100011110001110000000111001111"; WHEN "1101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101000100110001110111010010001"; WHEN "1101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101101010100110100100110101101"; WHEN "1101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110001111101011111011001010101"; WHEN "1101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110110100000001101100000100000"; WHEN "1101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111010111100111100111010111000"; WHEN "1101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111111010011101100010000110110"; WHEN "1101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000011100100011001011010100000"; WHEN "1110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000111101111000011000011110011"; WHEN "1110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001011110011100111011010000000"; WHEN "1110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001111110010000100101111100001"; WHEN "1110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010011101010011001110010000111"; WHEN "1110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010111011100100100111111111001"; WHEN "1110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011011001000100101000000101011"; WHEN "1110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011110101110011000001011101010"; WHEN "1110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100010001101111101010010100010"; WHEN "1111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100101100111010011001000110011"; WHEN "1111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101000111010011000011010000011"; WHEN "1111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101100000111001011110100010010"; WHEN "1111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101111001101101100001110011100"; WHEN "1111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110010001101111000100101110110"; WHEN "1111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110101000111101111110101001010"; WHEN "1111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110111111011010000111000110000"; WHEN "1111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110111010101000011010110000100000"; WHEN OTHERS => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; END CASE; END IF; END PROCESS; --sumAHighB_uid242_sinPiZPolyEval(ADD,241)@14 sumAHighB_uid242_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid229_sinPiZTableGenerator_q(34)) & memoryC3_uid229_sinPiZTableGenerator_q); sumAHighB_uid242_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((35 downto 28 => reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q(27)) & reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q); sumAHighB_uid242_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid242_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid242_sinPiZPolyEval_b)); sumAHighB_uid242_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_o(35 downto 0); --lowRangeB_uid240_sinPiZPolyEval(BITSELECT,239)@13 lowRangeB_uid240_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid240_sinPiZPolyEval_b <= lowRangeB_uid240_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a(DELAY,686)@13 ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid240_sinPiZPolyEval_b, xout => ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --s2_uid240_uid243_sinPiZPolyEval(BITJOIN,242)@14 s2_uid240_uid243_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_q & ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q; --yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval(BITSELECT,274)@14 yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in(36 downto 19); --reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9(REG,389)@14 reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor(LOGICAL,950) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top(CONSTANT,946) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q <= "0110"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp(LOGICAL,947) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b else "0"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg(REG,948) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena(REG,951) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q = "1") THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd(LOGICAL,952) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt(COUNTER,942) -- every=1, low=0, high=6, step=1, init=1 ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i = 5 THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i - 6; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i,3)); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg(REG,943) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux(MUX,944) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q) BEGIN CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s IS WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem(DUALMEM,1069) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 3, numwords_a => 7, width_b => 45, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg(DELAY,1068) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT3_uid244_sinPiZPolyEval(BITSELECT,243)@14 yT3_uid244_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q; yT3_uid244_sinPiZPolyEval_b <= yT3_uid244_sinPiZPolyEval_in(44 downto 10); --xBottomBits_uid274_pT3_uid245_sinPiZPolyEval(BITSELECT,273)@14 xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b(7 downto 0); xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in(7 downto 0); --pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval(BITJOIN,276)@14 pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7(REG,391)@14 reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid273_pT3_uid245_sinPiZPolyEval(BITSELECT,272)@14 yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q(9 downto 0); yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b <= yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in(9 downto 0); --spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval(BITJOIN,275)@14 spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q <= GND_q & yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b; --pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval(BITJOIN,277)@14 pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q <= spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6(REG,390)@14 reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval(BITSELECT,271)@14 xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in(34 downto 17); --reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4(REG,392)@14 reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma(CHAINMULTADD,345)@15 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1),38); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0); END IF; END PROCESS; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0),37)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval(BITSELECT,279)@18 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in(36 downto 7); --highBBits_uid282_pT3_uid245_sinPiZPolyEval(BITSELECT,281)@18 highBBits_uid282_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b; highBBits_uid282_pT3_uid245_sinPiZPolyEval_b <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_in(29 downto 1); --reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1(REG,395)@18 reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval(BITSELECT,269)@14 yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in(36 downto 10); --reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1(REG,393)@14 reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval(BITSELECT,268)@14 xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in(34 downto 8); --reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0(REG,394)@14 reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid271_pT3_uid245_sinPiZPolyEval(MULT,270)@15 topProd_uid271_pT3_uid245_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_b); topProd_uid271_pT3_uid245_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid271_pT3_uid245_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid271_pT3_uid245_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0(REG,396)@18 reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid283_pT3_uid245_sinPiZPolyEval(ADD,282)@19 sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q(53)) & reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b)); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid281_pT3_uid245_sinPiZPolyEval(BITSELECT,280)@18 lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b <= lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a(DELAY,724)@18 ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b, xout => ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid281_uid284_pT3_uid245_sinPiZPolyEval(BITJOIN,283)@19 add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q & ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q; --R_uid285_pT3_uid245_sinPiZPolyEval(BITSELECT,284)@19 R_uid285_pT3_uid245_sinPiZPolyEval_in <= add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q(54 downto 0); R_uid285_pT3_uid245_sinPiZPolyEval_b <= R_uid285_pT3_uid245_sinPiZPolyEval_in(54 downto 18); --reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1(REG,397)@19 reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= R_uid285_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor(LOGICAL,1168) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1164) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q <= "01011"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp(LOGICAL,1165) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg(REG,1166) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena(REG,1169) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1170) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1160) -- every=1, low=0, high=11, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i = 10 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i - 11; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i,4)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg(REG,1161) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1162) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1159) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 4, numwords_a => 12, width_b => 7, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg(DELAY,1158) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0(REG,381)@18 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC2_uid228_sinPiZTableGenerator(LOOKUP,227)@19 memoryC2_uid228_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; WHEN "0000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010010000000010011011110101101000"; WHEN "0000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010100110111111010000111001000101"; WHEN "0000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101011001101001111001000101101101011"; WHEN "0000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101100000010110001110010011100100110"; WHEN "0000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101101000111100110110110100100001100"; WHEN "0000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101110011011101101110110101011000001"; WHEN "0000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101111111111000110001101110000001000"; WHEN "0001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110001110001101111010000000001001001"; WHEN "0001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110011110011101000001010111100010011"; WHEN "0001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110110000100110000000101010101010010"; WHEN "0001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111000100101000101111111001111001110"; WHEN "0001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111011010100101000110010000000110000"; WHEN "0001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111110010011010111010000010100101101"; WHEN "0001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000001100001010000000110001101010110"; WHEN "0001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000100111110010001111000111001110001"; WHEN "0010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001000101010011011000111000110111111"; WHEN "0010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001100100101101010001000110100001110"; WHEN "0010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010000101111111101001111011000110110"; WHEN "0010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010101001001010010100101011111010000"; WHEN "0010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011001110001101000001111010001111100"; WHEN "0010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011110101000111100001010010001101000"; WHEN "0010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111100011101111001100001101011001010011"; WHEN "0010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101001000100010110001000111111011001"; WHEN "0011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101110101000010111100110110111011101"; WHEN "0011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111110100011011001110001010010101001001"; WHEN "0011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111111010011100110111010000000101010000"; WHEN "0011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000000101101010000001110011011110111"; WHEN "0011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000111001100010110010101001001001010"; WHEN "0011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000001101111010000110101101100011101100"; WHEN "0011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000010100110110011110011010100101011100"; WHEN "0011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000011100000001011010011000101010010101"; WHEN "0100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000100011011010110111011101111001100010"; WHEN "0100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000101011000010110010011010000011100100"; WHEN "0100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000110010111001000111110110011110000010"; WHEN "0100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000111010111101110100010110010000011111"; WHEN "0100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001000011010000110100010110001010111111"; WHEN "0100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001001011110010000100001100101110011011"; WHEN "0100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001010100100001100000001010001100011000"; WHEN "0100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001011101011111000100011000101001100001"; WHEN "0101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001100110101010101100111100000000011011"; WHEN "0101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001110000000100010101110001111101110010"; WHEN "0101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001111001101011111010110010001100011010"; WHEN "0101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010000011100001010111101110001010011110"; WHEN "0101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010001101100100101000010001011000100111"; WHEN "0101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010010111110101101000000001010011000010"; WHEN "0101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010100010010100010010011101010101101010"; WHEN "0101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010101101000000100010111111000010000011"; WHEN "0110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010110111111010010100111001111011100110"; WHEN "0110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011000011000001100011011011101110111001"; WHEN "0110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011001110010110001001101100001111110101"; WHEN "0110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011011001111000000010101101100000111100"; WHEN "0110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011100101100111001001011011101110011000"; WHEN "0110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011110001100011011000101101011001110101"; WHEN "0110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011111101101100101011010011010110110001"; WHEN "0110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100001010000010111011111000101001101100"; WHEN "0111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100010110100110000101000010110110110100"; WHEN "0111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100100011010110000001010001110101000110"; WHEN "0111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100110000010010101010111111111100101100"; WHEN "0111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100111101011011111100100010000110111111"; WHEN "0111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101001010110001110000000111101111100101"; WHEN "0111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101011000010011111111111010110011011100"; WHEN "0111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101100110000010100101111111111011010100"; WHEN "0111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101110011111101011100010110011100010110"; WHEN "1000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110000010000100011100111000010100111110"; WHEN "1000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110010000010111100001011010011001010101"; WHEN "1000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110011110110110100011101100001011001000"; WHEN "1000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110101101100001011101011000001011011001"; WHEN "1000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110111100011000001000000011101110001111"; WHEN "1000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111001011011010011101001111000101110001"; WHEN "1000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111011010101000010110010101100101000110"; WHEN "1000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111101010000001101100101101100010111111"; WHEN "1001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111111001100110011001101000011100111011"; WHEN "1001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000001001010110010110010010110100011100"; WHEN "1001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000011001010001011011110100100000011000"; WHEN "1001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000101001010111100011010000011111011101"; WHEN "1001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000111001101000100101100101001010011111"; WHEN "1001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001001010000100011011101100001100000010"; WHEN "1001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001011010101010111110011010101000110000"; WHEN "1001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001101011011100000110100001001001100100"; WHEN "1010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001111100010111101100101011101111001100"; WHEN "1010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010001101011101101001100010000010111010"; WHEN "1010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010011110101101110101100111011000000101"; WHEN "1010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010110000001000001001011010101000000100"; WHEN "1010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011000001101100011101010110100010000110"; WHEN "1010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011010011011010101001110001100010110011"; WHEN "1010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011100101010010100110111101111101101001"; WHEN "1010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011110111010100001101001010000001101110"; WHEN "1011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100001001011111010100011111111010110111"; WHEN "1011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100011011110011110101000101111001011001"; WHEN "1011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100101110010001100110111110001101101110"; WHEN "1011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101000000111000100010000111010010100101"; WHEN "1011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101010011101000011110011011110001111001"; WHEN "1011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101100110100001010011110010100110010101"; WHEN "1011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101111001100010111001111110111010001011"; WHEN "1011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110001100101101001000110000010101000001"; WHEN "1100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110011111111111110111110010111000010010"; WHEN "1100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110110011011010111110101111001000100111"; WHEN "1100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111000110111110010101001010001010011010"; WHEN "1100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111011010101001110010100101101110010111"; WHEN "1100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111101110011101001110100000001111101010"; WHEN "1100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000000010011000100000010100110110100000"; WHEN "1100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000010110011011011111011011100110110011"; WHEN "1100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000101010100110000011001001011000000001"; WHEN "1101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000111110111000000010101111111100010101"; WHEN "1101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001010011010001010101011110001011010100"; WHEN "1101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001100111110001110010100000000000010111"; WHEN "1101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001111100011001010000111110011101110000"; WHEN "1101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010010001000111100111111111110011011101"; WHEN "1101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010100101111100101110100111100110010101"; WHEN "1101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010111010111000011011110110101001010101"; WHEN "1101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011001111111010100110101011010011011011"; WHEN "1110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011100101000011000110000001010000000100"; WHEN "1110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011111010010001110000110001110011111011"; WHEN "1110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100001111100110011101110011111001111111"; WHEN "1110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100100101000001000011111100000011011011"; WHEN "1110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100111010100001011001111100100100101001"; WHEN "1110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101010000000111010110100101100100010111"; WHEN "1110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101100101110010110000100101000101101101"; WHEN "1110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101111011100011011110100111000011010111"; WHEN "1111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110010001011001010111010101011001010001"; WHEN "1111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110100111010100010001011000001010110100"; WHEN "1111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110111101010100000011010101100101100011"; WHEN "1111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111010011011000100011110010000011111011"; WHEN "1111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111101001100001101001010000010010001011"; WHEN "1111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111111111101111001010010001010101000011"; WHEN "1111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000010110000000111101010100101101001001"; WHEN "1111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000101100010110111000111000011010110101"; WHEN OTHERS => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid246_sinPiZPolyEval(CONSTANT,245) rndBit_uid246_sinPiZPolyEval_q <= "01"; --cIncludingRoundingBit_uid247_sinPiZPolyEval(BITJOIN,246)@19 cIncludingRoundingBit_uid247_sinPiZPolyEval_q <= memoryC2_uid228_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0(REG,398)@19 reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid247_sinPiZPolyEval_q; END IF; END PROCESS; --ts3_uid248_sinPiZPolyEval(ADD,247)@20 ts3_uid248_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q); ts3_uid248_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q(36)) & reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q); ts3_uid248_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid248_sinPiZPolyEval_a) + SIGNED(ts3_uid248_sinPiZPolyEval_b)); ts3_uid248_sinPiZPolyEval_q <= ts3_uid248_sinPiZPolyEval_o(45 downto 0); --s3_uid249_sinPiZPolyEval(BITSELECT,248)@20 s3_uid249_sinPiZPolyEval_in <= ts3_uid248_sinPiZPolyEval_q; s3_uid249_sinPiZPolyEval_b <= s3_uid249_sinPiZPolyEval_in(45 downto 1); --yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval(BITSELECT,286)@20 yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b; yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in(44 downto 18); --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9(REG,399)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor(LOGICAL,1091) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top(CONSTANT,1087) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q <= "01100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp(LOGICAL,1088) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg(REG,1089) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena(REG,1092) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd(LOGICAL,1093) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1083) -- every=1, low=0, high=12, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i = 11 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i - 12; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i,4)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg(REG,1084) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux(MUX,1085) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem(DUALMEM,1082) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 13, width_b => 45, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg(DELAY,1081) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT4_uid250_sinPiZPolyEval(BITSELECT,249)@20 yT4_uid250_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q; yT4_uid250_sinPiZPolyEval_b <= yT4_uid250_sinPiZPolyEval_in(44 downto 2); --xBottomBits_uid290_pT4_uid251_sinPiZPolyEval(BITSELECT,289)@20 xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in <= yT4_uid250_sinPiZPolyEval_b(15 downto 0); xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in(15 downto 0); --pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval(BITJOIN,291)@20 pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7(REG,401)@20 reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid289_pT4_uid251_sinPiZPolyEval(BITSELECT,288)@20 yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b(17 downto 0); yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b <= yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a(DELAY,733)@20 ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b, xout => ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval(BITJOIN,290)@21 spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q; --pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval(BITJOIN,292)@21 pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q <= spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6(REG,400)@21 reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a(DELAY,727)@20 ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 43, depth => 1 ) PORT MAP ( xin => yT4_uid250_sinPiZPolyEval_b, xout => ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval(BITSELECT,285)@21 xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in <= ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q; xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in(42 downto 16); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4(REG,402)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma(CHAINMULTADD,346)@22 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval(BITSELECT,294)@25 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in(54 downto 8); --highBBits_uid297_pT4_uid251_sinPiZPolyEval(BITSELECT,296)@25 highBBits_uid297_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b; highBBits_uid297_pT4_uid251_sinPiZPolyEval_b <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_in(46 downto 18); --reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1(REG,405)@25 reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1(REG,403)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b(DELAY,730)@21 ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0(REG,404)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid288_pT4_uid251_sinPiZPolyEval(MULT,287)@22 topProd_uid288_pT4_uid251_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_b); topProd_uid288_pT4_uid251_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid288_pT4_uid251_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid288_pT4_uid251_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0(REG,406)@25 reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid298_pT4_uid251_sinPiZPolyEval(ADD,297)@26 sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q(53)) & reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b)); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid296_pT4_uid251_sinPiZPolyEval(BITSELECT,295)@25 lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b(17 downto 0); lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b <= lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a(DELAY,741)@25 ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b, xout => ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid296_uid299_pT4_uid251_sinPiZPolyEval(BITJOIN,298)@26 add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q & ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q; --R_uid300_pT4_uid251_sinPiZPolyEval(BITSELECT,299)@26 R_uid300_pT4_uid251_sinPiZPolyEval_in <= add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q(71 downto 0); R_uid300_pT4_uid251_sinPiZPolyEval_b <= R_uid300_pT4_uid251_sinPiZPolyEval_in(71 downto 26); --reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1(REG,407)@26 reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= R_uid300_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor(LOGICAL,1155) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1151) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q <= "010010"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp(LOGICAL,1152) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg(REG,1153) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena(REG,1156) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1157) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1147) -- every=1, low=0, high=18, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i = 17 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i - 18; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg(REG,1148) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1149) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1146) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 19, width_b => 7, widthad_b => 5, numwords_b => 19, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg(DELAY,1145) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0(REG,380)@25 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC1_uid227_sinPiZTableGenerator(LOOKUP,226)@26 memoryC1_uid227_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; WHEN "0000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111110101101010100010101111000000010001111100011"; WHEN "0000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111101011010101001001010010110100010110001011110"; WHEN "0000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111100000111111110111100000001110010011010000110"; WHEN "0000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111010110101010110001001011111100110111111100011"; WHEN "0000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111001100010101111010001010101001101111010110100"; WHEN "0000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111000010000001010110010000110111110101011111000"; WHEN "0000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110110111101101001001010011000001101011000111010"; WHEN "0001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110101101011001010111000101010111101010010100111"; WHEN "0001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110100011000110000011011011111110011010111001110"; WHEN "0001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110011000110011010010001010101101000110101101101"; WHEN "0001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110001110100001000111000101001011101110011011101"; WHEN "0001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110000100001111100101111110110001011110001011001"; WHEN "0001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101111001111110110010101010100011000010010100110"; WHEN "0001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101101111101110110000111011010000111100011100100"; WHEN "0001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101100101011111100100100011010101111000101000111"; WHEN "0010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101011011010001010001010100110101000010011111000"; WHEN "0010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101010001000011111011000001011000011010110000100"; WHEN "0010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101000110110111100101011010001111001100111110010"; WHEN "0010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100111100101100010100010000001100000101010111010"; WHEN "0010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100110010100010001011010011100011100110101011100"; WHEN "0010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100101000011001001110010100001010100000101101100"; WHEN "0010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100011110010001100001000001010100000110110000000"; WHEN "0010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100010100001011000111001001110000100110010111000"; WHEN "0011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100001010000110000100011011101011011110011010110"; WHEN "0011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100000000000010011100100100101001110110011000010"; WHEN "0011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011110110000000010011010001101000110110000011100"; WHEN "0011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011101011111111101100001110111011111101010000000"; WHEN "0011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011100010000000101011001000001011011100001111010"; WHEN "0011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011011000000011010011101000010010101100000110110"; WHEN "0011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011001110000111101001011001011110100111101110010"; WHEN "0011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011000100001101110000000101001100000101000010010"; WHEN "0100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010111010010101101011010100000110001110011110001"; WHEN "0100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010110000011111011110101110000100111100111110101"; WHEN "0100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010100110101011001101111010001011010010011110011"; WHEN "0100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010011100111000111100011110100101110100010111000"; WHEN "0100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010010011001000101110000000101001000110111000111"; WHEN "0100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010001001011010100110000100110000001000100101001"; WHEN "0100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001111111101110101000001110011010101110010001110"; WHEN "0100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001110110000100111000000000001011111111100011001"; WHEN "0101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001101100011101011000111011101000110011100100000"; WHEN "0101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001100010111000001110100001010110001110100101001"; WHEN "0101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001011001010101011100010000110111111111100011001"; WHEN "0101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001001111110101000101101000101110111110101110110"; WHEN "0101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001000110010111001110000110010111101100001101110"; WHEN "0101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000111100111011111001000110001000101111011110000"; WHEN "0101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000110011100011001010000011010001010111001000100"; WHEN "0101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000101010001101000100010111110111111001010110011"; WHEN "0110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000100000111001101011011100111000010100110100100"; WHEN "0110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000010111101001000010101010000010110010001100101"; WHEN "0110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000001110011011001101010101111010000110001110001"; WHEN "0110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000000101010000001110110101110010010100010001010"; WHEN "0110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111111100001000001010011101101111010001101110100"; WHEN "0110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111110011000011000011100000100011001001100111111"; WHEN "0110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111101010000000111101001111101101000001001100111"; WHEN "0110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111100001000001111010111011010111011101000011000"; WHEN "0111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111011000000101111111110010010111000110100000100"; WHEN "0111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111001111001101001111000010001001010010011000111"; WHEN "0111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111000110010111101011110110110010100111101001111"; WHEN "0111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110111101100101011001011010111101100111001001111"; WHEN "0111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110110100110110011010110111111001010011111110011"; WHEN "0111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110101100001010110011010101010111111100100001011"; WHEN "0111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110100011100010100101111001101101100100000011010"; WHEN "0111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110011010111101110101101001101110101101001000101"; WHEN "1000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110010010011100100101101000101111000100111000101"; WHEN "1000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110001001111110111000111000100000001110100110010"; WHEN "1000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110000001100100110010011001010000010000100100001"; WHEN "1000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101111001001110010101001001101000100001000011111"; WHEN "1000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101110000111011100100000110101100010100101111011"; WHEN "1000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101101000101100100010001011110111101101010011001"; WHEN "1000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101100000100001010010010010111110001001000100100"; WHEN "1000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101011000011001110111010100001001010011011010001"; WHEN "1001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101010000010110010100000101110111110101110111011"; WHEN "1001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101001000010110101011011100111100001010010001010"; WHEN "1001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101000000011011000000001100011011001101001101101"; WHEN "1001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100111000100011010101000101101011010001111110100"; WHEN "1001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100110000101111101100111000010010110110101001010"; WHEN "1001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100101001000000001010010010000111011001100101001"; WHEN "1001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100100001010100101111111111001100001111011011000"; WHEN "1001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100011001101101100000101001110001011001110111100"; WHEN "1010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100010010001010011110111010010010011111110100100"; WHEN "1010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100001010101011101101010111010101100101110000010"; WHEN "1010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100000011010001001110100101101010000111010011101"; WHEN "1010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011111011111011000101001000000111110001110111111"; WHEN "1010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011110100101001010011011111101101011111101000010"; WHEN "1010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011101101011011111100001011100000010100000001101"; WHEN "1010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011100110010011000001101000101010011000110001101"; WHEN "1010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011111001110100110010010011001111011110111011"; WHEN "1011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011000001110101100100010000000001110100011101"; WHEN "1011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011010001010011010110101110110000100101001100010"; WHEN "1011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011001010011100100111001101111111011000001100001"; WHEN "1011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011000011101010100000010011000001000101101011001"; WHEN "1011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010111100111101000100001111001001010100001001100"; WHEN "1011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010110110010100010101010001101001110110001111011"; WHEN "1011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101111110000010101100111110001101111011011100"; WHEN "1011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101001010001000111011100101100011001011100101"; WHEN "1100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010100010110110101100111001100000101011000010000"; WHEN "1100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010011100100001001000000101001111111111010110011"; WHEN "1100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010110010000011011000100110101011110110000011"; WHEN "1100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010000000100100111111011000101001000001000001"; WHEN "1100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010001001111101110000101000101010111011100100101"; WHEN "1100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010000011111011110111001100001010000110000001000"; WHEN "1100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111101111110111101100001111100001101100011111"; WHEN "1100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111000000111000101100100010000011111010101010"; WHEN "1101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001110010010100010001001011001010111110000100010"; WHEN "1101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001101100100110100010001100100011110001100110110"; WHEN "1101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100110111101111010011100000110010111101110011"; WHEN "1101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100001011010011011101011010000110101111000110"; WHEN "1101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001011011111100000111101001010011001011111101101"; WHEN "1101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010110100011000000000011001110101000000001010"; WHEN "1101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010001001111000110100011110100111011011010110"; WHEN "1101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001001100000000011100110011100111110000011010110"; WHEN "1110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000110110111000100011000111000000001100101100"; WHEN "1110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000001110010111110110111100101010001100011100"; WHEN "1110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000111100110100001101110001011101000100010101000"; WHEN "1110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110111111010110010100101111010011001100111001"; WHEN "1110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110011000110101110110010000101000111111101001"; WHEN "1110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101110011000000011110000110001011001010001101"; WHEN "1110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101001101110110010111010011111001000001110011"; WHEN "1110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100101001010111101100101011001011110111111001"; WHEN "1111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100000101100100101000101010110010110110110011"; WHEN "1111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011100010011101010101011110101111000111101111"; WHEN "1111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011000000000001111101000000010000000010001101"; WHEN "1111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000010011110010010101000110101101111100100010110"; WHEN "1111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001111101001111100010010010101110110011110010"; WHEN "1111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001011100111000110010010111110010100110111110"; WHEN "1111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000111101001110100001110010100000011000001001"; WHEN "1111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000011110010000111000111101011011000001000111"; WHEN OTHERS => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; END CASE; -- End reserved scope level END PROCESS; --cIncludingRoundingBit_uid253_sinPiZPolyEval(BITJOIN,252)@26 cIncludingRoundingBit_uid253_sinPiZPolyEval_q <= memoryC1_uid227_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0(REG,408)@26 reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid253_sinPiZPolyEval_q; END IF; END PROCESS; --ts4_uid254_sinPiZPolyEval(ADD,253)@27 ts4_uid254_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((52 downto 52 => reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q(51)) & reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q); ts4_uid254_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((52 downto 46 => reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q(45)) & reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q); ts4_uid254_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid254_sinPiZPolyEval_a) + SIGNED(ts4_uid254_sinPiZPolyEval_b)); ts4_uid254_sinPiZPolyEval_q <= ts4_uid254_sinPiZPolyEval_o(52 downto 0); --s4_uid255_sinPiZPolyEval(BITSELECT,254)@27 s4_uid255_sinPiZPolyEval_in <= ts4_uid254_sinPiZPolyEval_q; s4_uid255_sinPiZPolyEval_b <= s4_uid255_sinPiZPolyEval_in(52 downto 1); --yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval(BITSELECT,301)@27 yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b; yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in(51 downto 25); --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9(REG,409)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor(LOGICAL,1117) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q <= not (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a or ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top(CONSTANT,1113) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q <= "010011"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp(LOGICAL,1114) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a = ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b else "0"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg(REG,1115) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena(REG,1118) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q = "1") THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd(LOGICAL,1119) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a and ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b; --xBottomBits_uid305_pT5_uid257_sinPiZPolyEval(BITSELECT,304)@5 xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b(17 downto 0); xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt(COUNTER,1109) -- every=1, low=0, high=19, step=1, init=1 ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i = 18 THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '1'; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i - 19; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i,5)); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg(REG,1110) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux(MUX,1111) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q) BEGIN CASE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s IS WHEN "0" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; WHEN "1" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; WHEN OTHERS => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem(DUALMEM,1108) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 <= areset; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 5, numwords_a => 20, width_b => 18, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0, clock1 => clk, address_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq, address_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa, data_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia ); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg(DELAY,1107) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q, xout => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q, clk => clk, aclr => areset ); --pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval(BITJOIN,306)@27 pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7(REG,411)@27 reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid304_pT5_uid257_sinPiZPolyEval(BITSELECT,303)@27 yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b(24 downto 0); yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b <= yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a(DELAY,750)@27 ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b, xout => ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval(BITJOIN,305)@28 spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q; --pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval(BITJOIN,307)@28 pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q <= spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q & GND_q; --reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6(REG,410)@28 reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor(LOGICAL,1104) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top(CONSTANT,1100) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q <= "010100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp(LOGICAL,1101) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg(REG,1102) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena(REG,1105) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd(LOGICAL,1106) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1096) -- every=1, low=0, high=20, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i = 19 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i - 20; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i,5)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg(REG,1097) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux(MUX,1098) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem(DUALMEM,1095) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 5, numwords_a => 21, width_b => 45, widthad_b => 5, numwords_b => 21, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg(DELAY,1094) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval(BITSELECT,300)@28 xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q; xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in(44 downto 18); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4(REG,412)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma(CHAINMULTADD,347)@29 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval(BITSELECT,309)@32 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in(54 downto 1); --highBBits_uid312_pT5_uid257_sinPiZPolyEval(BITSELECT,311)@32 highBBits_uid312_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b; highBBits_uid312_pT5_uid257_sinPiZPolyEval_b <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_in(53 downto 25); --reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1(REG,415)@32 reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1(REG,413)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b(DELAY,747)@28 ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0(REG,414)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid303_pT5_uid257_sinPiZPolyEval(MULT,302)@29 topProd_uid303_pT5_uid257_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_b); topProd_uid303_pT5_uid257_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid303_pT5_uid257_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid303_pT5_uid257_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0(REG,416)@32 reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid313_pT5_uid257_sinPiZPolyEval(ADD,312)@33 sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q(53)) & reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b)); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid311_pT5_uid257_sinPiZPolyEval(BITSELECT,310)@32 lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b(24 downto 0); lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b <= lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a(DELAY,758)@32 ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b, xout => ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid311_uid314_pT5_uid257_sinPiZPolyEval(BITJOIN,313)@33 add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q & ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q; --R_uid315_pT5_uid257_sinPiZPolyEval(BITSELECT,314)@33 R_uid315_pT5_uid257_sinPiZPolyEval_in <= add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q(78 downto 0); R_uid315_pT5_uid257_sinPiZPolyEval_b <= R_uid315_pT5_uid257_sinPiZPolyEval_in(78 downto 25); --reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1(REG,417)@33 reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= R_uid315_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor(LOGICAL,1142) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1138) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q <= "011001"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp(LOGICAL,1139) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg(REG,1140) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena(REG,1143) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1144) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1134) -- every=1, low=0, high=25, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i = 24 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i - 25; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg(REG,1135) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1136) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1133) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 26, width_b => 7, widthad_b => 5, numwords_b => 26, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg(DELAY,1132) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0(REG,379)@32 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC0_uid226_sinPiZTableGenerator(LOOKUP,225)@33 memoryC0_uid226_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; WHEN "0000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111010001111111001101111011000111100001001010"; WHEN "0000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000101010101111101111010001101100110011111100100"; WHEN "0000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000010000111010001110111000001110010011001110001"; WHEN "0000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001111101100101111100010000110111011000000101000010"; WHEN "0000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110111110001111110110010110011100111000110011101"; WHEN "0000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110000101011011011100110100000100010100111010101"; WHEN "0000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001101000010010010101010100001100000100101011101101"; WHEN "0001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001011110100110101111000010100110110100001011000010"; WHEN "0001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001010011101000101100010111000010101101001011110101"; WHEN "0001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001000111011000010001010101010001011100000010111010"; WHEN "0001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000111001110101100010011111100010101010110110110111"; WHEN "0001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000101011000000100100110110100010000001101000110010"; WHEN "0001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000011010111001011101111001010100111001000011000110"; WHEN "0001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000001001100000010011100101010111111111101111100110"; WHEN "0001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111110110110101001100010110011100110010010101101111"; WHEN "0010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111100010111000001111000110100110100110000010101111"; WHEN "0010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111001101101001100011001110000111100101111100011100"; WHEN "0010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110110111001001010000100011011101100011000000101111"; WHEN "0010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110011111010111011111011011001110010110110010111000"; WHEN "0010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110000110010100011000101000000100011000111000100110"; WHEN "0010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101101100000000000101011010101010100111001000011100"; WHEN "0010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101010000011010101111100001101000100000101011011110"; WHEN "0010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100110011100100100001001001011101110011110100001011"; WHEN "0011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100010101011101100100111100011101111110101100100111"; WHEN "0011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011110110000110000110000010101011100010111110000011"; WHEN "0011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011010101011110010000000001110011001100010100001001"; WHEN "0011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010110011100110001110111101000110101001111110010101"; WHEN "0011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010010000011110001111010101010111011011010001011111"; WHEN "0011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001101100000110011110001000110001001111001100110001"; WHEN "0011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001000110011111001000110010110100010111000011111111"; WHEN "0011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001000011111101000011101001100001111101100010010011001"; WHEN "0100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111110111100010101001101010111010101001011000110001"; WHEN "0100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111001110001101111101000001101110110110001001100100"; WHEN "0100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000110100011101010100110100000100001100111000110001110"; WHEN "0100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101110111111000110101110011111101010000010000111000"; WHEN "0100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101001010111000111011000101011010001011010101011100"; WHEN "0100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000100011100101011000110111010110111110001001101100111"; WHEN "0100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000011101101001111101010010110110101000111000011000010"; WHEN "0100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010111100100110110110111000001001011110110011001101"; WHEN "0101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010001010110000111110011001111100101011011000101100"; WHEN "0101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000001010111101110010011010011011111001000011101001111"; WHEN "0101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000000100011011111001000011000000001110101111000110101"; WHEN "0101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111111101110000011110000110110101110000111000001001000"; WHEN "0101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111110110111011100100000011010011101000101101101101111"; WHEN "0101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101111111101001101011001001101111001001010100111010"; WHEN "0101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101000110101011100101100110100011000001100101000111"; WHEN "0101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111100001100100010100100101110001100110101011111100110"; WHEN "0110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111011010001001110111101111001001100110110011000001101"; WHEN "0110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111010010100110001000110111011000110000110111110111111"; WHEN "0110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111001010111001001010110000010010100110110110111111101"; WHEN "0110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111000011000011000000001111000000100110010000101101101"; WHEN "0110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110111011000011101100001100000000111000101001011011010"; WHEN "0110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110110010111011010001100011000101000010101101011001001"; WHEN "0110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110101010101001110011010011010000110001111000101001011"; WHEN "0110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110100010001111010100011110111000101000100011101001111"; WHEN "0111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110011001101011111000001011100000101000110101010111101"; WHEN "0111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110010000111111100001100001111010111101111011010000110"; WHEN "0111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110001000001010010011101110000110100100001000000010111"; WHEN "0111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101111111001100010001111111001101101111011001101100100"; WHEN "0111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101110110000101011111100111100100110000100111011101101"; WHEN "0111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101101100110101111111111100101000011001011000100010101"; WHEN "0111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101100011011101110110010110111100011110100100000110011"; WHEN "0111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101011001111101000110010010001010011001011011010110110"; WHEN "1000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101010000010011110011001100111111100111011110011001101"; WHEN "1000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101000110100010000000101001001100001000111100100001001"; WHEN "1000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100111100100111110010001011100000111110000000101011101"; WHEN "1000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100110010100101001011011011101110100010101011000001110"; WHEN "1000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100101000011010010000000100100011001001010111111110011"; WHEN "1000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100011110000111000011110011101001010100010101110100101"; WHEN "1000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100010011101011101010011001100110001101101001100010111"; WHEN "1000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100001001001000000111101001110111111110000011100100111"; WHEN "1001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011111110011100011111011010110100000010100101010111001"; WHEN "1001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011110011101000110101100101100101100000111000011110001"; WHEN "1001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011101000101101001110000110001011011010011000000110010"; WHEN "1001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011011101101001101100111011010110111110001101101101010"; WHEN "1001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011010010011110010110000110101001111010000001101101100"; WHEN "1001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011000111001011001101101100010100101001100000111100110"; WHEN "1001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010111011110000010111110011010100100100110111110110011"; WHEN "1001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010110000001101111000100101010010001110000100000110101"; WHEN "1010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010100100100011110100001110011111011100111101101011110"; WHEN "1010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010011000110010001110111101110101101010011000000111111"; WHEN "1010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010001100111001001101000100110011111001111100111000001"; WHEN "1010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010000000111000110010110111011101000010111111101010001"; WHEN "1010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001110100110001000100101100010101111000001101101010100"; WHEN "1010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001101000100010000110111100100011001110011000100010010"; WHEN "1010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001011100001011111110000011101000000001111110000000000"; WHEN "1010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001001111101110101110011111100011011011101101000101110"; WHEN "1011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001000011001010011100110000101110110100001001110110000"; WHEN "1011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000110110011111001101011001111011110110010000011100000"; WHEN "1011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000101001101101000101000000010010100000111000101001110"; WHEN "1011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000011100110100001000001011001111000111011010101001101"; WHEN "1011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000001111110100011011100100100000010001010101111111000"; WHEN "1011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000000010101110000011111000000100111000111011110010110"; WHEN "1011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111110101100001000101110100001010001000111101001001101"; WHEN "1011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111101000001101100110001001001001011001011110100011010"; WHEN "1100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111011010110011101001101001100110001011110001011110000"; WHEN "1100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111001101010011010101001010001100000101010101000000111"; WHEN "1100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110111111101100101101100001101100101001111110101000001"; WHEN "1100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110110001111111110111101000111101010101001011110111000"; WHEN "1100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110100100001100111000011010110101010010011110001011110"; WHEN "1100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110010110010011110100110100001011010101000001111000001"; WHEN "1100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110001000010100110001110011110011101110100000111111001"; WHEN "1100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101111010001111110100011010011110000101000011010111010"; WHEN "1101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101101100000101000001101010110011001000011100110100101"; WHEN "1101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101011101110100011110101001010010100110101010011100110"; WHEN "1101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101001111011110010000011100010000111111100000000100011"; WHEN "1101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101000001000010011100001011110101010111100110111011100"; WHEN "1101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100110010100001000111000001110111001010101110101010001"; WHEN "1101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100100011111010010110001001111011111101010001100000100"; WHEN "1101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100010101001110001110110001010101001101001100111101111"; WHEN "1101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100000110011100110110000110111110000010001111110011101"; WHEN "1110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011110111100110010001011011011000111101011110100101010"; WHEN "1110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011101000101010100110000000101101101000001111101101101"; WHEN "1110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011011001101001111001001010100110100010100000001010111"; WHEN "1110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011001010100100010000001110001110110000100001110111001"; WHEN "1110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010111011011001110000100010001111101000000100110100000"; WHEN "1110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010101100001010011111011110101110011100111100001100101"; WHEN "1110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010011100110110100010011101001010001101000000010101011"; WHEN "1110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010001101011101111110111000011001001011101110101101100"; WHEN "1111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001111110000000111010001100100110101101001001001010110"; WHEN "1111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001101110011111011001110111010000110000010101010100001"; WHEN "1111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001011110111001100011010111000101101001011101010010011"; WHEN "1111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001001111001111011100001100000001101011010010111101001"; WHEN "1111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000111111100001001001110111001100110000010110101011110"; WHEN "1111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000101111101110110001111010111000000011100010110001010"; WHEN "1111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000011111111000011001111010011011101000011100101001111"; WHEN "1111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000001111111110000111011010010100000011001101000010011"; WHEN OTHERS => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid258_sinPiZPolyEval(CONSTANT,257) rndBit_uid258_sinPiZPolyEval_q <= "001"; --cIncludingRoundingBit_uid259_sinPiZPolyEval(BITJOIN,258)@33 cIncludingRoundingBit_uid259_sinPiZPolyEval_q <= memoryC0_uid226_sinPiZTableGenerator_q & rndBit_uid258_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0(REG,418)@33 reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid259_sinPiZPolyEval_q; END IF; END PROCESS; --ts5_uid260_sinPiZPolyEval(ADD,259)@34 ts5_uid260_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q); ts5_uid260_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((61 downto 54 => reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q(53)) & reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q); ts5_uid260_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid260_sinPiZPolyEval_a) + SIGNED(ts5_uid260_sinPiZPolyEval_b)); ts5_uid260_sinPiZPolyEval_q <= ts5_uid260_sinPiZPolyEval_o(61 downto 0); --s5_uid261_sinPiZPolyEval(BITSELECT,260)@34 s5_uid261_sinPiZPolyEval_in <= ts5_uid260_sinPiZPolyEval_q; s5_uid261_sinPiZPolyEval_b <= s5_uid261_sinPiZPolyEval_in(61 downto 1); --fxpSinRes_uid66_fpSinPiTest(BITSELECT,65)@34 fxpSinRes_uid66_fpSinPiTest_in <= s5_uid261_sinPiZPolyEval_b(58 downto 0); fxpSinRes_uid66_fpSinPiTest_b <= fxpSinRes_uid66_fpSinPiTest_in(58 downto 5); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor(LOGICAL,963) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q <= not (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a or ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top(CONSTANT,959) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q <= "011111"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp(LOGICAL,960) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q <= "1" when ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a = ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b else "0"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg(REG,961) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena(REG,964) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q = "1") THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd(LOGICAL,965) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a and ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt(COUNTER,955) -- every=1, low=0, high=31, step=1, init=1 ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ELSIF (clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg(REG,956) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux(MUX,957) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux: PROCESS (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem(DUALMEM,954) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia <= sinXIsX_uid30_fpSinPiTest_c; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 32, width_b => 1, widthad_b => 5, numwords_b => 32, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq, address_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa, data_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia ); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg(DELAY,953) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --multRightOp_uid68_fpSinPiTest(MUX,67)@34 multRightOp_uid68_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q; multRightOp_uid68_fpSinPiTest: PROCESS (multRightOp_uid68_fpSinPiTest_s, fxpSinRes_uid66_fpSinPiTest_b) BEGIN CASE multRightOp_uid68_fpSinPiTest_s IS WHEN "0" => multRightOp_uid68_fpSinPiTest_q <= fxpSinRes_uid66_fpSinPiTest_b; WHEN "1" => multRightOp_uid68_fpSinPiTest_q <= piwFP2_uid67_fpSinPiTest_q; WHEN OTHERS => multRightOp_uid68_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_b_1(BITSELECT,318)@34 mul2xSinRes_uid69_fpSinPiTest_b_1_in <= multRightOp_uid68_fpSinPiTest_q; mul2xSinRes_uid69_fpSinPiTest_b_1_b <= mul2xSinRes_uid69_fpSinPiTest_b_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1(REG,423)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor(LOGICAL,1129) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q <= not (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a or ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top(CONSTANT,1125) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q <= "010110"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp(LOGICAL,1126) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q <= "1" when ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a = ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b else "0"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg(REG,1127) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena(REG,1130) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q = "1") THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd(LOGICAL,1131) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a and ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor(LOGICAL,937) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a or ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top(CONSTANT,933) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q <= "0111"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp(LOGICAL,934) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a = ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b else "0"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg(REG,935) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena(REG,938) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q = "1") THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd(LOGICAL,939) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt(COUNTER,929) -- every=1, low=0, high=7, step=1, init=1 ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,3); ELSIF (clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i + 1; END IF; END PROCESS; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i,3)); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg(REG,930) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux(MUX,931) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q) BEGIN CASE ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s IS WHEN "0" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; WHEN "1" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; WHEN OTHERS => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem(DUALMEM,928) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 <= areset; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia <= oFracX_uid31_uid31_fpSinPiTest_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 3, numwords_a => 8, width_b => 53, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq, address_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa, data_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia ); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq(52 downto 0); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg(DELAY,927) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg : dspba_delay GENERIC MAP ( width => 53, depth => 1 ) PORT MAP ( xin => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q, xout => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q, clk => clk, aclr => areset ); --LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest(BITSELECT,220)@10 LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q(77 downto 0); LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in(77 downto 0); --leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest(BITJOIN,221)@10 leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b & GND_q; --LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest(BITSELECT,204)@9 LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(54 downto 0); LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in(54 downto 0); --leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest(BITJOIN,205)@9 leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest(BITSELECT,201)@9 LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(62 downto 0); LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in(62 downto 0); --leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest(BITJOIN,202)@9 leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest(BITSELECT,198)@9 LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(70 downto 0); LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in(70 downto 0); --leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest(BITJOIN,199)@9 leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --ozz_uid41_fpSinPiTest(CONSTANT,40) ozz_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor(LOGICAL,1040) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q <= not (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a or ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top(CONSTANT,1036) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q <= "011"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp(LOGICAL,1037) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q <= "1" when ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a = ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b else "0"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg(REG,1038) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena(REG,1041) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q = "1") THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd(LOGICAL,1042) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a and ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b; --vStage_uid149_lzcZ_uid51_fpSinPiTest(BITSELECT,148)@4 vStage_uid149_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(14 downto 0); vStage_uid149_lzcZ_uid51_fpSinPiTest_b <= vStage_uid149_lzcZ_uid51_fpSinPiTest_in(14 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt(COUNTER,1032) -- every=1, low=0, high=3, step=1, init=1 ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,2); ELSIF (clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i,2)); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg(REG,1033) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux(MUX,1034) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1043) ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= vStage_uid149_lzcZ_uid51_fpSinPiTest_b; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 2, numwords_a => 4, width_b => 15, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(14 downto 0); --leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest(BITJOIN,193)@9 leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X46dto0_uid190_alignedZ_uid52_fpSinPiTest(BITSELECT,189)@4 X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(46 downto 0); X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in(46 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1031) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 47, widthad_a => 2, numwords_a => 4, width_b => 47, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(46 downto 0); --leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest(BITJOIN,190)@9 leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor(LOGICAL,1065) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q <= not (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a or ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top(CONSTANT,1061) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q <= "010"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp(LOGICAL,1062) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q <= "1" when ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a = ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b else "0"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg(REG,1063) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena(REG,1066) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q = "1") THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd(LOGICAL,1067) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a and ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt(COUNTER,1057) -- every=1, low=0, high=2, step=1, init=1 ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i = 1 THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i - 2; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i,2)); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg(REG,1058) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux(MUX,1059) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux: PROCESS (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem(DUALMEM,1056) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia <= z_uid49_fpSinPiTest_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 79, widthad_a => 2, numwords_a => 3, width_b => 79, widthad_b => 2, numwords_b => 3, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq, address_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa, data_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia ); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq(78 downto 0); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg(DELAY,1055) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q, xout => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --rVStage_uid146_lzcZ_uid51_fpSinPiTest(BITSELECT,145)@4 rVStage_uid146_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; rVStage_uid146_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_in(78 downto 15); --reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0(REG,365)@4 reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid147_lzcZ_uid51_fpSinPiTest(LOGICAL,146)@5 vCount_uid147_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid147_lzcZ_uid51_fpSinPiTest_a = vCount_uid147_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g(DELAY,629)@5 ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => vCount_uid147_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q, clk => clk, aclr => areset ); --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b(DELAY,587)@4 ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => vStage_uid149_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q, clk => clk, aclr => areset ); --mO_uid148_lzcZ_uid51_fpSinPiTest(CONSTANT,147) mO_uid148_lzcZ_uid51_fpSinPiTest_q <= "1111111111111111111111111111111111111111111111111"; --cStage_uid150_lzcZ_uid51_fpSinPiTest(BITJOIN,149)@5 cStage_uid150_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q & mO_uid148_lzcZ_uid51_fpSinPiTest_q; --ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c(DELAY,589)@4 ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 64, depth => 1 ) PORT MAP ( xin => rVStage_uid146_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid152_lzcZ_uid51_fpSinPiTest(MUX,151)@5 vStagei_uid152_lzcZ_uid51_fpSinPiTest_s <= vCount_uid147_lzcZ_uid51_fpSinPiTest_q; vStagei_uid152_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid152_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, cStage_uid150_lzcZ_uid51_fpSinPiTest_q) BEGIN CASE vStagei_uid152_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= cStage_uid150_lzcZ_uid51_fpSinPiTest_q; WHEN OTHERS => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid154_lzcZ_uid51_fpSinPiTest(BITSELECT,153)@5 rVStage_uid154_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q; rVStage_uid154_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_in(63 downto 32); --reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0(REG,366)@5 reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= "00000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid155_lzcZ_uid51_fpSinPiTest(LOGICAL,154)@6 vCount_uid155_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid155_lzcZ_uid51_fpSinPiTest_a = vCount_uid155_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f(DELAY,628)@6 ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid155_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q, clk => clk, aclr => areset ); --vStage_uid156_lzcZ_uid51_fpSinPiTest(BITSELECT,155)@5 vStage_uid156_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q(31 downto 0); vStage_uid156_lzcZ_uid51_fpSinPiTest_b <= vStage_uid156_lzcZ_uid51_fpSinPiTest_in(31 downto 0); --ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d(DELAY,596)@5 ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => vStage_uid156_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c(DELAY,595)@5 ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => rVStage_uid154_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid158_lzcZ_uid51_fpSinPiTest(MUX,157)@6 vStagei_uid158_lzcZ_uid51_fpSinPiTest_s <= vCount_uid155_lzcZ_uid51_fpSinPiTest_q; vStagei_uid158_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid158_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid158_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid160_lzcZ_uid51_fpSinPiTest(BITSELECT,159)@6 rVStage_uid160_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q; rVStage_uid160_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_in(31 downto 16); --reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0(REG,367)@6 reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid161_lzcZ_uid51_fpSinPiTest(LOGICAL,160)@7 vCount_uid161_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid161_lzcZ_uid51_fpSinPiTest_a = vCount_uid161_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e(DELAY,627)@7 ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid161_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q, clk => clk, aclr => areset ); --vStage_uid162_lzcZ_uid51_fpSinPiTest(BITSELECT,161)@6 vStage_uid162_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q(15 downto 0); vStage_uid162_lzcZ_uid51_fpSinPiTest_b <= vStage_uid162_lzcZ_uid51_fpSinPiTest_in(15 downto 0); --ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d(DELAY,602)@6 ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => vStage_uid162_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c(DELAY,601)@6 ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => rVStage_uid160_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid164_lzcZ_uid51_fpSinPiTest(MUX,163)@7 vStagei_uid164_lzcZ_uid51_fpSinPiTest_s <= vCount_uid161_lzcZ_uid51_fpSinPiTest_q; vStagei_uid164_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid164_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid164_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid166_lzcZ_uid51_fpSinPiTest(BITSELECT,165)@7 rVStage_uid166_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q; rVStage_uid166_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_in(15 downto 8); --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0(REG,368)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid167_lzcZ_uid51_fpSinPiTest(LOGICAL,166)@8 vCount_uid167_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid167_lzcZ_uid51_fpSinPiTest_a = vCount_uid167_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid168_lzcZ_uid51_fpSinPiTest(BITSELECT,167)@7 vStage_uid168_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q(7 downto 0); vStage_uid168_lzcZ_uid51_fpSinPiTest_b <= vStage_uid168_lzcZ_uid51_fpSinPiTest_in(7 downto 0); --reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3(REG,369)@7 reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= vStage_uid168_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2(REG,370)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vStagei_uid170_lzcZ_uid51_fpSinPiTest(MUX,169)@8 vStagei_uid170_lzcZ_uid51_fpSinPiTest_s <= vCount_uid167_lzcZ_uid51_fpSinPiTest_q; vStagei_uid170_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid170_lzcZ_uid51_fpSinPiTest_s, reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q, reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q) BEGIN CASE vStagei_uid170_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q; WHEN "1" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q; WHEN OTHERS => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid172_lzcZ_uid51_fpSinPiTest(BITSELECT,171)@8 rVStage_uid172_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q; rVStage_uid172_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_in(7 downto 4); --vCount_uid173_lzcZ_uid51_fpSinPiTest(LOGICAL,172)@8 vCount_uid173_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; vCount_uid173_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; vCount_uid173_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid173_lzcZ_uid51_fpSinPiTest_a = vCount_uid173_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid174_lzcZ_uid51_fpSinPiTest(BITSELECT,173)@8 vStage_uid174_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q(3 downto 0); vStage_uid174_lzcZ_uid51_fpSinPiTest_b <= vStage_uid174_lzcZ_uid51_fpSinPiTest_in(3 downto 0); --vStagei_uid176_lzcZ_uid51_fpSinPiTest(MUX,175)@8 vStagei_uid176_lzcZ_uid51_fpSinPiTest_s <= vCount_uid173_lzcZ_uid51_fpSinPiTest_q; vStagei_uid176_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid176_lzcZ_uid51_fpSinPiTest_s, rVStage_uid172_lzcZ_uid51_fpSinPiTest_b, vStage_uid174_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid176_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= vStage_uid174_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid178_lzcZ_uid51_fpSinPiTest(BITSELECT,177)@8 rVStage_uid178_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q; rVStage_uid178_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_in(3 downto 2); --vCount_uid179_lzcZ_uid51_fpSinPiTest(LOGICAL,178)@8 vCount_uid179_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; vCount_uid179_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; vCount_uid179_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid179_lzcZ_uid51_fpSinPiTest_a = vCount_uid179_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid180_lzcZ_uid51_fpSinPiTest(BITSELECT,179)@8 vStage_uid180_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q(1 downto 0); vStage_uid180_lzcZ_uid51_fpSinPiTest_b <= vStage_uid180_lzcZ_uid51_fpSinPiTest_in(1 downto 0); --vStagei_uid182_lzcZ_uid51_fpSinPiTest(MUX,181)@8 vStagei_uid182_lzcZ_uid51_fpSinPiTest_s <= vCount_uid179_lzcZ_uid51_fpSinPiTest_q; vStagei_uid182_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid182_lzcZ_uid51_fpSinPiTest_s, rVStage_uid178_lzcZ_uid51_fpSinPiTest_b, vStage_uid180_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid182_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= vStage_uid180_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid184_lzcZ_uid51_fpSinPiTest(BITSELECT,183)@8 rVStage_uid184_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid51_fpSinPiTest_q; rVStage_uid184_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_in(1 downto 1); --vCount_uid185_lzcZ_uid51_fpSinPiTest(LOGICAL,184)@8 vCount_uid185_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_b; vCount_uid185_lzcZ_uid51_fpSinPiTest_b <= GND_q; vCount_uid185_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid185_lzcZ_uid51_fpSinPiTest_a = vCount_uid185_lzcZ_uid51_fpSinPiTest_b else "0"; --r_uid186_lzcZ_uid51_fpSinPiTest(BITJOIN,185)@8 r_uid186_lzcZ_uid51_fpSinPiTest_q <= ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q & ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q & ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q & vCount_uid167_lzcZ_uid51_fpSinPiTest_q & vCount_uid173_lzcZ_uid51_fpSinPiTest_q & vCount_uid179_lzcZ_uid51_fpSinPiTest_q & vCount_uid185_lzcZ_uid51_fpSinPiTest_q; --leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest(BITSELECT,195)@8 leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q; leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in(6 downto 5); --reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1(REG,371)@8 reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest(MUX,196)@9 leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q, leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q; WHEN "01" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ozz_uid41_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest(BITSELECT,206)@8 leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(4 downto 0); leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in(4 downto 3); --reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1(REG,372)@8 reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest(MUX,207)@9 leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s, leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest(BITSELECT,215)@9 LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(72 downto 0); LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in(72 downto 0); --leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest(BITJOIN,216)@9 leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5(REG,374)@9 reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest(BITSELECT,212)@9 LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest(BITJOIN,213)@9 leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4(REG,375)@9 reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest(BITSELECT,209)@9 LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest(BITJOIN,210)@9 leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3(REG,376)@9 reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2(REG,377)@9 reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest(BITSELECT,217)@8 leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(2 downto 0); leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in(2 downto 1); --reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1(REG,373)@8 reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b(DELAY,657)@9 ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest(MUX,218)@10 leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s, reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q, reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q, reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q, reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q) BEGIN CASE leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q; WHEN "01" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q; WHEN "10" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q; WHEN "11" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q; WHEN OTHERS => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest(BITSELECT,222)@8 leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(0 downto 0); leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in(0 downto 0); --reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1(REG,378)@8 reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b(DELAY,665)@9 ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest(MUX,223)@10 leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s, leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q, leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q; WHEN "1" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --alignedZLow_uid53_fpSinPiTest(BITSELECT,52)@10 alignedZLow_uid53_fpSinPiTest_in <= leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q; alignedZLow_uid53_fpSinPiTest_b <= alignedZLow_uid53_fpSinPiTest_in(78 downto 27); --pHardCase_uid54_fpSinPiTest(BITJOIN,53)@10 pHardCase_uid54_fpSinPiTest_q <= alignedZLow_uid53_fpSinPiTest_b & GND_q; --ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b(DELAY,474)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 10 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q, clk => clk, aclr => areset ); --p_uid55_fpSinPiTest(MUX,54)@10 p_uid55_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q; p_uid55_fpSinPiTest: PROCESS (p_uid55_fpSinPiTest_s, pHardCase_uid54_fpSinPiTest_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q) BEGIN CASE p_uid55_fpSinPiTest_s IS WHEN "0" => p_uid55_fpSinPiTest_q <= pHardCase_uid54_fpSinPiTest_q; WHEN "1" => p_uid55_fpSinPiTest_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q; WHEN OTHERS => p_uid55_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt(COUNTER,1121) -- every=1, low=0, high=22, step=1, init=1 ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i = 21 THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i - 22; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i,5)); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg(REG,1122) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux(MUX,1123) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux: PROCESS (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q) BEGIN CASE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s IS WHEN "0" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; WHEN "1" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem(DUALMEM,1120) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 <= areset; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia <= p_uid55_fpSinPiTest_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 5, numwords_a => 23, width_b => 53, widthad_b => 5, numwords_b => 23, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq, address_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa, data_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia ); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq(52 downto 0); --mul2xSinRes_uid69_fpSinPiTest_a_1(BITSELECT,316)@34 mul2xSinRes_uid69_fpSinPiTest_a_1_in <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q); mul2xSinRes_uid69_fpSinPiTest_a_1_b <= mul2xSinRes_uid69_fpSinPiTest_a_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0(REG,424)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b1(MULT,322)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_b); mul2xSinRes_uid69_fpSinPiTest_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1(BITSELECT,329)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1(REG,425)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a_0(BITSELECT,315)@34 mul2xSinRes_uid69_fpSinPiTest_a_0_in <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_a_0_b <= mul2xSinRes_uid69_fpSinPiTest_a_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0(REG,426)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b1(MULT,321)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_b); mul2xSinRes_uid69_fpSinPiTest_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1(BITSELECT,327)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_zero_36(CONSTANT,332) mul2xSinRes_uid69_fpSinPiTest_zero_36_q <= "000000000000000000000000000"; --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2(BITJOIN,336)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1(BITSELECT,328)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_b_0(BITSELECT,317)@34 mul2xSinRes_uid69_fpSinPiTest_b_0_in <= multRightOp_uid68_fpSinPiTest_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_b_0_b <= mul2xSinRes_uid69_fpSinPiTest_b_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1(REG,421)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0(REG,422)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b0(MULT,320)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_b); mul2xSinRes_uid69_fpSinPiTest_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0(BITSELECT,325)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1(BITJOIN,335)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC(LOGICAL,340)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b; --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1(BITSELECT,330)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0(BITSELECT,326)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1(REG,419)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0(REG,420)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b0(MULT,319)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_b); mul2xSinRes_uid69_fpSinPiTest_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0(BITSELECT,324)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0(BITSELECT,323)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0(BITJOIN,334)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC(LOGICAL,339)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB(LOGICAL,338)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne(LOGICAL,341)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c; --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS(BITSELECT,342)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q(106 downto 0); mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in(106 downto 0); --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ(BITJOIN,343)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b & GND_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b(BITJOIN,350)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b(BITSELECT,353)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne(LOGICAL,337)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a(BITJOIN,348)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a(BITSELECT,352)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2(ADD,354)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin <= GND_q; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b) & mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c(0) <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(90); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(89 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b(DELAY,822)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q, clk => clk, aclr => areset ); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a(DELAY,821)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2(ADD,355)@39 mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q) & mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o(20 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a(DELAY,824)@39 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a : dspba_delay GENERIC MAP ( width => 89, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q(BITJOIN,356)@40 mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q; --normBit_uid70_fpSinPiTest(BITSELECT,69)@40 normBit_uid70_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(106 downto 0); normBit_uid70_fpSinPiTest_b <= normBit_uid70_fpSinPiTest_in(106 downto 106); --ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c(DELAY,497)@40 ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => normBit_uid70_fpSinPiTest_b, xout => ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q, clk => clk, aclr => areset ); --rndExpUpdate_uid75_uid76_fpSinPiTest(BITJOIN,75)@41 rndExpUpdate_uid75_uid76_fpSinPiTest_q <= ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q & cstAllZWF_uid10_fpSinPiTest_q & VCC_q; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor(LOGICAL,976) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q <= not (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a or ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top(CONSTANT,972) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q <= "011100"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp(LOGICAL,973) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a = ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b else "0"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg(REG,974) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena(REG,977) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q = "1") THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd(LOGICAL,978) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a and ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem(DUALMEM,941) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 <= areset; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia <= expX_uid6_fpSinPiTest_b; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 3, numwords_a => 7, width_b => 11, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq, address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa, data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia ); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq(10 downto 0); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg(DELAY,940) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q, clk => clk, aclr => areset ); --expXP1_uid58_fpSinPiTest(ADD,57)@9 expXP1_uid58_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q); expXP1_uid58_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & VCC_q); expXP1_uid58_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid58_fpSinPiTest_a) + UNSIGNED(expXP1_uid58_fpSinPiTest_b)); expXP1_uid58_fpSinPiTest_q <= expXP1_uid58_fpSinPiTest_o(11 downto 0); --expXP1R_uid59_fpSinPiTest(BITSELECT,58)@9 expXP1R_uid59_fpSinPiTest_in <= expXP1_uid58_fpSinPiTest_q(10 downto 0); expXP1R_uid59_fpSinPiTest_b <= expXP1R_uid59_fpSinPiTest_in(10 downto 0); --reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1(REG,427)@8 reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= r_uid186_lzcZ_uid51_fpSinPiTest_q; END IF; END PROCESS; --expHardCase_uid57_fpSinPiTest(SUB,56)@9 expHardCase_uid57_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid27_fpSinPiTest_q); expHardCase_uid57_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000" & reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q); expHardCase_uid57_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid57_fpSinPiTest_a) - UNSIGNED(expHardCase_uid57_fpSinPiTest_b)); expHardCase_uid57_fpSinPiTest_q <= expHardCase_uid57_fpSinPiTest_o(11 downto 0); --expHardCaseR_uid60_fpSinPiTest(BITSELECT,59)@9 expHardCaseR_uid60_fpSinPiTest_in <= expHardCase_uid57_fpSinPiTest_q(10 downto 0); expHardCaseR_uid60_fpSinPiTest_b <= expHardCaseR_uid60_fpSinPiTest_in(10 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b(DELAY,481)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 9 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q, clk => clk, aclr => areset ); --expP_uid61_fpSinPiTest(MUX,60)@9 expP_uid61_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q; expP_uid61_fpSinPiTest: PROCESS (expP_uid61_fpSinPiTest_s, expHardCaseR_uid60_fpSinPiTest_b, expXP1R_uid59_fpSinPiTest_b) BEGIN CASE expP_uid61_fpSinPiTest_s IS WHEN "0" => expP_uid61_fpSinPiTest_q <= expHardCaseR_uid60_fpSinPiTest_b; WHEN "1" => expP_uid61_fpSinPiTest_q <= expXP1R_uid59_fpSinPiTest_b; WHEN OTHERS => expP_uid61_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt(COUNTER,968) -- every=1, low=0, high=28, step=1, init=1 ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i = 27 THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i - 28; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg(REG,969) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux(MUX,970) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem(DUALMEM,967) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia <= expP_uid61_fpSinPiTest_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 29, width_b => 11, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq, address_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa, data_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia ); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq(10 downto 0); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg(DELAY,966) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q, xout => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --highRes_uid71_fpSinPiTest(BITSELECT,70)@40 highRes_uid71_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(105 downto 0); highRes_uid71_fpSinPiTest_b <= highRes_uid71_fpSinPiTest_in(105 downto 53); --lowRes_uid72_fpSinPiTest(BITSELECT,71)@40 lowRes_uid72_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(104 downto 0); lowRes_uid72_fpSinPiTest_b <= lowRes_uid72_fpSinPiTest_in(104 downto 52); --fracRCompPreRnd_uid73_fpSinPiTest(MUX,72)@40 fracRCompPreRnd_uid73_fpSinPiTest_s <= normBit_uid70_fpSinPiTest_b; fracRCompPreRnd_uid73_fpSinPiTest: PROCESS (fracRCompPreRnd_uid73_fpSinPiTest_s, lowRes_uid72_fpSinPiTest_b, highRes_uid71_fpSinPiTest_b) BEGIN CASE fracRCompPreRnd_uid73_fpSinPiTest_s IS WHEN "0" => fracRCompPreRnd_uid73_fpSinPiTest_q <= lowRes_uid72_fpSinPiTest_b; WHEN "1" => fracRCompPreRnd_uid73_fpSinPiTest_q <= highRes_uid71_fpSinPiTest_b; WHEN OTHERS => fracRCompPreRnd_uid73_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracPreRnd_uid74_uid74_fpSinPiTest(BITJOIN,73)@40 expFracPreRnd_uid74_uid74_fpSinPiTest_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q & fracRCompPreRnd_uid73_fpSinPiTest_q; --reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0(REG,428)@40 reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= expFracPreRnd_uid74_uid74_fpSinPiTest_q; END IF; END PROCESS; --expFracComp_uid77_fpSinPiTest(ADD,76)@41 expFracComp_uid77_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q); expFracComp_uid77_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & rndExpUpdate_uid75_uid76_fpSinPiTest_q); expFracComp_uid77_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid77_fpSinPiTest_a) + UNSIGNED(expFracComp_uid77_fpSinPiTest_b)); expFracComp_uid77_fpSinPiTest_q <= expFracComp_uid77_fpSinPiTest_o(64 downto 0); --expRComp_uid79_fpSinPiTest(BITSELECT,78)@41 expRComp_uid79_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(63 downto 0); expRComp_uid79_fpSinPiTest_b <= expRComp_uid79_fpSinPiTest_in(63 downto 53); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor(LOGICAL,1015) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q <= not (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a or ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top(CONSTANT,1011) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q <= "0100010"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp(LOGICAL,1012) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q <= "1" when ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a = ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b else "0"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg(REG,1013) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena(REG,1016) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q = "1") THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd(LOGICAL,1017) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a and ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b; --reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1(REG,429)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c(DELAY,516)@0 ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q, xout => ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b(DELAY,515)@0 ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => expXIsZero_uid15_fpSinPiTest_q, xout => ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q, clk => clk, aclr => areset ); --reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0(REG,361)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --excRZero_uid87_fpSinPiTest(LOGICAL,86)@3 excRZero_uid87_fpSinPiTest_a <= reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q; excRZero_uid87_fpSinPiTest_b <= ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q; excRZero_uid87_fpSinPiTest_c <= ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q; excRZero_uid87_fpSinPiTest_q <= excRZero_uid87_fpSinPiTest_a or excRZero_uid87_fpSinPiTest_b or excRZero_uid87_fpSinPiTest_c; --Or2ExcRZeroXIsInt_uid92_fpSinPiTest(LOGICAL,91)@3 Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a <= excRZero_uid87_fpSinPiTest_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b <= reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a or Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt(COUNTER,1007) -- every=1, low=0, high=34, step=1, init=1 ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i = 33 THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i - 34; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg(REG,1008) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux(MUX,1009) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux: PROCESS (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem(DUALMEM,1006) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 35, width_b => 1, widthad_b => 6, numwords_b => 35, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq, address_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa, data_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia ); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg(DELAY,1005) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q, xout => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --expRPostExc1_uid95_fpSinPiTest(MUX,94)@41 expRPostExc1_uid95_fpSinPiTest_s <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q; expRPostExc1_uid95_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE expRPostExc1_uid95_fpSinPiTest_s IS WHEN "0" => expRPostExc1_uid95_fpSinPiTest_q <= expRComp_uid79_fpSinPiTest_b; WHEN "1" => expRPostExc1_uid95_fpSinPiTest_q <= cstAllZWE_uid11_fpSinPiTest_q; WHEN OTHERS => expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --InvXIntExp_uid84_fpSinPiTest(LOGICAL,83)@2 InvXIntExp_uid84_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; InvXIntExp_uid84_fpSinPiTest_q <= not InvXIntExp_uid84_fpSinPiTest_a; --join_uid42_fpSinPiTest(BITJOIN,41)@2 join_uid42_fpSinPiTest_q <= VCC_q & ozz_uid41_fpSinPiTest_q; --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0(REG,359)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid43_fpSinPiTest(LOGICAL,42)@2 yIsZero_uid43_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q; yIsZero_uid43_fpSinPiTest_b <= join_uid42_fpSinPiTest_q; yIsZero_uid43_fpSinPiTest_q <= "1" when yIsZero_uid43_fpSinPiTest_a = yIsZero_uid43_fpSinPiTest_b else "0"; --And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest(LOGICAL,85)@2 And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b <= yIsZero_uid43_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c <= InvSinXIsX_uid80_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d <= InvXIntExp_uid84_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d; --Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest(LOGICAL,95)@1 Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a <= GND_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q <= Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a or Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b; --ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a(DELAY,528)@1 ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q, xout => ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q, clk => clk, aclr => areset ); --join_uid97_fpSinPiTest(BITJOIN,96)@2 join_uid97_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q & ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q; --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg(DELAY,1195) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => join_uid97_fpSinPiTest_q, xout => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q, clk => clk, aclr => areset ); --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem(DUALMEM,1196) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 <= areset; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 6, numwords_a => 37, width_b => 2, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0, clock1 => clk, address_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq, address_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa, data_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia ); ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq(1 downto 0); --reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1(REG,430)@41 reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q; END IF; END PROCESS; --expRPostExc_uid98_fpSinPiTest(MUX,97)@42 expRPostExc_uid98_fpSinPiTest_s <= reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q; expRPostExc_uid98_fpSinPiTest: PROCESS (expRPostExc_uid98_fpSinPiTest_s, expRPostExc1_uid95_fpSinPiTest_q) BEGIN CASE expRPostExc_uid98_fpSinPiTest_s IS WHEN "00" => expRPostExc_uid98_fpSinPiTest_q <= expRPostExc1_uid95_fpSinPiTest_q; WHEN "01" => expRPostExc_uid98_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q; WHEN "10" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN "11" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN OTHERS => expRPostExc_uid98_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --oneFracRPostExc2_uid90_fpSinPiTest(CONSTANT,89) oneFracRPostExc2_uid90_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracRComp_uid78_fpSinPiTest(BITSELECT,77)@41 fracRComp_uid78_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(52 downto 0); fracRComp_uid78_fpSinPiTest_b <= fracRComp_uid78_fpSinPiTest_in(52 downto 1); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor(LOGICAL,989) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q <= not (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a or ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top(CONSTANT,985) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q <= "0100001"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp(LOGICAL,986) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q <= "1" when ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a = ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b else "0"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg(REG,987) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena(REG,990) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q = "1") THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd(LOGICAL,991) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a and ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b; --reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1(REG,362)@3 reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= excRZero_uid87_fpSinPiTest_q; END IF; END PROCESS; --ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a(DELAY,517)@2 ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q, xout => ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q, clk => clk, aclr => areset ); --or_uid88_fpSinPiTest(LOGICAL,87)@4 or_uid88_fpSinPiTest_a <= ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q; or_uid88_fpSinPiTest_b <= reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q; or_uid88_fpSinPiTest_c <= GND_q; or_uid88_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN or_uid88_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN or_uid88_fpSinPiTest_q <= or_uid88_fpSinPiTest_a or or_uid88_fpSinPiTest_b or or_uid88_fpSinPiTest_c; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt(COUNTER,981) -- every=1, low=0, high=33, step=1, init=1 ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i = 32 THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i - 33; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg(REG,982) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux(MUX,983) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux: PROCESS (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem(DUALMEM,980) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia <= or_uid88_fpSinPiTest_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 34, width_b => 1, widthad_b => 6, numwords_b => 34, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq, address_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa, data_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia ); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg(DELAY,979) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q, xout => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --fracRPostExc1_uid89_fpSinPiTest(MUX,88)@41 fracRPostExc1_uid89_fpSinPiTest_s <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q; fracRPostExc1_uid89_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE fracRPostExc1_uid89_fpSinPiTest_s IS WHEN "0" => fracRPostExc1_uid89_fpSinPiTest_q <= fracRComp_uid78_fpSinPiTest_b; WHEN "1" => fracRPostExc1_uid89_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q; WHEN OTHERS => fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor(LOGICAL,1002) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q <= not (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a or ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top(CONSTANT,998) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q <= "0100110"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp(LOGICAL,999) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q <= "1" when ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a = ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b else "0"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg(REG,1000) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena(REG,1003) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q = "1") THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd(LOGICAL,1004) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a and ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg(DELAY,992) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q, xout => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q, clk => clk, aclr => areset ); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt(COUNTER,994) -- every=1, low=0, high=38, step=1, init=1 ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i = 37 THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i - 38; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg(REG,995) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux(MUX,996) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux: PROCESS (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem(DUALMEM,993) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 39, width_b => 1, widthad_b => 6, numwords_b => 39, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq, address_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa, data_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia ); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq(0 downto 0); --fracRPostExc_uid91_fpSinPiTest(MUX,90)@42 fracRPostExc_uid91_fpSinPiTest_s <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q; fracRPostExc_uid91_fpSinPiTest: PROCESS (fracRPostExc_uid91_fpSinPiTest_s, fracRPostExc1_uid89_fpSinPiTest_q) BEGIN CASE fracRPostExc_uid91_fpSinPiTest_s IS WHEN "0" => fracRPostExc_uid91_fpSinPiTest_q <= fracRPostExc1_uid89_fpSinPiTest_q; WHEN "1" => fracRPostExc_uid91_fpSinPiTest_q <= oneFracRPostExc2_uid90_fpSinPiTest_q; WHEN OTHERS => fracRPostExc_uid91_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid105_fpSinPiTest(BITJOIN,104)@42 R_uid105_fpSinPiTest_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q & expRPostExc_uid98_fpSinPiTest_q & fracRPostExc_uid91_fpSinPiTest_q; --ld_xIn_v_to_xOut_v_nor(LOGICAL,910) ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b); --ld_xIn_v_to_xOut_v_mem_top(CONSTANT,906) ld_xIn_v_to_xOut_v_mem_top_q <= "0100111"; --ld_xIn_v_to_xOut_v_cmp(LOGICAL,907) ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q; ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q); ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0"; --ld_xIn_v_to_xOut_v_cmpReg(REG,908) ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_sticky_ena(REG,911) ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q; END IF; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,912) ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q; ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b; --ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,902) -- every=1, low=0, high=39, step=1, init=1 ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 38 THEN ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1'; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; END IF; IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 39; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,6)); --ld_xIn_v_to_xOut_v_replace_rdreg(REG,903) ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_replace_rdmux(MUX,904) ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q; ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q) BEGIN CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q; WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,914) ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset; ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c; ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 6, numwords_a => 40, width_b => 8, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_c_to_xOut_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_c_to_xOut_c_replace_mem_iq, address_a => ld_xIn_c_to_xOut_c_replace_mem_aa, data_a => ld_xIn_c_to_xOut_c_replace_mem_ia ); ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0); --ld_xIn_c_to_xOut_c_outputreg(DELAY,913) ld_xIn_c_to_xOut_c_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset ); --ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,901) ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset; ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v; ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 40, width_b => 1, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_v_to_xOut_v_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_v_to_xOut_v_replace_mem_iq, address_a => ld_xIn_v_to_xOut_v_replace_mem_aa, data_a => ld_xIn_v_to_xOut_v_replace_mem_ia ); ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0); --ld_xIn_v_to_xOut_v_outputreg(DELAY,900) ld_xIn_v_to_xOut_v_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset ); --xOut(PORTOUT,4)@42 xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q; xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q; xOut_0 <= R_uid105_fpSinPiTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Debug Version 12.0 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from SinPiDPStratixVf400 -- VHDL created on Wed Sep 05 17:55:57 2012 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; USE work.SinPiDPStratixVf400_safe_path.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; -- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240 entity SinPiDPStratixVf400 is port ( xIn_v : in std_logic_vector(0 downto 0); xIn_c : in std_logic_vector(7 downto 0); xIn_0 : in std_logic_vector(63 downto 0); xOut_v : out std_logic_vector(0 downto 0); xOut_c : out std_logic_vector(7 downto 0); xOut_0 : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic; bus_clk : in std_logic; h_areset : in std_logic ); end; architecture normal of SinPiDPStratixVf400 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBias_uid12_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBiasPwF_uid13_fpSinPiTest_q : std_logic_vector (10 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0); signal biasM1_uid27_fpSinPiTest_q : std_logic_vector (10 downto 0); signal biasMwShift_uid29_fpSinPiTest_q : std_logic_vector (10 downto 0); signal shiftBias_uid32_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cst01pWShift_uid34_fpSinPiTest_q : std_logic_vector (27 downto 0); signal ozz_uid41_fpSinPiTest_q : std_logic_vector (78 downto 0); signal cOne_uid44_fpSinPiTest_q : std_logic_vector (80 downto 0); signal oneMinusY_uid45_fpSinPiTest_a : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_b : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_o : std_logic_vector (81 downto 0); signal oneMinusY_uid45_fpSinPiTest_q : std_logic_vector (81 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_a : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_b : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_o : std_logic_vector (84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_c : std_logic_vector (0 downto 0); signal piwFP2_uid67_fpSinPiTest_q : std_logic_vector (53 downto 0); signal or_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_b : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_c : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_q : std_logic_vector (51 downto 0); signal oneFracRPostExc2_uid90_fpSinPiTest_q : std_logic_vector (51 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (10 downto 0); signal InvXIsInt_uid100_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIsInt_uid100_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (31 downto 0); signal leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (63 downto 0); signal leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (15 downto 0); signal leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (23 downto 0); signal leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (5 downto 0); signal mO_uid148_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (48 downto 0); signal memoryC3_uid229_sinPiZTableGenerator_q : std_logic_vector(34 downto 0); signal memoryC4_uid230_sinPiZTableGenerator_q : std_logic_vector(25 downto 0); signal memoryC5_uid231_sinPiZTableGenerator_q : std_logic_vector(16 downto 0); signal rndBit_uid246_sinPiZPolyEval_q : std_logic_vector (1 downto 0); signal rndBit_uid258_sinPiZPolyEval_q : std_logic_vector (2 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_a : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 : std_logic_vector (33 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr : SIGNED (34 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_q : std_logic_vector (33 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_a : std_logic_vector (25 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_zero_36_q : std_logic_vector (26 downto 0); type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type; signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q : std_logic_vector (36 downto 0); type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o : std_logic_vector (90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o : std_logic_vector (21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q : std_logic_vector (19 downto 0); signal reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q : std_logic_vector (80 downto 0); signal reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q : std_logic_vector (80 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q : std_logic_vector (0 downto 0); signal reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (31 downto 0); signal reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (15 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (7 downto 0); signal reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q : std_logic_vector (7 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q : std_logic_vector (7 downto 0); signal reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q : std_logic_vector (78 downto 0); signal reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q : std_logic_vector (16 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q : std_logic_vector (25 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q : std_logic_vector (16 downto 0); signal reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q : std_logic_vector (17 downto 0); signal reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q : std_logic_vector (36 downto 0); signal reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q : std_logic_vector (44 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q : std_logic_vector (45 downto 0); signal reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q : std_logic_vector (51 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q : std_logic_vector (53 downto 0); signal reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q : std_logic_vector (60 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q : std_logic_vector (26 downto 0); signal reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q : std_logic_vector (6 downto 0); signal reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q : std_logic_vector (78 downto 0); signal ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q : std_logic_vector (78 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q : std_logic_vector (78 downto 0); signal ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q : std_logic_vector (14 downto 0); signal ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (63 downto 0); signal ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (31 downto 0); signal ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (31 downto 0); signal ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (15 downto 0); signal ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (15 downto 0); signal ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q : std_logic_vector (0 downto 0); signal ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q : std_logic_vector (0 downto 0); signal ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (1 downto 0); signal ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (42 downto 0); signal ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q : std_logic_vector (88 downto 0); signal ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q : std_logic_vector (79 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic; signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic; signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic; signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 : std_logic; signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i : unsigned(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q : std_logic_vector (3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i : unsigned(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q : std_logic_vector (6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i : unsigned(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q : std_logic_vector (2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (14 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ir : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i : unsigned(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q : std_logic_vector (2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ir : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ir : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 : std_logic; signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ir : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0); signal yIsZero_uid40_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (18 downto 0); signal pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal z_uid49_fpSinPiTest_s : std_logic_vector (0 downto 0); signal z_uid49_fpSinPiTest_q : std_logic_vector (78 downto 0); signal expHardCase_uid57_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expHardCase_uid57_fpSinPiTest_q : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_q : std_logic_vector (11 downto 0); signal rndExpUpdate_uid75_uid76_fpSinPiTest_q : std_logic_vector (53 downto 0); signal expFracComp_uid77_fpSinPiTest_a : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_b : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_o : std_logic_vector (64 downto 0); signal expFracComp_uid77_fpSinPiTest_q : std_logic_vector (64 downto 0); signal fracRPostExc_uid91_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc_uid91_fpSinPiTest_q : std_logic_vector (51 downto 0); signal expRPostExc_uid98_fpSinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid98_fpSinPiTest_q : std_logic_vector (10 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal memoryC0_uid226_sinPiZTableGenerator_q : std_logic_vector(57 downto 0); signal memoryC1_uid227_sinPiZTableGenerator_q : std_logic_vector(49 downto 0); signal memoryC2_uid228_sinPiZTableGenerator_q : std_logic_vector(42 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_a : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_b : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_o : std_logic_vector (35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_q : std_logic_vector (35 downto 0); signal ts3_uid248_sinPiZPolyEval_a : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_b : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_o : std_logic_vector (45 downto 0); signal ts3_uid248_sinPiZPolyEval_q : std_logic_vector (45 downto 0); signal ts4_uid254_sinPiZPolyEval_a : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_b : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_o : std_logic_vector (52 downto 0); signal ts4_uid254_sinPiZPolyEval_q : std_logic_vector (52 downto 0); signal ts5_uid260_sinPiZPolyEval_a : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_b : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_o : std_logic_vector (61 downto 0); signal ts5_uid260_sinPiZPolyEval_q : std_logic_vector (61 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal join_uid42_fpSinPiTest_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal expX_uid6_fpSinPiTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSinPiTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSinPiTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSinPiTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0); signal expXIsMax_uid16_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSinPiTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid15_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_q : std_logic_vector(0 downto 0); signal xIntExp_uid26_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xIntExp_uid26_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xIntExp_uid26_fpSinPiTest_c : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xFrac_uid28_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_n : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_a : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_b : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_o : std_logic_vector (13 downto 0); signal sinXIsX_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0); signal shiftValue_uid33_fpSinPiTest_a : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_b : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_o : std_logic_vector (11 downto 0); signal shiftValue_uid33_fpSinPiTest_q : std_logic_vector (11 downto 0); signal oMyBottom_uid47_fpSinPiTest_in : std_logic_vector (78 downto 0); signal oMyBottom_uid47_fpSinPiTest_b : std_logic_vector (78 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid150_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal cIncludingRoundingBit_uid247_sinPiZPolyEval_q : std_logic_vector (44 downto 0); signal cIncludingRoundingBit_uid253_sinPiZPolyEval_q : std_logic_vector (51 downto 0); signal cIncludingRoundingBit_uid259_sinPiZPolyEval_q : std_logic_vector (60 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q : std_logic_vector (107 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (29 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (46 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q : std_logic_vector (108 downto 0); signal yIsZero_uid43_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zPPolyEval_uid64_fpSinPiTest_in : std_logic_vector (71 downto 0); signal zPPolyEval_uid64_fpSinPiTest_b : std_logic_vector (44 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_q : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_c : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (31 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (15 downto 0); signal s2_uid240_uid243_sinPiZPolyEval_q : std_logic_vector (36 downto 0); signal add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (55 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (42 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (72 downto 0); signal add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal R_uid105_fpSinPiTest_q : std_logic_vector (63 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal yT3_uid244_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT3_uid244_sinPiZPolyEval_b : std_logic_vector (34 downto 0); signal yT4_uid250_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT4_uid250_sinPiZPolyEval_b : std_logic_vector (42 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q : std_logic_vector(0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_b : std_logic_vector (26 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zAddr_uid63_fpSinPiTest_in : std_logic_vector (78 downto 0); signal zAddr_uid63_fpSinPiTest_b : std_logic_vector (6 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (78 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (63 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (14 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (14 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (46 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (46 downto 0); signal expHardCaseR_uid60_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expHardCaseR_uid60_fpSinPiTest_b : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracRComp_uid78_fpSinPiTest_in : std_logic_vector (52 downto 0); signal fracRComp_uid78_fpSinPiTest_b : std_logic_vector (51 downto 0); signal expRComp_uid79_fpSinPiTest_in : std_logic_vector (63 downto 0); signal expRComp_uid79_fpSinPiTest_b : std_logic_vector (10 downto 0); signal intXParity_uid38_fpSinPiTest_in : std_logic_vector (80 downto 0); signal intXParity_uid38_fpSinPiTest_b : std_logic_vector (0 downto 0); signal y_uid39_fpSinPiTest_in : std_logic_vector (79 downto 0); signal y_uid39_fpSinPiTest_b : std_logic_vector (79 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (77 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (77 downto 0); signal s3_uid249_sinPiZPolyEval_in : std_logic_vector (45 downto 0); signal s3_uid249_sinPiZPolyEval_b : std_logic_vector (44 downto 0); signal s4_uid255_sinPiZPolyEval_in : std_logic_vector (52 downto 0); signal s4_uid255_sinPiZPolyEval_b : std_logic_vector (51 downto 0); signal s5_uid261_sinPiZPolyEval_in : std_logic_vector (61 downto 0); signal s5_uid261_sinPiZPolyEval_b : std_logic_vector (60 downto 0); signal oFracX_uid31_uid31_fpSinPiTest_q : std_logic_vector (52 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_in : std_logic_vector (6 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_b : std_logic_vector (6 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid235_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal highBBits_uid235_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid241_sinPiZPolyEval_in : std_logic_vector (28 downto 0); signal highBBits_uid241_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q : std_logic_vector(107 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (29 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (46 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal normBit_uid70_fpSinPiTest_in : std_logic_vector (106 downto 0); signal normBit_uid70_fpSinPiTest_b : std_logic_vector (0 downto 0); signal highRes_uid71_fpSinPiTest_in : std_logic_vector (105 downto 0); signal highRes_uid71_fpSinPiTest_b : std_logic_vector (52 downto 0); signal lowRes_uid72_fpSinPiTest_in : std_logic_vector (104 downto 0); signal lowRes_uid72_fpSinPiTest_b : std_logic_vector (52 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (70 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (70 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (62 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (62 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (54 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (54 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q : std_logic_vector(0 downto 0); signal yT1_uid232_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT1_uid232_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal yT2_uid238_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT2_uid238_sinPiZPolyEval_b : std_logic_vector (25 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (63 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (9 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (9 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (36 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (71 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (45 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (78 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (7 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (7 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (15 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (15 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expP_uid61_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expP_uid61_fpSinPiTest_q : std_logic_vector (10 downto 0); signal yBottom_uid48_fpSinPiTest_in : std_logic_vector (78 downto 0); signal yBottom_uid48_fpSinPiTest_b : std_logic_vector (78 downto 0); signal leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (51 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal fxpSinRes_uid66_fpSinPiTest_in : std_logic_vector (58 downto 0); signal fxpSinRes_uid66_fpSinPiTest_b : std_logic_vector (53 downto 0); signal extendedFracX_uid35_fpSinPiTest_q : std_logic_vector (80 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (0 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_a : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_b : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_o : std_logic_vector (26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q : std_logic_vector(107 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_q : std_logic_vector (52 downto 0); signal join_uid97_fpSinPiTest_q : std_logic_vector (1 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal signR_uid104_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (10 downto 0); signal pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (16 downto 0); signal pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal xIsInt_uid83_fpSinPiTest_a : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_b : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal multRightOp_uid68_fpSinPiTest_s : std_logic_vector (0 downto 0); signal multRightOp_uid68_fpSinPiTest_q : std_logic_vector (53 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (48 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (48 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (16 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (16 downto 0); signal s1_uid234_uid237_sinPiZPolyEval_q : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c : std_logic_vector (19 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in : std_logic_vector (106 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b : std_logic_vector (106 downto 0); signal expFracPreRnd_uid74_uid74_fpSinPiTest_q : std_logic_vector (63 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (17 downto 0); signal alignedZLow_uid53_fpSinPiTest_in : std_logic_vector (78 downto 0); signal alignedZLow_uid53_fpSinPiTest_b : std_logic_vector (51 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_b : std_logic_vector (26 downto 0); signal leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q : std_logic_vector (107 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (1 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (74 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (72 downto 0); signal pHardCase_uid54_fpSinPiTest_q : std_logic_vector (52 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q : std_logic_vector (108 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (0 downto 0); signal leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal p_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0); signal p_uid55_fpSinPiTest_q : std_logic_vector (52 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (72 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (64 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (64 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (56 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (56 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c : std_logic_vector (19 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal r_uid186_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (6 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (0 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (78 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (78 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (74 downto 0); signal leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (79 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (79 downto 0); signal leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); begin --ld_xIn_v_to_xOut_v_notEnable(LOGICAL,909) ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q; ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor(LOGICAL,1028) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q <= not (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a or ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top(CONSTANT,1024) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q <= "0100100"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp(LOGICAL,1025) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q <= "1" when ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a = ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b else "0"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg(REG,1026) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena(REG,1029) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q = "1") THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd(LOGICAL,1030) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a and ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b; --LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest(BITSELECT,134)@0 LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest(CONSTANT,133) leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q <= "000000"; --leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest(BITJOIN,135)@0 leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest(BITSELECT,131)@0 LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest(CONSTANT,130) leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q <= "0000"; --leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest(BITJOIN,132)@0 leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest(BITSELECT,128)@0 LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(78 downto 0); LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in(78 downto 0); --leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest(CONSTANT,127) leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q <= "00"; --leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest(BITJOIN,129)@0 leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest(BITSELECT,123)@0 LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(56 downto 0); LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in(56 downto 0); --leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest(CONSTANT,122) leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000"; --leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest(BITJOIN,124)@0 leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest(BITSELECT,120)@0 LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(64 downto 0); LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in(64 downto 0); --leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest(CONSTANT,119) leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000"; --leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest(BITJOIN,121)@0 leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest(BITSELECT,117)@0 LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(72 downto 0); LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in(72 downto 0); --leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest(CONSTANT,116) leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q <= "00000000"; --leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest(BITJOIN,118)@0 leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest(CONSTANT,113) leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; --X16dto0_uid112_fixedPointX_uid37_fpSinPiTest(BITSELECT,111)@0 X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(16 downto 0); X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in(16 downto 0); --leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest(CONSTANT,110) leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000"; --leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest(BITJOIN,112)@0 leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X48dto0_uid109_fixedPointX_uid37_fpSinPiTest(BITSELECT,108)@0 X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(48 downto 0); X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in(48 downto 0); --leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest(CONSTANT,107) leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q <= "00000000000000000000000000000000"; --leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest(BITJOIN,109)@0 leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --cst01pWShift_uid34_fpSinPiTest(CONSTANT,33) cst01pWShift_uid34_fpSinPiTest_q <= "0000000000000000000000000000"; --xIn(PORTIN,3)@0 --fracX_uid7_fpSinPiTest(BITSELECT,6)@0 fracX_uid7_fpSinPiTest_in <= xIn_0(51 downto 0); fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(51 downto 0); --oFracX_uid31_uid31_fpSinPiTest(BITJOIN,30)@0 oFracX_uid31_uid31_fpSinPiTest_q <= VCC_q & fracX_uid7_fpSinPiTest_b; --extendedFracX_uid35_fpSinPiTest(BITJOIN,34)@0 extendedFracX_uid35_fpSinPiTest_q <= cst01pWShift_uid34_fpSinPiTest_q & oFracX_uid31_uid31_fpSinPiTest_q; --shiftBias_uid32_fpSinPiTest(CONSTANT,31) shiftBias_uid32_fpSinPiTest_q <= "01111100011"; --expX_uid6_fpSinPiTest(BITSELECT,5)@0 expX_uid6_fpSinPiTest_in <= xIn_0(62 downto 0); expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(62 downto 52); --shiftValue_uid33_fpSinPiTest(SUB,32)@0 shiftValue_uid33_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b); shiftValue_uid33_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid32_fpSinPiTest_q); shiftValue_uid33_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid33_fpSinPiTest_a) - UNSIGNED(shiftValue_uid33_fpSinPiTest_b)); shiftValue_uid33_fpSinPiTest_q <= shiftValue_uid33_fpSinPiTest_o(11 downto 0); --fxpShifterBits_uid36_fpSinPiTest(BITSELECT,35)@0 fxpShifterBits_uid36_fpSinPiTest_in <= shiftValue_uid33_fpSinPiTest_q(6 downto 0); fxpShifterBits_uid36_fpSinPiTest_b <= fxpShifterBits_uid36_fpSinPiTest_in(6 downto 0); --leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest(BITSELECT,114)@0 leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b; leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in(6 downto 5); --leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest(MUX,115)@0 leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s, extendedFracX_uid35_fpSinPiTest_q, leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= extendedFracX_uid35_fpSinPiTest_q; WHEN "01" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest(BITSELECT,125)@0 leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(4 downto 0); leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in(4 downto 3); --leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest(MUX,126)@0 leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest(BITSELECT,136)@0 leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(2 downto 0); leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in(2 downto 1); --leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest(MUX,137)@0 leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest(BITSELECT,139)@0 LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in(79 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest(BITJOIN,140)@0 leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b & GND_q; --reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3(REG,357)@0 reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2(REG,358)@0 reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest(BITSELECT,141)@0 leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(0 downto 0); leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in(0 downto 0); --ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b(DELAY,581)@0 ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest(MUX,142)@1 leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q; leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s, reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q, reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q) BEGIN CASE leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q; WHEN "1" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q; WHEN OTHERS => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --intXParity_uid38_fpSinPiTest(BITSELECT,37)@1 intXParity_uid38_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q; intXParity_uid38_fpSinPiTest_b <= intXParity_uid38_fpSinPiTest_in(80 downto 80); --ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c(DELAY,536)@1 ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => intXParity_uid38_fpSinPiTest_b, xout => ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q, clk => clk, aclr => areset ); --biasM1_uid27_fpSinPiTest(CONSTANT,26) biasM1_uid27_fpSinPiTest_q <= "01111111110"; --xFrac_uid28_fpSinPiTest(COMPARE,27)@0 xFrac_uid28_fpSinPiTest_cin <= GND_q; xFrac_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid27_fpSinPiTest_q) & '0'; xFrac_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid28_fpSinPiTest_cin(0); xFrac_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid28_fpSinPiTest_a) - UNSIGNED(xFrac_uid28_fpSinPiTest_b)); xFrac_uid28_fpSinPiTest_n(0) <= not xFrac_uid28_fpSinPiTest_o(13); --ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a(DELAY,532)@0 ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => xFrac_uid28_fpSinPiTest_n, xout => ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvXFrac_uid99_fpSinPiTest(LOGICAL,98)@3 InvXFrac_uid99_fpSinPiTest_a <= ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q; InvXFrac_uid99_fpSinPiTest_q <= not InvXFrac_uid99_fpSinPiTest_a; --biasMwShift_uid29_fpSinPiTest(CONSTANT,28) biasMwShift_uid29_fpSinPiTest_q <= "01111100100"; --sinXIsX_uid30_fpSinPiTest(COMPARE,29)@0 sinXIsX_uid30_fpSinPiTest_cin <= GND_q; sinXIsX_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0'; sinXIsX_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid29_fpSinPiTest_q) & sinXIsX_uid30_fpSinPiTest_cin(0); sinXIsX_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid30_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid30_fpSinPiTest_b)); sinXIsX_uid30_fpSinPiTest_c(0) <= sinXIsX_uid30_fpSinPiTest_o(13); --ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a(DELAY,502)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvSinXIsX_uid80_fpSinPiTest(LOGICAL,79)@2 InvSinXIsX_uid80_fpSinPiTest_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q; InvSinXIsX_uid80_fpSinPiTest_q <= not InvSinXIsX_uid80_fpSinPiTest_a; --y_uid39_fpSinPiTest(BITSELECT,38)@1 y_uid39_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); y_uid39_fpSinPiTest_b <= y_uid39_fpSinPiTest_in(79 downto 0); --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0(REG,360)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid40_fpSinPiTest(LOGICAL,39)@2 yIsZero_uid40_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q; yIsZero_uid40_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000000000000000000000000000000000000000000000000" & GND_q); yIsZero_uid40_fpSinPiTest_q <= "1" when yIsZero_uid40_fpSinPiTest_a = yIsZero_uid40_fpSinPiTest_b else "0"; --And2YIsZeroInvSinXIsX_uid81_fpSinPiTest(LOGICAL,80)@2 And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a <= yIsZero_uid40_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b <= InvSinXIsX_uid80_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a and And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b; --cstBiasPwF_uid13_fpSinPiTest(CONSTANT,12) cstBiasPwF_uid13_fpSinPiTest_q <= "10000110011"; --xIntExp_uid26_fpSinPiTest(COMPARE,25)@0 xIntExp_uid26_fpSinPiTest_cin <= GND_q; xIntExp_uid26_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid13_fpSinPiTest_q) & '0'; xIntExp_uid26_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid26_fpSinPiTest_cin(0); xIntExp_uid26_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid26_fpSinPiTest_a) - UNSIGNED(xIntExp_uid26_fpSinPiTest_b)); xIntExp_uid26_fpSinPiTest_c(0) <= xIntExp_uid26_fpSinPiTest_o(13); --ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a(DELAY,505)@0 ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => xIntExp_uid26_fpSinPiTest_c, xout => ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q, clk => clk, aclr => areset ); --Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest(LOGICAL,81)@2 Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a or Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b; --cstAllZWF_uid10_fpSinPiTest(CONSTANT,9) cstAllZWF_uid10_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracXIsZero_uid17_fpSinPiTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b; fracXIsZero_uid17_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q; fracXIsZero_uid17_fpSinPiTest_q <= "1" when fracXIsZero_uid17_fpSinPiTest_a = fracXIsZero_uid17_fpSinPiTest_b else "0"; --ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a(DELAY,442)@0 ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => fracXIsZero_uid17_fpSinPiTest_q, xout => ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvFracXIsZero_uid19_fpSinPiTest(LOGICAL,18)@1 InvFracXIsZero_uid19_fpSinPiTest_a <= ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q; InvFracXIsZero_uid19_fpSinPiTest_q <= not InvFracXIsZero_uid19_fpSinPiTest_a; --cstAllOWE_uid9_fpSinPiTest(CONSTANT,8) cstAllOWE_uid9_fpSinPiTest_q <= "11111111111"; --expXIsMax_uid16_fpSinPiTest(LOGICAL,15)@0 expXIsMax_uid16_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsMax_uid16_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q; expXIsMax_uid16_fpSinPiTest_q <= "1" when expXIsMax_uid16_fpSinPiTest_a = expXIsMax_uid16_fpSinPiTest_b else "0"; --ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a(DELAY,443)@0 ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsMax_uid16_fpSinPiTest_q, xout => ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest(LOGICAL,19)@1 And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a <= ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b <= InvFracXIsZero_uid19_fpSinPiTest_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a and And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b; --InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest(LOGICAL,20)@1 InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q <= not InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a; --And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0 And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a <= expXIsMax_uid16_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b <= fracXIsZero_uid17_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a and And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b; --InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0 InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q; InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q <= not InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a; --cstAllZWE_uid11_fpSinPiTest(CONSTANT,10) cstAllZWE_uid11_fpSinPiTest_q <= "00000000000"; --expXIsZero_uid15_fpSinPiTest(LOGICAL,14)@0 expXIsZero_uid15_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsZero_uid15_fpSinPiTest_b <= cstAllZWE_uid11_fpSinPiTest_q; expXIsZero_uid15_fpSinPiTest_q <= "1" when expXIsZero_uid15_fpSinPiTest_a = expXIsZero_uid15_fpSinPiTest_b else "0"; --InvExpXIsZero_uid23_fpSinPiTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSinPiTest_a <= expXIsZero_uid15_fpSinPiTest_q; InvExpXIsZero_uid23_fpSinPiTest_q <= not InvExpXIsZero_uid23_fpSinPiTest_a; --And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0 And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a <= InvExpXIsZero_uid23_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b <= InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a and And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b; --ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a(DELAY,450)@0 ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q, xout => ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest(LOGICAL,24)@1 And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a <= ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b <= InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a and And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b; END IF; END PROCESS; --xIsInt_uid83_fpSinPiTest(LOGICAL,82)@2 xIsInt_uid83_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_b <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_q <= xIsInt_uid83_fpSinPiTest_a and xIsInt_uid83_fpSinPiTest_b; --InvXIsInt_uid100_fpSinPiTest(LOGICAL,99)@2 InvXIsInt_uid100_fpSinPiTest_a <= xIsInt_uid83_fpSinPiTest_q; InvXIsInt_uid100_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= not InvXIsInt_uid100_fpSinPiTest_a; END IF; END PROCESS; --signComp_uid101_fpSinPiTest(LOGICAL,100)@3 signComp_uid101_fpSinPiTest_a <= InvXIsInt_uid100_fpSinPiTest_q; signComp_uid101_fpSinPiTest_b <= InvXFrac_uid99_fpSinPiTest_q; signComp_uid101_fpSinPiTest_c <= ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q; signComp_uid101_fpSinPiTest_q <= signComp_uid101_fpSinPiTest_a and signComp_uid101_fpSinPiTest_b and signComp_uid101_fpSinPiTest_c; --ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a(DELAY,537)@2 ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => yIsZero_uid40_fpSinPiTest_q, xout => ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvYIsZero_uid102_fpSinPiTest(LOGICAL,101)@3 InvYIsZero_uid102_fpSinPiTest_a <= ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q; InvYIsZero_uid102_fpSinPiTest_q <= not InvYIsZero_uid102_fpSinPiTest_a; --And2InvYIsZeroSignComp_uid103_fpSinPiTest(LOGICAL,102)@3 And2InvYIsZeroSignComp_uid103_fpSinPiTest_a <= InvYIsZero_uid102_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_b <= signComp_uid101_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_q <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_a and And2InvYIsZeroSignComp_uid103_fpSinPiTest_b; --signX_uid8_fpSinPiTest(BITSELECT,7)@0 signX_uid8_fpSinPiTest_in <= xIn_0; signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(63 downto 63); --ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a(DELAY,540)@0 ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q, clk => clk, aclr => areset ); --signR_uid104_fpSinPiTest(LOGICAL,103)@3 signR_uid104_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q; signR_uid104_fpSinPiTest_b <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_q; signR_uid104_fpSinPiTest_q <= signR_uid104_fpSinPiTest_a xor signR_uid104_fpSinPiTest_b; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt(COUNTER,1020) -- every=1, low=0, high=36, step=1, init=1 ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i = 35 THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i - 36; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i,6)); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg(REG,1021) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --VCC(CONSTANT,1) VCC_q <= "1"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux(MUX,1022) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux: PROCESS (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem(DUALMEM,1019) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia <= signR_uid104_fpSinPiTest_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 37, width_b => 1, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq, address_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa, data_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia ); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq(0 downto 0); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg(DELAY,1018) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q, xout => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --cstBias_uid12_fpSinPiTest(CONSTANT,11) cstBias_uid12_fpSinPiTest_q <= "01111111111"; --piwFP2_uid67_fpSinPiTest(CONSTANT,66) piwFP2_uid67_fpSinPiTest_q <= "110010010000111111011010101000100010000101101000110001"; --reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1(REG,363)@1 reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --cOne_uid44_fpSinPiTest(CONSTANT,43) cOne_uid44_fpSinPiTest_q <= "100000000000000000000000000000000000000000000000000000000000000000000000000000000"; --oneMinusY_uid45_fpSinPiTest(SUB,44)@2 oneMinusY_uid45_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid44_fpSinPiTest_q); oneMinusY_uid45_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q); oneMinusY_uid45_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid45_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid45_fpSinPiTest_b)); END IF; END PROCESS; oneMinusY_uid45_fpSinPiTest_q <= oneMinusY_uid45_fpSinPiTest_o(81 downto 0); --oMyBottom_uid47_fpSinPiTest(BITSELECT,46)@3 oMyBottom_uid47_fpSinPiTest_in <= oneMinusY_uid45_fpSinPiTest_q(78 downto 0); oMyBottom_uid47_fpSinPiTest_b <= oMyBottom_uid47_fpSinPiTest_in(78 downto 0); --ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d(DELAY,471)@3 ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => oMyBottom_uid47_fpSinPiTest_b, xout => ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q, clk => clk, aclr => areset ); --yBottom_uid48_fpSinPiTest(BITSELECT,47)@1 yBottom_uid48_fpSinPiTest_in <= y_uid39_fpSinPiTest_b(78 downto 0); yBottom_uid48_fpSinPiTest_b <= yBottom_uid48_fpSinPiTest_in(78 downto 0); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c(DELAY,470)@1 ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 79, depth => 2 ) PORT MAP ( xin => yBottom_uid48_fpSinPiTest_b, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg(DELAY,926) ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a(DELAY,833)@1 ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a : dspba_delay GENERIC MAP ( width => 80, depth => 1 ) PORT MAP ( xin => y_uid39_fpSinPiTest_b, xout => ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q, clk => clk, aclr => areset ); --reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1(REG,364)@2 reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q; END IF; END PROCESS; --cmpYToOneMinusY_uid46_fpSinPiTest(COMPARE,45)@3 cmpYToOneMinusY_uid46_fpSinPiTest_cin <= GND_q; cmpYToOneMinusY_uid46_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & oneMinusY_uid45_fpSinPiTest_q) & '0'; cmpYToOneMinusY_uid46_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q) & cmpYToOneMinusY_uid46_fpSinPiTest_cin(0); cmpYToOneMinusY_uid46_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_b)); END IF; END PROCESS; cmpYToOneMinusY_uid46_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid46_fpSinPiTest_o(84); --z_uid49_fpSinPiTest(MUX,48)@4 z_uid49_fpSinPiTest_s <= cmpYToOneMinusY_uid46_fpSinPiTest_c; z_uid49_fpSinPiTest: PROCESS (z_uid49_fpSinPiTest_s, ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q) BEGIN CASE z_uid49_fpSinPiTest_s IS WHEN "0" => z_uid49_fpSinPiTest_q <= ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q; WHEN "1" => z_uid49_fpSinPiTest_q <= ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q; WHEN OTHERS => z_uid49_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --zAddr_uid63_fpSinPiTest(BITSELECT,62)@4 zAddr_uid63_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; zAddr_uid63_fpSinPiTest_b <= zAddr_uid63_fpSinPiTest_in(78 downto 72); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0(REG,382)@4 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= zAddr_uid63_fpSinPiTest_b; END IF; END PROCESS; --memoryC5_uid231_sinPiZTableGenerator(LOOKUP,230)@5 memoryC5_uid231_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; WHEN "0000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111110101101000"; WHEN "0000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111101101011101"; WHEN "0000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100110001110"; WHEN "0000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100000000010"; WHEN "0000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111011000000000"; WHEN "0000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111010001101101"; WHEN "0000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111001010010111"; WHEN "0001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111000010110010"; WHEN "0001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110111100010100"; WHEN "0001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110110100011111"; WHEN "0001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110101100101101"; WHEN "0001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110100101101011"; WHEN "0001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110011111011101"; WHEN "0001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010111001010"; WHEN "0001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010001011011"; WHEN "0010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110001010101011"; WHEN "0010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110000011011001"; WHEN "0010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101111011000001"; WHEN "0010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101110101001010"; WHEN "0010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101101110100110"; WHEN "0010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101100111100011"; WHEN "0010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011111111111"; WHEN "0010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011001001010"; WHEN "0011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101010010100110"; WHEN "0011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101001010011011"; WHEN "0011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101000100011100"; WHEN "0011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100111101010110"; WHEN "0011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100110110111000"; WHEN "0011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100101111110010"; WHEN "0011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100111110010"; WHEN "0011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100001010101"; WHEN "0100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100011011011111"; WHEN "0100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100010011110111"; WHEN "0100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100001110001010"; WHEN "0100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100000111000100"; WHEN "0100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111111110101"; WHEN "0100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111001010110"; WHEN "0100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011110011000111"; WHEN "0100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011101101000000"; WHEN "0101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011100110000011"; WHEN "0101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011111111001"; WHEN "0101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011000100110"; WHEN "0101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011010010101100"; WHEN "0101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011001100010010"; WHEN "0101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011000101010111"; WHEN "0101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111111101010"; WHEN "0101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111001010000"; WHEN "0110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010110011010011"; WHEN "0110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010101100101011"; WHEN "0110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010100110111110"; WHEN "0110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011111111000"; WHEN "0110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011010110010"; WHEN "0110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010010101001110"; WHEN "0110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001110010011"; WHEN "0110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001000111011"; WHEN "0111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010000001111011"; WHEN "0111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001111011111110"; WHEN "0111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110111001010"; WHEN "0111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110001110111"; WHEN "0111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001101011000100"; WHEN "0111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100101010010"; WHEN "0111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100000011111"; WHEN "0111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001011010001010"; WHEN "1000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001010100111110"; WHEN "1000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001110110010"; WHEN "1000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001010111000"; WHEN "1000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001000100111111"; WHEN "1000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111111001100"; WHEN "1000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111010001001"; WHEN "1000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110101010110"; WHEN "1000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110000011101"; WHEN "1001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000101001110100"; WHEN "1001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000100101111001"; WHEN "1001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011111111010"; WHEN "1001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011011110110"; WHEN "1001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010110001100"; WHEN "1001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010001001000"; WHEN "1001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001101111001"; WHEN "1001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001000000111"; WHEN "1010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000000010111001"; WHEN "1010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111110110110"; WHEN "1010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111001111111"; WHEN "1010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110110010100"; WHEN "1010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110001011000"; WHEN "1010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101100010111"; WHEN "1010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101000010010"; WHEN "1010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100100010000"; WHEN "1011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100000111100"; WHEN "1011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111011011111111"; WHEN "1011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010111100000"; WHEN "1011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010011110100"; WHEN "1011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010000011100"; WHEN "1011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111001011011110"; WHEN "1011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000111111101"; WHEN "1011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000100101011"; WHEN "1100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000001100100"; WHEN "1100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111101101110"; WHEN "1100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111010011000"; WHEN "1100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110110110000"; WHEN "1100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110010011010"; WHEN "1100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110000011110"; WHEN "1100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101100101100"; WHEN "1100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101000101110"; WHEN "1101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100110100000"; WHEN "1101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100100010001"; WHEN "1101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100001000000"; WHEN "1101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011101101110"; WHEN "1101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011011011111"; WHEN "1101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010111000100"; WHEN "1101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010101110011"; WHEN "1101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010001111100"; WHEN "1110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010000001111"; WHEN "1110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001110011001"; WHEN "1110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001010100010"; WHEN "1110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000111111000"; WHEN "1110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101110110"; WHEN "1110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101000100"; WHEN "1110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000010100010"; WHEN "1110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111111110011"; WHEN "1111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111110010000"; WHEN "1111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111100110111"; WHEN "1111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111010111000"; WHEN "1111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111000101000"; WHEN "1111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110110110100"; WHEN "1111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110101011010"; WHEN "1111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110100000011"; WHEN "1111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110010001011"; WHEN OTHERS => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; END CASE; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a(DELAY,485)@4 ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => z_uid49_fpSinPiTest_q, xout => ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q, clk => clk, aclr => areset ); --zPPolyEval_uid64_fpSinPiTest(BITSELECT,63)@5 zPPolyEval_uid64_fpSinPiTest_in <= ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q(71 downto 0); zPPolyEval_uid64_fpSinPiTest_b <= zPPolyEval_uid64_fpSinPiTest_in(71 downto 27); --yT1_uid232_sinPiZPolyEval(BITSELECT,231)@5 yT1_uid232_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT1_uid232_sinPiZPolyEval_b <= yT1_uid232_sinPiZPolyEval_in(44 downto 28); --reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0(REG,383)@5 reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= yT1_uid232_sinPiZPolyEval_b; END IF; END PROCESS; --prodXY_uid263_pT1_uid233_sinPiZPolyEval(MULT,262)@6 prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_a),18)) * SIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_b); prodXY_uid263_pT1_uid233_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= memoryC5_uid231_sinPiZTableGenerator_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr,34)); END IF; END PROCESS; prodXY_uid263_pT1_uid233_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval(BITSELECT,263)@9 prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_q; prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in(33 downto 16); --highBBits_uid235_sinPiZPolyEval(BITSELECT,234)@9 highBBits_uid235_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b; highBBits_uid235_sinPiZPolyEval_b <= highBBits_uid235_sinPiZPolyEval_in(17 downto 1); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a(DELAY,853)@4 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a : dspba_delay GENERIC MAP ( width => 7, depth => 3 ) PORT MAP ( xin => zAddr_uid63_fpSinPiTest_b, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0(REG,384)@7 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q; END IF; END PROCESS; --memoryC4_uid230_sinPiZTableGenerator(LOOKUP,229)@8 memoryC4_uid230_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; WHEN "0000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110011111111100"; WHEN "0000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100101101100110011"; WHEN "0000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100100010011000101"; WHEN "0000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100010010010010110"; WHEN "0000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011111110011000100"; WHEN "0000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011100101011001100"; WHEN "0000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011001000001111000"; WHEN "0001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010100110101100100"; WHEN "0001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010000000010110001"; WHEN "0001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001001010101111100100"; WHEN "0001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001000100111000100010"; WHEN "0001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000111110011011110101"; WHEN "0001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000110111011001010101"; WHEN "0001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000101111111000110001"; WHEN "0001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000100111101101111110"; WHEN "0010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000011111000010010110"; WHEN "0010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000010101110100101111"; WHEN "0010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000001100000110110101"; WHEN "0010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000000001101111000000"; WHEN "0010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111110110110101110011"; WHEN "0010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111101011011010111001"; WHEN "0010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111011111011110000110"; WHEN "0010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111010010111100110100"; WHEN "0011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111000101110111111001"; WHEN "0011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110111000010100011101"; WHEN "0011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110101010001000110011"; WHEN "0011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110011011011101100111"; WHEN "0011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110001100001110001111"; WHEN "0011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101111100011110001010"; WHEN "0011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101101100001110100101"; WHEN "0011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101011011011000110110"; WHEN "0100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101001001111111101110"; WHEN "0100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100111000001001001111"; WHEN "0100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100100101101100011001"; WHEN "0100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100010010110001110000"; WHEN "0100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011111111010101110110"; WHEN "0100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011101011010111000111"; WHEN "0100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011010110110110011110"; WHEN "0100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011000001110100011110"; WHEN "0101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010101100010100010011"; WHEN "0101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010010110010001000111"; WHEN "0101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001111111110001000100"; WHEN "0101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001101000101100110110"; WHEN "0101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001010001001001111011"; WHEN "0101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000111001001000001110"; WHEN "0101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000100000100011110110"; WHEN "0101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000000111100001111001"; WHEN "0110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111101101111111011111"; WHEN "0110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111010011111111100110"; WHEN "0110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110111001011110100100"; WHEN "0110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110011110100010000111"; WHEN "0110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110000011000010001001"; WHEN "0110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101100111000101000011"; WHEN "0110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101001010101101011111"; WHEN "0110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100101101110011101110"; WHEN "0111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100010000100000111110"; WHEN "0111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011110010101101110100"; WHEN "0111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011010100011010011110"; WHEN "0111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010110101101011010111"; WHEN "0111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010010110100011011101"; WHEN "0111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001110110111100001001"; WHEN "0111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001010110110110010000"; WHEN "0111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000110110011000001101"; WHEN "1000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000010101011011011001"; WHEN "1000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111110100000101110010"; WHEN "1000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111010010001110101001"; WHEN "1000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110110000000001101011"; WHEN "1000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110001101011001110011"; WHEN "1000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101101010010101011101"; WHEN "1000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101000110110101111111"; WHEN "1000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111100100010111100111100"; WHEN "1001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011111110101110100100"; WHEN "1001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011011001111111110100"; WHEN "1001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010110100111101000111"; WHEN "1001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010001111011100101001"; WHEN "1001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001101001100111100001"; WHEN "1001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001000011011000101011"; WHEN "1001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111000011100101100110010"; WHEN "1001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111110101110000000011"; WHEN "1010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111001110011001111101"; WHEN "1010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110110100110101001110001"; WHEN "1010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101111110100101001011"; WHEN "1010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101010110000110010110"; WHEN "1010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100101101010100111010"; WHEN "1010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100000100001101101101"; WHEN "1010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110011011010101110011000"; WHEN "1010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010110000111001010011"; WHEN "1011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010000110101101010010"; WHEN "1011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110001011100010001000010"; WHEN "1011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000110001011111001110"; WHEN "1011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000000110010110110100"; WHEN "1011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101111011010111010001000"; WHEN "1011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110101111001110001011"; WHEN "1011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110000011001011001100"; WHEN "1011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101101010110110100111111"; WHEN "1100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101100101010001011011001"; WHEN "1100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011111101010010000000"; WHEN "1100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011010000000101001000"; WHEN "1100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101010100010100111110111"; WHEN "1100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001110100111011010110"; WHEN "1100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001000110110111101100"; WHEN "1100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101000011000101000001000"; WHEN "1100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100111101010001001010101"; WHEN "1101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110111011010110000011"; WHEN "1101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110001100010011011010"; WHEN "1101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100101011101000100011001"; WHEN "1101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100100101101100110100111"; WHEN "1101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011111101110111111010"; WHEN "1101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011001110000000101100"; WHEN "1101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100010011101110011110101"; WHEN "1101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100001101101100000010000"; WHEN "1110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000111100111010001011"; WHEN "1110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000001100000111111010"; WHEN "1110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011111011011001110101000"; WHEN "1110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011110101010000110010111"; WHEN "1110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101111000110001000001"; WHEN "1110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101000111001101001001"; WHEN "1110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011100010101100011001010"; WHEN "1110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011011100011101111010110"; WHEN "1111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011010110001101110011110"; WHEN "1111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001111111100011010111"; WHEN "1111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001001101010000100101"; WHEN "1111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011000011010110101101110"; WHEN "1111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010111101000010001000000"; WHEN "1111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110110101100011000101"; WHEN "1111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110000010101101010111"; WHEN "1111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010101001111110001011010"; WHEN OTHERS => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; END CASE; END IF; END PROCESS; --sumAHighB_uid236_sinPiZPolyEval(ADD,235)@9 sumAHighB_uid236_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((26 downto 26 => memoryC4_uid230_sinPiZTableGenerator_q(25)) & memoryC4_uid230_sinPiZTableGenerator_q); sumAHighB_uid236_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((26 downto 17 => highBBits_uid235_sinPiZPolyEval_b(16)) & highBBits_uid235_sinPiZPolyEval_b); sumAHighB_uid236_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid236_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid236_sinPiZPolyEval_b)); sumAHighB_uid236_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_o(26 downto 0); --lowRangeB_uid234_sinPiZPolyEval(BITSELECT,233)@9 lowRangeB_uid234_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid234_sinPiZPolyEval_b <= lowRangeB_uid234_sinPiZPolyEval_in(0 downto 0); --s1_uid234_uid237_sinPiZPolyEval(BITJOIN,236)@9 s1_uid234_uid237_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_q & lowRangeB_uid234_sinPiZPolyEval_b; --reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1(REG,385)@9 reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= s1_uid234_uid237_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor(LOGICAL,1179) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q <= not (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a or ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg(REG,1177) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= VCC_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena(REG,1180) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q = "1") THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd(LOGICAL,1181) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a and ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b; --yT2_uid238_sinPiZPolyEval(BITSELECT,237)@5 yT2_uid238_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT2_uid238_sinPiZPolyEval_b <= yT2_uid238_sinPiZPolyEval_in(44 downto 19); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt(COUNTER,1173) -- every=1, low=0, high=1, step=1, init=1 ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i + 1; END IF; END PROCESS; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i,1)); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg(REG,1174) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux(MUX,1175) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q) BEGIN CASE ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s IS WHEN "0" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; WHEN "1" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem(DUALMEM,1172) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia <= yT2_uid238_sinPiZPolyEval_b; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 26, widthad_a => 1, numwords_a => 2, width_b => 26, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq, address_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa, data_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia ); ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq(25 downto 0); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg(DELAY,1171) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q, xout => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0(REG,386)@9 reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q; END IF; END PROCESS; --prodXY_uid266_pT2_uid239_sinPiZPolyEval(MULT,265)@10 prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_a),27)) * SIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_b); prodXY_uid266_pT2_uid239_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr,54)); END IF; END PROCESS; prodXY_uid266_pT2_uid239_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval(BITSELECT,266)@13 prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_q; prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in(53 downto 25); --highBBits_uid241_sinPiZPolyEval(BITSELECT,240)@13 highBBits_uid241_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b; highBBits_uid241_sinPiZPolyEval_b <= highBBits_uid241_sinPiZPolyEval_in(28 downto 1); --reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1(REG,388)@13 reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= highBBits_uid241_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor(LOGICAL,1192) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1188) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q <= "0101"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp(LOGICAL,1189) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg(REG,1190) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena(REG,1193) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1194) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1184) -- every=1, low=0, high=5, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i = 4 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i - 5; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i,3)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg(REG,1185) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1186) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1183) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 3, numwords_a => 6, width_b => 7, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg(DELAY,1182) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0(REG,387)@12 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC3_uid229_sinPiZTableGenerator(LOOKUP,228)@13 memoryC3_uid229_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; WHEN "0000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000001010001100110101000111010101"; WHEN "0000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000010100011001100101101010110011"; WHEN "0000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000011110100110001101010100011011"; WHEN "0000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000101000110010100111100101110011"; WHEN "0000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000110010111110101111101101101000"; WHEN "0000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000111101001010100001100001001101"; WHEN "0000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001000111010101111000010100001000"; WHEN "0001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001010001100000101111101001011010"; WHEN "0001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001011011101011000011001000111110"; WHEN "0001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001100101110100101110001001110101"; WHEN "0001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001101111111101101100010100000001"; WHEN "0001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001111010000101111001001101010110"; WHEN "0001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010000100001101010000011000110101"; WHEN "0001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010001110010011101101001010101000"; WHEN "0001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010011000011001001011011101011111"; WHEN "0010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010100010011101100110100011101011"; WHEN "0010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010101100100000111010000011110001"; WHEN "0010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010110110100011000001011111010110"; WHEN "0010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011000000100011111000101110110101"; WHEN "0010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011001010100011011011001000001011"; WHEN "0010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011010100100001100100010010100101"; WHEN "0010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011011110011110001111110110101010"; WHEN "0010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011101000011001011001100000011011"; WHEN "0011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011110010010010111100111000010100"; WHEN "0011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011111100001010110101011110000110"; WHEN "0011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100000110000000111111001110100010"; WHEN "0011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100001111110101010101100100101101"; WHEN "0011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100011001100111110100010110001111"; WHEN "0011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100100011011000010111001001011111"; WHEN "0011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100101101000110111001101001101001"; WHEN "0011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100110110110011010111110011001100"; WHEN "0100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101000000011101101101010000100110"; WHEN "0100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101001010000101110101101000010110"; WHEN "0100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101010011101011101100111100100100"; WHEN "0100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101011101001111001110110000110010"; WHEN "0100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101100110110000010111000000110011"; WHEN "0100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101110000001111000001100011110100"; WHEN "0100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101111001101011001010010000000001"; WHEN "0100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110000011000100101100111100001110"; WHEN "0101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110001100011011100101011010100101"; WHEN "0101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110010101101111101111110000010101"; WHEN "0101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110011111000001000111101011101100"; WHEN "0101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110101000001111101001011001100010"; WHEN "0101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110110001011011010000101101010010"; WHEN "0101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110111010100011111001100111101100"; WHEN "0101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111000011101001100000010000100010"; WHEN "0101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111001100101100000000100001010000"; WHEN "0110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111010101101011010110100011101100"; WHEN "0110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111011110100111011110011000011110"; WHEN "0110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111100111100000010100001101010000"; WHEN "0110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111110000010101110100000001010000"; WHEN "0110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111111001000111111010001101010001"; WHEN "0110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000000001110110100010110001111010"; WHEN "0110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000001010100001101001110111110101"; WHEN "0110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000010011001001001011111110000001"; WHEN "0111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000011011101101000101000010101111"; WHEN "0111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000100100001101010001101000100100"; WHEN "0111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000101100101001101110000011010101"; WHEN "0111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000110101000010010110100001011010"; WHEN "0111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000111101010111000111010101011110"; WHEN "0111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001000101100111111101000110111000"; WHEN "0111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001001101110100110100001111001100"; WHEN "0111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001010101111101101001000001001010"; WHEN "1000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001011110000010011000001001000011"; WHEN "1000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001100110000010111101111101010011"; WHEN "1000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001101101111111010111010011001111"; WHEN "1000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001110101110111100000011010000110"; WHEN "1000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001111101101011010110000011010010"; WHEN "1000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010000101011010110100111100000101"; WHEN "1000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010001101000101111001101110100011"; WHEN "1000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010010100101100100001000101010010"; WHEN "1001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010011100001110100111101001010100"; WHEN "1001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010100011101100001010100001011100"; WHEN "1001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010101011000101000110001011100100"; WHEN "1001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010110010011001010111110000100100"; WHEN "1001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010111001101000111011111001000111"; WHEN "1001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000000110011101111101001011111"; WHEN "1001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000111111001110000000110011110"; WHEN "1001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011001110111010111001110111111110"; WHEN "1010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011010101110111001010010001110110"; WHEN "1010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011011100101110011110011000111101"; WHEN "1010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011100011100000110011001001001001"; WHEN "1010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011101010001110000101111000101100"; WHEN "1010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110000110110010011100011000111"; WHEN "1010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110111011001011001011101010011"; WHEN "1010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011111101110111010100111100011100"; WHEN "1010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100000100010000000011001111101101"; WHEN "1011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100001010100011100001101110011100"; WHEN "1011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010000110001101101100011100011"; WHEN "1011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010110111010100100010100000100"; WHEN "1011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100011100111110000011100000001010"; WHEN "1011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100100010111100001000100001101001"; WHEN "1011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101000110100110000110001111011"; WHEN "1011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101110100111111010000100111001"; WHEN "1011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100110100010101100001111010001101"; WHEN "1100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111001111101100101111101110000"; WHEN "1100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111111100000000011110011100101"; WHEN "1100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101000100111100111001010011110100"; WHEN "1100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001010010100000100001001001101"; WHEN "1100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001111100101100010000111001000"; WHEN "1100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101010100110001010001010100001101"; WHEN "1100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011001110111001111010101110101"; WHEN "1100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011110110111011010001101111010"; WHEN "1101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101100011110001110000000111001111"; WHEN "1101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101000100110001110111010010001"; WHEN "1101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101101010100110100100110101101"; WHEN "1101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110001111101011111011001010101"; WHEN "1101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110110100000001101100000100000"; WHEN "1101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111010111100111100111010111000"; WHEN "1101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111111010011101100010000110110"; WHEN "1101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000011100100011001011010100000"; WHEN "1110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000111101111000011000011110011"; WHEN "1110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001011110011100111011010000000"; WHEN "1110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001111110010000100101111100001"; WHEN "1110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010011101010011001110010000111"; WHEN "1110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010111011100100100111111111001"; WHEN "1110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011011001000100101000000101011"; WHEN "1110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011110101110011000001011101010"; WHEN "1110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100010001101111101010010100010"; WHEN "1111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100101100111010011001000110011"; WHEN "1111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101000111010011000011010000011"; WHEN "1111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101100000111001011110100010010"; WHEN "1111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101111001101101100001110011100"; WHEN "1111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110010001101111000100101110110"; WHEN "1111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110101000111101111110101001010"; WHEN "1111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110111111011010000111000110000"; WHEN "1111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110111010101000011010110000100000"; WHEN OTHERS => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; END CASE; END IF; END PROCESS; --sumAHighB_uid242_sinPiZPolyEval(ADD,241)@14 sumAHighB_uid242_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid229_sinPiZTableGenerator_q(34)) & memoryC3_uid229_sinPiZTableGenerator_q); sumAHighB_uid242_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((35 downto 28 => reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q(27)) & reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q); sumAHighB_uid242_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid242_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid242_sinPiZPolyEval_b)); sumAHighB_uid242_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_o(35 downto 0); --lowRangeB_uid240_sinPiZPolyEval(BITSELECT,239)@13 lowRangeB_uid240_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid240_sinPiZPolyEval_b <= lowRangeB_uid240_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a(DELAY,686)@13 ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid240_sinPiZPolyEval_b, xout => ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --s2_uid240_uid243_sinPiZPolyEval(BITJOIN,242)@14 s2_uid240_uid243_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_q & ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q; --yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval(BITSELECT,274)@14 yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in(36 downto 19); --reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9(REG,389)@14 reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor(LOGICAL,950) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top(CONSTANT,946) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q <= "0110"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp(LOGICAL,947) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b else "0"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg(REG,948) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena(REG,951) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q = "1") THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd(LOGICAL,952) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt(COUNTER,942) -- every=1, low=0, high=6, step=1, init=1 ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i = 5 THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i - 6; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i,3)); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg(REG,943) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux(MUX,944) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q) BEGIN CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s IS WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem(DUALMEM,1069) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 3, numwords_a => 7, width_b => 45, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg(DELAY,1068) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT3_uid244_sinPiZPolyEval(BITSELECT,243)@14 yT3_uid244_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q; yT3_uid244_sinPiZPolyEval_b <= yT3_uid244_sinPiZPolyEval_in(44 downto 10); --xBottomBits_uid274_pT3_uid245_sinPiZPolyEval(BITSELECT,273)@14 xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b(7 downto 0); xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in(7 downto 0); --pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval(BITJOIN,276)@14 pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7(REG,391)@14 reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid273_pT3_uid245_sinPiZPolyEval(BITSELECT,272)@14 yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q(9 downto 0); yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b <= yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in(9 downto 0); --spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval(BITJOIN,275)@14 spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q <= GND_q & yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b; --pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval(BITJOIN,277)@14 pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q <= spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6(REG,390)@14 reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval(BITSELECT,271)@14 xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in(34 downto 17); --reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4(REG,392)@14 reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma(CHAINMULTADD,345)@15 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1),38); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0); END IF; END PROCESS; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0),37)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval(BITSELECT,279)@18 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in(36 downto 7); --highBBits_uid282_pT3_uid245_sinPiZPolyEval(BITSELECT,281)@18 highBBits_uid282_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b; highBBits_uid282_pT3_uid245_sinPiZPolyEval_b <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_in(29 downto 1); --reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1(REG,395)@18 reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval(BITSELECT,269)@14 yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in(36 downto 10); --reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1(REG,393)@14 reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval(BITSELECT,268)@14 xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in(34 downto 8); --reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0(REG,394)@14 reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid271_pT3_uid245_sinPiZPolyEval(MULT,270)@15 topProd_uid271_pT3_uid245_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_b); topProd_uid271_pT3_uid245_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid271_pT3_uid245_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid271_pT3_uid245_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0(REG,396)@18 reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid283_pT3_uid245_sinPiZPolyEval(ADD,282)@19 sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q(53)) & reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b)); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid281_pT3_uid245_sinPiZPolyEval(BITSELECT,280)@18 lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b <= lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a(DELAY,724)@18 ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b, xout => ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid281_uid284_pT3_uid245_sinPiZPolyEval(BITJOIN,283)@19 add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q & ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q; --R_uid285_pT3_uid245_sinPiZPolyEval(BITSELECT,284)@19 R_uid285_pT3_uid245_sinPiZPolyEval_in <= add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q(54 downto 0); R_uid285_pT3_uid245_sinPiZPolyEval_b <= R_uid285_pT3_uid245_sinPiZPolyEval_in(54 downto 18); --reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1(REG,397)@19 reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= R_uid285_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor(LOGICAL,1168) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1164) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q <= "01011"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp(LOGICAL,1165) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg(REG,1166) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena(REG,1169) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1170) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1160) -- every=1, low=0, high=11, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i = 10 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i - 11; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i,4)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg(REG,1161) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1162) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1159) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 4, numwords_a => 12, width_b => 7, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg(DELAY,1158) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0(REG,381)@18 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC2_uid228_sinPiZTableGenerator(LOOKUP,227)@19 memoryC2_uid228_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; WHEN "0000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010010000000010011011110101101000"; WHEN "0000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010100110111111010000111001000101"; WHEN "0000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101011001101001111001000101101101011"; WHEN "0000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101100000010110001110010011100100110"; WHEN "0000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101101000111100110110110100100001100"; WHEN "0000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101110011011101101110110101011000001"; WHEN "0000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101111111111000110001101110000001000"; WHEN "0001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110001110001101111010000000001001001"; WHEN "0001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110011110011101000001010111100010011"; WHEN "0001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110110000100110000000101010101010010"; WHEN "0001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111000100101000101111111001111001110"; WHEN "0001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111011010100101000110010000000110000"; WHEN "0001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111110010011010111010000010100101101"; WHEN "0001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000001100001010000000110001101010110"; WHEN "0001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000100111110010001111000111001110001"; WHEN "0010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001000101010011011000111000110111111"; WHEN "0010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001100100101101010001000110100001110"; WHEN "0010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010000101111111101001111011000110110"; WHEN "0010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010101001001010010100101011111010000"; WHEN "0010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011001110001101000001111010001111100"; WHEN "0010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011110101000111100001010010001101000"; WHEN "0010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111100011101111001100001101011001010011"; WHEN "0010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101001000100010110001000111111011001"; WHEN "0011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101110101000010111100110110111011101"; WHEN "0011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111110100011011001110001010010101001001"; WHEN "0011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111111010011100110111010000000101010000"; WHEN "0011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000000101101010000001110011011110111"; WHEN "0011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000111001100010110010101001001001010"; WHEN "0011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000001101111010000110101101100011101100"; WHEN "0011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000010100110110011110011010100101011100"; WHEN "0011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000011100000001011010011000101010010101"; WHEN "0100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000100011011010110111011101111001100010"; WHEN "0100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000101011000010110010011010000011100100"; WHEN "0100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000110010111001000111110110011110000010"; WHEN "0100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000111010111101110100010110010000011111"; WHEN "0100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001000011010000110100010110001010111111"; WHEN "0100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001001011110010000100001100101110011011"; WHEN "0100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001010100100001100000001010001100011000"; WHEN "0100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001011101011111000100011000101001100001"; WHEN "0101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001100110101010101100111100000000011011"; WHEN "0101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001110000000100010101110001111101110010"; WHEN "0101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001111001101011111010110010001100011010"; WHEN "0101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010000011100001010111101110001010011110"; WHEN "0101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010001101100100101000010001011000100111"; WHEN "0101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010010111110101101000000001010011000010"; WHEN "0101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010100010010100010010011101010101101010"; WHEN "0101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010101101000000100010111111000010000011"; WHEN "0110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010110111111010010100111001111011100110"; WHEN "0110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011000011000001100011011011101110111001"; WHEN "0110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011001110010110001001101100001111110101"; WHEN "0110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011011001111000000010101101100000111100"; WHEN "0110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011100101100111001001011011101110011000"; WHEN "0110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011110001100011011000101101011001110101"; WHEN "0110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011111101101100101011010011010110110001"; WHEN "0110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100001010000010111011111000101001101100"; WHEN "0111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100010110100110000101000010110110110100"; WHEN "0111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100100011010110000001010001110101000110"; WHEN "0111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100110000010010101010111111111100101100"; WHEN "0111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100111101011011111100100010000110111111"; WHEN "0111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101001010110001110000000111101111100101"; WHEN "0111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101011000010011111111111010110011011100"; WHEN "0111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101100110000010100101111111111011010100"; WHEN "0111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101110011111101011100010110011100010110"; WHEN "1000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110000010000100011100111000010100111110"; WHEN "1000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110010000010111100001011010011001010101"; WHEN "1000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110011110110110100011101100001011001000"; WHEN "1000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110101101100001011101011000001011011001"; WHEN "1000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110111100011000001000000011101110001111"; WHEN "1000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111001011011010011101001111000101110001"; WHEN "1000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111011010101000010110010101100101000110"; WHEN "1000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111101010000001101100101101100010111111"; WHEN "1001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111111001100110011001101000011100111011"; WHEN "1001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000001001010110010110010010110100011100"; WHEN "1001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000011001010001011011110100100000011000"; WHEN "1001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000101001010111100011010000011111011101"; WHEN "1001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000111001101000100101100101001010011111"; WHEN "1001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001001010000100011011101100001100000010"; WHEN "1001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001011010101010111110011010101000110000"; WHEN "1001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001101011011100000110100001001001100100"; WHEN "1010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001111100010111101100101011101111001100"; WHEN "1010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010001101011101101001100010000010111010"; WHEN "1010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010011110101101110101100111011000000101"; WHEN "1010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010110000001000001001011010101000000100"; WHEN "1010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011000001101100011101010110100010000110"; WHEN "1010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011010011011010101001110001100010110011"; WHEN "1010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011100101010010100110111101111101101001"; WHEN "1010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011110111010100001101001010000001101110"; WHEN "1011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100001001011111010100011111111010110111"; WHEN "1011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100011011110011110101000101111001011001"; WHEN "1011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100101110010001100110111110001101101110"; WHEN "1011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101000000111000100010000111010010100101"; WHEN "1011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101010011101000011110011011110001111001"; WHEN "1011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101100110100001010011110010100110010101"; WHEN "1011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101111001100010111001111110111010001011"; WHEN "1011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110001100101101001000110000010101000001"; WHEN "1100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110011111111111110111110010111000010010"; WHEN "1100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110110011011010111110101111001000100111"; WHEN "1100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111000110111110010101001010001010011010"; WHEN "1100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111011010101001110010100101101110010111"; WHEN "1100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111101110011101001110100000001111101010"; WHEN "1100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000000010011000100000010100110110100000"; WHEN "1100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000010110011011011111011011100110110011"; WHEN "1100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000101010100110000011001001011000000001"; WHEN "1101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000111110111000000010101111111100010101"; WHEN "1101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001010011010001010101011110001011010100"; WHEN "1101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001100111110001110010100000000000010111"; WHEN "1101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001111100011001010000111110011101110000"; WHEN "1101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010010001000111100111111111110011011101"; WHEN "1101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010100101111100101110100111100110010101"; WHEN "1101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010111010111000011011110110101001010101"; WHEN "1101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011001111111010100110101011010011011011"; WHEN "1110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011100101000011000110000001010000000100"; WHEN "1110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011111010010001110000110001110011111011"; WHEN "1110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100001111100110011101110011111001111111"; WHEN "1110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100100101000001000011111100000011011011"; WHEN "1110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100111010100001011001111100100100101001"; WHEN "1110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101010000000111010110100101100100010111"; WHEN "1110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101100101110010110000100101000101101101"; WHEN "1110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101111011100011011110100111000011010111"; WHEN "1111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110010001011001010111010101011001010001"; WHEN "1111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110100111010100010001011000001010110100"; WHEN "1111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110111101010100000011010101100101100011"; WHEN "1111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111010011011000100011110010000011111011"; WHEN "1111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111101001100001101001010000010010001011"; WHEN "1111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111111111101111001010010001010101000011"; WHEN "1111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000010110000000111101010100101101001001"; WHEN "1111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000101100010110111000111000011010110101"; WHEN OTHERS => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid246_sinPiZPolyEval(CONSTANT,245) rndBit_uid246_sinPiZPolyEval_q <= "01"; --cIncludingRoundingBit_uid247_sinPiZPolyEval(BITJOIN,246)@19 cIncludingRoundingBit_uid247_sinPiZPolyEval_q <= memoryC2_uid228_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0(REG,398)@19 reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid247_sinPiZPolyEval_q; END IF; END PROCESS; --ts3_uid248_sinPiZPolyEval(ADD,247)@20 ts3_uid248_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q); ts3_uid248_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q(36)) & reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q); ts3_uid248_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid248_sinPiZPolyEval_a) + SIGNED(ts3_uid248_sinPiZPolyEval_b)); ts3_uid248_sinPiZPolyEval_q <= ts3_uid248_sinPiZPolyEval_o(45 downto 0); --s3_uid249_sinPiZPolyEval(BITSELECT,248)@20 s3_uid249_sinPiZPolyEval_in <= ts3_uid248_sinPiZPolyEval_q; s3_uid249_sinPiZPolyEval_b <= s3_uid249_sinPiZPolyEval_in(45 downto 1); --yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval(BITSELECT,286)@20 yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b; yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in(44 downto 18); --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9(REG,399)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor(LOGICAL,1091) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top(CONSTANT,1087) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q <= "01100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp(LOGICAL,1088) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg(REG,1089) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena(REG,1092) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd(LOGICAL,1093) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1083) -- every=1, low=0, high=12, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i = 11 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i - 12; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i,4)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg(REG,1084) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux(MUX,1085) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem(DUALMEM,1082) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 13, width_b => 45, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg(DELAY,1081) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT4_uid250_sinPiZPolyEval(BITSELECT,249)@20 yT4_uid250_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q; yT4_uid250_sinPiZPolyEval_b <= yT4_uid250_sinPiZPolyEval_in(44 downto 2); --xBottomBits_uid290_pT4_uid251_sinPiZPolyEval(BITSELECT,289)@20 xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in <= yT4_uid250_sinPiZPolyEval_b(15 downto 0); xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in(15 downto 0); --pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval(BITJOIN,291)@20 pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7(REG,401)@20 reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid289_pT4_uid251_sinPiZPolyEval(BITSELECT,288)@20 yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b(17 downto 0); yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b <= yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a(DELAY,733)@20 ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b, xout => ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval(BITJOIN,290)@21 spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q; --pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval(BITJOIN,292)@21 pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q <= spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6(REG,400)@21 reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a(DELAY,727)@20 ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 43, depth => 1 ) PORT MAP ( xin => yT4_uid250_sinPiZPolyEval_b, xout => ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval(BITSELECT,285)@21 xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in <= ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q; xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in(42 downto 16); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4(REG,402)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma(CHAINMULTADD,346)@22 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval(BITSELECT,294)@25 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in(54 downto 8); --highBBits_uid297_pT4_uid251_sinPiZPolyEval(BITSELECT,296)@25 highBBits_uid297_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b; highBBits_uid297_pT4_uid251_sinPiZPolyEval_b <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_in(46 downto 18); --reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1(REG,405)@25 reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1(REG,403)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b(DELAY,730)@21 ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0(REG,404)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid288_pT4_uid251_sinPiZPolyEval(MULT,287)@22 topProd_uid288_pT4_uid251_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_b); topProd_uid288_pT4_uid251_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid288_pT4_uid251_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid288_pT4_uid251_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0(REG,406)@25 reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid298_pT4_uid251_sinPiZPolyEval(ADD,297)@26 sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q(53)) & reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b)); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid296_pT4_uid251_sinPiZPolyEval(BITSELECT,295)@25 lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b(17 downto 0); lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b <= lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a(DELAY,741)@25 ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b, xout => ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid296_uid299_pT4_uid251_sinPiZPolyEval(BITJOIN,298)@26 add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q & ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q; --R_uid300_pT4_uid251_sinPiZPolyEval(BITSELECT,299)@26 R_uid300_pT4_uid251_sinPiZPolyEval_in <= add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q(71 downto 0); R_uid300_pT4_uid251_sinPiZPolyEval_b <= R_uid300_pT4_uid251_sinPiZPolyEval_in(71 downto 26); --reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1(REG,407)@26 reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= R_uid300_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor(LOGICAL,1155) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1151) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q <= "010010"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp(LOGICAL,1152) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg(REG,1153) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena(REG,1156) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1157) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1147) -- every=1, low=0, high=18, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i = 17 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i - 18; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg(REG,1148) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1149) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1146) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 19, width_b => 7, widthad_b => 5, numwords_b => 19, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg(DELAY,1145) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0(REG,380)@25 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC1_uid227_sinPiZTableGenerator(LOOKUP,226)@26 memoryC1_uid227_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; WHEN "0000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111110101101010100010101111000000010001111100011"; WHEN "0000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111101011010101001001010010110100010110001011110"; WHEN "0000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111100000111111110111100000001110010011010000110"; WHEN "0000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111010110101010110001001011111100110111111100011"; WHEN "0000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111001100010101111010001010101001101111010110100"; WHEN "0000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111000010000001010110010000110111110101011111000"; WHEN "0000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110110111101101001001010011000001101011000111010"; WHEN "0001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110101101011001010111000101010111101010010100111"; WHEN "0001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110100011000110000011011011111110011010111001110"; WHEN "0001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110011000110011010010001010101101000110101101101"; WHEN "0001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110001110100001000111000101001011101110011011101"; WHEN "0001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110000100001111100101111110110001011110001011001"; WHEN "0001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101111001111110110010101010100011000010010100110"; WHEN "0001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101101111101110110000111011010000111100011100100"; WHEN "0001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101100101011111100100100011010101111000101000111"; WHEN "0010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101011011010001010001010100110101000010011111000"; WHEN "0010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101010001000011111011000001011000011010110000100"; WHEN "0010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101000110110111100101011010001111001100111110010"; WHEN "0010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100111100101100010100010000001100000101010111010"; WHEN "0010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100110010100010001011010011100011100110101011100"; WHEN "0010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100101000011001001110010100001010100000101101100"; WHEN "0010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100011110010001100001000001010100000110110000000"; WHEN "0010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100010100001011000111001001110000100110010111000"; WHEN "0011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100001010000110000100011011101011011110011010110"; WHEN "0011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100000000000010011100100100101001110110011000010"; WHEN "0011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011110110000000010011010001101000110110000011100"; WHEN "0011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011101011111111101100001110111011111101010000000"; WHEN "0011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011100010000000101011001000001011011100001111010"; WHEN "0011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011011000000011010011101000010010101100000110110"; WHEN "0011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011001110000111101001011001011110100111101110010"; WHEN "0011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011000100001101110000000101001100000101000010010"; WHEN "0100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010111010010101101011010100000110001110011110001"; WHEN "0100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010110000011111011110101110000100111100111110101"; WHEN "0100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010100110101011001101111010001011010010011110011"; WHEN "0100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010011100111000111100011110100101110100010111000"; WHEN "0100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010010011001000101110000000101001000110111000111"; WHEN "0100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010001001011010100110000100110000001000100101001"; WHEN "0100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001111111101110101000001110011010101110010001110"; WHEN "0100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001110110000100111000000000001011111111100011001"; WHEN "0101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001101100011101011000111011101000110011100100000"; WHEN "0101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001100010111000001110100001010110001110100101001"; WHEN "0101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001011001010101011100010000110111111111100011001"; WHEN "0101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001001111110101000101101000101110111110101110110"; WHEN "0101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001000110010111001110000110010111101100001101110"; WHEN "0101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000111100111011111001000110001000101111011110000"; WHEN "0101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000110011100011001010000011010001010111001000100"; WHEN "0101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000101010001101000100010111110111111001010110011"; WHEN "0110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000100000111001101011011100111000010100110100100"; WHEN "0110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000010111101001000010101010000010110010001100101"; WHEN "0110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000001110011011001101010101111010000110001110001"; WHEN "0110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000000101010000001110110101110010010100010001010"; WHEN "0110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111111100001000001010011101101111010001101110100"; WHEN "0110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111110011000011000011100000100011001001100111111"; WHEN "0110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111101010000000111101001111101101000001001100111"; WHEN "0110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111100001000001111010111011010111011101000011000"; WHEN "0111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111011000000101111111110010010111000110100000100"; WHEN "0111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111001111001101001111000010001001010010011000111"; WHEN "0111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111000110010111101011110110110010100111101001111"; WHEN "0111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110111101100101011001011010111101100111001001111"; WHEN "0111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110110100110110011010110111111001010011111110011"; WHEN "0111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110101100001010110011010101010111111100100001011"; WHEN "0111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110100011100010100101111001101101100100000011010"; WHEN "0111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110011010111101110101101001101110101101001000101"; WHEN "1000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110010010011100100101101000101111000100111000101"; WHEN "1000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110001001111110111000111000100000001110100110010"; WHEN "1000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110000001100100110010011001010000010000100100001"; WHEN "1000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101111001001110010101001001101000100001000011111"; WHEN "1000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101110000111011100100000110101100010100101111011"; WHEN "1000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101101000101100100010001011110111101101010011001"; WHEN "1000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101100000100001010010010010111110001001000100100"; WHEN "1000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101011000011001110111010100001001010011011010001"; WHEN "1001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101010000010110010100000101110111110101110111011"; WHEN "1001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101001000010110101011011100111100001010010001010"; WHEN "1001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101000000011011000000001100011011001101001101101"; WHEN "1001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100111000100011010101000101101011010001111110100"; WHEN "1001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100110000101111101100111000010010110110101001010"; WHEN "1001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100101001000000001010010010000111011001100101001"; WHEN "1001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100100001010100101111111111001100001111011011000"; WHEN "1001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100011001101101100000101001110001011001110111100"; WHEN "1010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100010010001010011110111010010010011111110100100"; WHEN "1010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100001010101011101101010111010101100101110000010"; WHEN "1010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100000011010001001110100101101010000111010011101"; WHEN "1010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011111011111011000101001000000111110001110111111"; WHEN "1010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011110100101001010011011111101101011111101000010"; WHEN "1010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011101101011011111100001011100000010100000001101"; WHEN "1010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011100110010011000001101000101010011000110001101"; WHEN "1010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011111001110100110010010011001111011110111011"; WHEN "1011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011000001110101100100010000000001110100011101"; WHEN "1011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011010001010011010110101110110000100101001100010"; WHEN "1011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011001010011100100111001101111111011000001100001"; WHEN "1011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011000011101010100000010011000001000101101011001"; WHEN "1011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010111100111101000100001111001001010100001001100"; WHEN "1011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010110110010100010101010001101001110110001111011"; WHEN "1011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101111110000010101100111110001101111011011100"; WHEN "1011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101001010001000111011100101100011001011100101"; WHEN "1100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010100010110110101100111001100000101011000010000"; WHEN "1100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010011100100001001000000101001111111111010110011"; WHEN "1100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010110010000011011000100110101011110110000011"; WHEN "1100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010000000100100111111011000101001000001000001"; WHEN "1100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010001001111101110000101000101010111011100100101"; WHEN "1100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010000011111011110111001100001010000110000001000"; WHEN "1100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111101111110111101100001111100001101100011111"; WHEN "1100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111000000111000101100100010000011111010101010"; WHEN "1101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001110010010100010001001011001010111110000100010"; WHEN "1101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001101100100110100010001100100011110001100110110"; WHEN "1101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100110111101111010011100000110010111101110011"; WHEN "1101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100001011010011011101011010000110101111000110"; WHEN "1101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001011011111100000111101001010011001011111101101"; WHEN "1101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010110100011000000000011001110101000000001010"; WHEN "1101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010001001111000110100011110100111011011010110"; WHEN "1101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001001100000000011100110011100111110000011010110"; WHEN "1110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000110110111000100011000111000000001100101100"; WHEN "1110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000001110010111110110111100101010001100011100"; WHEN "1110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000111100110100001101110001011101000100010101000"; WHEN "1110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110111111010110010100101111010011001100111001"; WHEN "1110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110011000110101110110010000101000111111101001"; WHEN "1110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101110011000000011110000110001011001010001101"; WHEN "1110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101001101110110010111010011111001000001110011"; WHEN "1110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100101001010111101100101011001011110111111001"; WHEN "1111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100000101100100101000101010110010110110110011"; WHEN "1111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011100010011101010101011110101111000111101111"; WHEN "1111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011000000000001111101000000010000000010001101"; WHEN "1111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000010011110010010101000110101101111100100010110"; WHEN "1111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001111101001111100010010010101110110011110010"; WHEN "1111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001011100111000110010010111110010100110111110"; WHEN "1111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000111101001110100001110010100000011000001001"; WHEN "1111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000011110010000111000111101011011000001000111"; WHEN OTHERS => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; END CASE; -- End reserved scope level END PROCESS; --cIncludingRoundingBit_uid253_sinPiZPolyEval(BITJOIN,252)@26 cIncludingRoundingBit_uid253_sinPiZPolyEval_q <= memoryC1_uid227_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0(REG,408)@26 reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid253_sinPiZPolyEval_q; END IF; END PROCESS; --ts4_uid254_sinPiZPolyEval(ADD,253)@27 ts4_uid254_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((52 downto 52 => reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q(51)) & reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q); ts4_uid254_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((52 downto 46 => reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q(45)) & reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q); ts4_uid254_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid254_sinPiZPolyEval_a) + SIGNED(ts4_uid254_sinPiZPolyEval_b)); ts4_uid254_sinPiZPolyEval_q <= ts4_uid254_sinPiZPolyEval_o(52 downto 0); --s4_uid255_sinPiZPolyEval(BITSELECT,254)@27 s4_uid255_sinPiZPolyEval_in <= ts4_uid254_sinPiZPolyEval_q; s4_uid255_sinPiZPolyEval_b <= s4_uid255_sinPiZPolyEval_in(52 downto 1); --yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval(BITSELECT,301)@27 yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b; yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in(51 downto 25); --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9(REG,409)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor(LOGICAL,1117) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q <= not (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a or ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top(CONSTANT,1113) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q <= "010011"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp(LOGICAL,1114) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a = ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b else "0"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg(REG,1115) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena(REG,1118) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q = "1") THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd(LOGICAL,1119) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a and ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b; --xBottomBits_uid305_pT5_uid257_sinPiZPolyEval(BITSELECT,304)@5 xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b(17 downto 0); xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt(COUNTER,1109) -- every=1, low=0, high=19, step=1, init=1 ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i = 18 THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '1'; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i - 19; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i,5)); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg(REG,1110) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux(MUX,1111) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q) BEGIN CASE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s IS WHEN "0" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; WHEN "1" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; WHEN OTHERS => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem(DUALMEM,1108) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 <= areset; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 5, numwords_a => 20, width_b => 18, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0, clock1 => clk, address_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq, address_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa, data_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia ); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg(DELAY,1107) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q, xout => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q, clk => clk, aclr => areset ); --pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval(BITJOIN,306)@27 pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7(REG,411)@27 reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid304_pT5_uid257_sinPiZPolyEval(BITSELECT,303)@27 yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b(24 downto 0); yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b <= yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a(DELAY,750)@27 ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b, xout => ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval(BITJOIN,305)@28 spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q; --pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval(BITJOIN,307)@28 pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q <= spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q & GND_q; --reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6(REG,410)@28 reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor(LOGICAL,1104) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top(CONSTANT,1100) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q <= "010100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp(LOGICAL,1101) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg(REG,1102) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena(REG,1105) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd(LOGICAL,1106) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1096) -- every=1, low=0, high=20, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i = 19 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i - 20; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i,5)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg(REG,1097) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux(MUX,1098) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem(DUALMEM,1095) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 5, numwords_a => 21, width_b => 45, widthad_b => 5, numwords_b => 21, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg(DELAY,1094) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval(BITSELECT,300)@28 xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q; xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in(44 downto 18); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4(REG,412)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma(CHAINMULTADD,347)@29 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval(BITSELECT,309)@32 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in(54 downto 1); --highBBits_uid312_pT5_uid257_sinPiZPolyEval(BITSELECT,311)@32 highBBits_uid312_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b; highBBits_uid312_pT5_uid257_sinPiZPolyEval_b <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_in(53 downto 25); --reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1(REG,415)@32 reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1(REG,413)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b(DELAY,747)@28 ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0(REG,414)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid303_pT5_uid257_sinPiZPolyEval(MULT,302)@29 topProd_uid303_pT5_uid257_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_b); topProd_uid303_pT5_uid257_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid303_pT5_uid257_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid303_pT5_uid257_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0(REG,416)@32 reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid313_pT5_uid257_sinPiZPolyEval(ADD,312)@33 sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q(53)) & reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b)); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid311_pT5_uid257_sinPiZPolyEval(BITSELECT,310)@32 lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b(24 downto 0); lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b <= lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a(DELAY,758)@32 ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b, xout => ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid311_uid314_pT5_uid257_sinPiZPolyEval(BITJOIN,313)@33 add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q & ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q; --R_uid315_pT5_uid257_sinPiZPolyEval(BITSELECT,314)@33 R_uid315_pT5_uid257_sinPiZPolyEval_in <= add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q(78 downto 0); R_uid315_pT5_uid257_sinPiZPolyEval_b <= R_uid315_pT5_uid257_sinPiZPolyEval_in(78 downto 25); --reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1(REG,417)@33 reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= R_uid315_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor(LOGICAL,1142) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1138) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q <= "011001"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp(LOGICAL,1139) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg(REG,1140) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena(REG,1143) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1144) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1134) -- every=1, low=0, high=25, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i = 24 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i - 25; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg(REG,1135) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1136) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1133) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 26, width_b => 7, widthad_b => 5, numwords_b => 26, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg(DELAY,1132) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0(REG,379)@32 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC0_uid226_sinPiZTableGenerator(LOOKUP,225)@33 memoryC0_uid226_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; WHEN "0000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111010001111111001101111011000111100001001010"; WHEN "0000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000101010101111101111010001101100110011111100100"; WHEN "0000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000010000111010001110111000001110010011001110001"; WHEN "0000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001111101100101111100010000110111011000000101000010"; WHEN "0000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110111110001111110110010110011100111000110011101"; WHEN "0000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110000101011011011100110100000100010100111010101"; WHEN "0000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001101000010010010101010100001100000100101011101101"; WHEN "0001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001011110100110101111000010100110110100001011000010"; WHEN "0001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001010011101000101100010111000010101101001011110101"; WHEN "0001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001000111011000010001010101010001011100000010111010"; WHEN "0001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000111001110101100010011111100010101010110110110111"; WHEN "0001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000101011000000100100110110100010000001101000110010"; WHEN "0001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000011010111001011101111001010100111001000011000110"; WHEN "0001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000001001100000010011100101010111111111101111100110"; WHEN "0001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111110110110101001100010110011100110010010101101111"; WHEN "0010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111100010111000001111000110100110100110000010101111"; WHEN "0010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111001101101001100011001110000111100101111100011100"; WHEN "0010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110110111001001010000100011011101100011000000101111"; WHEN "0010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110011111010111011111011011001110010110110010111000"; WHEN "0010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110000110010100011000101000000100011000111000100110"; WHEN "0010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101101100000000000101011010101010100111001000011100"; WHEN "0010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101010000011010101111100001101000100000101011011110"; WHEN "0010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100110011100100100001001001011101110011110100001011"; WHEN "0011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100010101011101100100111100011101111110101100100111"; WHEN "0011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011110110000110000110000010101011100010111110000011"; WHEN "0011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011010101011110010000000001110011001100010100001001"; WHEN "0011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010110011100110001110111101000110101001111110010101"; WHEN "0011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010010000011110001111010101010111011011010001011111"; WHEN "0011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001101100000110011110001000110001001111001100110001"; WHEN "0011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001000110011111001000110010110100010111000011111111"; WHEN "0011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001000011111101000011101001100001111101100010010011001"; WHEN "0100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111110111100010101001101010111010101001011000110001"; WHEN "0100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111001110001101111101000001101110110110001001100100"; WHEN "0100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000110100011101010100110100000100001100111000110001110"; WHEN "0100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101110111111000110101110011111101010000010000111000"; WHEN "0100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101001010111000111011000101011010001011010101011100"; WHEN "0100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000100011100101011000110111010110111110001001101100111"; WHEN "0100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000011101101001111101010010110110101000111000011000010"; WHEN "0100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010111100100110110110111000001001011110110011001101"; WHEN "0101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010001010110000111110011001111100101011011000101100"; WHEN "0101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000001010111101110010011010011011111001000011101001111"; WHEN "0101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000000100011011111001000011000000001110101111000110101"; WHEN "0101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111111101110000011110000110110101110000111000001001000"; WHEN "0101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111110110111011100100000011010011101000101101101101111"; WHEN "0101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101111111101001101011001001101111001001010100111010"; WHEN "0101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101000110101011100101100110100011000001100101000111"; WHEN "0101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111100001100100010100100101110001100110101011111100110"; WHEN "0110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111011010001001110111101111001001100110110011000001101"; WHEN "0110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111010010100110001000110111011000110000110111110111111"; WHEN "0110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111001010111001001010110000010010100110110110111111101"; WHEN "0110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111000011000011000000001111000000100110010000101101101"; WHEN "0110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110111011000011101100001100000000111000101001011011010"; WHEN "0110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110110010111011010001100011000101000010101101011001001"; WHEN "0110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110101010101001110011010011010000110001111000101001011"; WHEN "0110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110100010001111010100011110111000101000100011101001111"; WHEN "0111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110011001101011111000001011100000101000110101010111101"; WHEN "0111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110010000111111100001100001111010111101111011010000110"; WHEN "0111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110001000001010010011101110000110100100001000000010111"; WHEN "0111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101111111001100010001111111001101101111011001101100100"; WHEN "0111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101110110000101011111100111100100110000100111011101101"; WHEN "0111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101101100110101111111111100101000011001011000100010101"; WHEN "0111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101100011011101110110010110111100011110100100000110011"; WHEN "0111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101011001111101000110010010001010011001011011010110110"; WHEN "1000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101010000010011110011001100111111100111011110011001101"; WHEN "1000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101000110100010000000101001001100001000111100100001001"; WHEN "1000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100111100100111110010001011100000111110000000101011101"; WHEN "1000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100110010100101001011011011101110100010101011000001110"; WHEN "1000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100101000011010010000000100100011001001010111111110011"; WHEN "1000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100011110000111000011110011101001010100010101110100101"; WHEN "1000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100010011101011101010011001100110001101101001100010111"; WHEN "1000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100001001001000000111101001110111111110000011100100111"; WHEN "1001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011111110011100011111011010110100000010100101010111001"; WHEN "1001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011110011101000110101100101100101100000111000011110001"; WHEN "1001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011101000101101001110000110001011011010011000000110010"; WHEN "1001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011011101101001101100111011010110111110001101101101010"; WHEN "1001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011010010011110010110000110101001111010000001101101100"; WHEN "1001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011000111001011001101101100010100101001100000111100110"; WHEN "1001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010111011110000010111110011010100100100110111110110011"; WHEN "1001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010110000001101111000100101010010001110000100000110101"; WHEN "1010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010100100100011110100001110011111011100111101101011110"; WHEN "1010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010011000110010001110111101110101101010011000000111111"; WHEN "1010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010001100111001001101000100110011111001111100111000001"; WHEN "1010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010000000111000110010110111011101000010111111101010001"; WHEN "1010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001110100110001000100101100010101111000001101101010100"; WHEN "1010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001101000100010000110111100100011001110011000100010010"; WHEN "1010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001011100001011111110000011101000000001111110000000000"; WHEN "1010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001001111101110101110011111100011011011101101000101110"; WHEN "1011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001000011001010011100110000101110110100001001110110000"; WHEN "1011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000110110011111001101011001111011110110010000011100000"; WHEN "1011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000101001101101000101000000010010100000111000101001110"; WHEN "1011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000011100110100001000001011001111000111011010101001101"; WHEN "1011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000001111110100011011100100100000010001010101111111000"; WHEN "1011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000000010101110000011111000000100111000111011110010110"; WHEN "1011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111110101100001000101110100001010001000111101001001101"; WHEN "1011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111101000001101100110001001001001011001011110100011010"; WHEN "1100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111011010110011101001101001100110001011110001011110000"; WHEN "1100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111001101010011010101001010001100000101010101000000111"; WHEN "1100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110111111101100101101100001101100101001111110101000001"; WHEN "1100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110110001111111110111101000111101010101001011110111000"; WHEN "1100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110100100001100111000011010110101010010011110001011110"; WHEN "1100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110010110010011110100110100001011010101000001111000001"; WHEN "1100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110001000010100110001110011110011101110100000111111001"; WHEN "1100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101111010001111110100011010011110000101000011010111010"; WHEN "1101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101101100000101000001101010110011001000011100110100101"; WHEN "1101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101011101110100011110101001010010100110101010011100110"; WHEN "1101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101001111011110010000011100010000111111100000000100011"; WHEN "1101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101000001000010011100001011110101010111100110111011100"; WHEN "1101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100110010100001000111000001110111001010101110101010001"; WHEN "1101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100100011111010010110001001111011111101010001100000100"; WHEN "1101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100010101001110001110110001010101001101001100111101111"; WHEN "1101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100000110011100110110000110111110000010001111110011101"; WHEN "1110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011110111100110010001011011011000111101011110100101010"; WHEN "1110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011101000101010100110000000101101101000001111101101101"; WHEN "1110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011011001101001111001001010100110100010100000001010111"; WHEN "1110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011001010100100010000001110001110110000100001110111001"; WHEN "1110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010111011011001110000100010001111101000000100110100000"; WHEN "1110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010101100001010011111011110101110011100111100001100101"; WHEN "1110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010011100110110100010011101001010001101000000010101011"; WHEN "1110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010001101011101111110111000011001001011101110101101100"; WHEN "1111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001111110000000111010001100100110101101001001001010110"; WHEN "1111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001101110011111011001110111010000110000010101010100001"; WHEN "1111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001011110111001100011010111000101101001011101010010011"; WHEN "1111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001001111001111011100001100000001101011010010111101001"; WHEN "1111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000111111100001001001110111001100110000010110101011110"; WHEN "1111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000101111101110110001111010111000000011100010110001010"; WHEN "1111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000011111111000011001111010011011101000011100101001111"; WHEN "1111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000001111111110000111011010010100000011001101000010011"; WHEN OTHERS => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid258_sinPiZPolyEval(CONSTANT,257) rndBit_uid258_sinPiZPolyEval_q <= "001"; --cIncludingRoundingBit_uid259_sinPiZPolyEval(BITJOIN,258)@33 cIncludingRoundingBit_uid259_sinPiZPolyEval_q <= memoryC0_uid226_sinPiZTableGenerator_q & rndBit_uid258_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0(REG,418)@33 reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid259_sinPiZPolyEval_q; END IF; END PROCESS; --ts5_uid260_sinPiZPolyEval(ADD,259)@34 ts5_uid260_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q); ts5_uid260_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((61 downto 54 => reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q(53)) & reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q); ts5_uid260_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid260_sinPiZPolyEval_a) + SIGNED(ts5_uid260_sinPiZPolyEval_b)); ts5_uid260_sinPiZPolyEval_q <= ts5_uid260_sinPiZPolyEval_o(61 downto 0); --s5_uid261_sinPiZPolyEval(BITSELECT,260)@34 s5_uid261_sinPiZPolyEval_in <= ts5_uid260_sinPiZPolyEval_q; s5_uid261_sinPiZPolyEval_b <= s5_uid261_sinPiZPolyEval_in(61 downto 1); --fxpSinRes_uid66_fpSinPiTest(BITSELECT,65)@34 fxpSinRes_uid66_fpSinPiTest_in <= s5_uid261_sinPiZPolyEval_b(58 downto 0); fxpSinRes_uid66_fpSinPiTest_b <= fxpSinRes_uid66_fpSinPiTest_in(58 downto 5); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor(LOGICAL,963) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q <= not (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a or ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top(CONSTANT,959) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q <= "011111"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp(LOGICAL,960) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q <= "1" when ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a = ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b else "0"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg(REG,961) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena(REG,964) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q = "1") THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd(LOGICAL,965) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a and ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt(COUNTER,955) -- every=1, low=0, high=31, step=1, init=1 ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ELSIF (clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg(REG,956) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux(MUX,957) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux: PROCESS (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem(DUALMEM,954) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia <= sinXIsX_uid30_fpSinPiTest_c; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 32, width_b => 1, widthad_b => 5, numwords_b => 32, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq, address_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa, data_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia ); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg(DELAY,953) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --multRightOp_uid68_fpSinPiTest(MUX,67)@34 multRightOp_uid68_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q; multRightOp_uid68_fpSinPiTest: PROCESS (multRightOp_uid68_fpSinPiTest_s, fxpSinRes_uid66_fpSinPiTest_b) BEGIN CASE multRightOp_uid68_fpSinPiTest_s IS WHEN "0" => multRightOp_uid68_fpSinPiTest_q <= fxpSinRes_uid66_fpSinPiTest_b; WHEN "1" => multRightOp_uid68_fpSinPiTest_q <= piwFP2_uid67_fpSinPiTest_q; WHEN OTHERS => multRightOp_uid68_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_b_1(BITSELECT,318)@34 mul2xSinRes_uid69_fpSinPiTest_b_1_in <= multRightOp_uid68_fpSinPiTest_q; mul2xSinRes_uid69_fpSinPiTest_b_1_b <= mul2xSinRes_uid69_fpSinPiTest_b_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1(REG,423)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor(LOGICAL,1129) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q <= not (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a or ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top(CONSTANT,1125) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q <= "010110"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp(LOGICAL,1126) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q <= "1" when ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a = ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b else "0"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg(REG,1127) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena(REG,1130) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q = "1") THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd(LOGICAL,1131) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a and ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor(LOGICAL,937) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a or ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top(CONSTANT,933) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q <= "0111"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp(LOGICAL,934) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a = ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b else "0"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg(REG,935) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena(REG,938) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q = "1") THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd(LOGICAL,939) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt(COUNTER,929) -- every=1, low=0, high=7, step=1, init=1 ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,3); ELSIF (clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i + 1; END IF; END PROCESS; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i,3)); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg(REG,930) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux(MUX,931) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q) BEGIN CASE ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s IS WHEN "0" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; WHEN "1" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; WHEN OTHERS => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem(DUALMEM,928) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 <= areset; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia <= oFracX_uid31_uid31_fpSinPiTest_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 3, numwords_a => 8, width_b => 53, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq, address_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa, data_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia ); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq(52 downto 0); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg(DELAY,927) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg : dspba_delay GENERIC MAP ( width => 53, depth => 1 ) PORT MAP ( xin => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q, xout => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q, clk => clk, aclr => areset ); --LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest(BITSELECT,220)@10 LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q(77 downto 0); LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in(77 downto 0); --leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest(BITJOIN,221)@10 leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b & GND_q; --LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest(BITSELECT,204)@9 LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(54 downto 0); LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in(54 downto 0); --leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest(BITJOIN,205)@9 leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest(BITSELECT,201)@9 LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(62 downto 0); LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in(62 downto 0); --leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest(BITJOIN,202)@9 leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest(BITSELECT,198)@9 LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(70 downto 0); LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in(70 downto 0); --leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest(BITJOIN,199)@9 leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --ozz_uid41_fpSinPiTest(CONSTANT,40) ozz_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor(LOGICAL,1040) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q <= not (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a or ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top(CONSTANT,1036) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q <= "011"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp(LOGICAL,1037) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q <= "1" when ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a = ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b else "0"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg(REG,1038) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena(REG,1041) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q = "1") THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd(LOGICAL,1042) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a and ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b; --vStage_uid149_lzcZ_uid51_fpSinPiTest(BITSELECT,148)@4 vStage_uid149_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(14 downto 0); vStage_uid149_lzcZ_uid51_fpSinPiTest_b <= vStage_uid149_lzcZ_uid51_fpSinPiTest_in(14 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt(COUNTER,1032) -- every=1, low=0, high=3, step=1, init=1 ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,2); ELSIF (clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i,2)); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg(REG,1033) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux(MUX,1034) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1043) ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= vStage_uid149_lzcZ_uid51_fpSinPiTest_b; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 2, numwords_a => 4, width_b => 15, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(14 downto 0); --leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest(BITJOIN,193)@9 leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X46dto0_uid190_alignedZ_uid52_fpSinPiTest(BITSELECT,189)@4 X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(46 downto 0); X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in(46 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1031) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 47, widthad_a => 2, numwords_a => 4, width_b => 47, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(46 downto 0); --leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest(BITJOIN,190)@9 leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor(LOGICAL,1065) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q <= not (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a or ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top(CONSTANT,1061) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q <= "010"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp(LOGICAL,1062) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q <= "1" when ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a = ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b else "0"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg(REG,1063) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena(REG,1066) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q = "1") THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd(LOGICAL,1067) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a and ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt(COUNTER,1057) -- every=1, low=0, high=2, step=1, init=1 ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i = 1 THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i - 2; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i,2)); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg(REG,1058) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux(MUX,1059) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux: PROCESS (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem(DUALMEM,1056) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia <= z_uid49_fpSinPiTest_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 79, widthad_a => 2, numwords_a => 3, width_b => 79, widthad_b => 2, numwords_b => 3, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq, address_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa, data_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia ); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq(78 downto 0); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg(DELAY,1055) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q, xout => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --rVStage_uid146_lzcZ_uid51_fpSinPiTest(BITSELECT,145)@4 rVStage_uid146_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; rVStage_uid146_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_in(78 downto 15); --reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0(REG,365)@4 reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid147_lzcZ_uid51_fpSinPiTest(LOGICAL,146)@5 vCount_uid147_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid147_lzcZ_uid51_fpSinPiTest_a = vCount_uid147_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g(DELAY,629)@5 ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => vCount_uid147_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q, clk => clk, aclr => areset ); --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b(DELAY,587)@4 ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => vStage_uid149_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q, clk => clk, aclr => areset ); --mO_uid148_lzcZ_uid51_fpSinPiTest(CONSTANT,147) mO_uid148_lzcZ_uid51_fpSinPiTest_q <= "1111111111111111111111111111111111111111111111111"; --cStage_uid150_lzcZ_uid51_fpSinPiTest(BITJOIN,149)@5 cStage_uid150_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q & mO_uid148_lzcZ_uid51_fpSinPiTest_q; --ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c(DELAY,589)@4 ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 64, depth => 1 ) PORT MAP ( xin => rVStage_uid146_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid152_lzcZ_uid51_fpSinPiTest(MUX,151)@5 vStagei_uid152_lzcZ_uid51_fpSinPiTest_s <= vCount_uid147_lzcZ_uid51_fpSinPiTest_q; vStagei_uid152_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid152_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, cStage_uid150_lzcZ_uid51_fpSinPiTest_q) BEGIN CASE vStagei_uid152_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= cStage_uid150_lzcZ_uid51_fpSinPiTest_q; WHEN OTHERS => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid154_lzcZ_uid51_fpSinPiTest(BITSELECT,153)@5 rVStage_uid154_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q; rVStage_uid154_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_in(63 downto 32); --reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0(REG,366)@5 reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= "00000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid155_lzcZ_uid51_fpSinPiTest(LOGICAL,154)@6 vCount_uid155_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid155_lzcZ_uid51_fpSinPiTest_a = vCount_uid155_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f(DELAY,628)@6 ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid155_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q, clk => clk, aclr => areset ); --vStage_uid156_lzcZ_uid51_fpSinPiTest(BITSELECT,155)@5 vStage_uid156_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q(31 downto 0); vStage_uid156_lzcZ_uid51_fpSinPiTest_b <= vStage_uid156_lzcZ_uid51_fpSinPiTest_in(31 downto 0); --ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d(DELAY,596)@5 ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => vStage_uid156_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c(DELAY,595)@5 ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => rVStage_uid154_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid158_lzcZ_uid51_fpSinPiTest(MUX,157)@6 vStagei_uid158_lzcZ_uid51_fpSinPiTest_s <= vCount_uid155_lzcZ_uid51_fpSinPiTest_q; vStagei_uid158_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid158_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid158_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid160_lzcZ_uid51_fpSinPiTest(BITSELECT,159)@6 rVStage_uid160_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q; rVStage_uid160_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_in(31 downto 16); --reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0(REG,367)@6 reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid161_lzcZ_uid51_fpSinPiTest(LOGICAL,160)@7 vCount_uid161_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid161_lzcZ_uid51_fpSinPiTest_a = vCount_uid161_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e(DELAY,627)@7 ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid161_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q, clk => clk, aclr => areset ); --vStage_uid162_lzcZ_uid51_fpSinPiTest(BITSELECT,161)@6 vStage_uid162_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q(15 downto 0); vStage_uid162_lzcZ_uid51_fpSinPiTest_b <= vStage_uid162_lzcZ_uid51_fpSinPiTest_in(15 downto 0); --ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d(DELAY,602)@6 ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => vStage_uid162_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c(DELAY,601)@6 ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => rVStage_uid160_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid164_lzcZ_uid51_fpSinPiTest(MUX,163)@7 vStagei_uid164_lzcZ_uid51_fpSinPiTest_s <= vCount_uid161_lzcZ_uid51_fpSinPiTest_q; vStagei_uid164_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid164_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid164_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid166_lzcZ_uid51_fpSinPiTest(BITSELECT,165)@7 rVStage_uid166_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q; rVStage_uid166_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_in(15 downto 8); --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0(REG,368)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid167_lzcZ_uid51_fpSinPiTest(LOGICAL,166)@8 vCount_uid167_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid167_lzcZ_uid51_fpSinPiTest_a = vCount_uid167_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid168_lzcZ_uid51_fpSinPiTest(BITSELECT,167)@7 vStage_uid168_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q(7 downto 0); vStage_uid168_lzcZ_uid51_fpSinPiTest_b <= vStage_uid168_lzcZ_uid51_fpSinPiTest_in(7 downto 0); --reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3(REG,369)@7 reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= vStage_uid168_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2(REG,370)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vStagei_uid170_lzcZ_uid51_fpSinPiTest(MUX,169)@8 vStagei_uid170_lzcZ_uid51_fpSinPiTest_s <= vCount_uid167_lzcZ_uid51_fpSinPiTest_q; vStagei_uid170_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid170_lzcZ_uid51_fpSinPiTest_s, reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q, reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q) BEGIN CASE vStagei_uid170_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q; WHEN "1" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q; WHEN OTHERS => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid172_lzcZ_uid51_fpSinPiTest(BITSELECT,171)@8 rVStage_uid172_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q; rVStage_uid172_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_in(7 downto 4); --vCount_uid173_lzcZ_uid51_fpSinPiTest(LOGICAL,172)@8 vCount_uid173_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; vCount_uid173_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; vCount_uid173_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid173_lzcZ_uid51_fpSinPiTest_a = vCount_uid173_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid174_lzcZ_uid51_fpSinPiTest(BITSELECT,173)@8 vStage_uid174_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q(3 downto 0); vStage_uid174_lzcZ_uid51_fpSinPiTest_b <= vStage_uid174_lzcZ_uid51_fpSinPiTest_in(3 downto 0); --vStagei_uid176_lzcZ_uid51_fpSinPiTest(MUX,175)@8 vStagei_uid176_lzcZ_uid51_fpSinPiTest_s <= vCount_uid173_lzcZ_uid51_fpSinPiTest_q; vStagei_uid176_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid176_lzcZ_uid51_fpSinPiTest_s, rVStage_uid172_lzcZ_uid51_fpSinPiTest_b, vStage_uid174_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid176_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= vStage_uid174_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid178_lzcZ_uid51_fpSinPiTest(BITSELECT,177)@8 rVStage_uid178_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q; rVStage_uid178_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_in(3 downto 2); --vCount_uid179_lzcZ_uid51_fpSinPiTest(LOGICAL,178)@8 vCount_uid179_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; vCount_uid179_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; vCount_uid179_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid179_lzcZ_uid51_fpSinPiTest_a = vCount_uid179_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid180_lzcZ_uid51_fpSinPiTest(BITSELECT,179)@8 vStage_uid180_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q(1 downto 0); vStage_uid180_lzcZ_uid51_fpSinPiTest_b <= vStage_uid180_lzcZ_uid51_fpSinPiTest_in(1 downto 0); --vStagei_uid182_lzcZ_uid51_fpSinPiTest(MUX,181)@8 vStagei_uid182_lzcZ_uid51_fpSinPiTest_s <= vCount_uid179_lzcZ_uid51_fpSinPiTest_q; vStagei_uid182_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid182_lzcZ_uid51_fpSinPiTest_s, rVStage_uid178_lzcZ_uid51_fpSinPiTest_b, vStage_uid180_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid182_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= vStage_uid180_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid184_lzcZ_uid51_fpSinPiTest(BITSELECT,183)@8 rVStage_uid184_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid51_fpSinPiTest_q; rVStage_uid184_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_in(1 downto 1); --vCount_uid185_lzcZ_uid51_fpSinPiTest(LOGICAL,184)@8 vCount_uid185_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_b; vCount_uid185_lzcZ_uid51_fpSinPiTest_b <= GND_q; vCount_uid185_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid185_lzcZ_uid51_fpSinPiTest_a = vCount_uid185_lzcZ_uid51_fpSinPiTest_b else "0"; --r_uid186_lzcZ_uid51_fpSinPiTest(BITJOIN,185)@8 r_uid186_lzcZ_uid51_fpSinPiTest_q <= ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q & ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q & ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q & vCount_uid167_lzcZ_uid51_fpSinPiTest_q & vCount_uid173_lzcZ_uid51_fpSinPiTest_q & vCount_uid179_lzcZ_uid51_fpSinPiTest_q & vCount_uid185_lzcZ_uid51_fpSinPiTest_q; --leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest(BITSELECT,195)@8 leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q; leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in(6 downto 5); --reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1(REG,371)@8 reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest(MUX,196)@9 leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q, leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q; WHEN "01" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ozz_uid41_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest(BITSELECT,206)@8 leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(4 downto 0); leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in(4 downto 3); --reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1(REG,372)@8 reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest(MUX,207)@9 leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s, leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest(BITSELECT,215)@9 LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(72 downto 0); LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in(72 downto 0); --leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest(BITJOIN,216)@9 leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5(REG,374)@9 reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest(BITSELECT,212)@9 LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest(BITJOIN,213)@9 leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4(REG,375)@9 reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest(BITSELECT,209)@9 LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest(BITJOIN,210)@9 leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3(REG,376)@9 reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2(REG,377)@9 reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest(BITSELECT,217)@8 leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(2 downto 0); leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in(2 downto 1); --reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1(REG,373)@8 reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b(DELAY,657)@9 ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest(MUX,218)@10 leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s, reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q, reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q, reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q, reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q) BEGIN CASE leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q; WHEN "01" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q; WHEN "10" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q; WHEN "11" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q; WHEN OTHERS => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest(BITSELECT,222)@8 leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(0 downto 0); leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in(0 downto 0); --reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1(REG,378)@8 reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b(DELAY,665)@9 ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest(MUX,223)@10 leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s, leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q, leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q; WHEN "1" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --alignedZLow_uid53_fpSinPiTest(BITSELECT,52)@10 alignedZLow_uid53_fpSinPiTest_in <= leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q; alignedZLow_uid53_fpSinPiTest_b <= alignedZLow_uid53_fpSinPiTest_in(78 downto 27); --pHardCase_uid54_fpSinPiTest(BITJOIN,53)@10 pHardCase_uid54_fpSinPiTest_q <= alignedZLow_uid53_fpSinPiTest_b & GND_q; --ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b(DELAY,474)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 10 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q, clk => clk, aclr => areset ); --p_uid55_fpSinPiTest(MUX,54)@10 p_uid55_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q; p_uid55_fpSinPiTest: PROCESS (p_uid55_fpSinPiTest_s, pHardCase_uid54_fpSinPiTest_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q) BEGIN CASE p_uid55_fpSinPiTest_s IS WHEN "0" => p_uid55_fpSinPiTest_q <= pHardCase_uid54_fpSinPiTest_q; WHEN "1" => p_uid55_fpSinPiTest_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q; WHEN OTHERS => p_uid55_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt(COUNTER,1121) -- every=1, low=0, high=22, step=1, init=1 ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i = 21 THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i - 22; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i,5)); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg(REG,1122) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux(MUX,1123) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux: PROCESS (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q) BEGIN CASE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s IS WHEN "0" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; WHEN "1" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem(DUALMEM,1120) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 <= areset; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia <= p_uid55_fpSinPiTest_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 5, numwords_a => 23, width_b => 53, widthad_b => 5, numwords_b => 23, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq, address_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa, data_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia ); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq(52 downto 0); --mul2xSinRes_uid69_fpSinPiTest_a_1(BITSELECT,316)@34 mul2xSinRes_uid69_fpSinPiTest_a_1_in <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q); mul2xSinRes_uid69_fpSinPiTest_a_1_b <= mul2xSinRes_uid69_fpSinPiTest_a_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0(REG,424)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b1(MULT,322)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_b); mul2xSinRes_uid69_fpSinPiTest_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1(BITSELECT,329)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1(REG,425)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a_0(BITSELECT,315)@34 mul2xSinRes_uid69_fpSinPiTest_a_0_in <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_a_0_b <= mul2xSinRes_uid69_fpSinPiTest_a_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0(REG,426)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b1(MULT,321)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_b); mul2xSinRes_uid69_fpSinPiTest_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1(BITSELECT,327)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_zero_36(CONSTANT,332) mul2xSinRes_uid69_fpSinPiTest_zero_36_q <= "000000000000000000000000000"; --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2(BITJOIN,336)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1(BITSELECT,328)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_b_0(BITSELECT,317)@34 mul2xSinRes_uid69_fpSinPiTest_b_0_in <= multRightOp_uid68_fpSinPiTest_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_b_0_b <= mul2xSinRes_uid69_fpSinPiTest_b_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1(REG,421)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0(REG,422)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b0(MULT,320)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_b); mul2xSinRes_uid69_fpSinPiTest_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0(BITSELECT,325)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1(BITJOIN,335)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC(LOGICAL,340)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b; --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1(BITSELECT,330)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0(BITSELECT,326)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1(REG,419)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0(REG,420)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b0(MULT,319)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_b); mul2xSinRes_uid69_fpSinPiTest_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0(BITSELECT,324)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0(BITSELECT,323)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0(BITJOIN,334)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC(LOGICAL,339)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB(LOGICAL,338)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne(LOGICAL,341)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c; --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS(BITSELECT,342)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q(106 downto 0); mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in(106 downto 0); --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ(BITJOIN,343)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b & GND_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b(BITJOIN,350)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b(BITSELECT,353)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne(LOGICAL,337)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a(BITJOIN,348)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a(BITSELECT,352)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2(ADD,354)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin <= GND_q; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b) & mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c(0) <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(90); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(89 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b(DELAY,822)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q, clk => clk, aclr => areset ); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a(DELAY,821)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2(ADD,355)@39 mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q) & mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o(20 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a(DELAY,824)@39 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a : dspba_delay GENERIC MAP ( width => 89, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q(BITJOIN,356)@40 mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q; --normBit_uid70_fpSinPiTest(BITSELECT,69)@40 normBit_uid70_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(106 downto 0); normBit_uid70_fpSinPiTest_b <= normBit_uid70_fpSinPiTest_in(106 downto 106); --ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c(DELAY,497)@40 ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => normBit_uid70_fpSinPiTest_b, xout => ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q, clk => clk, aclr => areset ); --rndExpUpdate_uid75_uid76_fpSinPiTest(BITJOIN,75)@41 rndExpUpdate_uid75_uid76_fpSinPiTest_q <= ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q & cstAllZWF_uid10_fpSinPiTest_q & VCC_q; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor(LOGICAL,976) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q <= not (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a or ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top(CONSTANT,972) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q <= "011100"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp(LOGICAL,973) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a = ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b else "0"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg(REG,974) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena(REG,977) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q = "1") THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd(LOGICAL,978) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a and ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem(DUALMEM,941) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 <= areset; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia <= expX_uid6_fpSinPiTest_b; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 3, numwords_a => 7, width_b => 11, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq, address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa, data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia ); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq(10 downto 0); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg(DELAY,940) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q, clk => clk, aclr => areset ); --expXP1_uid58_fpSinPiTest(ADD,57)@9 expXP1_uid58_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q); expXP1_uid58_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & VCC_q); expXP1_uid58_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid58_fpSinPiTest_a) + UNSIGNED(expXP1_uid58_fpSinPiTest_b)); expXP1_uid58_fpSinPiTest_q <= expXP1_uid58_fpSinPiTest_o(11 downto 0); --expXP1R_uid59_fpSinPiTest(BITSELECT,58)@9 expXP1R_uid59_fpSinPiTest_in <= expXP1_uid58_fpSinPiTest_q(10 downto 0); expXP1R_uid59_fpSinPiTest_b <= expXP1R_uid59_fpSinPiTest_in(10 downto 0); --reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1(REG,427)@8 reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= r_uid186_lzcZ_uid51_fpSinPiTest_q; END IF; END PROCESS; --expHardCase_uid57_fpSinPiTest(SUB,56)@9 expHardCase_uid57_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid27_fpSinPiTest_q); expHardCase_uid57_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000" & reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q); expHardCase_uid57_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid57_fpSinPiTest_a) - UNSIGNED(expHardCase_uid57_fpSinPiTest_b)); expHardCase_uid57_fpSinPiTest_q <= expHardCase_uid57_fpSinPiTest_o(11 downto 0); --expHardCaseR_uid60_fpSinPiTest(BITSELECT,59)@9 expHardCaseR_uid60_fpSinPiTest_in <= expHardCase_uid57_fpSinPiTest_q(10 downto 0); expHardCaseR_uid60_fpSinPiTest_b <= expHardCaseR_uid60_fpSinPiTest_in(10 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b(DELAY,481)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 9 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q, clk => clk, aclr => areset ); --expP_uid61_fpSinPiTest(MUX,60)@9 expP_uid61_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q; expP_uid61_fpSinPiTest: PROCESS (expP_uid61_fpSinPiTest_s, expHardCaseR_uid60_fpSinPiTest_b, expXP1R_uid59_fpSinPiTest_b) BEGIN CASE expP_uid61_fpSinPiTest_s IS WHEN "0" => expP_uid61_fpSinPiTest_q <= expHardCaseR_uid60_fpSinPiTest_b; WHEN "1" => expP_uid61_fpSinPiTest_q <= expXP1R_uid59_fpSinPiTest_b; WHEN OTHERS => expP_uid61_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt(COUNTER,968) -- every=1, low=0, high=28, step=1, init=1 ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i = 27 THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i - 28; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg(REG,969) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux(MUX,970) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem(DUALMEM,967) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia <= expP_uid61_fpSinPiTest_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 29, width_b => 11, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq, address_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa, data_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia ); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq(10 downto 0); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg(DELAY,966) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q, xout => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --highRes_uid71_fpSinPiTest(BITSELECT,70)@40 highRes_uid71_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(105 downto 0); highRes_uid71_fpSinPiTest_b <= highRes_uid71_fpSinPiTest_in(105 downto 53); --lowRes_uid72_fpSinPiTest(BITSELECT,71)@40 lowRes_uid72_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(104 downto 0); lowRes_uid72_fpSinPiTest_b <= lowRes_uid72_fpSinPiTest_in(104 downto 52); --fracRCompPreRnd_uid73_fpSinPiTest(MUX,72)@40 fracRCompPreRnd_uid73_fpSinPiTest_s <= normBit_uid70_fpSinPiTest_b; fracRCompPreRnd_uid73_fpSinPiTest: PROCESS (fracRCompPreRnd_uid73_fpSinPiTest_s, lowRes_uid72_fpSinPiTest_b, highRes_uid71_fpSinPiTest_b) BEGIN CASE fracRCompPreRnd_uid73_fpSinPiTest_s IS WHEN "0" => fracRCompPreRnd_uid73_fpSinPiTest_q <= lowRes_uid72_fpSinPiTest_b; WHEN "1" => fracRCompPreRnd_uid73_fpSinPiTest_q <= highRes_uid71_fpSinPiTest_b; WHEN OTHERS => fracRCompPreRnd_uid73_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracPreRnd_uid74_uid74_fpSinPiTest(BITJOIN,73)@40 expFracPreRnd_uid74_uid74_fpSinPiTest_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q & fracRCompPreRnd_uid73_fpSinPiTest_q; --reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0(REG,428)@40 reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= expFracPreRnd_uid74_uid74_fpSinPiTest_q; END IF; END PROCESS; --expFracComp_uid77_fpSinPiTest(ADD,76)@41 expFracComp_uid77_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q); expFracComp_uid77_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & rndExpUpdate_uid75_uid76_fpSinPiTest_q); expFracComp_uid77_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid77_fpSinPiTest_a) + UNSIGNED(expFracComp_uid77_fpSinPiTest_b)); expFracComp_uid77_fpSinPiTest_q <= expFracComp_uid77_fpSinPiTest_o(64 downto 0); --expRComp_uid79_fpSinPiTest(BITSELECT,78)@41 expRComp_uid79_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(63 downto 0); expRComp_uid79_fpSinPiTest_b <= expRComp_uid79_fpSinPiTest_in(63 downto 53); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor(LOGICAL,1015) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q <= not (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a or ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top(CONSTANT,1011) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q <= "0100010"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp(LOGICAL,1012) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q <= "1" when ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a = ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b else "0"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg(REG,1013) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena(REG,1016) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q = "1") THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd(LOGICAL,1017) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a and ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b; --reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1(REG,429)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c(DELAY,516)@0 ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q, xout => ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b(DELAY,515)@0 ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => expXIsZero_uid15_fpSinPiTest_q, xout => ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q, clk => clk, aclr => areset ); --reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0(REG,361)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --excRZero_uid87_fpSinPiTest(LOGICAL,86)@3 excRZero_uid87_fpSinPiTest_a <= reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q; excRZero_uid87_fpSinPiTest_b <= ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q; excRZero_uid87_fpSinPiTest_c <= ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q; excRZero_uid87_fpSinPiTest_q <= excRZero_uid87_fpSinPiTest_a or excRZero_uid87_fpSinPiTest_b or excRZero_uid87_fpSinPiTest_c; --Or2ExcRZeroXIsInt_uid92_fpSinPiTest(LOGICAL,91)@3 Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a <= excRZero_uid87_fpSinPiTest_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b <= reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a or Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt(COUNTER,1007) -- every=1, low=0, high=34, step=1, init=1 ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i = 33 THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i - 34; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg(REG,1008) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux(MUX,1009) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux: PROCESS (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem(DUALMEM,1006) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 35, width_b => 1, widthad_b => 6, numwords_b => 35, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq, address_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa, data_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia ); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg(DELAY,1005) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q, xout => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --expRPostExc1_uid95_fpSinPiTest(MUX,94)@41 expRPostExc1_uid95_fpSinPiTest_s <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q; expRPostExc1_uid95_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE expRPostExc1_uid95_fpSinPiTest_s IS WHEN "0" => expRPostExc1_uid95_fpSinPiTest_q <= expRComp_uid79_fpSinPiTest_b; WHEN "1" => expRPostExc1_uid95_fpSinPiTest_q <= cstAllZWE_uid11_fpSinPiTest_q; WHEN OTHERS => expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --InvXIntExp_uid84_fpSinPiTest(LOGICAL,83)@2 InvXIntExp_uid84_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; InvXIntExp_uid84_fpSinPiTest_q <= not InvXIntExp_uid84_fpSinPiTest_a; --join_uid42_fpSinPiTest(BITJOIN,41)@2 join_uid42_fpSinPiTest_q <= VCC_q & ozz_uid41_fpSinPiTest_q; --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0(REG,359)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid43_fpSinPiTest(LOGICAL,42)@2 yIsZero_uid43_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q; yIsZero_uid43_fpSinPiTest_b <= join_uid42_fpSinPiTest_q; yIsZero_uid43_fpSinPiTest_q <= "1" when yIsZero_uid43_fpSinPiTest_a = yIsZero_uid43_fpSinPiTest_b else "0"; --And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest(LOGICAL,85)@2 And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b <= yIsZero_uid43_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c <= InvSinXIsX_uid80_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d <= InvXIntExp_uid84_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d; --Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest(LOGICAL,95)@1 Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a <= GND_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q <= Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a or Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b; --ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a(DELAY,528)@1 ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q, xout => ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q, clk => clk, aclr => areset ); --join_uid97_fpSinPiTest(BITJOIN,96)@2 join_uid97_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q & ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q; --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg(DELAY,1195) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => join_uid97_fpSinPiTest_q, xout => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q, clk => clk, aclr => areset ); --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem(DUALMEM,1196) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 <= areset; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 6, numwords_a => 37, width_b => 2, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0, clock1 => clk, address_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq, address_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa, data_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia ); ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq(1 downto 0); --reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1(REG,430)@41 reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q; END IF; END PROCESS; --expRPostExc_uid98_fpSinPiTest(MUX,97)@42 expRPostExc_uid98_fpSinPiTest_s <= reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q; expRPostExc_uid98_fpSinPiTest: PROCESS (expRPostExc_uid98_fpSinPiTest_s, expRPostExc1_uid95_fpSinPiTest_q) BEGIN CASE expRPostExc_uid98_fpSinPiTest_s IS WHEN "00" => expRPostExc_uid98_fpSinPiTest_q <= expRPostExc1_uid95_fpSinPiTest_q; WHEN "01" => expRPostExc_uid98_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q; WHEN "10" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN "11" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN OTHERS => expRPostExc_uid98_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --oneFracRPostExc2_uid90_fpSinPiTest(CONSTANT,89) oneFracRPostExc2_uid90_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracRComp_uid78_fpSinPiTest(BITSELECT,77)@41 fracRComp_uid78_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(52 downto 0); fracRComp_uid78_fpSinPiTest_b <= fracRComp_uid78_fpSinPiTest_in(52 downto 1); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor(LOGICAL,989) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q <= not (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a or ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top(CONSTANT,985) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q <= "0100001"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp(LOGICAL,986) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q <= "1" when ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a = ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b else "0"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg(REG,987) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena(REG,990) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q = "1") THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd(LOGICAL,991) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a and ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b; --reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1(REG,362)@3 reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= excRZero_uid87_fpSinPiTest_q; END IF; END PROCESS; --ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a(DELAY,517)@2 ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q, xout => ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q, clk => clk, aclr => areset ); --or_uid88_fpSinPiTest(LOGICAL,87)@4 or_uid88_fpSinPiTest_a <= ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q; or_uid88_fpSinPiTest_b <= reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q; or_uid88_fpSinPiTest_c <= GND_q; or_uid88_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN or_uid88_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN or_uid88_fpSinPiTest_q <= or_uid88_fpSinPiTest_a or or_uid88_fpSinPiTest_b or or_uid88_fpSinPiTest_c; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt(COUNTER,981) -- every=1, low=0, high=33, step=1, init=1 ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i = 32 THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i - 33; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg(REG,982) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux(MUX,983) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux: PROCESS (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem(DUALMEM,980) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia <= or_uid88_fpSinPiTest_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 34, width_b => 1, widthad_b => 6, numwords_b => 34, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq, address_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa, data_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia ); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg(DELAY,979) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q, xout => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --fracRPostExc1_uid89_fpSinPiTest(MUX,88)@41 fracRPostExc1_uid89_fpSinPiTest_s <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q; fracRPostExc1_uid89_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE fracRPostExc1_uid89_fpSinPiTest_s IS WHEN "0" => fracRPostExc1_uid89_fpSinPiTest_q <= fracRComp_uid78_fpSinPiTest_b; WHEN "1" => fracRPostExc1_uid89_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q; WHEN OTHERS => fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor(LOGICAL,1002) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q <= not (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a or ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top(CONSTANT,998) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q <= "0100110"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp(LOGICAL,999) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q <= "1" when ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a = ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b else "0"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg(REG,1000) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena(REG,1003) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q = "1") THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd(LOGICAL,1004) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a and ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg(DELAY,992) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q, xout => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q, clk => clk, aclr => areset ); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt(COUNTER,994) -- every=1, low=0, high=38, step=1, init=1 ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i = 37 THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i - 38; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg(REG,995) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux(MUX,996) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux: PROCESS (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem(DUALMEM,993) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 39, width_b => 1, widthad_b => 6, numwords_b => 39, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq, address_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa, data_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia ); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq(0 downto 0); --fracRPostExc_uid91_fpSinPiTest(MUX,90)@42 fracRPostExc_uid91_fpSinPiTest_s <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q; fracRPostExc_uid91_fpSinPiTest: PROCESS (fracRPostExc_uid91_fpSinPiTest_s, fracRPostExc1_uid89_fpSinPiTest_q) BEGIN CASE fracRPostExc_uid91_fpSinPiTest_s IS WHEN "0" => fracRPostExc_uid91_fpSinPiTest_q <= fracRPostExc1_uid89_fpSinPiTest_q; WHEN "1" => fracRPostExc_uid91_fpSinPiTest_q <= oneFracRPostExc2_uid90_fpSinPiTest_q; WHEN OTHERS => fracRPostExc_uid91_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid105_fpSinPiTest(BITJOIN,104)@42 R_uid105_fpSinPiTest_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q & expRPostExc_uid98_fpSinPiTest_q & fracRPostExc_uid91_fpSinPiTest_q; --ld_xIn_v_to_xOut_v_nor(LOGICAL,910) ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b); --ld_xIn_v_to_xOut_v_mem_top(CONSTANT,906) ld_xIn_v_to_xOut_v_mem_top_q <= "0100111"; --ld_xIn_v_to_xOut_v_cmp(LOGICAL,907) ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q; ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q); ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0"; --ld_xIn_v_to_xOut_v_cmpReg(REG,908) ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_sticky_ena(REG,911) ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q; END IF; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,912) ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q; ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b; --ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,902) -- every=1, low=0, high=39, step=1, init=1 ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 38 THEN ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1'; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; END IF; IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 39; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,6)); --ld_xIn_v_to_xOut_v_replace_rdreg(REG,903) ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_replace_rdmux(MUX,904) ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q; ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q) BEGIN CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q; WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,914) ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset; ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c; ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 6, numwords_a => 40, width_b => 8, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_c_to_xOut_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_c_to_xOut_c_replace_mem_iq, address_a => ld_xIn_c_to_xOut_c_replace_mem_aa, data_a => ld_xIn_c_to_xOut_c_replace_mem_ia ); ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0); --ld_xIn_c_to_xOut_c_outputreg(DELAY,913) ld_xIn_c_to_xOut_c_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset ); --ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,901) ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset; ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v; ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 40, width_b => 1, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_v_to_xOut_v_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_v_to_xOut_v_replace_mem_iq, address_a => ld_xIn_v_to_xOut_v_replace_mem_aa, data_a => ld_xIn_v_to_xOut_v_replace_mem_ia ); ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0); --ld_xIn_v_to_xOut_v_outputreg(DELAY,900) ld_xIn_v_to_xOut_v_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset ); --xOut(PORTOUT,4)@42 xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q; xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q; xOut_0 <= R_uid105_fpSinPiTest_q; end normal;
----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Debug Version 12.0 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from SinPiDPStratixVf400 -- VHDL created on Wed Sep 05 17:55:57 2012 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; USE work.SinPiDPStratixVf400_safe_path.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; -- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240 entity SinPiDPStratixVf400 is port ( xIn_v : in std_logic_vector(0 downto 0); xIn_c : in std_logic_vector(7 downto 0); xIn_0 : in std_logic_vector(63 downto 0); xOut_v : out std_logic_vector(0 downto 0); xOut_c : out std_logic_vector(7 downto 0); xOut_0 : out std_logic_vector(63 downto 0); clk : in std_logic; areset : in std_logic; bus_clk : in std_logic; h_areset : in std_logic ); end; architecture normal of SinPiDPStratixVf400 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (51 downto 0); signal cstAllZWE_uid11_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBias_uid12_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cstBiasPwF_uid13_fpSinPiTest_q : std_logic_vector (10 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0); signal biasM1_uid27_fpSinPiTest_q : std_logic_vector (10 downto 0); signal biasMwShift_uid29_fpSinPiTest_q : std_logic_vector (10 downto 0); signal shiftBias_uid32_fpSinPiTest_q : std_logic_vector (10 downto 0); signal cst01pWShift_uid34_fpSinPiTest_q : std_logic_vector (27 downto 0); signal ozz_uid41_fpSinPiTest_q : std_logic_vector (78 downto 0); signal cOne_uid44_fpSinPiTest_q : std_logic_vector (80 downto 0); signal oneMinusY_uid45_fpSinPiTest_a : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_b : std_logic_vector(81 downto 0); signal oneMinusY_uid45_fpSinPiTest_o : std_logic_vector (81 downto 0); signal oneMinusY_uid45_fpSinPiTest_q : std_logic_vector (81 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_a : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_b : std_logic_vector(84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_o : std_logic_vector (84 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal cmpYToOneMinusY_uid46_fpSinPiTest_c : std_logic_vector (0 downto 0); signal piwFP2_uid67_fpSinPiTest_q : std_logic_vector (53 downto 0); signal or_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_b : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_c : std_logic_vector(0 downto 0); signal or_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc1_uid89_fpSinPiTest_q : std_logic_vector (51 downto 0); signal oneFracRPostExc2_uid90_fpSinPiTest_q : std_logic_vector (51 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (10 downto 0); signal InvXIsInt_uid100_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIsInt_uid100_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (31 downto 0); signal leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (63 downto 0); signal leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (15 downto 0); signal leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (23 downto 0); signal leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (5 downto 0); signal mO_uid148_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (48 downto 0); signal memoryC3_uid229_sinPiZTableGenerator_q : std_logic_vector(34 downto 0); signal memoryC4_uid230_sinPiZTableGenerator_q : std_logic_vector(25 downto 0); signal memoryC5_uid231_sinPiZTableGenerator_q : std_logic_vector(16 downto 0); signal rndBit_uid246_sinPiZPolyEval_q : std_logic_vector (1 downto 0); signal rndBit_uid258_sinPiZPolyEval_q : std_logic_vector (2 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_a : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 : std_logic_vector (33 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr : SIGNED (34 downto 0); signal prodXY_uid263_pT1_uid233_sinPiZPolyEval_q : std_logic_vector (33 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_a : std_logic_vector (25 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal prodXY_uid266_pT2_uid239_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid271_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid288_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_a : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_pr : SIGNED (54 downto 0); signal topProd_uid303_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b0_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a0_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_a : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr : UNSIGNED (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a1_b1_q : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_zero_36_q : std_logic_vector (26 downto 0); type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(18 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y_type; type multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s : multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s_type; signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 : std_logic_vector(36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q : std_logic_vector (36 downto 0); type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s : multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y_type; type multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s : multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s_type; signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b : std_logic_vector(90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o : std_logic_vector (90 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : std_logic_vector(21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o : std_logic_vector (21 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin : std_logic_vector (0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q : std_logic_vector (19 downto 0); signal reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q : std_logic_vector (80 downto 0); signal reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q : std_logic_vector (80 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q : std_logic_vector (79 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q : std_logic_vector (0 downto 0); signal reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q : std_logic_vector (79 downto 0); signal reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (31 downto 0); signal reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (15 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q : std_logic_vector (7 downto 0); signal reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q : std_logic_vector (7 downto 0); signal reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q : std_logic_vector (7 downto 0); signal reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q : std_logic_vector (78 downto 0); signal reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q : std_logic_vector (78 downto 0); signal reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q : std_logic_vector (16 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q : std_logic_vector (25 downto 0); signal reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0); signal reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0); signal reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q : std_logic_vector (17 downto 0); signal reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q : std_logic_vector (17 downto 0); signal reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q : std_logic_vector (16 downto 0); signal reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q : std_logic_vector (17 downto 0); signal reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q : std_logic_vector (36 downto 0); signal reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q : std_logic_vector (44 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q : std_logic_vector (45 downto 0); signal reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q : std_logic_vector (51 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0); signal reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0); signal reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q : std_logic_vector (25 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q : std_logic_vector (26 downto 0); signal reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0); signal reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (26 downto 0); signal reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0); signal reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0); signal reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q : std_logic_vector (53 downto 0); signal reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q : std_logic_vector (60 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q : std_logic_vector (26 downto 0); signal reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q : std_logic_vector (26 downto 0); signal reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q : std_logic_vector (6 downto 0); signal reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q : std_logic_vector (63 downto 0); signal reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q : std_logic_vector (1 downto 0); signal ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q : std_logic_vector (78 downto 0); signal ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q : std_logic_vector (78 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q : std_logic_vector (78 downto 0); signal ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q : std_logic_vector (14 downto 0); signal ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (63 downto 0); signal ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (31 downto 0); signal ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (31 downto 0); signal ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q : std_logic_vector (15 downto 0); signal ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q : std_logic_vector (15 downto 0); signal ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q : std_logic_vector (0 downto 0); signal ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q : std_logic_vector (0 downto 0); signal ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (1 downto 0); signal ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0); signal ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (42 downto 0); signal ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0); signal ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0); signal ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q : std_logic_vector (19 downto 0); signal ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q : std_logic_vector (88 downto 0); signal ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q : std_logic_vector (79 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic; signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(5 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic; signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (6 downto 0); signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic; signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0); signal ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 : std_logic; signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q : std_logic_vector (52 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i : unsigned(2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q : std_logic_vector (3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq : std_logic; signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ir : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q : std_logic_vector (10 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ir : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i : unsigned(5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q : std_logic_vector (6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (46 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i : unsigned(1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q : std_logic_vector (2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 : std_logic; signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ir : std_logic_vector (14 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q : std_logic_vector (14 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ir : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q : std_logic_vector (78 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i : unsigned(1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq : std_logic; signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q : std_logic_vector (2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ir : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q : std_logic_vector (17 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq : std_logic; signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q : std_logic_vector (5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ir : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q : std_logic_vector (52 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq : std_logic; signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ir : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q : std_logic_vector (25 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ir : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q : std_logic_vector (6 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq : std_logic; signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 : std_logic; signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ir : std_logic_vector (1 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0); signal yIsZero_uid40_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid40_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (18 downto 0); signal pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal z_uid49_fpSinPiTest_s : std_logic_vector (0 downto 0); signal z_uid49_fpSinPiTest_q : std_logic_vector (78 downto 0); signal expHardCase_uid57_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expHardCase_uid57_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expHardCase_uid57_fpSinPiTest_q : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_a : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_b : std_logic_vector(11 downto 0); signal expXP1_uid58_fpSinPiTest_o : std_logic_vector (11 downto 0); signal expXP1_uid58_fpSinPiTest_q : std_logic_vector (11 downto 0); signal rndExpUpdate_uid75_uid76_fpSinPiTest_q : std_logic_vector (53 downto 0); signal expFracComp_uid77_fpSinPiTest_a : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_b : std_logic_vector(64 downto 0); signal expFracComp_uid77_fpSinPiTest_o : std_logic_vector (64 downto 0); signal expFracComp_uid77_fpSinPiTest_q : std_logic_vector (64 downto 0); signal fracRPostExc_uid91_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostExc_uid91_fpSinPiTest_q : std_logic_vector (51 downto 0); signal expRPostExc_uid98_fpSinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid98_fpSinPiTest_q : std_logic_vector (10 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal memoryC0_uid226_sinPiZTableGenerator_q : std_logic_vector(57 downto 0); signal memoryC1_uid227_sinPiZTableGenerator_q : std_logic_vector(49 downto 0); signal memoryC2_uid228_sinPiZTableGenerator_q : std_logic_vector(42 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_a : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_b : std_logic_vector(35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_o : std_logic_vector (35 downto 0); signal sumAHighB_uid242_sinPiZPolyEval_q : std_logic_vector (35 downto 0); signal ts3_uid248_sinPiZPolyEval_a : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_b : std_logic_vector(45 downto 0); signal ts3_uid248_sinPiZPolyEval_o : std_logic_vector (45 downto 0); signal ts3_uid248_sinPiZPolyEval_q : std_logic_vector (45 downto 0); signal ts4_uid254_sinPiZPolyEval_a : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_b : std_logic_vector(52 downto 0); signal ts4_uid254_sinPiZPolyEval_o : std_logic_vector (52 downto 0); signal ts4_uid254_sinPiZPolyEval_q : std_logic_vector (52 downto 0); signal ts5_uid260_sinPiZPolyEval_a : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_b : std_logic_vector(61 downto 0); signal ts5_uid260_sinPiZPolyEval_o : std_logic_vector (61 downto 0); signal ts5_uid260_sinPiZPolyEval_q : std_logic_vector (61 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b : std_logic_vector(54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o : std_logic_vector (54 downto 0); signal sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (54 downto 0); signal join_uid42_fpSinPiTest_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal expX_uid6_fpSinPiTest_in : std_logic_vector (62 downto 0); signal expX_uid6_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracX_uid7_fpSinPiTest_in : std_logic_vector (51 downto 0); signal fracX_uid7_fpSinPiTest_b : std_logic_vector (51 downto 0); signal signX_uid8_fpSinPiTest_in : std_logic_vector (63 downto 0); signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0); signal expXIsMax_uid16_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsMax_uid16_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid17_fpSinPiTest_a : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_b : std_logic_vector(51 downto 0); signal fracXIsZero_uid17_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid15_fpSinPiTest_a : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_b : std_logic_vector(10 downto 0); signal expXIsZero_uid15_fpSinPiTest_q : std_logic_vector(0 downto 0); signal xIntExp_uid26_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xIntExp_uid26_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xIntExp_uid26_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xIntExp_uid26_fpSinPiTest_c : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_a : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_b : std_logic_vector(13 downto 0); signal xFrac_uid28_fpSinPiTest_o : std_logic_vector (13 downto 0); signal xFrac_uid28_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal xFrac_uid28_fpSinPiTest_n : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_a : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_b : std_logic_vector(13 downto 0); signal sinXIsX_uid30_fpSinPiTest_o : std_logic_vector (13 downto 0); signal sinXIsX_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0); signal sinXIsX_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0); signal shiftValue_uid33_fpSinPiTest_a : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_b : std_logic_vector(11 downto 0); signal shiftValue_uid33_fpSinPiTest_o : std_logic_vector (11 downto 0); signal shiftValue_uid33_fpSinPiTest_q : std_logic_vector (11 downto 0); signal oMyBottom_uid47_fpSinPiTest_in : std_logic_vector (78 downto 0); signal oMyBottom_uid47_fpSinPiTest_b : std_logic_vector (78 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid155_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(63 downto 0); signal vCount_uid147_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid167_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid161_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid150_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal cIncludingRoundingBit_uid247_sinPiZPolyEval_q : std_logic_vector (44 downto 0); signal cIncludingRoundingBit_uid253_sinPiZPolyEval_q : std_logic_vector (51 downto 0); signal cIncludingRoundingBit_uid259_sinPiZPolyEval_q : std_logic_vector (60 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in : std_logic_vector (33 downto 0); signal prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q : std_logic_vector (107 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (29 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (46 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q : std_logic_vector (108 downto 0); signal yIsZero_uid43_fpSinPiTest_a : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_b : std_logic_vector(79 downto 0); signal yIsZero_uid43_fpSinPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid170_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid19_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zPPolyEval_uid64_fpSinPiTest_in : std_logic_vector (71 downto 0); signal zPPolyEval_uid64_fpSinPiTest_b : std_logic_vector (44 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvSinXIsX_uid80_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXIntExp_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvXFrac_uid99_fpSinPiTest_q : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_c : std_logic_vector(0 downto 0); signal signComp_uid101_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvYIsZero_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid152_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (63 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid158_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (31 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid164_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (15 downto 0); signal s2_uid240_uid243_sinPiZPolyEval_q : std_logic_vector (36 downto 0); signal add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (55 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (42 downto 0); signal xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (72 downto 0); signal add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q : std_logic_vector (79 downto 0); signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(6 downto 0); signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0); signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b : std_logic_vector(3 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b : std_logic_vector(5 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal R_uid105_fpSinPiTest_q : std_logic_vector (63 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b : std_logic_vector(6 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b : std_logic_vector(2 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b : std_logic_vector(2 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal yT3_uid244_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT3_uid244_sinPiZPolyEval_b : std_logic_vector (34 downto 0); signal yT4_uid250_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT4_uid250_sinPiZPolyEval_b : std_logic_vector (42 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b : std_logic_vector(5 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b : std_logic_vector(0 downto 0); signal ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q : std_logic_vector(0 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_a_1_b : std_logic_vector (26 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b : std_logic_vector(3 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q : std_logic_vector(0 downto 0); signal zAddr_uid63_fpSinPiTest_in : std_logic_vector (78 downto 0); signal zAddr_uid63_fpSinPiTest_b : std_logic_vector (6 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (78 downto 0); signal rVStage_uid146_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (63 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (14 downto 0); signal vStage_uid149_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (14 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (46 downto 0); signal X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (46 downto 0); signal expHardCaseR_uid60_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expHardCaseR_uid60_fpSinPiTest_b : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_in : std_logic_vector (10 downto 0); signal expXP1R_uid59_fpSinPiTest_b : std_logic_vector (10 downto 0); signal fracRComp_uid78_fpSinPiTest_in : std_logic_vector (52 downto 0); signal fracRComp_uid78_fpSinPiTest_b : std_logic_vector (51 downto 0); signal expRComp_uid79_fpSinPiTest_in : std_logic_vector (63 downto 0); signal expRComp_uid79_fpSinPiTest_b : std_logic_vector (10 downto 0); signal intXParity_uid38_fpSinPiTest_in : std_logic_vector (80 downto 0); signal intXParity_uid38_fpSinPiTest_b : std_logic_vector (0 downto 0); signal y_uid39_fpSinPiTest_in : std_logic_vector (79 downto 0); signal y_uid39_fpSinPiTest_b : std_logic_vector (79 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (77 downto 0); signal LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (77 downto 0); signal s3_uid249_sinPiZPolyEval_in : std_logic_vector (45 downto 0); signal s3_uid249_sinPiZPolyEval_b : std_logic_vector (44 downto 0); signal s4_uid255_sinPiZPolyEval_in : std_logic_vector (52 downto 0); signal s4_uid255_sinPiZPolyEval_b : std_logic_vector (51 downto 0); signal s5_uid261_sinPiZPolyEval_in : std_logic_vector (61 downto 0); signal s5_uid261_sinPiZPolyEval_b : std_logic_vector (60 downto 0); signal oFracX_uid31_uid31_fpSinPiTest_q : std_logic_vector (52 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_in : std_logic_vector (6 downto 0); signal fxpShifterBits_uid36_fpSinPiTest_b : std_logic_vector (6 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid234_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid235_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal highBBits_uid235_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid240_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid241_sinPiZPolyEval_in : std_logic_vector (28 downto 0); signal highBBits_uid241_sinPiZPolyEval_b : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q : std_logic_vector (107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q : std_logic_vector(107 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (29 downto 0); signal highBBits_uid282_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (46 downto 0); signal highBBits_uid297_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (53 downto 0); signal highBBits_uid312_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (28 downto 0); signal normBit_uid70_fpSinPiTest_in : std_logic_vector (106 downto 0); signal normBit_uid70_fpSinPiTest_b : std_logic_vector (0 downto 0); signal highRes_uid71_fpSinPiTest_in : std_logic_vector (105 downto 0); signal highRes_uid71_fpSinPiTest_b : std_logic_vector (52 downto 0); signal lowRes_uid72_fpSinPiTest_in : std_logic_vector (104 downto 0); signal lowRes_uid72_fpSinPiTest_b : std_logic_vector (52 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d : std_logic_vector(0 downto 0); signal And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal rVStage_uid172_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal vStage_uid174_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (3 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (70 downto 0); signal LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (70 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (62 downto 0); signal LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (62 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (54 downto 0); signal LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (54 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q : std_logic_vector(0 downto 0); signal yT1_uid232_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT1_uid232_sinPiZPolyEval_b : std_logic_vector (16 downto 0); signal yT2_uid238_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yT2_uid238_sinPiZPolyEval_b : std_logic_vector (25 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvYIsZeroSignComp_uid103_fpSinPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (63 downto 0); signal rVStage_uid154_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal vStage_uid156_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (31 downto 0); signal rVStage_uid160_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal vStage_uid162_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (15 downto 0); signal rVStage_uid166_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (7 downto 0); signal vStage_uid168_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (7 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (9 downto 0); signal yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (9 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (36 downto 0); signal yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (54 downto 0); signal R_uid285_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (36 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (71 downto 0); signal R_uid300_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (45 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (78 downto 0); signal R_uid315_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (53 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (34 downto 0); signal xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in : std_logic_vector (7 downto 0); signal xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b : std_logic_vector (7 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (15 downto 0); signal xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (15 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b : std_logic_vector(0 downto 0); signal Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q : std_logic_vector(0 downto 0); signal expP_uid61_fpSinPiTest_s : std_logic_vector (0 downto 0); signal expP_uid61_fpSinPiTest_q : std_logic_vector (10 downto 0); signal yBottom_uid48_fpSinPiTest_in : std_logic_vector (78 downto 0); signal yBottom_uid48_fpSinPiTest_b : std_logic_vector (78 downto 0); signal leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (44 downto 0); signal yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b : std_logic_vector (17 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (51 downto 0); signal yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (26 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in : std_logic_vector (24 downto 0); signal yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b : std_logic_vector (24 downto 0); signal fxpSinRes_uid66_fpSinPiTest_in : std_logic_vector (58 downto 0); signal fxpSinRes_uid66_fpSinPiTest_b : std_logic_vector (53 downto 0); signal extendedFracX_uid35_fpSinPiTest_q : std_logic_vector (80 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(0 downto 0); signal InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b : std_logic_vector(0 downto 0); signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (0 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_a : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_b : std_logic_vector(26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_o : std_logic_vector (26 downto 0); signal sumAHighB_uid236_sinPiZPolyEval_q : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c : std_logic_vector(107 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q : std_logic_vector(107 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_s : std_logic_vector (0 downto 0); signal fracRCompPreRnd_uid73_fpSinPiTest_q : std_logic_vector (52 downto 0); signal join_uid97_fpSinPiTest_q : std_logic_vector (1 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid173_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid176_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal signR_uid104_fpSinPiTest_a : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_b : std_logic_vector(0 downto 0); signal signR_uid104_fpSinPiTest_q : std_logic_vector(0 downto 0); signal spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (10 downto 0); signal pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (16 downto 0); signal pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal xIsInt_uid83_fpSinPiTest_a : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_b : std_logic_vector(0 downto 0); signal xIsInt_uid83_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal multRightOp_uid68_fpSinPiTest_s : std_logic_vector (0 downto 0); signal multRightOp_uid68_fpSinPiTest_q : std_logic_vector (53 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (48 downto 0); signal X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (48 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (16 downto 0); signal X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (16 downto 0); signal s1_uid234_uid237_sinPiZPolyEval_q : std_logic_vector (27 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c : std_logic_vector (19 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in : std_logic_vector (106 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b : std_logic_vector (106 downto 0); signal expFracPreRnd_uid74_uid74_fpSinPiTest_q : std_logic_vector (63 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (3 downto 0); signal rVStage_uid178_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal vStage_uid180_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q : std_logic_vector (17 downto 0); signal alignedZLow_uid53_fpSinPiTest_in : std_logic_vector (78 downto 0); signal alignedZLow_uid53_fpSinPiTest_b : std_logic_vector (51 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_in : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_0_b : std_logic_vector (26 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_in : std_logic_vector (53 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_b_1_b : std_logic_vector (26 downto 0); signal leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q : std_logic_vector (107 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid179_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid182_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (1 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (74 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (72 downto 0); signal pHardCase_uid54_fpSinPiTest_q : std_logic_vector (52 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q : std_logic_vector (108 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_in : std_logic_vector (1 downto 0); signal rVStage_uid184_lzcZ_uid51_fpSinPiTest_b : std_logic_vector (0 downto 0); signal leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q : std_logic_vector (78 downto 0); signal p_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0); signal p_uid55_fpSinPiTest_q : std_logic_vector (52 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (72 downto 0); signal LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (72 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (64 downto 0); signal LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (64 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (56 downto 0); signal LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (56 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in : std_logic_vector (108 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b : std_logic_vector (88 downto 0); signal mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c : std_logic_vector (19 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid185_lzcZ_uid51_fpSinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal r_uid186_lzcZ_uid51_fpSinPiTest_q : std_logic_vector (6 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (6 downto 0); signal leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b : std_logic_vector (0 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (78 downto 0); signal LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (78 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (76 downto 0); signal LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (76 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (74 downto 0); signal leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in : std_logic_vector (79 downto 0); signal LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b : std_logic_vector (79 downto 0); signal leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q : std_logic_vector (80 downto 0); begin --ld_xIn_v_to_xOut_v_notEnable(LOGICAL,909) ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q; ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor(LOGICAL,1028) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q <= not (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_a or ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_b); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top(CONSTANT,1024) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q <= "0100100"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp(LOGICAL,1025) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_mem_top_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q <= "1" when ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_a = ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_b else "0"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg(REG,1026) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena(REG,1029) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_nor_q = "1") THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd(LOGICAL,1030) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_sticky_ena_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_a and ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_b; --LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest(BITSELECT,134)@0 LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest(CONSTANT,133) leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q <= "000000"; --leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest(BITJOIN,135)@0 leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage174dto0_uid135_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest(BITSELECT,131)@0 LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest(CONSTANT,130) leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q <= "0000"; --leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest(BITJOIN,132)@0 leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage176dto0_uid132_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest(BITSELECT,128)@0 LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q(78 downto 0); LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_in(78 downto 0); --leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest(CONSTANT,127) leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q <= "00"; --leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest(BITJOIN,129)@0 leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage178dto0_uid129_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest(BITSELECT,123)@0 LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(56 downto 0); LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_in(56 downto 0); --leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest(CONSTANT,122) leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000"; --leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest(BITJOIN,124)@0 leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage056dto0_uid124_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest(BITSELECT,120)@0 LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(64 downto 0); LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_in(64 downto 0); --leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest(CONSTANT,119) leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000"; --leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest(BITJOIN,121)@0 leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage064dto0_uid121_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest(BITSELECT,117)@0 LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q(72 downto 0); LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_in(72 downto 0); --leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest(CONSTANT,116) leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q <= "00000000"; --leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest(BITJOIN,118)@0 leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage072dto0_uid118_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest(CONSTANT,113) leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; --X16dto0_uid112_fixedPointX_uid37_fpSinPiTest(BITSELECT,111)@0 X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(16 downto 0); X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_in(16 downto 0); --leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest(CONSTANT,110) leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000"; --leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest(BITJOIN,112)@0 leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q <= X16dto0_uid112_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X48dto0_uid109_fixedPointX_uid37_fpSinPiTest(BITSELECT,108)@0 X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in <= extendedFracX_uid35_fpSinPiTest_q(48 downto 0); X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_in(48 downto 0); --leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest(CONSTANT,107) leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q <= "00000000000000000000000000000000"; --leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest(BITJOIN,109)@0 leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q <= X48dto0_uid109_fixedPointX_uid37_fpSinPiTest_b & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --cst01pWShift_uid34_fpSinPiTest(CONSTANT,33) cst01pWShift_uid34_fpSinPiTest_q <= "0000000000000000000000000000"; --xIn(PORTIN,3)@0 --fracX_uid7_fpSinPiTest(BITSELECT,6)@0 fracX_uid7_fpSinPiTest_in <= xIn_0(51 downto 0); fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(51 downto 0); --oFracX_uid31_uid31_fpSinPiTest(BITJOIN,30)@0 oFracX_uid31_uid31_fpSinPiTest_q <= VCC_q & fracX_uid7_fpSinPiTest_b; --extendedFracX_uid35_fpSinPiTest(BITJOIN,34)@0 extendedFracX_uid35_fpSinPiTest_q <= cst01pWShift_uid34_fpSinPiTest_q & oFracX_uid31_uid31_fpSinPiTest_q; --shiftBias_uid32_fpSinPiTest(CONSTANT,31) shiftBias_uid32_fpSinPiTest_q <= "01111100011"; --expX_uid6_fpSinPiTest(BITSELECT,5)@0 expX_uid6_fpSinPiTest_in <= xIn_0(62 downto 0); expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(62 downto 52); --shiftValue_uid33_fpSinPiTest(SUB,32)@0 shiftValue_uid33_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b); shiftValue_uid33_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid32_fpSinPiTest_q); shiftValue_uid33_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid33_fpSinPiTest_a) - UNSIGNED(shiftValue_uid33_fpSinPiTest_b)); shiftValue_uid33_fpSinPiTest_q <= shiftValue_uid33_fpSinPiTest_o(11 downto 0); --fxpShifterBits_uid36_fpSinPiTest(BITSELECT,35)@0 fxpShifterBits_uid36_fpSinPiTest_in <= shiftValue_uid33_fpSinPiTest_q(6 downto 0); fxpShifterBits_uid36_fpSinPiTest_b <= fxpShifterBits_uid36_fpSinPiTest_in(6 downto 0); --leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest(BITSELECT,114)@0 leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b; leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_in(6 downto 5); --leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest(MUX,115)@0 leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel6Dto5_uid115_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s, extendedFracX_uid35_fpSinPiTest_q, leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= extendedFracX_uid35_fpSinPiTest_q; WHEN "01" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx1_uid110_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx2_uid113_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0Idx3_uid114_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest(BITSELECT,125)@0 leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(4 downto 0); leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_in(4 downto 3); --leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest(MUX,126)@0 leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel4Dto3_uid126_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage0_uid116_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx1_uid119_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx2_uid122_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1Idx3_uid125_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest(BITSELECT,136)@0 leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(2 downto 0); leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_in(2 downto 1); --leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest(MUX,137)@0 leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s <= leftShiftStageSel2Dto1_uid137_fixedPointX_uid37_fpSinPiTest_b; leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s, leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q, leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q) BEGIN CASE leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage1_uid127_fixedPointX_uid37_fpSinPiTest_q; WHEN "01" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx1_uid130_fixedPointX_uid37_fpSinPiTest_q; WHEN "10" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx2_uid133_fixedPointX_uid37_fpSinPiTest_q; WHEN "11" => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= leftShiftStage2Idx3_uid136_fixedPointX_uid37_fpSinPiTest_q; WHEN OTHERS => leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest(BITSELECT,139)@0 LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_in(79 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest(BITJOIN,140)@0 leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q <= LeftShiftStage279dto0_uid140_fixedPointX_uid37_fpSinPiTest_b & GND_q; --reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3(REG,357)@0 reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q <= leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2(REG,358)@0 reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q <= leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest(BITSELECT,141)@0 leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in <= fxpShifterBits_uid36_fpSinPiTest_b(0 downto 0); leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_in(0 downto 0); --ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b(DELAY,581)@0 ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest(MUX,142)@1 leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid142_fixedPointX_uid37_fpSinPiTest_b_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_b_q; leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest: PROCESS (leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s, reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q, reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q) BEGIN CASE leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage2_uid138_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_2_q; WHEN "1" => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= reg_leftShiftStage3Idx1_uid141_fixedPointX_uid37_fpSinPiTest_0_to_leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_3_q; WHEN OTHERS => leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --intXParity_uid38_fpSinPiTest(BITSELECT,37)@1 intXParity_uid38_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q; intXParity_uid38_fpSinPiTest_b <= intXParity_uid38_fpSinPiTest_in(80 downto 80); --ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c(DELAY,536)@1 ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => intXParity_uid38_fpSinPiTest_b, xout => ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q, clk => clk, aclr => areset ); --biasM1_uid27_fpSinPiTest(CONSTANT,26) biasM1_uid27_fpSinPiTest_q <= "01111111110"; --xFrac_uid28_fpSinPiTest(COMPARE,27)@0 xFrac_uid28_fpSinPiTest_cin <= GND_q; xFrac_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid27_fpSinPiTest_q) & '0'; xFrac_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid28_fpSinPiTest_cin(0); xFrac_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid28_fpSinPiTest_a) - UNSIGNED(xFrac_uid28_fpSinPiTest_b)); xFrac_uid28_fpSinPiTest_n(0) <= not xFrac_uid28_fpSinPiTest_o(13); --ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a(DELAY,532)@0 ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => xFrac_uid28_fpSinPiTest_n, xout => ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvXFrac_uid99_fpSinPiTest(LOGICAL,98)@3 InvXFrac_uid99_fpSinPiTest_a <= ld_xFrac_uid28_fpSinPiTest_n_to_InvXFrac_uid99_fpSinPiTest_a_q; InvXFrac_uid99_fpSinPiTest_q <= not InvXFrac_uid99_fpSinPiTest_a; --biasMwShift_uid29_fpSinPiTest(CONSTANT,28) biasMwShift_uid29_fpSinPiTest_q <= "01111100100"; --sinXIsX_uid30_fpSinPiTest(COMPARE,29)@0 sinXIsX_uid30_fpSinPiTest_cin <= GND_q; sinXIsX_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0'; sinXIsX_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid29_fpSinPiTest_q) & sinXIsX_uid30_fpSinPiTest_cin(0); sinXIsX_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid30_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid30_fpSinPiTest_b)); sinXIsX_uid30_fpSinPiTest_c(0) <= sinXIsX_uid30_fpSinPiTest_o(13); --ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a(DELAY,502)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvSinXIsX_uid80_fpSinPiTest(LOGICAL,79)@2 InvSinXIsX_uid80_fpSinPiTest_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_InvSinXIsX_uid80_fpSinPiTest_a_q; InvSinXIsX_uid80_fpSinPiTest_q <= not InvSinXIsX_uid80_fpSinPiTest_a; --y_uid39_fpSinPiTest(BITSELECT,38)@1 y_uid39_fpSinPiTest_in <= leftShiftStage3_uid143_fixedPointX_uid37_fpSinPiTest_q(79 downto 0); y_uid39_fpSinPiTest_b <= y_uid39_fpSinPiTest_in(79 downto 0); --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0(REG,360)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid40_fpSinPiTest(LOGICAL,39)@2 yIsZero_uid40_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid40_fpSinPiTest_0_q; yIsZero_uid40_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000000000000000000000000000000000000000000000000" & GND_q); yIsZero_uid40_fpSinPiTest_q <= "1" when yIsZero_uid40_fpSinPiTest_a = yIsZero_uid40_fpSinPiTest_b else "0"; --And2YIsZeroInvSinXIsX_uid81_fpSinPiTest(LOGICAL,80)@2 And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a <= yIsZero_uid40_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b <= InvSinXIsX_uid80_fpSinPiTest_q; And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_a and And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_b; --cstBiasPwF_uid13_fpSinPiTest(CONSTANT,12) cstBiasPwF_uid13_fpSinPiTest_q <= "10000110011"; --xIntExp_uid26_fpSinPiTest(COMPARE,25)@0 xIntExp_uid26_fpSinPiTest_cin <= GND_q; xIntExp_uid26_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid13_fpSinPiTest_q) & '0'; xIntExp_uid26_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid26_fpSinPiTest_cin(0); xIntExp_uid26_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid26_fpSinPiTest_a) - UNSIGNED(xIntExp_uid26_fpSinPiTest_b)); xIntExp_uid26_fpSinPiTest_c(0) <= xIntExp_uid26_fpSinPiTest_o(13); --ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a(DELAY,505)@0 ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => xIntExp_uid26_fpSinPiTest_c, xout => ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q, clk => clk, aclr => areset ); --Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest(LOGICAL,81)@2 Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b <= And2YIsZeroInvSinXIsX_uid81_fpSinPiTest_q; Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a or Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_b; --cstAllZWF_uid10_fpSinPiTest(CONSTANT,9) cstAllZWF_uid10_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000"; --fracXIsZero_uid17_fpSinPiTest(LOGICAL,16)@0 fracXIsZero_uid17_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b; fracXIsZero_uid17_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q; fracXIsZero_uid17_fpSinPiTest_q <= "1" when fracXIsZero_uid17_fpSinPiTest_a = fracXIsZero_uid17_fpSinPiTest_b else "0"; --ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a(DELAY,442)@0 ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => fracXIsZero_uid17_fpSinPiTest_q, xout => ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvFracXIsZero_uid19_fpSinPiTest(LOGICAL,18)@1 InvFracXIsZero_uid19_fpSinPiTest_a <= ld_fracXIsZero_uid17_fpSinPiTest_q_to_InvFracXIsZero_uid19_fpSinPiTest_a_q; InvFracXIsZero_uid19_fpSinPiTest_q <= not InvFracXIsZero_uid19_fpSinPiTest_a; --cstAllOWE_uid9_fpSinPiTest(CONSTANT,8) cstAllOWE_uid9_fpSinPiTest_q <= "11111111111"; --expXIsMax_uid16_fpSinPiTest(LOGICAL,15)@0 expXIsMax_uid16_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsMax_uid16_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q; expXIsMax_uid16_fpSinPiTest_q <= "1" when expXIsMax_uid16_fpSinPiTest_a = expXIsMax_uid16_fpSinPiTest_b else "0"; --ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a(DELAY,443)@0 ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsMax_uid16_fpSinPiTest_q, xout => ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest(LOGICAL,19)@1 And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a <= ld_expXIsMax_uid16_fpSinPiTest_q_to_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b <= InvFracXIsZero_uid19_fpSinPiTest_q; And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_a and And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_b; --InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest(LOGICAL,20)@1 InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q <= not InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_a; --And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0 And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a <= expXIsMax_uid16_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b <= fracXIsZero_uid17_fpSinPiTest_q; And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_a and And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_b; --InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0 InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a <= And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q; InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q <= not InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_a; --cstAllZWE_uid11_fpSinPiTest(CONSTANT,10) cstAllZWE_uid11_fpSinPiTest_q <= "00000000000"; --expXIsZero_uid15_fpSinPiTest(LOGICAL,14)@0 expXIsZero_uid15_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b; expXIsZero_uid15_fpSinPiTest_b <= cstAllZWE_uid11_fpSinPiTest_q; expXIsZero_uid15_fpSinPiTest_q <= "1" when expXIsZero_uid15_fpSinPiTest_a = expXIsZero_uid15_fpSinPiTest_b else "0"; --InvExpXIsZero_uid23_fpSinPiTest(LOGICAL,22)@0 InvExpXIsZero_uid23_fpSinPiTest_a <= expXIsZero_uid15_fpSinPiTest_q; InvExpXIsZero_uid23_fpSinPiTest_q <= not InvExpXIsZero_uid23_fpSinPiTest_a; --And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0 And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a <= InvExpXIsZero_uid23_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b <= InvAnd2ExpXIsMaxFracXIsZero_uid22_fpSinPiTest_q; And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_a and And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_b; --ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a(DELAY,450)@0 ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q, xout => ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q, clk => clk, aclr => areset ); --And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest(LOGICAL,24)@1 And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a <= ld_And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid24_fpSinPiTest_q_to_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b <= InvAnd2ExpXIsMaxInvFracXIsZero_uid21_fpSinPiTest_q; And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_a and And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_b; END IF; END PROCESS; --xIsInt_uid83_fpSinPiTest(LOGICAL,82)@2 xIsInt_uid83_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_b <= Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_q; xIsInt_uid83_fpSinPiTest_q <= xIsInt_uid83_fpSinPiTest_a and xIsInt_uid83_fpSinPiTest_b; --InvXIsInt_uid100_fpSinPiTest(LOGICAL,99)@2 InvXIsInt_uid100_fpSinPiTest_a <= xIsInt_uid83_fpSinPiTest_q; InvXIsInt_uid100_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN InvXIsInt_uid100_fpSinPiTest_q <= not InvXIsInt_uid100_fpSinPiTest_a; END IF; END PROCESS; --signComp_uid101_fpSinPiTest(LOGICAL,100)@3 signComp_uid101_fpSinPiTest_a <= InvXIsInt_uid100_fpSinPiTest_q; signComp_uid101_fpSinPiTest_b <= InvXFrac_uid99_fpSinPiTest_q; signComp_uid101_fpSinPiTest_c <= ld_intXParity_uid38_fpSinPiTest_b_to_signComp_uid101_fpSinPiTest_c_q; signComp_uid101_fpSinPiTest_q <= signComp_uid101_fpSinPiTest_a and signComp_uid101_fpSinPiTest_b and signComp_uid101_fpSinPiTest_c; --ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a(DELAY,537)@2 ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => yIsZero_uid40_fpSinPiTest_q, xout => ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q, clk => clk, aclr => areset ); --InvYIsZero_uid102_fpSinPiTest(LOGICAL,101)@3 InvYIsZero_uid102_fpSinPiTest_a <= ld_yIsZero_uid40_fpSinPiTest_q_to_InvYIsZero_uid102_fpSinPiTest_a_q; InvYIsZero_uid102_fpSinPiTest_q <= not InvYIsZero_uid102_fpSinPiTest_a; --And2InvYIsZeroSignComp_uid103_fpSinPiTest(LOGICAL,102)@3 And2InvYIsZeroSignComp_uid103_fpSinPiTest_a <= InvYIsZero_uid102_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_b <= signComp_uid101_fpSinPiTest_q; And2InvYIsZeroSignComp_uid103_fpSinPiTest_q <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_a and And2InvYIsZeroSignComp_uid103_fpSinPiTest_b; --signX_uid8_fpSinPiTest(BITSELECT,7)@0 signX_uid8_fpSinPiTest_in <= xIn_0; signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(63 downto 63); --ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a(DELAY,540)@0 ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q, clk => clk, aclr => areset ); --signR_uid104_fpSinPiTest(LOGICAL,103)@3 signR_uid104_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid104_fpSinPiTest_a_q; signR_uid104_fpSinPiTest_b <= And2InvYIsZeroSignComp_uid103_fpSinPiTest_q; signR_uid104_fpSinPiTest_q <= signR_uid104_fpSinPiTest_a xor signR_uid104_fpSinPiTest_b; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt(COUNTER,1020) -- every=1, low=0, high=36, step=1, init=1 ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i = 35 THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i - 36; ELSE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_i,6)); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg(REG,1021) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --VCC(CONSTANT,1) VCC_q <= "1"; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux(MUX,1022) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux: PROCESS (ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q, ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem(DUALMEM,1019) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia <= signR_uid104_fpSinPiTest_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 37, width_b => 1, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq, address_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_aa, data_a => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_ia ); ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_iq(0 downto 0); --ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg(DELAY,1018) ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_mem_q, xout => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --cstBias_uid12_fpSinPiTest(CONSTANT,11) cstBias_uid12_fpSinPiTest_q <= "01111111111"; --piwFP2_uid67_fpSinPiTest(CONSTANT,66) piwFP2_uid67_fpSinPiTest_q <= "110010010000111111011010101000100010000101101000110001"; --reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1(REG,363)@1 reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --cOne_uid44_fpSinPiTest(CONSTANT,43) cOne_uid44_fpSinPiTest_q <= "100000000000000000000000000000000000000000000000000000000000000000000000000000000"; --oneMinusY_uid45_fpSinPiTest(SUB,44)@2 oneMinusY_uid45_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid44_fpSinPiTest_q); oneMinusY_uid45_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid39_fpSinPiTest_0_to_oneMinusY_uid45_fpSinPiTest_1_q); oneMinusY_uid45_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN oneMinusY_uid45_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid45_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid45_fpSinPiTest_b)); END IF; END PROCESS; oneMinusY_uid45_fpSinPiTest_q <= oneMinusY_uid45_fpSinPiTest_o(81 downto 0); --oMyBottom_uid47_fpSinPiTest(BITSELECT,46)@3 oMyBottom_uid47_fpSinPiTest_in <= oneMinusY_uid45_fpSinPiTest_q(78 downto 0); oMyBottom_uid47_fpSinPiTest_b <= oMyBottom_uid47_fpSinPiTest_in(78 downto 0); --ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d(DELAY,471)@3 ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => oMyBottom_uid47_fpSinPiTest_b, xout => ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q, clk => clk, aclr => areset ); --yBottom_uid48_fpSinPiTest(BITSELECT,47)@1 yBottom_uid48_fpSinPiTest_in <= y_uid39_fpSinPiTest_b(78 downto 0); yBottom_uid48_fpSinPiTest_b <= yBottom_uid48_fpSinPiTest_in(78 downto 0); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c(DELAY,470)@1 ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 79, depth => 2 ) PORT MAP ( xin => yBottom_uid48_fpSinPiTest_b, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg(DELAY,926) ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_q, xout => ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a(DELAY,833)@1 ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a : dspba_delay GENERIC MAP ( width => 80, depth => 1 ) PORT MAP ( xin => y_uid39_fpSinPiTest_b, xout => ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q, clk => clk, aclr => areset ); --reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1(REG,364)@2 reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q <= ld_y_uid39_fpSinPiTest_b_to_reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_a_q; END IF; END PROCESS; --cmpYToOneMinusY_uid46_fpSinPiTest(COMPARE,45)@3 cmpYToOneMinusY_uid46_fpSinPiTest_cin <= GND_q; cmpYToOneMinusY_uid46_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & oneMinusY_uid45_fpSinPiTest_q) & '0'; cmpYToOneMinusY_uid46_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & reg_y_uid39_fpSinPiTest_0_to_cmpYToOneMinusY_uid46_fpSinPiTest_1_q) & cmpYToOneMinusY_uid46_fpSinPiTest_cin(0); cmpYToOneMinusY_uid46_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN cmpYToOneMinusY_uid46_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid46_fpSinPiTest_b)); END IF; END PROCESS; cmpYToOneMinusY_uid46_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid46_fpSinPiTest_o(84); --z_uid49_fpSinPiTest(MUX,48)@4 z_uid49_fpSinPiTest_s <= cmpYToOneMinusY_uid46_fpSinPiTest_c; z_uid49_fpSinPiTest: PROCESS (z_uid49_fpSinPiTest_s, ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q, ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q) BEGIN CASE z_uid49_fpSinPiTest_s IS WHEN "0" => z_uid49_fpSinPiTest_q <= ld_yBottom_uid48_fpSinPiTest_b_to_z_uid49_fpSinPiTest_c_outputreg_q; WHEN "1" => z_uid49_fpSinPiTest_q <= ld_oMyBottom_uid47_fpSinPiTest_b_to_z_uid49_fpSinPiTest_d_q; WHEN OTHERS => z_uid49_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --zAddr_uid63_fpSinPiTest(BITSELECT,62)@4 zAddr_uid63_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; zAddr_uid63_fpSinPiTest_b <= zAddr_uid63_fpSinPiTest_in(78 downto 72); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0(REG,382)@4 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q <= zAddr_uid63_fpSinPiTest_b; END IF; END PROCESS; --memoryC5_uid231_sinPiZTableGenerator(LOOKUP,230)@5 memoryC5_uid231_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC5_uid231_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; WHEN "0000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111110101101000"; WHEN "0000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111101101011101"; WHEN "0000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100110001110"; WHEN "0000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111100000000010"; WHEN "0000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111011000000000"; WHEN "0000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111010001101101"; WHEN "0000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111001010010111"; WHEN "0001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11111000010110010"; WHEN "0001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110111100010100"; WHEN "0001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110110100011111"; WHEN "0001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110101100101101"; WHEN "0001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110100101101011"; WHEN "0001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110011111011101"; WHEN "0001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010111001010"; WHEN "0001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110010001011011"; WHEN "0010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110001010101011"; WHEN "0010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11110000011011001"; WHEN "0010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101111011000001"; WHEN "0010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101110101001010"; WHEN "0010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101101110100110"; WHEN "0010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101100111100011"; WHEN "0010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011111111111"; WHEN "0010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101011001001010"; WHEN "0011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101010010100110"; WHEN "0011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101001010011011"; WHEN "0011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11101000100011100"; WHEN "0011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100111101010110"; WHEN "0011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100110110111000"; WHEN "0011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100101111110010"; WHEN "0011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100111110010"; WHEN "0011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100100001010101"; WHEN "0100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100011011011111"; WHEN "0100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100010011110111"; WHEN "0100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100001110001010"; WHEN "0100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11100000111000100"; WHEN "0100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111111110101"; WHEN "0100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011111001010110"; WHEN "0100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011110011000111"; WHEN "0100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011101101000000"; WHEN "0101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011100110000011"; WHEN "0101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011111111001"; WHEN "0101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011011000100110"; WHEN "0101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011010010101100"; WHEN "0101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011001100010010"; WHEN "0101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11011000101010111"; WHEN "0101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111111101010"; WHEN "0101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010111001010000"; WHEN "0110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010110011010011"; WHEN "0110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010101100101011"; WHEN "0110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010100110111110"; WHEN "0110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011111111000"; WHEN "0110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010011010110010"; WHEN "0110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010010101001110"; WHEN "0110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001110010011"; WHEN "0110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010001000111011"; WHEN "0111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11010000001111011"; WHEN "0111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001111011111110"; WHEN "0111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110111001010"; WHEN "0111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001110001110111"; WHEN "0111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001101011000100"; WHEN "0111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100101010010"; WHEN "0111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001100000011111"; WHEN "0111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001011010001010"; WHEN "1000000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001010100111110"; WHEN "1000001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001110110010"; WHEN "1000010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001001010111000"; WHEN "1000011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11001000100111111"; WHEN "1000100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111111001100"; WHEN "1000101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000111010001001"; WHEN "1000110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110101010110"; WHEN "1000111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000110000011101"; WHEN "1001000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000101001110100"; WHEN "1001001" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000100101111001"; WHEN "1001010" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011111111010"; WHEN "1001011" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000011011110110"; WHEN "1001100" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010110001100"; WHEN "1001101" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000010001001000"; WHEN "1001110" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001101111001"; WHEN "1001111" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000001000000111"; WHEN "1010000" => memoryC5_uid231_sinPiZTableGenerator_q <= "11000000010111001"; WHEN "1010001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111110110110"; WHEN "1010010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111111001111111"; WHEN "1010011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110110010100"; WHEN "1010100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111110001011000"; WHEN "1010101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101100010111"; WHEN "1010110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111101000010010"; WHEN "1010111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100100010000"; WHEN "1011000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111100000111100"; WHEN "1011001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111011011111111"; WHEN "1011010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010111100000"; WHEN "1011011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010011110100"; WHEN "1011100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111010000011100"; WHEN "1011101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111001011011110"; WHEN "1011110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000111111101"; WHEN "1011111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000100101011"; WHEN "1100000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10111000001100100"; WHEN "1100001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111101101110"; WHEN "1100010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110111010011000"; WHEN "1100011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110110110000"; WHEN "1100100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110010011010"; WHEN "1100101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110110000011110"; WHEN "1100110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101100101100"; WHEN "1100111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110101000101110"; WHEN "1101000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100110100000"; WHEN "1101001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100100010001"; WHEN "1101010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110100001000000"; WHEN "1101011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011101101110"; WHEN "1101100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110011011011111"; WHEN "1101101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010111000100"; WHEN "1101110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010101110011"; WHEN "1101111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010001111100"; WHEN "1110000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110010000001111"; WHEN "1110001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001110011001"; WHEN "1110010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110001010100010"; WHEN "1110011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000111111000"; WHEN "1110100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101110110"; WHEN "1110101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000101000100"; WHEN "1110110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10110000010100010"; WHEN "1110111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111111110011"; WHEN "1111000" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111110010000"; WHEN "1111001" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111100110111"; WHEN "1111010" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111010111000"; WHEN "1111011" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101111000101000"; WHEN "1111100" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110110110100"; WHEN "1111101" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110101011010"; WHEN "1111110" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110100000011"; WHEN "1111111" => memoryC5_uid231_sinPiZTableGenerator_q <= "10101110010001011"; WHEN OTHERS => memoryC5_uid231_sinPiZTableGenerator_q <= "11111111101000001"; END CASE; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a(DELAY,485)@4 ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => z_uid49_fpSinPiTest_q, xout => ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q, clk => clk, aclr => areset ); --zPPolyEval_uid64_fpSinPiTest(BITSELECT,63)@5 zPPolyEval_uid64_fpSinPiTest_in <= ld_z_uid49_fpSinPiTest_q_to_zPPolyEval_uid64_fpSinPiTest_a_q(71 downto 0); zPPolyEval_uid64_fpSinPiTest_b <= zPPolyEval_uid64_fpSinPiTest_in(71 downto 27); --yT1_uid232_sinPiZPolyEval(BITSELECT,231)@5 yT1_uid232_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT1_uid232_sinPiZPolyEval_b <= yT1_uid232_sinPiZPolyEval_in(44 downto 28); --reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0(REG,383)@5 reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q <= yT1_uid232_sinPiZPolyEval_b; END IF; END PROCESS; --prodXY_uid263_pT1_uid233_sinPiZPolyEval(MULT,262)@6 prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_a),18)) * SIGNED(prodXY_uid263_pT1_uid233_sinPiZPolyEval_b); prodXY_uid263_pT1_uid233_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= (others => '0'); prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_a <= reg_yT1_uid232_sinPiZPolyEval_0_to_prodXY_uid263_pT1_uid233_sinPiZPolyEval_0_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_b <= memoryC5_uid231_sinPiZTableGenerator_q; prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid263_pT1_uid233_sinPiZPolyEval_pr,34)); END IF; END PROCESS; prodXY_uid263_pT1_uid233_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid263_pT1_uid233_sinPiZPolyEval_q <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval(BITSELECT,263)@9 prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in <= prodXY_uid263_pT1_uid233_sinPiZPolyEval_q; prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_in(33 downto 16); --highBBits_uid235_sinPiZPolyEval(BITSELECT,234)@9 highBBits_uid235_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b; highBBits_uid235_sinPiZPolyEval_b <= highBBits_uid235_sinPiZPolyEval_in(17 downto 1); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a(DELAY,853)@4 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a : dspba_delay GENERIC MAP ( width => 7, depth => 3 ) PORT MAP ( xin => zAddr_uid63_fpSinPiTest_b, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0(REG,384)@7 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_a_q; END IF; END PROCESS; --memoryC4_uid230_sinPiZTableGenerator(LOOKUP,229)@8 memoryC4_uid230_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC4_uid230_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; WHEN "0000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110011111111100"; WHEN "0000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100101101100110011"; WHEN "0000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100100010011000101"; WHEN "0000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100010010010010110"; WHEN "0000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011111110011000100"; WHEN "0000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011100101011001100"; WHEN "0000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001011001000001111000"; WHEN "0001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010100110101100100"; WHEN "0001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001010000000010110001"; WHEN "0001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001001010101111100100"; WHEN "0001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001000100111000100010"; WHEN "0001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000111110011011110101"; WHEN "0001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000110111011001010101"; WHEN "0001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000101111111000110001"; WHEN "0001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000100111101101111110"; WHEN "0010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000011111000010010110"; WHEN "0010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000010101110100101111"; WHEN "0010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000001100000110110101"; WHEN "0010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01010000000001101111000000"; WHEN "0010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111110110110101110011"; WHEN "0010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111101011011010111001"; WHEN "0010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111011111011110000110"; WHEN "0010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111010010111100110100"; WHEN "0011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001111000101110111111001"; WHEN "0011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110111000010100011101"; WHEN "0011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110101010001000110011"; WHEN "0011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110011011011101100111"; WHEN "0011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001110001100001110001111"; WHEN "0011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101111100011110001010"; WHEN "0011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101101100001110100101"; WHEN "0011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101011011011000110110"; WHEN "0100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001101001001111111101110"; WHEN "0100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100111000001001001111"; WHEN "0100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100100101101100011001"; WHEN "0100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001100010010110001110000"; WHEN "0100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011111111010101110110"; WHEN "0100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011101011010111000111"; WHEN "0100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011010110110110011110"; WHEN "0100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001011000001110100011110"; WHEN "0101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010101100010100010011"; WHEN "0101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001010010110010001000111"; WHEN "0101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001111111110001000100"; WHEN "0101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001101000101100110110"; WHEN "0101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001001010001001001111011"; WHEN "0101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000111001001000001110"; WHEN "0101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000100000100011110110"; WHEN "0101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01001000000111100001111001"; WHEN "0110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111101101111111011111"; WHEN "0110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000111010011111111100110"; WHEN "0110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110111001011110100100"; WHEN "0110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110011110100010000111"; WHEN "0110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000110000011000010001001"; WHEN "0110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101100111000101000011"; WHEN "0110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000101001010101101011111"; WHEN "0110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100101101110011101110"; WHEN "0111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000100010000100000111110"; WHEN "0111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011110010101101110100"; WHEN "0111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000011010100011010011110"; WHEN "0111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010110101101011010111"; WHEN "0111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000010010110100011011101"; WHEN "0111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001110110111100001001"; WHEN "0111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000001010110110110010000"; WHEN "0111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000110110011000001101"; WHEN "1000000" => memoryC4_uid230_sinPiZTableGenerator_q <= "01000000010101011011011001"; WHEN "1000001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111110100000101110010"; WHEN "1000010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111111010010001110101001"; WHEN "1000011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110110000000001101011"; WHEN "1000100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111110001101011001110011"; WHEN "1000101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101101010010101011101"; WHEN "1000110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111101000110110101111111"; WHEN "1000111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111100100010111100111100"; WHEN "1001000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011111110101110100100"; WHEN "1001001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111011011001111111110100"; WHEN "1001010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010110100111101000111"; WHEN "1001011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111010001111011100101001"; WHEN "1001100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001101001100111100001"; WHEN "1001101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111001000011011000101011"; WHEN "1001110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00111000011100101100110010"; WHEN "1001111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111110101110000000011"; WHEN "1010000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110111001110011001111101"; WHEN "1010001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110110100110101001110001"; WHEN "1010010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101111110100101001011"; WHEN "1010011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110101010110000110010110"; WHEN "1010100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100101101010100111010"; WHEN "1010101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110100000100001101101101"; WHEN "1010110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110011011010101110011000"; WHEN "1010111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010110000111001010011"; WHEN "1011000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110010000110101101010010"; WHEN "1011001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110001011100010001000010"; WHEN "1011010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000110001011111001110"; WHEN "1011011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00110000000110010110110100"; WHEN "1011100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101111011010111010001000"; WHEN "1011101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110101111001110001011"; WHEN "1011110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101110000011001011001100"; WHEN "1011111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101101010110110100111111"; WHEN "1100000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101100101010001011011001"; WHEN "1100001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011111101010010000000"; WHEN "1100010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101011010000000101001000"; WHEN "1100011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101010100010100111110111"; WHEN "1100100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001110100111011010110"; WHEN "1100101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101001000110110111101100"; WHEN "1100110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00101000011000101000001000"; WHEN "1100111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100111101010001001010101"; WHEN "1101000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110111011010110000011"; WHEN "1101001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100110001100010011011010"; WHEN "1101010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100101011101000100011001"; WHEN "1101011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100100101101100110100111"; WHEN "1101100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011111101110111111010"; WHEN "1101101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100011001110000000101100"; WHEN "1101110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100010011101110011110101"; WHEN "1101111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100001101101100000010000"; WHEN "1110000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000111100111010001011"; WHEN "1110001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00100000001100000111111010"; WHEN "1110010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011111011011001110101000"; WHEN "1110011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011110101010000110010111"; WHEN "1110100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101111000110001000001"; WHEN "1110101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011101000111001101001001"; WHEN "1110110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011100010101100011001010"; WHEN "1110111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011011100011101111010110"; WHEN "1111000" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011010110001101110011110"; WHEN "1111001" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001111111100011010111"; WHEN "1111010" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011001001101010000100101"; WHEN "1111011" => memoryC4_uid230_sinPiZTableGenerator_q <= "00011000011010110101101110"; WHEN "1111100" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010111101000010001000000"; WHEN "1111101" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110110101100011000101"; WHEN "1111110" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010110000010101101010111"; WHEN "1111111" => memoryC4_uid230_sinPiZTableGenerator_q <= "00010101001111110001011010"; WHEN OTHERS => memoryC4_uid230_sinPiZTableGenerator_q <= "01010001100110110001011110"; END CASE; END IF; END PROCESS; --sumAHighB_uid236_sinPiZPolyEval(ADD,235)@9 sumAHighB_uid236_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((26 downto 26 => memoryC4_uid230_sinPiZTableGenerator_q(25)) & memoryC4_uid230_sinPiZTableGenerator_q); sumAHighB_uid236_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((26 downto 17 => highBBits_uid235_sinPiZPolyEval_b(16)) & highBBits_uid235_sinPiZPolyEval_b); sumAHighB_uid236_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid236_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid236_sinPiZPolyEval_b)); sumAHighB_uid236_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_o(26 downto 0); --lowRangeB_uid234_sinPiZPolyEval(BITSELECT,233)@9 lowRangeB_uid234_sinPiZPolyEval_in <= prodXYTruncFR_uid264_pT1_uid233_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid234_sinPiZPolyEval_b <= lowRangeB_uid234_sinPiZPolyEval_in(0 downto 0); --s1_uid234_uid237_sinPiZPolyEval(BITJOIN,236)@9 s1_uid234_uid237_sinPiZPolyEval_q <= sumAHighB_uid236_sinPiZPolyEval_q & lowRangeB_uid234_sinPiZPolyEval_b; --reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1(REG,385)@9 reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q <= s1_uid234_uid237_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor(LOGICAL,1179) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q <= not (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_a or ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_b); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg(REG,1177) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q <= VCC_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena(REG,1180) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_nor_q = "1") THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd(LOGICAL,1181) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_sticky_ena_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_a and ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_b; --yT2_uid238_sinPiZPolyEval(BITSELECT,237)@5 yT2_uid238_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b; yT2_uid238_sinPiZPolyEval_b <= yT2_uid238_sinPiZPolyEval_in(44 downto 19); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt(COUNTER,1173) -- every=1, low=0, high=1, step=1, init=1 ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i + 1; END IF; END PROCESS; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_i,1)); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg(REG,1174) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux(MUX,1175) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s <= VCC_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q, ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q) BEGIN CASE ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_s IS WHEN "0" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; WHEN "1" => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdcnt_q; WHEN OTHERS => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem(DUALMEM,1172) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0 <= areset; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia <= yT2_uid238_sinPiZPolyEval_b; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdreg_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_rdmux_q; ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 26, widthad_a => 1, numwords_a => 2, width_b => 26, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq, address_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_aa, data_a => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_ia ); ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_iq(25 downto 0); --ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg(DELAY,1171) ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_replace_mem_q, xout => ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0(REG,386)@9 reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q <= ld_yT2_uid238_sinPiZPolyEval_b_to_reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_a_outputreg_q; END IF; END PROCESS; --prodXY_uid266_pT2_uid239_sinPiZPolyEval(MULT,265)@10 prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_a),27)) * SIGNED(prodXY_uid266_pT2_uid239_sinPiZPolyEval_b); prodXY_uid266_pT2_uid239_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= (others => '0'); prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_a <= reg_yT2_uid238_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_0_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_b <= reg_s1_uid234_uid237_sinPiZPolyEval_0_to_prodXY_uid266_pT2_uid239_sinPiZPolyEval_1_q; prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid266_pT2_uid239_sinPiZPolyEval_pr,54)); END IF; END PROCESS; prodXY_uid266_pT2_uid239_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prodXY_uid266_pT2_uid239_sinPiZPolyEval_q <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_s1; END IF; END PROCESS; --prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval(BITSELECT,266)@13 prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in <= prodXY_uid266_pT2_uid239_sinPiZPolyEval_q; prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_in(53 downto 25); --highBBits_uid241_sinPiZPolyEval(BITSELECT,240)@13 highBBits_uid241_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b; highBBits_uid241_sinPiZPolyEval_b <= highBBits_uid241_sinPiZPolyEval_in(28 downto 1); --reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1(REG,388)@13 reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= "0000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q <= highBBits_uid241_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor(LOGICAL,1192) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1188) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q <= "0101"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp(LOGICAL,1189) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg(REG,1190) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena(REG,1193) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1194) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1184) -- every=1, low=0, high=5, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i = 4 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i - 5; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_i,3)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg(REG,1185) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1186) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1183) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 3, numwords_a => 6, width_b => 7, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg(DELAY,1182) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0(REG,387)@12 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC3_uid229_sinPiZTableGenerator(LOOKUP,228)@13 memoryC3_uid229_sinPiZTableGenerator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC3_uid229_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; WHEN "0000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000001010001100110101000111010101"; WHEN "0000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000010100011001100101101010110011"; WHEN "0000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000011110100110001101010100011011"; WHEN "0000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000101000110010100111100101110011"; WHEN "0000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000110010111110101111101101101000"; WHEN "0000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00000111101001010100001100001001101"; WHEN "0000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001000111010101111000010100001000"; WHEN "0001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001010001100000101111101001011010"; WHEN "0001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001011011101011000011001000111110"; WHEN "0001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001100101110100101110001001110101"; WHEN "0001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001101111111101101100010100000001"; WHEN "0001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00001111010000101111001001101010110"; WHEN "0001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010000100001101010000011000110101"; WHEN "0001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010001110010011101101001010101000"; WHEN "0001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010011000011001001011011101011111"; WHEN "0010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010100010011101100110100011101011"; WHEN "0010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010101100100000111010000011110001"; WHEN "0010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00010110110100011000001011111010110"; WHEN "0010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011000000100011111000101110110101"; WHEN "0010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011001010100011011011001000001011"; WHEN "0010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011010100100001100100010010100101"; WHEN "0010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011011110011110001111110110101010"; WHEN "0010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011101000011001011001100000011011"; WHEN "0011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011110010010010111100111000010100"; WHEN "0011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00011111100001010110101011110000110"; WHEN "0011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100000110000000111111001110100010"; WHEN "0011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100001111110101010101100100101101"; WHEN "0011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100011001100111110100010110001111"; WHEN "0011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100100011011000010111001001011111"; WHEN "0011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100101101000110111001101001101001"; WHEN "0011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00100110110110011010111110011001100"; WHEN "0100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101000000011101101101010000100110"; WHEN "0100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101001010000101110101101000010110"; WHEN "0100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101010011101011101100111100100100"; WHEN "0100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101011101001111001110110000110010"; WHEN "0100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101100110110000010111000000110011"; WHEN "0100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101110000001111000001100011110100"; WHEN "0100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00101111001101011001010010000000001"; WHEN "0100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110000011000100101100111100001110"; WHEN "0101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110001100011011100101011010100101"; WHEN "0101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110010101101111101111110000010101"; WHEN "0101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110011111000001000111101011101100"; WHEN "0101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110101000001111101001011001100010"; WHEN "0101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110110001011011010000101101010010"; WHEN "0101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "00110111010100011111001100111101100"; WHEN "0101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111000011101001100000010000100010"; WHEN "0101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111001100101100000000100001010000"; WHEN "0110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111010101101011010110100011101100"; WHEN "0110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111011110100111011110011000011110"; WHEN "0110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111100111100000010100001101010000"; WHEN "0110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111110000010101110100000001010000"; WHEN "0110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "00111111001000111111010001101010001"; WHEN "0110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000000001110110100010110001111010"; WHEN "0110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000001010100001101001110111110101"; WHEN "0110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000010011001001001011111110000001"; WHEN "0111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000011011101101000101000010101111"; WHEN "0111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000100100001101010001101000100100"; WHEN "0111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000101100101001101110000011010101"; WHEN "0111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000110101000010010110100001011010"; WHEN "0111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01000111101010111000111010101011110"; WHEN "0111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001000101100111111101000110111000"; WHEN "0111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001001101110100110100001111001100"; WHEN "0111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001010101111101101001000001001010"; WHEN "1000000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001011110000010011000001001000011"; WHEN "1000001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001100110000010111101111101010011"; WHEN "1000010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001101101111111010111010011001111"; WHEN "1000011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001110101110111100000011010000110"; WHEN "1000100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01001111101101011010110000011010010"; WHEN "1000101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010000101011010110100111100000101"; WHEN "1000110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010001101000101111001101110100011"; WHEN "1000111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010010100101100100001000101010010"; WHEN "1001000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010011100001110100111101001010100"; WHEN "1001001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010100011101100001010100001011100"; WHEN "1001010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010101011000101000110001011100100"; WHEN "1001011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010110010011001010111110000100100"; WHEN "1001100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01010111001101000111011111001000111"; WHEN "1001101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000000110011101111101001011111"; WHEN "1001110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011000111111001110000000110011110"; WHEN "1001111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011001110111010111001110111111110"; WHEN "1010000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011010101110111001010010001110110"; WHEN "1010001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011011100101110011110011000111101"; WHEN "1010010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011100011100000110011001001001001"; WHEN "1010011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011101010001110000101111000101100"; WHEN "1010100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110000110110010011100011000111"; WHEN "1010101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011110111011001011001011101010011"; WHEN "1010110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01011111101110111010100111100011100"; WHEN "1010111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100000100010000000011001111101101"; WHEN "1011000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100001010100011100001101110011100"; WHEN "1011001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010000110001101101100011100011"; WHEN "1011010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100010110111010100100010100000100"; WHEN "1011011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100011100111110000011100000001010"; WHEN "1011100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100100010111100001000100001101001"; WHEN "1011101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101000110100110000110001111011"; WHEN "1011110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100101110100111111010000100111001"; WHEN "1011111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100110100010101100001111010001101"; WHEN "1100000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111001111101100101111101110000"; WHEN "1100001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01100111111100000000011110011100101"; WHEN "1100010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101000100111100111001010011110100"; WHEN "1100011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001010010100000100001001001101"; WHEN "1100100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101001111100101100010000111001000"; WHEN "1100101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101010100110001010001010100001101"; WHEN "1100110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011001110111001111010101110101"; WHEN "1100111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101011110110111011010001101111010"; WHEN "1101000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101100011110001110000000111001111"; WHEN "1101001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101000100110001110111010010001"; WHEN "1101010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101101101010100110100100110101101"; WHEN "1101011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110001111101011111011001010101"; WHEN "1101100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101110110100000001101100000100000"; WHEN "1101101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111010111100111100111010111000"; WHEN "1101110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01101111111010011101100010000110110"; WHEN "1101111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000011100100011001011010100000"; WHEN "1110000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110000111101111000011000011110011"; WHEN "1110001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001011110011100111011010000000"; WHEN "1110010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110001111110010000100101111100001"; WHEN "1110011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010011101010011001110010000111"; WHEN "1110100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110010111011100100100111111111001"; WHEN "1110101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011011001000100101000000101011"; WHEN "1110110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110011110101110011000001011101010"; WHEN "1110111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100010001101111101010010100010"; WHEN "1111000" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110100101100111010011001000110011"; WHEN "1111001" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101000111010011000011010000011"; WHEN "1111010" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101100000111001011110100010010"; WHEN "1111011" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110101111001101101100001110011100"; WHEN "1111100" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110010001101111000100101110110"; WHEN "1111101" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110101000111101111110101001010"; WHEN "1111110" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110110111111011010000111000110000"; WHEN "1111111" => memoryC3_uid229_sinPiZTableGenerator_q <= "01110111010101000011010110000100000"; WHEN OTHERS => memoryC3_uid229_sinPiZTableGenerator_q <= "11111111111111111111111111111001011"; END CASE; END IF; END PROCESS; --sumAHighB_uid242_sinPiZPolyEval(ADD,241)@14 sumAHighB_uid242_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid229_sinPiZTableGenerator_q(34)) & memoryC3_uid229_sinPiZTableGenerator_q); sumAHighB_uid242_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((35 downto 28 => reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q(27)) & reg_highBBits_uid241_sinPiZPolyEval_0_to_sumAHighB_uid242_sinPiZPolyEval_1_q); sumAHighB_uid242_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid242_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid242_sinPiZPolyEval_b)); sumAHighB_uid242_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_o(35 downto 0); --lowRangeB_uid240_sinPiZPolyEval(BITSELECT,239)@13 lowRangeB_uid240_sinPiZPolyEval_in <= prodXYTruncFR_uid267_pT2_uid239_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid240_sinPiZPolyEval_b <= lowRangeB_uid240_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a(DELAY,686)@13 ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid240_sinPiZPolyEval_b, xout => ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --s2_uid240_uid243_sinPiZPolyEval(BITJOIN,242)@14 s2_uid240_uid243_sinPiZPolyEval_q <= sumAHighB_uid242_sinPiZPolyEval_q & ld_lowRangeB_uid240_sinPiZPolyEval_b_to_s2_uid240_uid243_sinPiZPolyEval_a_q; --yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval(BITSELECT,274)@14 yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_in(36 downto 19); --reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9(REG,389)@14 reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q <= yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor(LOGICAL,950) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_b); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top(CONSTANT,946) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q <= "0110"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp(LOGICAL,947) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_mem_top_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_b else "0"; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg(REG,948) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmp_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena(REG,951) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_nor_q = "1") THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd(LOGICAL,952) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_sticky_ena_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt(COUNTER,942) -- every=1, low=0, high=6, step=1, init=1 ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i = 5 THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_eq = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i - 6; ELSE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_i,3)); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg(REG,943) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; END IF; END PROCESS; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux(MUX,944) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s <= VCC_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q) BEGIN CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_s IS WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem(DUALMEM,1069) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 3, numwords_a => 7, width_b => 45, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg(DELAY,1068) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT3_uid244_sinPiZPolyEval(BITSELECT,243)@14 yT3_uid244_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT3_uid244_sinPiZPolyEval_a_outputreg_q; yT3_uid244_sinPiZPolyEval_b <= yT3_uid244_sinPiZPolyEval_in(44 downto 10); --xBottomBits_uid274_pT3_uid245_sinPiZPolyEval(BITSELECT,273)@14 xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b(7 downto 0); xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_in(7 downto 0); --pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval(BITJOIN,276)@14 pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q <= xBottomBits_uid274_pT3_uid245_sinPiZPolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7(REG,391)@14 reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= "00000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid273_pT3_uid245_sinPiZPolyEval(BITSELECT,272)@14 yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q(9 downto 0); yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b <= yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_in(9 downto 0); --spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval(BITJOIN,275)@14 spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q <= GND_q & yBottomBits_uid273_pT3_uid245_sinPiZPolyEval_b; --pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval(BITJOIN,277)@14 pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q <= spad_yBottomBits_uid273_uid276_pT3_uid245_sinPiZPolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6(REG,390)@14 reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval(BITSELECT,271)@14 xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_in(34 downto 17); --reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4(REG,392)@14 reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= "000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q <= xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma(CHAINMULTADD,345)@15 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) * multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_p(1),38); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_w(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_x(0); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop18Bits_uid272_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_4_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid274_uid277_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_7_q),19)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid273_uid278_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_6_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid275_pT3_uid245_sinPiZPolyEval_0_to_multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_9_q),18)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0) <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_y(0); END IF; END PROCESS; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s(0),37)); multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval(BITSELECT,279)@18 multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_cma_q; multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_in(36 downto 7); --highBBits_uid282_pT3_uid245_sinPiZPolyEval(BITSELECT,281)@18 highBBits_uid282_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b; highBBits_uid282_pT3_uid245_sinPiZPolyEval_b <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_in(29 downto 1); --reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1(REG,395)@18 reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q <= highBBits_uid282_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval(BITSELECT,269)@14 yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in <= s2_uid240_uid243_sinPiZPolyEval_q; yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_in(36 downto 10); --reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1(REG,393)@14 reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q <= yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval(BITSELECT,268)@14 xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in <= yT3_uid244_sinPiZPolyEval_b; xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_in(34 downto 8); --reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0(REG,394)@14 reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q <= xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid271_pT3_uid245_sinPiZPolyEval(MULT,270)@15 topProd_uid271_pT3_uid245_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid271_pT3_uid245_sinPiZPolyEval_b); topProd_uid271_pT3_uid245_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= (others => '0'); topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_a <= reg_xTop27Bits_uid269_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_b <= reg_yTop27Bits_uid270_pT3_uid245_sinPiZPolyEval_0_to_topProd_uid271_pT3_uid245_sinPiZPolyEval_1_q; topProd_uid271_pT3_uid245_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid271_pT3_uid245_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid271_pT3_uid245_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid271_pT3_uid245_sinPiZPolyEval_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0(REG,396)@18 reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q <= topProd_uid271_pT3_uid245_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid283_pT3_uid245_sinPiZPolyEval(ADD,282)@19 sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q(53)) & reg_topProd_uid271_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_0_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid282_pT3_uid245_sinPiZPolyEval_0_to_sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_1_q); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_b)); sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid281_pT3_uid245_sinPiZPolyEval(BITSELECT,280)@18 lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in <= multSumOfTwo18_uid276_pT3_uid245_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b <= lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_in(0 downto 0); --ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a(DELAY,724)@18 ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b, xout => ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid281_uid284_pT3_uid245_sinPiZPolyEval(BITJOIN,283)@19 add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q <= sumAHighB_uid283_pT3_uid245_sinPiZPolyEval_q & ld_lowRangeB_uid281_pT3_uid245_sinPiZPolyEval_b_to_add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_a_q; --R_uid285_pT3_uid245_sinPiZPolyEval(BITSELECT,284)@19 R_uid285_pT3_uid245_sinPiZPolyEval_in <= add0_uid281_uid284_pT3_uid245_sinPiZPolyEval_q(54 downto 0); R_uid285_pT3_uid245_sinPiZPolyEval_b <= R_uid285_pT3_uid245_sinPiZPolyEval_in(54 downto 18); --reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1(REG,397)@19 reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q <= R_uid285_pT3_uid245_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor(LOGICAL,1168) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1164) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q <= "01011"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp(LOGICAL,1165) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg(REG,1166) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena(REG,1169) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1170) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1160) -- every=1, low=0, high=11, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i = 10 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i - 11; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_i,4)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg(REG,1161) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1162) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1159) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 4, numwords_a => 12, width_b => 7, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg(DELAY,1158) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0(REG,381)@18 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC2_uid228_sinPiZTableGenerator(LOOKUP,227)@19 memoryC2_uid228_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC2_uid228_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; WHEN "0000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010010000000010011011110101101000"; WHEN "0000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010100110111111010000111001000101"; WHEN "0000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101011001101001111001000101101101011"; WHEN "0000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101100000010110001110010011100100110"; WHEN "0000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101101000111100110110110100100001100"; WHEN "0000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101110011011101101110110101011000001"; WHEN "0000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101111111111000110001101110000001000"; WHEN "0001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110001110001101111010000000001001001"; WHEN "0001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110011110011101000001010111100010011"; WHEN "0001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110110110000100110000000101010101010010"; WHEN "0001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111000100101000101111111001111001110"; WHEN "0001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111011010100101000110010000000110000"; WHEN "0001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110111110010011010111010000010100101101"; WHEN "0001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000001100001010000000110001101010110"; WHEN "0001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111000100111110010001111000111001110001"; WHEN "0010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001000101010011011000111000110111111"; WHEN "0010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111001100100101101010001000110100001110"; WHEN "0010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010000101111111101001111011000110110"; WHEN "0010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111010101001001010010100101011111010000"; WHEN "0010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011001110001101000001111010001111100"; WHEN "0010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111011110101000111100001010010001101000"; WHEN "0010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111100011101111001100001101011001010011"; WHEN "0010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101001000100010110001000111111011001"; WHEN "0011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111101110101000010111100110110111011101"; WHEN "0011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111110100011011001110001010010101001001"; WHEN "0011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1010111111010011100110111010000000101010000"; WHEN "0011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000000101101010000001110011011110111"; WHEN "0011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000000111001100010110010101001001001010"; WHEN "0011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000001101111010000110101101100011101100"; WHEN "0011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000010100110110011110011010100101011100"; WHEN "0011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000011100000001011010011000101010010101"; WHEN "0100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000100011011010110111011101111001100010"; WHEN "0100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000101011000010110010011010000011100100"; WHEN "0100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000110010111001000111110110011110000010"; WHEN "0100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011000111010111101110100010110010000011111"; WHEN "0100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001000011010000110100010110001010111111"; WHEN "0100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001001011110010000100001100101110011011"; WHEN "0100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001010100100001100000001010001100011000"; WHEN "0100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001011101011111000100011000101001100001"; WHEN "0101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001100110101010101100111100000000011011"; WHEN "0101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001110000000100010101110001111101110010"; WHEN "0101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011001111001101011111010110010001100011010"; WHEN "0101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010000011100001010111101110001010011110"; WHEN "0101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010001101100100101000010001011000100111"; WHEN "0101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010010111110101101000000001010011000010"; WHEN "0101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010100010010100010010011101010101101010"; WHEN "0101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010101101000000100010111111000010000011"; WHEN "0110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011010110111111010010100111001111011100110"; WHEN "0110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011000011000001100011011011101110111001"; WHEN "0110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011001110010110001001101100001111110101"; WHEN "0110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011011001111000000010101101100000111100"; WHEN "0110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011100101100111001001011011101110011000"; WHEN "0110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011110001100011011000101101011001110101"; WHEN "0110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011011111101101100101011010011010110110001"; WHEN "0110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100001010000010111011111000101001101100"; WHEN "0111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100010110100110000101000010110110110100"; WHEN "0111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100100011010110000001010001110101000110"; WHEN "0111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100110000010010101010111111111100101100"; WHEN "0111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011100111101011011111100100010000110111111"; WHEN "0111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101001010110001110000000111101111100101"; WHEN "0111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101011000010011111111111010110011011100"; WHEN "0111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101100110000010100101111111111011010100"; WHEN "0111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011101110011111101011100010110011100010110"; WHEN "1000000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110000010000100011100111000010100111110"; WHEN "1000001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110010000010111100001011010011001010101"; WHEN "1000010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110011110110110100011101100001011001000"; WHEN "1000011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110101101100001011101011000001011011001"; WHEN "1000100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011110111100011000001000000011101110001111"; WHEN "1000101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111001011011010011101001111000101110001"; WHEN "1000110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111011010101000010110010101100101000110"; WHEN "1000111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111101010000001101100101101100010111111"; WHEN "1001000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1011111111001100110011001101000011100111011"; WHEN "1001001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000001001010110010110010010110100011100"; WHEN "1001010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000011001010001011011110100100000011000"; WHEN "1001011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000101001010111100011010000011111011101"; WHEN "1001100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100000111001101000100101100101001010011111"; WHEN "1001101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001001010000100011011101100001100000010"; WHEN "1001110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001011010101010111110011010101000110000"; WHEN "1001111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001101011011100000110100001001001100100"; WHEN "1010000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100001111100010111101100101011101111001100"; WHEN "1010001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010001101011101101001100010000010111010"; WHEN "1010010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010011110101101110101100111011000000101"; WHEN "1010011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100010110000001000001001011010101000000100"; WHEN "1010100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011000001101100011101010110100010000110"; WHEN "1010101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011010011011010101001110001100010110011"; WHEN "1010110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011100101010010100110111101111101101001"; WHEN "1010111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100011110111010100001101001010000001101110"; WHEN "1011000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100001001011111010100011111111010110111"; WHEN "1011001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100011011110011110101000101111001011001"; WHEN "1011010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100100101110010001100110111110001101101110"; WHEN "1011011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101000000111000100010000111010010100101"; WHEN "1011100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101010011101000011110011011110001111001"; WHEN "1011101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101100110100001010011110010100110010101"; WHEN "1011110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100101111001100010111001111110111010001011"; WHEN "1011111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110001100101101001000110000010101000001"; WHEN "1100000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110011111111111110111110010111000010010"; WHEN "1100001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100110110011011010111110101111001000100111"; WHEN "1100010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111000110111110010101001010001010011010"; WHEN "1100011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111011010101001110010100101101110010111"; WHEN "1100100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1100111101110011101001110100000001111101010"; WHEN "1100101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000000010011000100000010100110110100000"; WHEN "1100110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000010110011011011111011011100110110011"; WHEN "1100111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000101010100110000011001001011000000001"; WHEN "1101000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101000111110111000000010101111111100010101"; WHEN "1101001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001010011010001010101011110001011010100"; WHEN "1101010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001100111110001110010100000000000010111"; WHEN "1101011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101001111100011001010000111110011101110000"; WHEN "1101100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010010001000111100111111111110011011101"; WHEN "1101101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010100101111100101110100111100110010101"; WHEN "1101110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101010111010111000011011110110101001010101"; WHEN "1101111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011001111111010100110101011010011011011"; WHEN "1110000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011100101000011000110000001010000000100"; WHEN "1110001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101011111010010001110000110001110011111011"; WHEN "1110010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100001111100110011101110011111001111111"; WHEN "1110011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100100101000001000011111100000011011011"; WHEN "1110100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101100111010100001011001111100100100101001"; WHEN "1110101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101010000000111010110100101100100010111"; WHEN "1110110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101100101110010110000100101000101101101"; WHEN "1110111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101101111011100011011110100111000011010111"; WHEN "1111000" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110010001011001010111010101011001010001"; WHEN "1111001" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110100111010100010001011000001010110100"; WHEN "1111010" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101110111101010100000011010101100101100011"; WHEN "1111011" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111010011011000100011110010000011111011"; WHEN "1111100" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111101001100001101001010000010010001011"; WHEN "1111101" => memoryC2_uid228_sinPiZTableGenerator_q <= "1101111111111101111001010010001010101000011"; WHEN "1111110" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000010110000000111101010100101101001001"; WHEN "1111111" => memoryC2_uid228_sinPiZTableGenerator_q <= "1110000101100010110111000111000011010110101"; WHEN OTHERS => memoryC2_uid228_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid246_sinPiZPolyEval(CONSTANT,245) rndBit_uid246_sinPiZPolyEval_q <= "01"; --cIncludingRoundingBit_uid247_sinPiZPolyEval(BITJOIN,246)@19 cIncludingRoundingBit_uid247_sinPiZPolyEval_q <= memoryC2_uid228_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0(REG,398)@19 reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid247_sinPiZPolyEval_q; END IF; END PROCESS; --ts3_uid248_sinPiZPolyEval(ADD,247)@20 ts3_uid248_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid247_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_0_q); ts3_uid248_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q(36)) & reg_R_uid285_pT3_uid245_sinPiZPolyEval_0_to_ts3_uid248_sinPiZPolyEval_1_q); ts3_uid248_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid248_sinPiZPolyEval_a) + SIGNED(ts3_uid248_sinPiZPolyEval_b)); ts3_uid248_sinPiZPolyEval_q <= ts3_uid248_sinPiZPolyEval_o(45 downto 0); --s3_uid249_sinPiZPolyEval(BITSELECT,248)@20 s3_uid249_sinPiZPolyEval_in <= ts3_uid248_sinPiZPolyEval_q; s3_uid249_sinPiZPolyEval_b <= s3_uid249_sinPiZPolyEval_in(45 downto 1); --yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval(BITSELECT,286)@20 yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b; yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_in(44 downto 18); --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9(REG,399)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor(LOGICAL,1091) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top(CONSTANT,1087) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q <= "01100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp(LOGICAL,1088) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg(REG,1089) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena(REG,1092) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd(LOGICAL,1093) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1083) -- every=1, low=0, high=12, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i = 11 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i - 12; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_i,4)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg(REG,1084) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= "0000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux(MUX,1085) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem(DUALMEM,1082) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 4, numwords_a => 13, width_b => 45, widthad_b => 4, numwords_b => 13, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg(DELAY,1081) ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --yT4_uid250_sinPiZPolyEval(BITSELECT,249)@20 yT4_uid250_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_yT4_uid250_sinPiZPolyEval_a_outputreg_q; yT4_uid250_sinPiZPolyEval_b <= yT4_uid250_sinPiZPolyEval_in(44 downto 2); --xBottomBits_uid290_pT4_uid251_sinPiZPolyEval(BITSELECT,289)@20 xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in <= yT4_uid250_sinPiZPolyEval_b(15 downto 0); xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_in(15 downto 0); --pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval(BITJOIN,291)@20 pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q <= xBottomBits_uid290_pT4_uid251_sinPiZPolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7(REG,401)@20 reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid289_pT4_uid251_sinPiZPolyEval(BITSELECT,288)@20 yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in <= s3_uid249_sinPiZPolyEval_b(17 downto 0); yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b <= yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a(DELAY,733)@20 ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b, xout => ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval(BITJOIN,290)@21 spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid289_pT4_uid251_sinPiZPolyEval_b_to_spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_a_q; --pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval(BITJOIN,292)@21 pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q <= spad_yBottomBits_uid289_uid291_pT4_uid251_sinPiZPolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6(REG,400)@21 reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a(DELAY,727)@20 ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 43, depth => 1 ) PORT MAP ( xin => yT4_uid250_sinPiZPolyEval_b, xout => ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval(BITSELECT,285)@21 xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in <= ld_yT4_uid250_sinPiZPolyEval_b_to_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_a_q; xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_in(42 downto 16); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4(REG,402)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma(CHAINMULTADD,346)@22 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid290_uid292_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid289_uid293_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval(BITSELECT,294)@25 multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_cma_q; multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_in(54 downto 8); --highBBits_uid297_pT4_uid251_sinPiZPolyEval(BITSELECT,296)@25 highBBits_uid297_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b; highBBits_uid297_pT4_uid251_sinPiZPolyEval_b <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_in(46 downto 18); --reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1(REG,405)@25 reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q <= highBBits_uid297_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1(REG,403)@20 reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q <= yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b(DELAY,730)@21 ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0(REG,404)@21 reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q <= xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid288_pT4_uid251_sinPiZPolyEval(MULT,287)@22 topProd_uid288_pT4_uid251_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid288_pT4_uid251_sinPiZPolyEval_b); topProd_uid288_pT4_uid251_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= (others => '0'); topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_a <= reg_xTop27Bits_uid286_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid287_pT4_uid251_sinPiZPolyEval_0_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_1_q_to_topProd_uid288_pT4_uid251_sinPiZPolyEval_b_q; topProd_uid288_pT4_uid251_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid288_pT4_uid251_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid288_pT4_uid251_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid288_pT4_uid251_sinPiZPolyEval_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0(REG,406)@25 reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q <= topProd_uid288_pT4_uid251_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid298_pT4_uid251_sinPiZPolyEval(ADD,297)@26 sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q(53)) & reg_topProd_uid288_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_0_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid297_pT4_uid251_sinPiZPolyEval_0_to_sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_1_q); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_b)); sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid296_pT4_uid251_sinPiZPolyEval(BITSELECT,295)@25 lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in <= multSumOfTwo27_uid291_pT4_uid251_sinPiZPolyEval_b(17 downto 0); lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b <= lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_in(17 downto 0); --ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a(DELAY,741)@25 ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b, xout => ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid296_uid299_pT4_uid251_sinPiZPolyEval(BITJOIN,298)@26 add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q <= sumAHighB_uid298_pT4_uid251_sinPiZPolyEval_q & ld_lowRangeB_uid296_pT4_uid251_sinPiZPolyEval_b_to_add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_a_q; --R_uid300_pT4_uid251_sinPiZPolyEval(BITSELECT,299)@26 R_uid300_pT4_uid251_sinPiZPolyEval_in <= add0_uid296_uid299_pT4_uid251_sinPiZPolyEval_q(71 downto 0); R_uid300_pT4_uid251_sinPiZPolyEval_b <= R_uid300_pT4_uid251_sinPiZPolyEval_in(71 downto 26); --reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1(REG,407)@26 reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q <= R_uid300_pT4_uid251_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor(LOGICAL,1155) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1151) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q <= "010010"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp(LOGICAL,1152) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg(REG,1153) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena(REG,1156) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1157) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1147) -- every=1, low=0, high=18, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i = 17 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i - 18; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg(REG,1148) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1149) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1146) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 19, width_b => 7, widthad_b => 5, numwords_b => 19, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg(DELAY,1145) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0(REG,380)@25 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC1_uid227_sinPiZTableGenerator(LOOKUP,226)@26 memoryC1_uid227_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC1_uid227_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; WHEN "0000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111110101101010100010101111000000010001111100011"; WHEN "0000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111101011010101001001010010110100010110001011110"; WHEN "0000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111100000111111110111100000001110010011010000110"; WHEN "0000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111010110101010110001001011111100110111111100011"; WHEN "0000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111001100010101111010001010101001101111010110100"; WHEN "0000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11111000010000001010110010000110111110101011111000"; WHEN "0000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110110111101101001001010011000001101011000111010"; WHEN "0001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110101101011001010111000101010111101010010100111"; WHEN "0001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110100011000110000011011011111110011010111001110"; WHEN "0001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110011000110011010010001010101101000110101101101"; WHEN "0001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110001110100001000111000101001011101110011011101"; WHEN "0001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11110000100001111100101111110110001011110001011001"; WHEN "0001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101111001111110110010101010100011000010010100110"; WHEN "0001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101101111101110110000111011010000111100011100100"; WHEN "0001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101100101011111100100100011010101111000101000111"; WHEN "0010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101011011010001010001010100110101000010011111000"; WHEN "0010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101010001000011111011000001011000011010110000100"; WHEN "0010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11101000110110111100101011010001111001100111110010"; WHEN "0010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100111100101100010100010000001100000101010111010"; WHEN "0010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100110010100010001011010011100011100110101011100"; WHEN "0010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100101000011001001110010100001010100000101101100"; WHEN "0010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100011110010001100001000001010100000110110000000"; WHEN "0010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100010100001011000111001001110000100110010111000"; WHEN "0011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100001010000110000100011011101011011110011010110"; WHEN "0011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11100000000000010011100100100101001110110011000010"; WHEN "0011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011110110000000010011010001101000110110000011100"; WHEN "0011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011101011111111101100001110111011111101010000000"; WHEN "0011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011100010000000101011001000001011011100001111010"; WHEN "0011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011011000000011010011101000010010101100000110110"; WHEN "0011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011001110000111101001011001011110100111101110010"; WHEN "0011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11011000100001101110000000101001100000101000010010"; WHEN "0100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010111010010101101011010100000110001110011110001"; WHEN "0100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010110000011111011110101110000100111100111110101"; WHEN "0100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010100110101011001101111010001011010010011110011"; WHEN "0100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010011100111000111100011110100101110100010111000"; WHEN "0100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010010011001000101110000000101001000110111000111"; WHEN "0100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11010001001011010100110000100110000001000100101001"; WHEN "0100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001111111101110101000001110011010101110010001110"; WHEN "0100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001110110000100111000000000001011111111100011001"; WHEN "0101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001101100011101011000111011101000110011100100000"; WHEN "0101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001100010111000001110100001010110001110100101001"; WHEN "0101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001011001010101011100010000110111111111100011001"; WHEN "0101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001001111110101000101101000101110111110101110110"; WHEN "0101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "11001000110010111001110000110010111101100001101110"; WHEN "0101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000111100111011111001000110001000101111011110000"; WHEN "0101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000110011100011001010000011010001010111001000100"; WHEN "0101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000101010001101000100010111110111111001010110011"; WHEN "0110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000100000111001101011011100111000010100110100100"; WHEN "0110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000010111101001000010101010000010110010001100101"; WHEN "0110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000001110011011001101010101111010000110001110001"; WHEN "0110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "11000000101010000001110110101110010010100010001010"; WHEN "0110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111111100001000001010011101101111010001101110100"; WHEN "0110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111110011000011000011100000100011001001100111111"; WHEN "0110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111101010000000111101001111101101000001001100111"; WHEN "0110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111100001000001111010111011010111011101000011000"; WHEN "0111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111011000000101111111110010010111000110100000100"; WHEN "0111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111001111001101001111000010001001010010011000111"; WHEN "0111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10111000110010111101011110110110010100111101001111"; WHEN "0111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110111101100101011001011010111101100111001001111"; WHEN "0111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110110100110110011010110111111001010011111110011"; WHEN "0111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110101100001010110011010101010111111100100001011"; WHEN "0111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110100011100010100101111001101101100100000011010"; WHEN "0111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110011010111101110101101001101110101101001000101"; WHEN "1000000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110010010011100100101101000101111000100111000101"; WHEN "1000001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110001001111110111000111000100000001110100110010"; WHEN "1000010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10110000001100100110010011001010000010000100100001"; WHEN "1000011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101111001001110010101001001101000100001000011111"; WHEN "1000100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101110000111011100100000110101100010100101111011"; WHEN "1000101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101101000101100100010001011110111101101010011001"; WHEN "1000110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101100000100001010010010010111110001001000100100"; WHEN "1000111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101011000011001110111010100001001010011011010001"; WHEN "1001000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101010000010110010100000101110111110101110111011"; WHEN "1001001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101001000010110101011011100111100001010010001010"; WHEN "1001010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10101000000011011000000001100011011001101001101101"; WHEN "1001011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100111000100011010101000101101011010001111110100"; WHEN "1001100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100110000101111101100111000010010110110101001010"; WHEN "1001101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100101001000000001010010010000111011001100101001"; WHEN "1001110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100100001010100101111111111001100001111011011000"; WHEN "1001111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100011001101101100000101001110001011001110111100"; WHEN "1010000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100010010001010011110111010010010011111110100100"; WHEN "1010001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100001010101011101101010111010101100101110000010"; WHEN "1010010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10100000011010001001110100101101010000111010011101"; WHEN "1010011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011111011111011000101001000000111110001110111111"; WHEN "1010100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011110100101001010011011111101101011111101000010"; WHEN "1010101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011101101011011111100001011100000010100000001101"; WHEN "1010110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011100110010011000001101000101010011000110001101"; WHEN "1010111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011111001110100110010010011001111011110111011"; WHEN "1011000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011011000001110101100100010000000001110100011101"; WHEN "1011001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011010001010011010110101110110000100101001100010"; WHEN "1011010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011001010011100100111001101111111011000001100001"; WHEN "1011011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10011000011101010100000010011000001000101101011001"; WHEN "1011100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010111100111101000100001111001001010100001001100"; WHEN "1011101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010110110010100010101010001101001110110001111011"; WHEN "1011110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101111110000010101100111110001101111011011100"; WHEN "1011111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010101001010001000111011100101100011001011100101"; WHEN "1100000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010100010110110101100111001100000101011000010000"; WHEN "1100001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010011100100001001000000101001111111111010110011"; WHEN "1100010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010110010000011011000100110101011110110000011"; WHEN "1100011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010010000000100100111111011000101001000001000001"; WHEN "1100100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010001001111101110000101000101010111011100100101"; WHEN "1100101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10010000011111011110111001100001010000110000001000"; WHEN "1100110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111101111110111101100001111100001101100011111"; WHEN "1100111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001111000000111000101100100010000011111010101010"; WHEN "1101000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001110010010100010001001011001010111110000100010"; WHEN "1101001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001101100100110100010001100100011110001100110110"; WHEN "1101010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100110111101111010011100000110010111101110011"; WHEN "1101011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001100001011010011011101011010000110101111000110"; WHEN "1101100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001011011111100000111101001010011001011111101101"; WHEN "1101101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010110100011000000000011001110101000000001010"; WHEN "1101110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001010001001111000110100011110100111011011010110"; WHEN "1101111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001001100000000011100110011100111110000011010110"; WHEN "1110000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000110110111000100011000111000000001100101100"; WHEN "1110001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10001000001110010111110110111100101010001100011100"; WHEN "1110010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000111100110100001101110001011101000100010101000"; WHEN "1110011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110111111010110010100101111010011001100111001"; WHEN "1110100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000110011000110101110110010000101000111111101001"; WHEN "1110101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101110011000000011110000110001011001010001101"; WHEN "1110110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000101001101110110010111010011111001000001110011"; WHEN "1110111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100101001010111101100101011001011110111111001"; WHEN "1111000" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000100000101100100101000101010110010110110110011"; WHEN "1111001" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011100010011101010101011110101111000111101111"; WHEN "1111010" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000011000000000001111101000000010000000010001101"; WHEN "1111011" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000010011110010010101000110101101111100100010110"; WHEN "1111100" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001111101001111100010010010101110110011110010"; WHEN "1111101" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000001011100111000110010010111110010100110111110"; WHEN "1111110" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000111101001110100001110010100000011000001001"; WHEN "1111111" => memoryC1_uid227_sinPiZTableGenerator_q <= "10000000011110010000111000111101011011000001000111"; WHEN OTHERS => memoryC1_uid227_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110"; END CASE; -- End reserved scope level END PROCESS; --cIncludingRoundingBit_uid253_sinPiZPolyEval(BITJOIN,252)@26 cIncludingRoundingBit_uid253_sinPiZPolyEval_q <= memoryC1_uid227_sinPiZTableGenerator_q & rndBit_uid246_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0(REG,408)@26 reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid253_sinPiZPolyEval_q; END IF; END PROCESS; --ts4_uid254_sinPiZPolyEval(ADD,253)@27 ts4_uid254_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((52 downto 52 => reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q(51)) & reg_cIncludingRoundingBit_uid253_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_0_q); ts4_uid254_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((52 downto 46 => reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q(45)) & reg_R_uid300_pT4_uid251_sinPiZPolyEval_0_to_ts4_uid254_sinPiZPolyEval_1_q); ts4_uid254_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid254_sinPiZPolyEval_a) + SIGNED(ts4_uid254_sinPiZPolyEval_b)); ts4_uid254_sinPiZPolyEval_q <= ts4_uid254_sinPiZPolyEval_o(52 downto 0); --s4_uid255_sinPiZPolyEval(BITSELECT,254)@27 s4_uid255_sinPiZPolyEval_in <= ts4_uid254_sinPiZPolyEval_q; s4_uid255_sinPiZPolyEval_b <= s4_uid255_sinPiZPolyEval_in(52 downto 1); --yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval(BITSELECT,301)@27 yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b; yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_in(51 downto 25); --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9(REG,409)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor(LOGICAL,1117) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q <= not (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_a or ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_b); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top(CONSTANT,1113) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q <= "010011"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp(LOGICAL,1114) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_mem_top_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_a = ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_b else "0"; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg(REG,1115) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmp_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena(REG,1118) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_nor_q = "1") THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd(LOGICAL,1119) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_sticky_ena_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_a and ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_b; --xBottomBits_uid305_pT5_uid257_sinPiZPolyEval(BITSELECT,304)@5 xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in <= zPPolyEval_uid64_fpSinPiTest_b(17 downto 0); xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_in(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt(COUNTER,1109) -- every=1, low=0, high=19, step=1, init=1 ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i = 18 THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '1'; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_eq = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i - 19; ELSE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_i,5)); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg(REG,1110) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; END IF; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux(MUX,1111) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s <= VCC_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q) BEGIN CASE ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_s IS WHEN "0" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; WHEN "1" => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdcnt_q; WHEN OTHERS => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem(DUALMEM,1108) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0 <= areset; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia <= xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdreg_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_rdmux_q; ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 5, numwords_a => 20, width_b => 18, widthad_b => 5, numwords_b => 20, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_reset0, clock1 => clk, address_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq, address_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_aa, data_a => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_ia ); ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_iq(17 downto 0); --ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg(DELAY,1107) ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_replace_mem_q, xout => ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q, clk => clk, aclr => areset ); --pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval(BITJOIN,306)@27 pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q <= ld_xBottomBits_uid305_pT5_uid257_sinPiZPolyEval_b_to_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q); --reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7(REG,411)@27 reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= "00000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q <= pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --yBottomBits_uid304_pT5_uid257_sinPiZPolyEval(BITSELECT,303)@27 yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in <= s4_uid255_sinPiZPolyEval_b(24 downto 0); yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b <= yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a(DELAY,750)@27 ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b, xout => ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval(BITJOIN,305)@28 spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid304_pT5_uid257_sinPiZPolyEval_b_to_spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_a_q; --pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval(BITJOIN,307)@28 pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q <= spad_yBottomBits_uid304_uid306_pT5_uid257_sinPiZPolyEval_q & GND_q; --reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6(REG,410)@28 reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor(LOGICAL,1104) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_b); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top(CONSTANT,1100) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q <= "010100"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp(LOGICAL,1101) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_mem_top_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_b else "0"; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg(REG,1102) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmp_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena(REG,1105) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_nor_q = "1") THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd(LOGICAL,1106) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_sticky_ena_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_b; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1096) -- every=1, low=0, high=20, step=1, init=1 ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i = 19 THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i - 20; ELSE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_i,5)); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg(REG,1097) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux(MUX,1098) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem(DUALMEM,1095) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid64_fpSinPiTest_b; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdreg_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_rdmux_q; ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 45, widthad_a => 5, numwords_a => 21, width_b => 45, widthad_b => 5, numwords_b => 21, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_ia ); ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_iq(44 downto 0); --ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg(DELAY,1094) ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg : dspba_delay GENERIC MAP ( width => 45, depth => 1 ) PORT MAP ( xin => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset ); --xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval(BITSELECT,300)@28 xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in <= ld_zPPolyEval_uid64_fpSinPiTest_b_to_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_a_outputreg_q; xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_in(44 downto 18); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4(REG,412)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma(CHAINMULTADD,347)@29 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(0),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_p(1),56); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_w(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_x(1); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c <= (others => (others => '0')); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s <= (others => (others => '0')); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_4_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(reg_pad_xBottomBits_uid305_uid307_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_7_q),28)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid304_uid308_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_6_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_9_q),27)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(0); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_y(1); END IF; END PROCESS; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s(0),55)); multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_s0; END IF; END PROCESS; --multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval(BITSELECT,309)@32 multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_cma_q; multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_in(54 downto 1); --highBBits_uid312_pT5_uid257_sinPiZPolyEval(BITSELECT,311)@32 highBBits_uid312_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b; highBBits_uid312_pT5_uid257_sinPiZPolyEval_b <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_in(53 downto 25); --reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1(REG,415)@32 reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= "00000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q <= highBBits_uid312_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1(REG,413)@27 reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q <= yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b(DELAY,747)@28 ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b : dspba_delay GENERIC MAP ( width => 27, depth => 1 ) PORT MAP ( xin => reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q, clk => clk, aclr => areset ); --reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0(REG,414)@28 reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q <= xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --topProd_uid303_pT5_uid257_sinPiZPolyEval(MULT,302)@29 topProd_uid303_pT5_uid257_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid303_pT5_uid257_sinPiZPolyEval_b); topProd_uid303_pT5_uid257_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= (others => '0'); topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_a <= reg_xTop27Bits_uid301_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid302_pT5_uid257_sinPiZPolyEval_0_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_1_q_to_topProd_uid303_pT5_uid257_sinPiZPolyEval_b_q; topProd_uid303_pT5_uid257_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid303_pT5_uid257_sinPiZPolyEval_pr,54)); END IF; END PROCESS; topProd_uid303_pT5_uid257_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN topProd_uid303_pT5_uid257_sinPiZPolyEval_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_s1; END IF; END PROCESS; --reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0(REG,416)@32 reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q <= topProd_uid303_pT5_uid257_sinPiZPolyEval_q; END IF; END PROCESS; --sumAHighB_uid313_pT5_uid257_sinPiZPolyEval(ADD,312)@33 sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q(53)) & reg_topProd_uid303_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_0_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid312_pT5_uid257_sinPiZPolyEval_0_to_sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_1_q); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_b)); sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_o(54 downto 0); --lowRangeB_uid311_pT5_uid257_sinPiZPolyEval(BITSELECT,310)@32 lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in <= multSumOfTwo27_uid306_pT5_uid257_sinPiZPolyEval_b(24 downto 0); lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b <= lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_in(24 downto 0); --ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a(DELAY,758)@32 ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b, xout => ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q, clk => clk, aclr => areset ); --add0_uid311_uid314_pT5_uid257_sinPiZPolyEval(BITJOIN,313)@33 add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q <= sumAHighB_uid313_pT5_uid257_sinPiZPolyEval_q & ld_lowRangeB_uid311_pT5_uid257_sinPiZPolyEval_b_to_add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_a_q; --R_uid315_pT5_uid257_sinPiZPolyEval(BITSELECT,314)@33 R_uid315_pT5_uid257_sinPiZPolyEval_in <= add0_uid311_uid314_pT5_uid257_sinPiZPolyEval_q(78 downto 0); R_uid315_pT5_uid257_sinPiZPolyEval_b <= R_uid315_pT5_uid257_sinPiZPolyEval_in(78 downto 25); --reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1(REG,417)@33 reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= "000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q <= R_uid315_pT5_uid257_sinPiZPolyEval_b; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor(LOGICAL,1142) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q <= not (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_a or ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_b); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top(CONSTANT,1138) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q <= "011001"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp(LOGICAL,1139) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_mem_top_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q <= "1" when ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_a = ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_b else "0"; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg(REG,1140) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmp_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena(REG,1143) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_nor_q = "1") THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd(LOGICAL,1144) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_sticky_ena_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_a and ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_b; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt(COUNTER,1134) -- every=1, low=0, high=25, step=1, init=1 ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i = 24 THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '1'; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_eq = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i - 25; ELSE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_i,5)); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg(REG,1135) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux(MUX,1136) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s <= VCC_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux: PROCESS (ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q, ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q) BEGIN CASE ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_s IS WHEN "0" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; WHEN "1" => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem(DUALMEM,1133) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia <= zAddr_uid63_fpSinPiTest_b; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdreg_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_rdmux_q; ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 7, widthad_a => 5, numwords_a => 26, width_b => 7, widthad_b => 5, numwords_b => 26, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq, address_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_aa, data_a => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_ia ); ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_iq(6 downto 0); --ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg(DELAY,1132) ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg : dspba_delay GENERIC MAP ( width => 7, depth => 1 ) PORT MAP ( xin => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_replace_mem_q, xout => ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q, clk => clk, aclr => areset ); --reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0(REG,379)@32 reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q <= ld_zAddr_uid63_fpSinPiTest_b_to_reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_a_outputreg_q; END IF; END PROCESS; --memoryC0_uid226_sinPiZTableGenerator(LOOKUP,225)@33 memoryC0_uid226_sinPiZTableGenerator: PROCESS (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) BEGIN -- Begin reserved scope level CASE (reg_zAddr_uid63_fpSinPiTest_0_to_memoryC0_uid226_sinPiZTableGenerator_0_q) IS WHEN "0000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; WHEN "0000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111010001111111001101111011000111100001001010"; WHEN "0000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000101010101111101111010001101100110011111100100"; WHEN "0000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000010000111010001110111000001110010011001110001"; WHEN "0000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001111101100101111100010000110111011000000101000010"; WHEN "0000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110111110001111110110010110011100111000110011101"; WHEN "0000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001110000101011011011100110100000100010100111010101"; WHEN "0000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001101000010010010101010100001100000100101011101101"; WHEN "0001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001011110100110101111000010100110110100001011000010"; WHEN "0001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001010011101000101100010111000010101101001011110101"; WHEN "0001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010001000111011000010001010101010001011100000010111010"; WHEN "0001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000111001110101100010011111100010101010110110110111"; WHEN "0001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000101011000000100100110110100010000001101000110010"; WHEN "0001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000011010111001011101111001010100111001000011000110"; WHEN "0001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010000001001100000010011100101010111111111101111100110"; WHEN "0001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111110110110101001100010110011100110010010101101111"; WHEN "0010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111100010111000001111000110100110100110000010101111"; WHEN "0010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001111001101101001100011001110000111100101111100011100"; WHEN "0010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110110111001001010000100011011101100011000000101111"; WHEN "0010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110011111010111011111011011001110010110110010111000"; WHEN "0010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001110000110010100011000101000000100011000111000100110"; WHEN "0010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101101100000000000101011010101010100111001000011100"; WHEN "0010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001101010000011010101111100001101000100000101011011110"; WHEN "0010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100110011100100100001001001011101110011110100001011"; WHEN "0011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001100010101011101100100111100011101111110101100100111"; WHEN "0011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011110110000110000110000010101011100010111110000011"; WHEN "0011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001011010101011110010000000001110011001100010100001001"; WHEN "0011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010110011100110001110111101000110101001111110010101"; WHEN "0011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001010010000011110001111010101010111011011010001011111"; WHEN "0011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001101100000110011110001000110001001111001100110001"; WHEN "0011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001001000110011111001000110010110100010111000011111111"; WHEN "0011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110001000011111101000011101001100001111101100010010011001"; WHEN "0100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111110111100010101001101010111010101001011000110001"; WHEN "0100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000111001110001101111101000001101110110110001001100100"; WHEN "0100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000110100011101010100110100000100001100111000110001110"; WHEN "0100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101110111111000110101110011111101010000010000111000"; WHEN "0100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000101001010111000111011000101011010001011010101011100"; WHEN "0100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000100011100101011000110111010110111110001001101100111"; WHEN "0100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000011101101001111101010010110110101000111000011000010"; WHEN "0100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010111100100110110110111000001001011110110011001101"; WHEN "0101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000010001010110000111110011001111100101011011000101100"; WHEN "0101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000001010111101110010011010011011111001000011101001111"; WHEN "0101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0110000000100011011111001000011000000001110101111000110101"; WHEN "0101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111111101110000011110000110110101110000111000001001000"; WHEN "0101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111110110111011100100000011010011101000101101101101111"; WHEN "0101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101111111101001101011001001101111001001010100111010"; WHEN "0101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111101000110101011100101100110100011000001100101000111"; WHEN "0101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111100001100100010100100101110001100110101011111100110"; WHEN "0110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111011010001001110111101111001001100110110011000001101"; WHEN "0110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111010010100110001000110111011000110000110111110111111"; WHEN "0110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111001010111001001010110000010010100110110110111111101"; WHEN "0110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101111000011000011000000001111000000100110010000101101101"; WHEN "0110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110111011000011101100001100000000111000101001011011010"; WHEN "0110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110110010111011010001100011000101000010101101011001001"; WHEN "0110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110101010101001110011010011010000110001111000101001011"; WHEN "0110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110100010001111010100011110111000101000100011101001111"; WHEN "0111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110011001101011111000001011100000101000110101010111101"; WHEN "0111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110010000111111100001100001111010111101111011010000110"; WHEN "0111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101110001000001010010011101110000110100100001000000010111"; WHEN "0111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101111111001100010001111111001101101111011001101100100"; WHEN "0111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101110110000101011111100111100100110000100111011101101"; WHEN "0111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101101100110101111111111100101000011001011000100010101"; WHEN "0111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101100011011101110110010110111100011110100100000110011"; WHEN "0111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101011001111101000110010010001010011001011011010110110"; WHEN "1000000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101010000010011110011001100111111100111011110011001101"; WHEN "1000001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101101000110100010000000101001001100001000111100100001001"; WHEN "1000010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100111100100111110010001011100000111110000000101011101"; WHEN "1000011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100110010100101001011011011101110100010101011000001110"; WHEN "1000100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100101000011010010000000100100011001001010111111110011"; WHEN "1000101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100011110000111000011110011101001010100010101110100101"; WHEN "1000110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100010011101011101010011001100110001101101001100010111"; WHEN "1000111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101100001001001000000111101001110111111110000011100100111"; WHEN "1001000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011111110011100011111011010110100000010100101010111001"; WHEN "1001001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011110011101000110101100101100101100000111000011110001"; WHEN "1001010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011101000101101001110000110001011011010011000000110010"; WHEN "1001011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011011101101001101100111011010110111110001101101101010"; WHEN "1001100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011010010011110010110000110101001111010000001101101100"; WHEN "1001101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101011000111001011001101101100010100101001100000111100110"; WHEN "1001110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010111011110000010111110011010100100100110111110110011"; WHEN "1001111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010110000001101111000100101010010001110000100000110101"; WHEN "1010000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010100100100011110100001110011111011100111101101011110"; WHEN "1010001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010011000110010001110111101110101101010011000000111111"; WHEN "1010010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010001100111001001101000100110011111001111100111000001"; WHEN "1010011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101010000000111000110010110111011101000010111111101010001"; WHEN "1010100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001110100110001000100101100010101111000001101101010100"; WHEN "1010101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001101000100010000110111100100011001110011000100010010"; WHEN "1010110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001011100001011111110000011101000000001111110000000000"; WHEN "1010111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001001111101110101110011111100011011011101101000101110"; WHEN "1011000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101001000011001010011100110000101110110100001001110110000"; WHEN "1011001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000110110011111001101011001111011110110010000011100000"; WHEN "1011010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000101001101101000101000000010010100000111000101001110"; WHEN "1011011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000011100110100001000001011001111000111011010101001101"; WHEN "1011100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000001111110100011011100100100000010001010101111111000"; WHEN "1011101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0101000000010101110000011111000000100111000111011110010110"; WHEN "1011110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111110101100001000101110100001010001000111101001001101"; WHEN "1011111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111101000001101100110001001001001011001011110100011010"; WHEN "1100000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111011010110011101001101001100110001011110001011110000"; WHEN "1100001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100111001101010011010101001010001100000101010101000000111"; WHEN "1100010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110111111101100101101100001101100101001111110101000001"; WHEN "1100011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110110001111111110111101000111101010101001011110111000"; WHEN "1100100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110100100001100111000011010110101010010011110001011110"; WHEN "1100101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110010110010011110100110100001011010101000001111000001"; WHEN "1100110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100110001000010100110001110011110011101110100000111111001"; WHEN "1100111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101111010001111110100011010011110000101000011010111010"; WHEN "1101000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101101100000101000001101010110011001000011100110100101"; WHEN "1101001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101011101110100011110101001010010100110101010011100110"; WHEN "1101010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101001111011110010000011100010000111111100000000100011"; WHEN "1101011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100101000001000010011100001011110101010111100110111011100"; WHEN "1101100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100110010100001000111000001110111001010101110101010001"; WHEN "1101101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100100011111010010110001001111011111101010001100000100"; WHEN "1101110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100010101001110001110110001010101001101001100111101111"; WHEN "1101111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100100000110011100110110000110111110000010001111110011101"; WHEN "1110000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011110111100110010001011011011000111101011110100101010"; WHEN "1110001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011101000101010100110000000101101101000001111101101101"; WHEN "1110010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011011001101001111001001010100110100010100000001010111"; WHEN "1110011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100011001010100100010000001110001110110000100001110111001"; WHEN "1110100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010111011011001110000100010001111101000000100110100000"; WHEN "1110101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010101100001010011111011110101110011100111100001100101"; WHEN "1110110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010011100110110100010011101001010001101000000010101011"; WHEN "1110111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100010001101011101111110111000011001001011101110101101100"; WHEN "1111000" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001111110000000111010001100100110101101001001001010110"; WHEN "1111001" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001101110011111011001110111010000110000010101010100001"; WHEN "1111010" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001011110111001100011010111000101101001011101010010011"; WHEN "1111011" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100001001111001111011100001100000001101011010010111101001"; WHEN "1111100" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000111111100001001001110111001100110000010110101011110"; WHEN "1111101" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000101111101110110001111010111000000011100010110001010"; WHEN "1111110" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000011111111000011001111010011011101000011100101001111"; WHEN "1111111" => memoryC0_uid226_sinPiZTableGenerator_q <= "0100000001111111110000111011010010100000011001101000010011"; WHEN OTHERS => memoryC0_uid226_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000"; END CASE; -- End reserved scope level END PROCESS; --rndBit_uid258_sinPiZPolyEval(CONSTANT,257) rndBit_uid258_sinPiZPolyEval_q <= "001"; --cIncludingRoundingBit_uid259_sinPiZPolyEval(BITJOIN,258)@33 cIncludingRoundingBit_uid259_sinPiZPolyEval_q <= memoryC0_uid226_sinPiZTableGenerator_q & rndBit_uid258_sinPiZPolyEval_q; --reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0(REG,418)@33 reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid259_sinPiZPolyEval_q; END IF; END PROCESS; --ts5_uid260_sinPiZPolyEval(ADD,259)@34 ts5_uid260_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid259_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_0_q); ts5_uid260_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((61 downto 54 => reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q(53)) & reg_R_uid315_pT5_uid257_sinPiZPolyEval_0_to_ts5_uid260_sinPiZPolyEval_1_q); ts5_uid260_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid260_sinPiZPolyEval_a) + SIGNED(ts5_uid260_sinPiZPolyEval_b)); ts5_uid260_sinPiZPolyEval_q <= ts5_uid260_sinPiZPolyEval_o(61 downto 0); --s5_uid261_sinPiZPolyEval(BITSELECT,260)@34 s5_uid261_sinPiZPolyEval_in <= ts5_uid260_sinPiZPolyEval_q; s5_uid261_sinPiZPolyEval_b <= s5_uid261_sinPiZPolyEval_in(61 downto 1); --fxpSinRes_uid66_fpSinPiTest(BITSELECT,65)@34 fxpSinRes_uid66_fpSinPiTest_in <= s5_uid261_sinPiZPolyEval_b(58 downto 0); fxpSinRes_uid66_fpSinPiTest_b <= fxpSinRes_uid66_fpSinPiTest_in(58 downto 5); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor(LOGICAL,963) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q <= not (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_a or ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_b); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top(CONSTANT,959) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q <= "011111"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp(LOGICAL,960) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_mem_top_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q <= "1" when ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_a = ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_b else "0"; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg(REG,961) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena(REG,964) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_nor_q = "1") THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd(LOGICAL,965) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_sticky_ena_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_a and ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_b; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt(COUNTER,955) -- every=1, low=0, high=31, step=1, init=1 ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ELSIF (clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg(REG,956) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux(MUX,957) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux: PROCESS (ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q, ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem(DUALMEM,954) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia <= sinXIsX_uid30_fpSinPiTest_c; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdreg_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_rdmux_q; ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 32, width_b => 1, widthad_b => 5, numwords_b => 32, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq, address_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_aa, data_a => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_ia ); ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg(DELAY,953) ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_replace_mem_q, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --multRightOp_uid68_fpSinPiTest(MUX,67)@34 multRightOp_uid68_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_multRightOp_uid68_fpSinPiTest_b_outputreg_q; multRightOp_uid68_fpSinPiTest: PROCESS (multRightOp_uid68_fpSinPiTest_s, fxpSinRes_uid66_fpSinPiTest_b) BEGIN CASE multRightOp_uid68_fpSinPiTest_s IS WHEN "0" => multRightOp_uid68_fpSinPiTest_q <= fxpSinRes_uid66_fpSinPiTest_b; WHEN "1" => multRightOp_uid68_fpSinPiTest_q <= piwFP2_uid67_fpSinPiTest_q; WHEN OTHERS => multRightOp_uid68_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_b_1(BITSELECT,318)@34 mul2xSinRes_uid69_fpSinPiTest_b_1_in <= multRightOp_uid68_fpSinPiTest_q; mul2xSinRes_uid69_fpSinPiTest_b_1_b <= mul2xSinRes_uid69_fpSinPiTest_b_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1(REG,423)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor(LOGICAL,1129) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q <= not (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_a or ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_b); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top(CONSTANT,1125) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q <= "010110"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp(LOGICAL,1126) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_mem_top_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q <= "1" when ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_a = ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_b else "0"; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg(REG,1127) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmp_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena(REG,1130) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_nor_q = "1") THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd(LOGICAL,1131) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_sticky_ena_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_a and ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor(LOGICAL,937) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_a or ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_b); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top(CONSTANT,933) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q <= "0111"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp(LOGICAL,934) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_mem_top_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_a = ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_b else "0"; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg(REG,935) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmp_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena(REG,938) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_nor_q = "1") THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd(LOGICAL,939) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_sticky_ena_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_b; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt(COUNTER,929) -- every=1, low=0, high=7, step=1, init=1 ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,3); ELSIF (clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i + 1; END IF; END PROCESS; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_i,3)); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg(REG,930) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= "000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; END IF; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux(MUX,931) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s <= VCC_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q) BEGIN CASE ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_s IS WHEN "0" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; WHEN "1" => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdcnt_q; WHEN OTHERS => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem(DUALMEM,928) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0 <= areset; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia <= oFracX_uid31_uid31_fpSinPiTest_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdreg_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_rdmux_q; ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 3, numwords_a => 8, width_b => 53, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq, address_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_aa, data_a => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_ia ); ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_iq(52 downto 0); --ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg(DELAY,927) ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg : dspba_delay GENERIC MAP ( width => 53, depth => 1 ) PORT MAP ( xin => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_replace_mem_q, xout => ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q, clk => clk, aclr => areset ); --LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest(BITSELECT,220)@10 LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q(77 downto 0); LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_in(77 downto 0); --leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest(BITJOIN,221)@10 leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage277dto0_uid221_alignedZ_uid52_fpSinPiTest_b & GND_q; --LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest(BITSELECT,204)@9 LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(54 downto 0); LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_in(54 downto 0); --leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest(BITJOIN,205)@9 leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage054dto0_uid205_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid123_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest(BITSELECT,201)@9 LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(62 downto 0); LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_in(62 downto 0); --leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest(BITJOIN,202)@9 leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage062dto0_uid202_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; --LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest(BITSELECT,198)@9 LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q(70 downto 0); LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_in(70 downto 0); --leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest(BITJOIN,199)@9 leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage070dto0_uid199_alignedZ_uid52_fpSinPiTest_b & leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; --ozz_uid41_fpSinPiTest(CONSTANT,40) ozz_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor(LOGICAL,1040) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q <= not (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_a or ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_b); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top(CONSTANT,1036) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q <= "011"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp(LOGICAL,1037) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_mem_top_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q <= "1" when ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_a = ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_b else "0"; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg(REG,1038) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena(REG,1041) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_nor_q = "1") THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd(LOGICAL,1042) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_sticky_ena_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_a and ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_b; --vStage_uid149_lzcZ_uid51_fpSinPiTest(BITSELECT,148)@4 vStage_uid149_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(14 downto 0); vStage_uid149_lzcZ_uid51_fpSinPiTest_b <= vStage_uid149_lzcZ_uid51_fpSinPiTest_in(14 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt(COUNTER,1032) -- every=1, low=0, high=3, step=1, init=1 ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,2); ELSIF (clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END PROCESS; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_i,2)); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg(REG,1033) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux(MUX,1034) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q, ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1043) ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= vStage_uid149_lzcZ_uid51_fpSinPiTest_b; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 2, numwords_a => 4, width_b => 15, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(14 downto 0); --leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest(BITJOIN,193)@9 leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; --X46dto0_uid190_alignedZ_uid52_fpSinPiTest(BITSELECT,189)@4 X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in <= z_uid49_fpSinPiTest_q(46 downto 0); X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_in(46 downto 0); --ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem(DUALMEM,1031) ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia <= X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdreg_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_rdmux_q; ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 47, widthad_a => 2, numwords_a => 4, width_b => 47, widthad_b => 2, numwords_b => 4, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq, address_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_aa, data_a => ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_ia ); ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_iq(46 downto 0); --leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest(BITJOIN,190)@9 leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q <= ld_X46dto0_uid190_alignedZ_uid52_fpSinPiTest_b_to_leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor(LOGICAL,1065) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q <= not (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_a or ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_b); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top(CONSTANT,1061) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q <= "010"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp(LOGICAL,1062) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_mem_top_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q <= "1" when ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_a = ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_b else "0"; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg(REG,1063) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmp_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena(REG,1066) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_nor_q = "1") THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd(LOGICAL,1067) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_sticky_ena_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_a and ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_b; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt(COUNTER,1057) -- every=1, low=0, high=2, step=1, init=1 ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i = 1 THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_eq = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i - 2; ELSE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_i,2)); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg(REG,1058) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; END IF; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux(MUX,1059) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s <= VCC_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux: PROCESS (ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q) BEGIN CASE ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_s IS WHEN "0" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; WHEN "1" => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem(DUALMEM,1056) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0 <= areset; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia <= z_uid49_fpSinPiTest_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdreg_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_rdmux_q; ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 79, widthad_a => 2, numwords_a => 3, width_b => 79, widthad_b => 2, numwords_b => 3, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq, address_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_aa, data_a => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_ia ); ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_iq(78 downto 0); --ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg(DELAY,1055) ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg : dspba_delay GENERIC MAP ( width => 79, depth => 1 ) PORT MAP ( xin => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_replace_mem_q, xout => ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, clk => clk, aclr => areset ); --rVStage_uid146_lzcZ_uid51_fpSinPiTest(BITSELECT,145)@4 rVStage_uid146_lzcZ_uid51_fpSinPiTest_in <= z_uid49_fpSinPiTest_q; rVStage_uid146_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_in(78 downto 15); --reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0(REG,365)@4 reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid146_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid147_lzcZ_uid51_fpSinPiTest(LOGICAL,146)@5 vCount_uid147_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid146_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid147_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx2Pad64_uid111_fixedPointX_uid37_fpSinPiTest_q; vCount_uid147_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid147_lzcZ_uid51_fpSinPiTest_a = vCount_uid147_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g(DELAY,629)@5 ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => vCount_uid147_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q, clk => clk, aclr => areset ); --ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b(DELAY,587)@4 ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => vStage_uid149_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q, clk => clk, aclr => areset ); --mO_uid148_lzcZ_uid51_fpSinPiTest(CONSTANT,147) mO_uid148_lzcZ_uid51_fpSinPiTest_q <= "1111111111111111111111111111111111111111111111111"; --cStage_uid150_lzcZ_uid51_fpSinPiTest(BITJOIN,149)@5 cStage_uid150_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid149_lzcZ_uid51_fpSinPiTest_b_to_cStage_uid150_lzcZ_uid51_fpSinPiTest_b_q & mO_uid148_lzcZ_uid51_fpSinPiTest_q; --ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c(DELAY,589)@4 ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 64, depth => 1 ) PORT MAP ( xin => rVStage_uid146_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid152_lzcZ_uid51_fpSinPiTest(MUX,151)@5 vStagei_uid152_lzcZ_uid51_fpSinPiTest_s <= vCount_uid147_lzcZ_uid51_fpSinPiTest_q; vStagei_uid152_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid152_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q, cStage_uid150_lzcZ_uid51_fpSinPiTest_q) BEGIN CASE vStagei_uid152_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid146_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid152_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= cStage_uid150_lzcZ_uid51_fpSinPiTest_q; WHEN OTHERS => vStagei_uid152_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid154_lzcZ_uid51_fpSinPiTest(BITSELECT,153)@5 rVStage_uid154_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q; rVStage_uid154_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_in(63 downto 32); --reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0(REG,366)@5 reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= "00000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid154_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid155_lzcZ_uid51_fpSinPiTest(LOGICAL,154)@6 vCount_uid155_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid154_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid155_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage0Idx1Pad32_uid108_fixedPointX_uid37_fpSinPiTest_q; vCount_uid155_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid155_lzcZ_uid51_fpSinPiTest_a = vCount_uid155_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f(DELAY,628)@6 ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid155_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q, clk => clk, aclr => areset ); --vStage_uid156_lzcZ_uid51_fpSinPiTest(BITSELECT,155)@5 vStage_uid156_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid152_lzcZ_uid51_fpSinPiTest_q(31 downto 0); vStage_uid156_lzcZ_uid51_fpSinPiTest_b <= vStage_uid156_lzcZ_uid51_fpSinPiTest_in(31 downto 0); --ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d(DELAY,596)@5 ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => vStage_uid156_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c(DELAY,595)@5 ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => rVStage_uid154_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid158_lzcZ_uid51_fpSinPiTest(MUX,157)@6 vStagei_uid158_lzcZ_uid51_fpSinPiTest_s <= vCount_uid155_lzcZ_uid51_fpSinPiTest_q; vStagei_uid158_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid158_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid158_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid154_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid156_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid158_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid158_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid160_lzcZ_uid51_fpSinPiTest(BITSELECT,159)@6 rVStage_uid160_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q; rVStage_uid160_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_in(31 downto 16); --reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0(REG,367)@6 reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= "0000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid160_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid161_lzcZ_uid51_fpSinPiTest(LOGICAL,160)@7 vCount_uid161_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid160_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid161_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx2Pad16_uid120_fixedPointX_uid37_fpSinPiTest_q; vCount_uid161_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid161_lzcZ_uid51_fpSinPiTest_a = vCount_uid161_lzcZ_uid51_fpSinPiTest_b else "0"; --ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e(DELAY,627)@7 ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid161_lzcZ_uid51_fpSinPiTest_q, xout => ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q, clk => clk, aclr => areset ); --vStage_uid162_lzcZ_uid51_fpSinPiTest(BITSELECT,161)@6 vStage_uid162_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid158_lzcZ_uid51_fpSinPiTest_q(15 downto 0); vStage_uid162_lzcZ_uid51_fpSinPiTest_b <= vStage_uid162_lzcZ_uid51_fpSinPiTest_in(15 downto 0); --ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d(DELAY,602)@6 ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => vStage_uid162_lzcZ_uid51_fpSinPiTest_b, xout => ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q, clk => clk, aclr => areset ); --ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c(DELAY,601)@6 ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => rVStage_uid160_lzcZ_uid51_fpSinPiTest_b, xout => ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, clk => clk, aclr => areset ); --vStagei_uid164_lzcZ_uid51_fpSinPiTest(MUX,163)@7 vStagei_uid164_lzcZ_uid51_fpSinPiTest_s <= vCount_uid161_lzcZ_uid51_fpSinPiTest_q; vStagei_uid164_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid164_lzcZ_uid51_fpSinPiTest_s, ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q, ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q) BEGIN CASE vStagei_uid164_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_rVStage_uid160_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_c_q; WHEN "1" => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= ld_vStage_uid162_lzcZ_uid51_fpSinPiTest_b_to_vStagei_uid164_lzcZ_uid51_fpSinPiTest_d_q; WHEN OTHERS => vStagei_uid164_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid166_lzcZ_uid51_fpSinPiTest(BITSELECT,165)@7 rVStage_uid166_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q; rVStage_uid166_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_in(15 downto 8); --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0(REG,368)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vCount_uid167_lzcZ_uid51_fpSinPiTest(LOGICAL,166)@8 vCount_uid167_lzcZ_uid51_fpSinPiTest_a <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vCount_uid167_lzcZ_uid51_fpSinPiTest_0_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage1Idx1Pad8_uid117_fixedPointX_uid37_fpSinPiTest_q; vCount_uid167_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid167_lzcZ_uid51_fpSinPiTest_a = vCount_uid167_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid168_lzcZ_uid51_fpSinPiTest(BITSELECT,167)@7 vStage_uid168_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid164_lzcZ_uid51_fpSinPiTest_q(7 downto 0); vStage_uid168_lzcZ_uid51_fpSinPiTest_b <= vStage_uid168_lzcZ_uid51_fpSinPiTest_in(7 downto 0); --reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3(REG,369)@7 reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q <= vStage_uid168_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2(REG,370)@7 reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= "00000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q <= rVStage_uid166_lzcZ_uid51_fpSinPiTest_b; END IF; END PROCESS; --vStagei_uid170_lzcZ_uid51_fpSinPiTest(MUX,169)@8 vStagei_uid170_lzcZ_uid51_fpSinPiTest_s <= vCount_uid167_lzcZ_uid51_fpSinPiTest_q; vStagei_uid170_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid170_lzcZ_uid51_fpSinPiTest_s, reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q, reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q) BEGIN CASE vStagei_uid170_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_rVStage_uid166_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_2_q; WHEN "1" => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= reg_vStage_uid168_lzcZ_uid51_fpSinPiTest_0_to_vStagei_uid170_lzcZ_uid51_fpSinPiTest_3_q; WHEN OTHERS => vStagei_uid170_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid172_lzcZ_uid51_fpSinPiTest(BITSELECT,171)@8 rVStage_uid172_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q; rVStage_uid172_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_in(7 downto 4); --vCount_uid173_lzcZ_uid51_fpSinPiTest(LOGICAL,172)@8 vCount_uid173_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; vCount_uid173_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; vCount_uid173_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid173_lzcZ_uid51_fpSinPiTest_a = vCount_uid173_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid174_lzcZ_uid51_fpSinPiTest(BITSELECT,173)@8 vStage_uid174_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid170_lzcZ_uid51_fpSinPiTest_q(3 downto 0); vStage_uid174_lzcZ_uid51_fpSinPiTest_b <= vStage_uid174_lzcZ_uid51_fpSinPiTest_in(3 downto 0); --vStagei_uid176_lzcZ_uid51_fpSinPiTest(MUX,175)@8 vStagei_uid176_lzcZ_uid51_fpSinPiTest_s <= vCount_uid173_lzcZ_uid51_fpSinPiTest_q; vStagei_uid176_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid176_lzcZ_uid51_fpSinPiTest_s, rVStage_uid172_lzcZ_uid51_fpSinPiTest_b, vStage_uid174_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid176_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid172_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= vStage_uid174_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid176_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid178_lzcZ_uid51_fpSinPiTest(BITSELECT,177)@8 rVStage_uid178_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q; rVStage_uid178_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_in(3 downto 2); --vCount_uid179_lzcZ_uid51_fpSinPiTest(LOGICAL,178)@8 vCount_uid179_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; vCount_uid179_lzcZ_uid51_fpSinPiTest_b <= leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; vCount_uid179_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid179_lzcZ_uid51_fpSinPiTest_a = vCount_uid179_lzcZ_uid51_fpSinPiTest_b else "0"; --vStage_uid180_lzcZ_uid51_fpSinPiTest(BITSELECT,179)@8 vStage_uid180_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid51_fpSinPiTest_q(1 downto 0); vStage_uid180_lzcZ_uid51_fpSinPiTest_b <= vStage_uid180_lzcZ_uid51_fpSinPiTest_in(1 downto 0); --vStagei_uid182_lzcZ_uid51_fpSinPiTest(MUX,181)@8 vStagei_uid182_lzcZ_uid51_fpSinPiTest_s <= vCount_uid179_lzcZ_uid51_fpSinPiTest_q; vStagei_uid182_lzcZ_uid51_fpSinPiTest: PROCESS (vStagei_uid182_lzcZ_uid51_fpSinPiTest_s, rVStage_uid178_lzcZ_uid51_fpSinPiTest_b, vStage_uid180_lzcZ_uid51_fpSinPiTest_b) BEGIN CASE vStagei_uid182_lzcZ_uid51_fpSinPiTest_s IS WHEN "0" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= rVStage_uid178_lzcZ_uid51_fpSinPiTest_b; WHEN "1" => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= vStage_uid180_lzcZ_uid51_fpSinPiTest_b; WHEN OTHERS => vStagei_uid182_lzcZ_uid51_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid184_lzcZ_uid51_fpSinPiTest(BITSELECT,183)@8 rVStage_uid184_lzcZ_uid51_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid51_fpSinPiTest_q; rVStage_uid184_lzcZ_uid51_fpSinPiTest_b <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_in(1 downto 1); --vCount_uid185_lzcZ_uid51_fpSinPiTest(LOGICAL,184)@8 vCount_uid185_lzcZ_uid51_fpSinPiTest_a <= rVStage_uid184_lzcZ_uid51_fpSinPiTest_b; vCount_uid185_lzcZ_uid51_fpSinPiTest_b <= GND_q; vCount_uid185_lzcZ_uid51_fpSinPiTest_q <= "1" when vCount_uid185_lzcZ_uid51_fpSinPiTest_a = vCount_uid185_lzcZ_uid51_fpSinPiTest_b else "0"; --r_uid186_lzcZ_uid51_fpSinPiTest(BITJOIN,185)@8 r_uid186_lzcZ_uid51_fpSinPiTest_q <= ld_vCount_uid147_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_g_q & ld_vCount_uid155_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_f_q & ld_vCount_uid161_lzcZ_uid51_fpSinPiTest_q_to_r_uid186_lzcZ_uid51_fpSinPiTest_e_q & vCount_uid167_lzcZ_uid51_fpSinPiTest_q & vCount_uid173_lzcZ_uid51_fpSinPiTest_q & vCount_uid179_lzcZ_uid51_fpSinPiTest_q & vCount_uid185_lzcZ_uid51_fpSinPiTest_q; --leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest(BITSELECT,195)@8 leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q; leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_in(6 downto 5); --reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1(REG,371)@8 reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest(MUX,196)@9 leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel6Dto5_uid196_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s, ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q, leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q, leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ld_z_uid49_fpSinPiTest_q_to_leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_c_outputreg_q; WHEN "01" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx1_uid191_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0Idx2_uid194_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= ozz_uid41_fpSinPiTest_q; WHEN OTHERS => leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest(BITSELECT,206)@8 leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(4 downto 0); leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_in(4 downto 3); --reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1(REG,372)@8 reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest(MUX,207)@9 leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s <= reg_leftShiftStageSel4Dto3_uid207_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_1_q; leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s, leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q, leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage0_uid197_alignedZ_uid52_fpSinPiTest_q; WHEN "01" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx1_uid200_alignedZ_uid52_fpSinPiTest_q; WHEN "10" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx2_uid203_alignedZ_uid52_fpSinPiTest_q; WHEN "11" => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage1Idx3_uid206_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest(BITSELECT,215)@9 LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(72 downto 0); LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_in(72 downto 0); --leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest(BITJOIN,216)@9 leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage172dto0_uid216_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid134_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5(REG,374)@9 reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q <= leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest(BITSELECT,212)@9 LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(74 downto 0); LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_in(74 downto 0); --leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest(BITJOIN,213)@9 leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage174dto0_uid213_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx2Pad4_uid131_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4(REG,375)@9 reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q <= leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest(BITSELECT,209)@9 LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q(76 downto 0); LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_in(76 downto 0); --leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest(BITJOIN,210)@9 leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q <= LeftShiftStage176dto0_uid210_alignedZ_uid52_fpSinPiTest_b & leftShiftStage2Idx1Pad2_uid128_fixedPointX_uid37_fpSinPiTest_q; --reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3(REG,376)@9 reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q <= leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2(REG,377)@9 reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q <= leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_q; END IF; END PROCESS; --leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest(BITSELECT,217)@8 leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(2 downto 0); leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_in(2 downto 1); --reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1(REG,373)@8 reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b(DELAY,657)@9 ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest(MUX,218)@10 leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel2Dto1_uid218_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s, reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q, reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q, reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q, reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q) BEGIN CASE leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_s IS WHEN "00" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage1_uid208_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_2_q; WHEN "01" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx1_uid211_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_3_q; WHEN "10" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx2_uid214_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_4_q; WHEN "11" => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= reg_leftShiftStage2Idx3_uid217_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_5_q; WHEN OTHERS => leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest(BITSELECT,222)@8 leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in <= r_uid186_lzcZ_uid51_fpSinPiTest_q(0 downto 0); leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_in(0 downto 0); --reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1(REG,378)@8 reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q <= leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_b; END IF; END PROCESS; --ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b(DELAY,665)@9 ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q, clk => clk, aclr => areset ); --leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest(MUX,223)@10 leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s <= ld_reg_leftShiftStageSel0Dto0_uid223_alignedZ_uid52_fpSinPiTest_0_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_1_q_to_leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_b_q; leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest: PROCESS (leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s, leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q, leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q) BEGIN CASE leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_s IS WHEN "0" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage2_uid219_alignedZ_uid52_fpSinPiTest_q; WHEN "1" => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= leftShiftStage3Idx1_uid222_alignedZ_uid52_fpSinPiTest_q; WHEN OTHERS => leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --alignedZLow_uid53_fpSinPiTest(BITSELECT,52)@10 alignedZLow_uid53_fpSinPiTest_in <= leftShiftStage3_uid224_alignedZ_uid52_fpSinPiTest_q; alignedZLow_uid53_fpSinPiTest_b <= alignedZLow_uid53_fpSinPiTest_in(78 downto 27); --pHardCase_uid54_fpSinPiTest(BITJOIN,53)@10 pHardCase_uid54_fpSinPiTest_q <= alignedZLow_uid53_fpSinPiTest_b & GND_q; --ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b(DELAY,474)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 10 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q, clk => clk, aclr => areset ); --p_uid55_fpSinPiTest(MUX,54)@10 p_uid55_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_p_uid55_fpSinPiTest_b_q; p_uid55_fpSinPiTest: PROCESS (p_uid55_fpSinPiTest_s, pHardCase_uid54_fpSinPiTest_q, ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q) BEGIN CASE p_uid55_fpSinPiTest_s IS WHEN "0" => p_uid55_fpSinPiTest_q <= pHardCase_uid54_fpSinPiTest_q; WHEN "1" => p_uid55_fpSinPiTest_q <= ld_oFracX_uid31_uid31_fpSinPiTest_q_to_p_uid55_fpSinPiTest_d_outputreg_q; WHEN OTHERS => p_uid55_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt(COUNTER,1121) -- every=1, low=0, high=22, step=1, init=1 ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i = 21 THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '1'; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_eq = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i - 22; ELSE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_i,5)); --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg(REG,1122) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; END IF; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux(MUX,1123) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s <= VCC_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux: PROCESS (ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q, ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q) BEGIN CASE ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_s IS WHEN "0" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; WHEN "1" => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdcnt_q; WHEN OTHERS => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem(DUALMEM,1120) ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0 <= areset; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia <= p_uid55_fpSinPiTest_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdreg_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_rdmux_q; ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 53, widthad_a => 5, numwords_a => 23, width_b => 53, widthad_b => 5, numwords_b => 23, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq, address_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_aa, data_a => ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_ia ); ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_iq(52 downto 0); --mul2xSinRes_uid69_fpSinPiTest_a_1(BITSELECT,316)@34 mul2xSinRes_uid69_fpSinPiTest_a_1_in <= STD_LOGIC_VECTOR("0" & ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q); mul2xSinRes_uid69_fpSinPiTest_a_1_b <= mul2xSinRes_uid69_fpSinPiTest_a_1_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0(REG,424)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b1(MULT,322)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b1_b); mul2xSinRes_uid69_fpSinPiTest_a1_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1(BITSELECT,329)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1(REG,425)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a_0(BITSELECT,315)@34 mul2xSinRes_uid69_fpSinPiTest_a_0_in <= ld_p_uid55_fpSinPiTest_q_to_mul2xSinRes_uid69_fpSinPiTest_a_0_a_replace_mem_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_a_0_b <= mul2xSinRes_uid69_fpSinPiTest_a_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0(REG,426)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b1(MULT,321)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b1_b); mul2xSinRes_uid69_fpSinPiTest_a0_b1_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b1_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b1_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b1_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1(BITSELECT,327)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_zero_36(CONSTANT,332) mul2xSinRes_uid69_fpSinPiTest_zero_36_q <= "000000000000000000000000000"; --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2(BITJOIN,336)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1(BITSELECT,328)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_b_0(BITSELECT,317)@34 mul2xSinRes_uid69_fpSinPiTest_b_0_in <= multRightOp_uid68_fpSinPiTest_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_b_0_b <= mul2xSinRes_uid69_fpSinPiTest_b_0_in(26 downto 0); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1(REG,421)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0(REG,422)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_1_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a1_b0(MULT,320)@35 mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a1_b0_b); mul2xSinRes_uid69_fpSinPiTest_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_1_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a1_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a1_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a1_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0(BITSELECT,325)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1(BITJOIN,335)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q <= mul2xSinRes_uid69_fpSinPiTest_zero_36_q & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b1_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_zero_36_q; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC(LOGICAL,340)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_b; --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1(BITSELECT,330)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b1_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0(BITSELECT,326)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a1_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_in(53 downto 27); --reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1(REG,419)@34 reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q <= mul2xSinRes_uid69_fpSinPiTest_b_0_b; END IF; END PROCESS; --reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0(REG,420)@34 reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= "000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q <= mul2xSinRes_uid69_fpSinPiTest_a_0_b; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_a0_b0(MULT,319)@35 mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr <= UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_a) * UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_a0_b0_b); mul2xSinRes_uid69_fpSinPiTest_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= (others => '0'); mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_a <= reg_mul2xSinRes_uid69_fpSinPiTest_a_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_0_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_b <= reg_mul2xSinRes_uid69_fpSinPiTest_b_0_0_to_mul2xSinRes_uid69_fpSinPiTest_a0_b0_1_q; mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid69_fpSinPiTest_a0_b0_pr); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_a0_b0_q <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_s1; END IF; END PROCESS; --mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0(BITSELECT,324)@38 mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q; mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_in(53 downto 27); --mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0(BITSELECT,323)@38 mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in <= mul2xSinRes_uid69_fpSinPiTest_a0_b0_q(26 downto 0); mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b <= mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_in(26 downto 0); --mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0(BITJOIN,334)@38 mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q <= mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b1_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a1_b0_b & mul2xSinRes_uid69_fpSinPiTest_MSB_a0_b0_b & mul2xSinRes_uid69_fpSinPiTest_LSB_a0_b0_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC(LOGICAL,339)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB(LOGICAL,338)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_a and mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_b; --mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne(LOGICAL,341)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAB_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andAC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_andBC_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_a or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_b or mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_c; --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS(BITSELECT,342)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_orOne_q(106 downto 0); mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_in(106 downto 0); --mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ(BITJOIN,343)@38 mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q <= mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_lsb_BS_b & GND_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b(BITJOIN,350)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_comp_0_out1_BJ_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b(BITSELECT,353)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_b_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne(LOGICAL,337)@38 mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_0_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_1_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c <= mul2xSinRes_uid69_fpSinPiTest_joined_BJ_2_q; mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q <= mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_a xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_b xor mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_c; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a(BITJOIN,348)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q <= GND_q & mul2xSinRes_uid69_fpSinPiTest_32COMP0_xorOne_q; --mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a(BITSELECT,352)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitExpansion_for_a_q; mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(88 downto 0); mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_in(108 downto 89); --mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2(ADD,354)@38 mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin <= GND_q; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_b) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_b) & mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c(0) <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(90); mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_o(89 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b(DELAY,822)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q, clk => clk, aclr => areset ); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a(DELAY,821)@38 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a : dspba_delay GENERIC MAP ( width => 20, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2(ADD,355)@39 mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin <= mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_c; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a_q) & '1'; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b_q) & mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_cin(0); mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_a) + UNSIGNED(mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_b)); END IF; END PROCESS; mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_o(20 downto 1); --ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a(DELAY,824)@39 ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a : dspba_delay GENERIC MAP ( width => 89, depth => 1 ) PORT MAP ( xin => mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q, xout => ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q, clk => clk, aclr => areset ); --mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q(BITJOIN,356)@40 mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q <= mul2xSinRes_uid69_fpSinPiTest_ADD_p2_of_2_q & ld_mul2xSinRes_uid69_fpSinPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_a_q; --normBit_uid70_fpSinPiTest(BITSELECT,69)@40 normBit_uid70_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(106 downto 0); normBit_uid70_fpSinPiTest_b <= normBit_uid70_fpSinPiTest_in(106 downto 106); --ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c(DELAY,497)@40 ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => normBit_uid70_fpSinPiTest_b, xout => ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q, clk => clk, aclr => areset ); --rndExpUpdate_uid75_uid76_fpSinPiTest(BITJOIN,75)@41 rndExpUpdate_uid75_uid76_fpSinPiTest_q <= ld_normBit_uid70_fpSinPiTest_b_to_rndExpUpdate_uid75_uid76_fpSinPiTest_c_q & cstAllZWF_uid10_fpSinPiTest_q & VCC_q; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor(LOGICAL,976) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q <= not (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_a or ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_b); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top(CONSTANT,972) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q <= "011100"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp(LOGICAL,973) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_mem_top_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_a = ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_b else "0"; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg(REG,974) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena(REG,977) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_nor_q = "1") THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd(LOGICAL,978) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_sticky_ena_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_a and ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_b; --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem(DUALMEM,941) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0 <= areset; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia <= expX_uid6_fpSinPiTest_b; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdreg_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_rdmux_q; ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 3, numwords_a => 7, width_b => 11, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq, address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_aa, data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_ia ); ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_iq(10 downto 0); --ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg(DELAY,940) ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_replace_mem_q, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q, clk => clk, aclr => areset ); --expXP1_uid58_fpSinPiTest(ADD,57)@9 expXP1_uid58_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid58_fpSinPiTest_a_outputreg_q); expXP1_uid58_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & VCC_q); expXP1_uid58_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid58_fpSinPiTest_a) + UNSIGNED(expXP1_uid58_fpSinPiTest_b)); expXP1_uid58_fpSinPiTest_q <= expXP1_uid58_fpSinPiTest_o(11 downto 0); --expXP1R_uid59_fpSinPiTest(BITSELECT,58)@9 expXP1R_uid59_fpSinPiTest_in <= expXP1_uid58_fpSinPiTest_q(10 downto 0); expXP1R_uid59_fpSinPiTest_b <= expXP1R_uid59_fpSinPiTest_in(10 downto 0); --reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1(REG,427)@8 reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= "0000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q <= r_uid186_lzcZ_uid51_fpSinPiTest_q; END IF; END PROCESS; --expHardCase_uid57_fpSinPiTest(SUB,56)@9 expHardCase_uid57_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid27_fpSinPiTest_q); expHardCase_uid57_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000" & reg_r_uid186_lzcZ_uid51_fpSinPiTest_0_to_expHardCase_uid57_fpSinPiTest_1_q); expHardCase_uid57_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid57_fpSinPiTest_a) - UNSIGNED(expHardCase_uid57_fpSinPiTest_b)); expHardCase_uid57_fpSinPiTest_q <= expHardCase_uid57_fpSinPiTest_o(11 downto 0); --expHardCaseR_uid60_fpSinPiTest(BITSELECT,59)@9 expHardCaseR_uid60_fpSinPiTest_in <= expHardCase_uid57_fpSinPiTest_q(10 downto 0); expHardCaseR_uid60_fpSinPiTest_b <= expHardCaseR_uid60_fpSinPiTest_in(10 downto 0); --ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b(DELAY,481)@0 ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 9 ) PORT MAP ( xin => sinXIsX_uid30_fpSinPiTest_c, xout => ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q, clk => clk, aclr => areset ); --expP_uid61_fpSinPiTest(MUX,60)@9 expP_uid61_fpSinPiTest_s <= ld_sinXIsX_uid30_fpSinPiTest_c_to_expP_uid61_fpSinPiTest_b_q; expP_uid61_fpSinPiTest: PROCESS (expP_uid61_fpSinPiTest_s, expHardCaseR_uid60_fpSinPiTest_b, expXP1R_uid59_fpSinPiTest_b) BEGIN CASE expP_uid61_fpSinPiTest_s IS WHEN "0" => expP_uid61_fpSinPiTest_q <= expHardCaseR_uid60_fpSinPiTest_b; WHEN "1" => expP_uid61_fpSinPiTest_q <= expXP1R_uid59_fpSinPiTest_b; WHEN OTHERS => expP_uid61_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt(COUNTER,968) -- every=1, low=0, high=28, step=1, init=1 ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i = 27 THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i - 28; ELSE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_i,5)); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg(REG,969) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= "00000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux(MUX,970) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem(DUALMEM,967) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia <= expP_uid61_fpSinPiTest_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdreg_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_rdmux_q; ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 11, widthad_a => 5, numwords_a => 29, width_b => 11, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq, address_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_aa, data_a => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_ia ); ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_iq(10 downto 0); --ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg(DELAY,966) ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 11, depth => 1 ) PORT MAP ( xin => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_replace_mem_q, xout => ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --highRes_uid71_fpSinPiTest(BITSELECT,70)@40 highRes_uid71_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(105 downto 0); highRes_uid71_fpSinPiTest_b <= highRes_uid71_fpSinPiTest_in(105 downto 53); --lowRes_uid72_fpSinPiTest(BITSELECT,71)@40 lowRes_uid72_fpSinPiTest_in <= mul2xSinRes_uid69_fpSinPiTest_ADD_BitJoin_for_q_q(104 downto 0); lowRes_uid72_fpSinPiTest_b <= lowRes_uid72_fpSinPiTest_in(104 downto 52); --fracRCompPreRnd_uid73_fpSinPiTest(MUX,72)@40 fracRCompPreRnd_uid73_fpSinPiTest_s <= normBit_uid70_fpSinPiTest_b; fracRCompPreRnd_uid73_fpSinPiTest: PROCESS (fracRCompPreRnd_uid73_fpSinPiTest_s, lowRes_uid72_fpSinPiTest_b, highRes_uid71_fpSinPiTest_b) BEGIN CASE fracRCompPreRnd_uid73_fpSinPiTest_s IS WHEN "0" => fracRCompPreRnd_uid73_fpSinPiTest_q <= lowRes_uid72_fpSinPiTest_b; WHEN "1" => fracRCompPreRnd_uid73_fpSinPiTest_q <= highRes_uid71_fpSinPiTest_b; WHEN OTHERS => fracRCompPreRnd_uid73_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracPreRnd_uid74_uid74_fpSinPiTest(BITJOIN,73)@40 expFracPreRnd_uid74_uid74_fpSinPiTest_q <= ld_expP_uid61_fpSinPiTest_q_to_expFracPreRnd_uid74_uid74_fpSinPiTest_b_outputreg_q & fracRCompPreRnd_uid73_fpSinPiTest_q; --reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0(REG,428)@40 reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q <= expFracPreRnd_uid74_uid74_fpSinPiTest_q; END IF; END PROCESS; --expFracComp_uid77_fpSinPiTest(ADD,76)@41 expFracComp_uid77_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid74_uid74_fpSinPiTest_0_to_expFracComp_uid77_fpSinPiTest_0_q); expFracComp_uid77_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000" & rndExpUpdate_uid75_uid76_fpSinPiTest_q); expFracComp_uid77_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid77_fpSinPiTest_a) + UNSIGNED(expFracComp_uid77_fpSinPiTest_b)); expFracComp_uid77_fpSinPiTest_q <= expFracComp_uid77_fpSinPiTest_o(64 downto 0); --expRComp_uid79_fpSinPiTest(BITSELECT,78)@41 expRComp_uid79_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(63 downto 0); expRComp_uid79_fpSinPiTest_b <= expRComp_uid79_fpSinPiTest_in(63 downto 53); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor(LOGICAL,1015) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q <= not (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_a or ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_b); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top(CONSTANT,1011) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q <= "0100010"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp(LOGICAL,1012) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_mem_top_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q <= "1" when ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_a = ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_b else "0"; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg(REG,1013) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena(REG,1016) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_nor_q = "1") THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd(LOGICAL,1017) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_sticky_ena_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_a and ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_b; --reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1(REG,429)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c(DELAY,516)@0 ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q, xout => ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q, clk => clk, aclr => areset ); --ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b(DELAY,515)@0 ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => expXIsZero_uid15_fpSinPiTest_q, xout => ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q, clk => clk, aclr => areset ); --reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0(REG,361)@2 reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q <= xIsInt_uid83_fpSinPiTest_q; END IF; END PROCESS; --excRZero_uid87_fpSinPiTest(LOGICAL,86)@3 excRZero_uid87_fpSinPiTest_a <= reg_xIsInt_uid83_fpSinPiTest_0_to_excRZero_uid87_fpSinPiTest_0_q; excRZero_uid87_fpSinPiTest_b <= ld_expXIsZero_uid15_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_b_q; excRZero_uid87_fpSinPiTest_c <= ld_And2ExpXIsMaxFracXIsZero_uid18_fpSinPiTest_q_to_excRZero_uid87_fpSinPiTest_c_q; excRZero_uid87_fpSinPiTest_q <= excRZero_uid87_fpSinPiTest_a or excRZero_uid87_fpSinPiTest_b or excRZero_uid87_fpSinPiTest_c; --Or2ExcRZeroXIsInt_uid92_fpSinPiTest(LOGICAL,91)@3 Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a <= excRZero_uid87_fpSinPiTest_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b <= reg_xIsInt_uid83_fpSinPiTest_0_to_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_1_q; Or2ExcRZeroXIsInt_uid92_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_a or Or2ExcRZeroXIsInt_uid92_fpSinPiTest_b; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt(COUNTER,1007) -- every=1, low=0, high=34, step=1, init=1 ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i = 33 THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i - 34; ELSE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg(REG,1008) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux(MUX,1009) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux: PROCESS (ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q, ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem(DUALMEM,1006) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia <= Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdreg_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_rdmux_q; ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 35, width_b => 1, widthad_b => 6, numwords_b => 35, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq, address_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_aa, data_a => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_ia ); ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg(DELAY,1005) ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_replace_mem_q, xout => ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --expRPostExc1_uid95_fpSinPiTest(MUX,94)@41 expRPostExc1_uid95_fpSinPiTest_s <= ld_Or2ExcRZeroXIsInt_uid92_fpSinPiTest_q_to_expRPostExc1_uid95_fpSinPiTest_b_outputreg_q; expRPostExc1_uid95_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE expRPostExc1_uid95_fpSinPiTest_s IS WHEN "0" => expRPostExc1_uid95_fpSinPiTest_q <= expRComp_uid79_fpSinPiTest_b; WHEN "1" => expRPostExc1_uid95_fpSinPiTest_q <= cstAllZWE_uid11_fpSinPiTest_q; WHEN OTHERS => expRPostExc1_uid95_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --InvXIntExp_uid84_fpSinPiTest(LOGICAL,83)@2 InvXIntExp_uid84_fpSinPiTest_a <= ld_xIntExp_uid26_fpSinPiTest_c_to_Or2XIntExpAnd2YIsZeroInvSinXIsX_uid82_fpSinPiTest_a_q; InvXIntExp_uid84_fpSinPiTest_q <= not InvXIntExp_uid84_fpSinPiTest_a; --join_uid42_fpSinPiTest(BITJOIN,41)@2 join_uid42_fpSinPiTest_q <= VCC_q & ozz_uid41_fpSinPiTest_q; --reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0(REG,359)@1 reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF(clk'EVENT AND clk = '1') THEN reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q <= y_uid39_fpSinPiTest_b; END IF; END PROCESS; --yIsZero_uid43_fpSinPiTest(LOGICAL,42)@2 yIsZero_uid43_fpSinPiTest_a <= reg_y_uid39_fpSinPiTest_0_to_yIsZero_uid43_fpSinPiTest_0_q; yIsZero_uid43_fpSinPiTest_b <= join_uid42_fpSinPiTest_q; yIsZero_uid43_fpSinPiTest_q <= "1" when yIsZero_uid43_fpSinPiTest_a = yIsZero_uid43_fpSinPiTest_b else "0"; --And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest(LOGICAL,85)@2 And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid25_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b <= yIsZero_uid43_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c <= InvSinXIsX_uid80_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d <= InvXIntExp_uid84_fpSinPiTest_q; And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_a and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_b and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_c and And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_d; --Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest(LOGICAL,95)@1 Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a <= GND_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b <= And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q; Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q <= Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_a or Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_b; --ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a(DELAY,528)@1 ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q, xout => ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q, clk => clk, aclr => areset ); --join_uid97_fpSinPiTest(BITJOIN,96)@2 join_uid97_fpSinPiTest_q <= And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q & ld_Or2ZeroAnd2ExpXIsMaxInvFracXIsZero_uid96_fpSinPiTest_q_to_join_uid97_fpSinPiTest_a_q; --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg(DELAY,1195) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => join_uid97_fpSinPiTest_q, xout => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q, clk => clk, aclr => areset ); --ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem(DUALMEM,1196) ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0 <= areset; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_inputreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdreg_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_replace_rdmux_q; ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 6, numwords_a => 37, width_b => 2, widthad_b => 6, numwords_b => 37, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_reset0, clock1 => clk, address_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq, address_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_aa, data_a => ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_ia ); ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_iq(1 downto 0); --reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1(REG,430)@41 reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= "00"; ELSIF(clk'EVENT AND clk = '1') THEN reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q <= ld_join_uid97_fpSinPiTest_q_to_reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_a_replace_mem_q; END IF; END PROCESS; --expRPostExc_uid98_fpSinPiTest(MUX,97)@42 expRPostExc_uid98_fpSinPiTest_s <= reg_join_uid97_fpSinPiTest_0_to_expRPostExc_uid98_fpSinPiTest_1_q; expRPostExc_uid98_fpSinPiTest: PROCESS (expRPostExc_uid98_fpSinPiTest_s, expRPostExc1_uid95_fpSinPiTest_q) BEGIN CASE expRPostExc_uid98_fpSinPiTest_s IS WHEN "00" => expRPostExc_uid98_fpSinPiTest_q <= expRPostExc1_uid95_fpSinPiTest_q; WHEN "01" => expRPostExc_uid98_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q; WHEN "10" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN "11" => expRPostExc_uid98_fpSinPiTest_q <= cstBias_uid12_fpSinPiTest_q; WHEN OTHERS => expRPostExc_uid98_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --oneFracRPostExc2_uid90_fpSinPiTest(CONSTANT,89) oneFracRPostExc2_uid90_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000001"; --fracRComp_uid78_fpSinPiTest(BITSELECT,77)@41 fracRComp_uid78_fpSinPiTest_in <= expFracComp_uid77_fpSinPiTest_q(52 downto 0); fracRComp_uid78_fpSinPiTest_b <= fracRComp_uid78_fpSinPiTest_in(52 downto 1); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor(LOGICAL,989) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q <= not (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_a or ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_b); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top(CONSTANT,985) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q <= "0100001"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp(LOGICAL,986) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_mem_top_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q <= "1" when ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_a = ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_b else "0"; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg(REG,987) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena(REG,990) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_nor_q = "1") THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd(LOGICAL,991) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_sticky_ena_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_a and ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_b; --reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1(REG,362)@3 reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q <= excRZero_uid87_fpSinPiTest_q; END IF; END PROCESS; --ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a(DELAY,517)@2 ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q, xout => ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q, clk => clk, aclr => areset ); --or_uid88_fpSinPiTest(LOGICAL,87)@4 or_uid88_fpSinPiTest_a <= ld_And4And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXI_uid86_fpSinPiTest_q_to_or_uid88_fpSinPiTest_a_q; or_uid88_fpSinPiTest_b <= reg_excRZero_uid87_fpSinPiTest_0_to_or_uid88_fpSinPiTest_1_q; or_uid88_fpSinPiTest_c <= GND_q; or_uid88_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN or_uid88_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN or_uid88_fpSinPiTest_q <= or_uid88_fpSinPiTest_a or or_uid88_fpSinPiTest_b or or_uid88_fpSinPiTest_c; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt(COUNTER,981) -- every=1, low=0, high=33, step=1, init=1 ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i = 32 THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i - 33; ELSE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg(REG,982) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux(MUX,983) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux: PROCESS (ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q, ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem(DUALMEM,980) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia <= or_uid88_fpSinPiTest_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdreg_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_rdmux_q; ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 34, width_b => 1, widthad_b => 6, numwords_b => 34, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq, address_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_aa, data_a => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_ia ); ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_iq(0 downto 0); --ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg(DELAY,979) ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_replace_mem_q, xout => ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q, clk => clk, aclr => areset ); --fracRPostExc1_uid89_fpSinPiTest(MUX,88)@41 fracRPostExc1_uid89_fpSinPiTest_s <= ld_or_uid88_fpSinPiTest_q_to_fracRPostExc1_uid89_fpSinPiTest_b_outputreg_q; fracRPostExc1_uid89_fpSinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN CASE fracRPostExc1_uid89_fpSinPiTest_s IS WHEN "0" => fracRPostExc1_uid89_fpSinPiTest_q <= fracRComp_uid78_fpSinPiTest_b; WHEN "1" => fracRPostExc1_uid89_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q; WHEN OTHERS => fracRPostExc1_uid89_fpSinPiTest_q <= (others => '0'); END CASE; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor(LOGICAL,1002) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q <= not (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_a or ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_b); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top(CONSTANT,998) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q <= "0100110"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp(LOGICAL,999) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_mem_top_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q <= "1" when ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_a = ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_b else "0"; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg(REG,1000) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmp_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena(REG,1003) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_nor_q = "1") THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd(LOGICAL,1004) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_sticky_ena_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_a and ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_b; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg(DELAY,992) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q, xout => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q, clk => clk, aclr => areset ); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt(COUNTER,994) -- every=1, low=0, high=38, step=1, init=1 ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i = 37 THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i - 38; ELSE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_i,6)); --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg(REG,995) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; END IF; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux(MUX,996) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s <= VCC_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux: PROCESS (ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q, ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; WHEN "1" => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem(DUALMEM,993) ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0 <= areset; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_inputreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdreg_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_rdmux_q; ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 39, width_b => 1, widthad_b => 6, numwords_b => 39, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq, address_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_aa, data_a => ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_ia ); ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_iq(0 downto 0); --fracRPostExc_uid91_fpSinPiTest(MUX,90)@42 fracRPostExc_uid91_fpSinPiTest_s <= ld_And2ExpXIsMaxInvFracXIsZero_uid20_fpSinPiTest_q_to_fracRPostExc_uid91_fpSinPiTest_b_replace_mem_q; fracRPostExc_uid91_fpSinPiTest: PROCESS (fracRPostExc_uid91_fpSinPiTest_s, fracRPostExc1_uid89_fpSinPiTest_q) BEGIN CASE fracRPostExc_uid91_fpSinPiTest_s IS WHEN "0" => fracRPostExc_uid91_fpSinPiTest_q <= fracRPostExc1_uid89_fpSinPiTest_q; WHEN "1" => fracRPostExc_uid91_fpSinPiTest_q <= oneFracRPostExc2_uid90_fpSinPiTest_q; WHEN OTHERS => fracRPostExc_uid91_fpSinPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid105_fpSinPiTest(BITJOIN,104)@42 R_uid105_fpSinPiTest_q <= ld_signR_uid104_fpSinPiTest_q_to_R_uid105_fpSinPiTest_c_outputreg_q & expRPostExc_uid98_fpSinPiTest_q & fracRPostExc_uid91_fpSinPiTest_q; --ld_xIn_v_to_xOut_v_nor(LOGICAL,910) ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q; ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b); --ld_xIn_v_to_xOut_v_mem_top(CONSTANT,906) ld_xIn_v_to_xOut_v_mem_top_q <= "0100111"; --ld_xIn_v_to_xOut_v_cmp(LOGICAL,907) ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q; ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q); ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0"; --ld_xIn_v_to_xOut_v_cmpReg(REG,908) ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_sticky_ena(REG,911) ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= "0"; ELSIF(clk'EVENT AND clk = '1') THEN IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q; END IF; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,912) ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q; ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q; ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b; --ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,902) -- every=1, low=0, high=39, step=1, init=1 ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 38 THEN ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1'; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0'; END IF; IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 39; ELSE ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,6)); --ld_xIn_v_to_xOut_v_replace_rdreg(REG,903) ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= "000000"; ELSIF(clk'EVENT AND clk = '1') THEN ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; END IF; END PROCESS; --ld_xIn_v_to_xOut_v_replace_rdmux(MUX,904) ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q; ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q) BEGIN CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q; WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q; WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,914) ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset; ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c; ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 6, numwords_a => 40, width_b => 8, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_c_to_xOut_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_c_to_xOut_c_replace_mem_iq, address_a => ld_xIn_c_to_xOut_c_replace_mem_aa, data_a => ld_xIn_c_to_xOut_c_replace_mem_ia ); ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0); --ld_xIn_c_to_xOut_c_outputreg(DELAY,913) ld_xIn_c_to_xOut_c_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset ); --ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,901) ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset; ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v; ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q; ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q; ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 40, width_b => 1, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_a => "CLOCK1", outdata_reg_b => "CLOCK1", outdata_aclr_a => "CLEAR1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", -- indata_aclr_a => "CLEAR0", -- indata_aclr_b => "CLEAR0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0), clocken0 => '1', wren_a => VCC_q(0), clock0 => clk, aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_v_to_xOut_v_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_v_to_xOut_v_replace_mem_iq, address_a => ld_xIn_v_to_xOut_v_replace_mem_aa, data_a => ld_xIn_v_to_xOut_v_replace_mem_ia ); ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0); --ld_xIn_v_to_xOut_v_outputreg(DELAY,900) ld_xIn_v_to_xOut_v_outputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset ); --xOut(PORTOUT,4)@42 xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q; xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q; xOut_0 <= R_uid105_fpSinPiTest_q; end normal;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.ffaccel_imem_mau.all; package ffaccel_imem_image is type std_logic_imem_matrix is array (natural range <>) of std_logic_vector(IMEMMAUWIDTH-1 downto 0); constant imem_array : std_logic_imem_matrix := ( "0000000001001010000000000011111111000101010", "0000101110001010110000000000000001011001010", "0000101100000000000000100110000000001000100", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000000000100000001000000000000011011001011", "0000000000010000100101111111111111111111111", "0000000000000000101101111111111111111111111", "0000000001010000110101111111111111111111111", "0000000000011001110000100000000001110110011", "0000101100001001000000000000000000011001101", "0010100011011010100101111111111111111111111", "0010100010000111100101111111111111111111111", "0000000000001001100000000000000001101010000", "0101111111111111111101111111111111111111111", "0000111010000100111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110110001010000000001111110000000100001", "0101111111111111111101111111111111111111111", "0000101100000000111000100110000000000110001", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000111111110100001", "0101111111111111111101111111111111111111111", "0000101100000001001000100110000000001010000", "0000000000010100010101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000000100001001011", "0001000000001001100001000000000001101010000", "0101111111111111111101111111111111111111111", "0001111010000100111101111111111111111111111", "0000000000100100010000100000000010011010000", "0000001110000100000000100000000001111010000", "0000101100001001000101111111111111111111111", "0000101100000110000001000000101011001001011", "0010000000110100010010100000000010011010000", "0101111111111111111101111111111111111111111", "0000101010000001000010100110000000001001000", "0101111111111111111001000000111001011001011", "0001000010000100000001100000000001111010000", "0101111111111111111101111111111111111111111", "0001101100000001001001100110000000000110000", "0000100001101010000101111111111111111111111", "0000100010010100010101111111111111111111111", "0000100000010001101101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111010000000000010111001011", "0010000000000100010010100000000010001010000", "0010100001110110011010000000000000011001110", "0010101100001001000010000000000000011001101", "0000000010000100000000100000000001111010000", "0000100001010001001101111111111111111111111", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000010100001001011", "0001000100000100000001100000000001111010000", "0010100010100110000101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000100000000001010100010", "0101111111111111111101111111111111111111111", "0000101100001010000000000000000000010101011", "0101111111111111111101111111111111111111111", "0000101100001001000000100110000000001010000", "0000000000010100001001000000101000101001011", "0101111111111111111101111111111111111111111", "0000101100000001001101111111111111111111111", "0001000000000100010001100000000010011010000", "0000000100000100000000100000000001111010000", "0101111111111111111101111111111111111111111", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000011001011001011", "0001000110000100000001100000000001111010000", "0010100010100110000101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000100000000001010100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100001000001101010000000000010011001011", "0101111111111111111101111111111111111111111", "0001000110000100000001100000000001111010000", "0010000000000100010010100000000010001010000", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000011110101001011", "0001001000000100000001100000000001111010000", "0010100010100110000101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000100000000001010100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100001000001101010000000000010011001011", "0101111111111111111101111111111111111111111", "0001001000000100000001100000000001111010000", "0010000000000100010010100000000010001010000", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000100011111001011", "0001001010000100000001100000000001111010000", "0010100010100110000101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000100000000001010100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100001000001101010000000000010011001011", "0101111111111111111101111111111111111111111", "0001001010000100000001100000000001111010000", "0010000000000100010010100000000010001010000", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100010100110000001000000101001001001011", "0001000000000100010001100000000010011010000", "0101111111111111111101111111111111111111111", "0001101100001001000010100100000000000111000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100001000001101010000000000010011001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0010000000000100010010100000000010001010000", "0000000000000100010000100000000010011010000", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000001101111001011", "0001000010000100000001100000000001111010000", "0001100001010001001101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111000000001011011101001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000000011000100000000100000000001111010000", "0000000100000100000000100000000001111010000", "0000101100000110000000100000000001111010000", "0000101100000110000000000000001000000100000", "0000100001111010000101111111111111111111111", "0000101010000001001000100110000000000110000", "0101111111111111111000000000001010000100000", "0000100010011010000000100100000000000100110", "0000101100000110000000100100000000000001101", "0000000101000100000000100000000001111010000", "0000000000100100010000100000000011011010000", "0000101010000001100000100110000000000110000", "0000101010000111000000100110000000001001000", "0000000010000100000000100100000000001010000", "0000101010001010000000110010000000000100110", "0000101100000111000000100000000011001010000", "0000110000000001010000000000000001000100000", "0101111111111111111101111111111111111111111", "0000111000000001001000100110000000000111000", "0000110000000001011001000001010110101001011", "0101111111111111111101111111111111111111111", "0000110000000001100101111111111111111111111", "0001000000000100010001100000000010011010000", "0000100001001010000101111111111111111111111", "0000100011010100010101111111111111111111111", "0000100000010001101101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111010000000000010111001011", "0010000000000100010010100000000010001010000", "0010100001110110011010000000000000011001110", "0010101100001001000010000000000000011001101", "0000000000000100010000100000000010011010000", "0000100001000001101101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000000010111001011", "0001000000000100010001100000000010001010000", "0001100001110110011001000000000000011001110", "0001101100001001000001000000000000011001101", "0000011111110100000000100000000010011010000", "0000100010100111000101111111111111111111111", "0000101100000001001000100000000011000111000", "0000101100001010000000000000000000000100010", "0000110000001010000101111111111111111111111", "0000110000000100000000100110000000001001000", "0000000001000100000000100000000010101010000", "0000101100001010100000100000000011001010000", "0000101100000001010000000000000001000100000", "0000100010110111100000100000000010111010000", "0000101100000001100000000000000001000100000", "0101111111111111111010000000110101001001011", "0000101100000001011101111111111111111111111", "0010011111110100000010100000000010011010000", "0010100010100111000101111111111111111111111", "0101111111111111111000000001011011101001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000111110111001011", "0001000100000100000001100000000001111010000", "0010100010010110000101111111111111111111111", "0001101100000001001001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000000111101001001011", "0101111111111111111101111111111111111111111", "0010000100000100000010100000000001111010000", "0001110000001010000001000000000000000100010", "0000101100000001001000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000001000100011001011", "0001000110000100000001100000000001111010000", "0010100010010110000101111111111111111111111", "0001101100000001001001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000001000010101001011", "0101111111111111111101111111111111111111111", "0010000110000100000010100000000001111010000", "0001110000001010000001000000000000000100010", "0000101100000001001000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000001001001111001011", "0001001000000100000001100000000001111010000", "0010100010010110000101111111111111111111111", "0001101100000001001001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000001001000001001011", "0101111111111111111101111111111111111111111", "0010001000000100000010100000000001111010000", "0001110000001010000001000000000000000100010", "0000101100000001001000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000001001111111001011", "0001001010000100000001100000000001111010000", "0001100001000001101010100000000010010110000", "0001101100000001001001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000001001101101001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0001110000001010000001000000000000000100010", "0000001010000100000000100000000001111010000", "0000100001000001101101111111111111111111111", "0000101100000001001000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000000010111001011", "0001000000000100010001100000000010001010000", "0001100001110110011001000000000000011001110", "0001101100001001000001000000000000011001101", "0000100010010110000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000001010100001001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0001110000001010000001000000000000000100010", "0101111111111111111000000001011011101001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000100001000001101101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000000010111001011", "0001000000000100010001100000000010001010000", "0001100001110110011001000000000000011001110", "0001101100001001000001000000000000011001101", "0000100010100111000000100000000010101010000", "0000100011000111000000000000000001000100000", "0000100010011010000000011111111111110100000", "0000110000001010000000100110000000000001010", "0000110000000100110000100110000000000001001", "0000101100001010000000100000000001010100010", "0000000001000100000000100000000011001010000", "0000101100001001000000100000000010111010000", "0000111000001010100000100000000010110111100", "0000101100000001100000000000000001000100000", "0101111111111111111010000001011000101001011", "0000101100000001011101111111111111111111111", "0010100010100111000010100000000010101010000", "0010000001000100000010100000000011000111000", "0000100001000001101000000000000010011001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000000000000100010000100000000010001010000"); end ffaccel_imem_image;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.ffaccel_imem_mau.all; package ffaccel_imem_image is type std_logic_imem_matrix is array (natural range <>) of std_logic_vector(IMEMMAUWIDTH-1 downto 0); constant imem_array : std_logic_imem_matrix := ( "0000000001001010000000000011111111000101010", "0000101110001010110000000000000001011001010", "0000101100000000000000100110000000001000100", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000000000100000001000000000000011011001011", "0000000000010000100101111111111111111111111", "0000000000000000101101111111111111111111111", "0000000001010000110101111111111111111111111", "0000000000011001110000100000000001110110011", "0000101100001001000000000000000000011001101", "0010100011011010100101111111111111111111111", "0010100010000111100101111111111111111111111", "0000000000001001100000000000000001101010000", "0101111111111111111101111111111111111111111", "0000111010000100111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110110001010000000001111110000000100001", "0101111111111111111101111111111111111111111", "0000101100000000111000100110000000000110001", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000111111110100001", "0101111111111111111101111111111111111111111", "0000101100000001001000100110000000001010000", "0000000000010100010101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000000100001001011", "0001000000001001100001000000000001101010000", "0101111111111111111101111111111111111111111", "0001111010000100111101111111111111111111111", "0000000000100100010000100000000010011010000", "0000001110000100000000100000000001111010000", "0000101100001001000101111111111111111111111", "0000101100000110000001000000101011001001011", "0010000000110100010010100000000010011010000", "0101111111111111111101111111111111111111111", "0000101010000001000010100110000000001001000", "0101111111111111111001000000111001011001011", "0001000010000100000001100000000001111010000", "0101111111111111111101111111111111111111111", "0001101100000001001001100110000000000110000", "0000100001101010000101111111111111111111111", "0000100010010100010101111111111111111111111", "0000100000010001101101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111010000000000010111001011", "0010000000000100010010100000000010001010000", "0010100001110110011010000000000000011001110", "0010101100001001000010000000000000011001101", "0000000010000100000000100000000001111010000", "0000100001010001001101111111111111111111111", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000010100001001011", "0001000100000100000001100000000001111010000", "0010100010100110000101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000100000000001010100010", "0101111111111111111101111111111111111111111", "0000101100001010000000000000000000010101011", "0101111111111111111101111111111111111111111", "0000101100001001000000100110000000001010000", "0000000000010100001001000000101000101001011", "0101111111111111111101111111111111111111111", "0000101100000001001101111111111111111111111", "0001000000000100010001100000000010011010000", "0000000100000100000000100000000001111010000", "0101111111111111111101111111111111111111111", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000011001011001011", "0001000110000100000001100000000001111010000", "0010100010100110000101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000100000000001010100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100001000001101010000000000010011001011", "0101111111111111111101111111111111111111111", "0001000110000100000001100000000001111010000", "0010000000000100010010100000000010001010000", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000011110101001011", "0001001000000100000001100000000001111010000", "0010100010100110000101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000100000000001010100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100001000001101010000000000010011001011", "0101111111111111111101111111111111111111111", "0001001000000100000001100000000001111010000", "0010000000000100010010100000000010001010000", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000100011111001011", "0001001010000100000001100000000001111010000", "0010100010100110000101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000100000000001010100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100001000001101010000000000010011001011", "0101111111111111111101111111111111111111111", "0001001010000100000001100000000001111010000", "0010000000000100010010100000000010001010000", "0000101100000001010000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100010100110000001000000101001001001011", "0001000000000100010001100000000010011010000", "0101111111111111111101111111111111111111111", "0001101100001001000010100100000000000111000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0010100001000001101010000000000010011001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0010000000000100010010100000000010001010000", "0000000000000100010000100000000010011010000", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000001101111001011", "0001000010000100000001100000000001111010000", "0001100001010001001101111111111111111111111", "0001101100000001010001100110000000000110000", "0101111111111111111000000001011011101001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000000011000100000000100000000001111010000", "0000000100000100000000100000000001111010000", "0000101100000110000000100000000001111010000", "0000101100000110000000000000001000000100000", "0000100001111010000101111111111111111111111", "0000101010000001001000100110000000000110000", "0101111111111111111000000000001010000100000", "0000100010011010000000100100000000000100110", "0000101100000110000000100100000000000001101", "0000000101000100000000100000000001111010000", "0000000000100100010000100000000011011010000", "0000101010000001100000100110000000000110000", "0000101010000111000000100110000000001001000", "0000000010000100000000100100000000001010000", "0000101010001010000000110010000000000100110", "0000101100000111000000100000000011001010000", "0000110000000001010000000000000001000100000", "0101111111111111111101111111111111111111111", "0000111000000001001000100110000000000111000", "0000110000000001011001000001010110101001011", "0101111111111111111101111111111111111111111", "0000110000000001100101111111111111111111111", "0001000000000100010001100000000010011010000", "0000100001001010000101111111111111111111111", "0000100011010100010101111111111111111111111", "0000100000010001101101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111010000000000010111001011", "0010000000000100010010100000000010001010000", "0010100001110110011010000000000000011001110", "0010101100001001000010000000000000011001101", "0000000000000100010000100000000010011010000", "0000100001000001101101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000000010111001011", "0001000000000100010001100000000010001010000", "0001100001110110011001000000000000011001110", "0001101100001001000001000000000000011001101", "0000011111110100000000100000000010011010000", "0000100010100111000101111111111111111111111", "0000101100000001001000100000000011000111000", "0000101100001010000000000000000000000100010", "0000110000001010000101111111111111111111111", "0000110000000100000000100110000000001001000", "0000000001000100000000100000000010101010000", "0000101100001010100000100000000011001010000", "0000101100000001010000000000000001000100000", "0000100010110111100000100000000010111010000", "0000101100000001100000000000000001000100000", "0101111111111111111010000000110101001001011", "0000101100000001011101111111111111111111111", "0010011111110100000010100000000010011010000", "0010100010100111000101111111111111111111111", "0101111111111111111000000001011011101001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000111110111001011", "0001000100000100000001100000000001111010000", "0010100010010110000101111111111111111111111", "0001101100000001001001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000000111101001001011", "0101111111111111111101111111111111111111111", "0010000100000100000010100000000001111010000", "0001110000001010000001000000000000000100010", "0000101100000001001000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000001000100011001011", "0001000110000100000001100000000001111010000", "0010100010010110000101111111111111111111111", "0001101100000001001001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000001000010101001011", "0101111111111111111101111111111111111111111", "0010000110000100000010100000000001111010000", "0001110000001010000001000000000000000100010", "0000101100000001001000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000001001001111001011", "0001001000000100000001100000000001111010000", "0010100010010110000101111111111111111111111", "0001101100000001001001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000001001000001001011", "0101111111111111111101111111111111111111111", "0010001000000100000010100000000001111010000", "0001110000001010000001000000000000000100010", "0000101100000001001000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000001001111111001011", "0001001010000100000001100000000001111010000", "0001100001000001101010100000000010010110000", "0001101100000001001001100110000000000110000", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000001001101101001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0001110000001010000001000000000000000100010", "0000001010000100000000100000000001111010000", "0000100001000001101101111111111111111111111", "0000101100000001001000100110000000000110000", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000000010111001011", "0001000000000100010001100000000010001010000", "0001100001110110011001000000000000011001110", "0001101100001001000001000000000000011001101", "0000100010010110000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000101010000001001101111111111111111111111", "0000100010010111000101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000110000001010000000000000000000000100010", "0101111111111111111101111111111111111111111", "0000101100001001000101111111111111111111111", "0001100010010111000001000001010100001001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0001110000001010000001000000000000000100010", "0101111111111111111000000001011011101001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000100001000001101101111111111111111111111", "0000101100001001000101111111111111111111111", "0101111111111111111001000000000010111001011", "0001000000000100010001100000000010001010000", "0001100001110110011001000000000000011001110", "0001101100001001000001000000000000011001101", "0000100010100111000000100000000010101010000", "0000100011000111000000000000000001000100000", "0000100010011010000000011111111111110100000", "0000110000001010000000100110000000000001010", "0000110000000100110000100110000000000001001", "0000101100001010000000100000000001010100010", "0000000001000100000000100000000011001010000", "0000101100001001000000100000000010111010000", "0000111000001010100000100000000010110111100", "0000101100000001100000000000000001000100000", "0101111111111111111010000001011000101001011", "0000101100000001011101111111111111111111111", "0010100010100111000010100000000010101010000", "0010000001000100000010100000000011000111000", "0000100001000001101000000000000010011001011", "0101111111111111111101111111111111111111111", "0101111111111111111101111111111111111111111", "0000000000000100010000100000000010001010000"); end ffaccel_imem_image;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Gct/uIPzc0i1NIb2WUOmNkw/P9mkWgE+av3+XcZgONpQjHkUSm6mhOBblanfwG53ifeZzv2he/yA kUFzXQkGKA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block HHqDTkC4HJ5w/u60aALx0AOcI6Y2bB2b0PbzUmDglE4MnBl5IussFMSyoANhd1y7tmLXZc28RSgr yZkwiaiC81/6YapUsUkN7iI7dzxe3hJX9OANajuZyyDI+hXCLRD9Uu/osiKpcvzpw9w5GG7KVcL9 K06jQdh7Mtp17qJUqgo= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block VHmPHUcspS9rMHMyb5PldS21HYgXrVrEPvP2SLYM8GHqzqUWtXMk0cayWXJFw9ZucXATYCapeYtt c7lshAhqaD8EYf/j8UTc0jTGotqiWqK1x/wY7vHDTn/FvjImIwSrNO4b4WV001E54Csg/RiwLXIe YNKQPvWQjj6hC/WQ2K/fS8Xf520w+iBajNfHNBdvgl5MO+MT4r7QHAzj+MrWyEFPhX4WGOV3ax4h YEvBOxjNkq1SapFBFGS55pZKvsQY1RFyq/7Cw/nhojJdZR5oaI0RPtQPgUvGA8Bl0VIadq5y3dmD uHpAVWTFazili2V9eD/+/bKIPdmnXx3JGLag0A== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block X4MBCXMJB2QRvZgQFT76Zu+KPNwU0oUILEvKVPuSWL7ppRdfzESSEIMkoMbN5rcgisCgkeBdNicb UL4H7xmpRZFgeYLVYDKFJ2rM/nPHTuueakQG485kpVaEcoOXfBQOl/p1HUrsqbBfOuFpy1zoX4/R yHsrYIFialrrZC8QVhs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Bd7VV62aBct/KZ7lv+k+J7GMOzo0uW1A7HgmHEqMv+X/ksCXXU6aNw/29YgEhHAe8caLMvfwoSBV 1gdbIRYZwl1Xd8SX5n4y7c6eo6cQkLbHU5o1eS2ku3OXk4NpsIY/1IithHdMZ7wrQ3cPyYb41TMv BmftqC1xDXLLsIjXzJBqfV3RFZO4McADN/vC5K1k7yarS4rRfY1DZyC0ZfUdYNpSoHtYrhOvp1YU jySfiRCtlrLydo9VksOkOqoifykF73iRHcuujg2HctQO+9yyG5FEPodYM9lLEdPH+U40+f3ANfTd CdDWoYINsasgQXfKm1l9he2JqvZwAn8EzM2h7g== `protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block OYTYlTCqaEBv9tjHXsSmTvF8Y5+U5CS0jpnBFMNUV0VVo45ksNvj6f2fI7tE1Oen9ix3ISyTvP7O 7YpDUlyTE7meb/fmKvdZCWIuAsN/wef5HuukSJ4M3Indf2UWWa1KQ4El31VCeIcePgq5upCUflma V6DxdR5+f7maSPI92gt28G5nuYJ2zD67RsMwuAkxoUhOpxjuc8eV+G5557x1LzTWJp2u2PypsKc5 T0uPg9UYfMS74vmL19/UoNPWLNBmQKsGVOZIXHvgv/Yy3kcEVaoitqmrmLf2iGjJ8l02Ihr5Z6TS l29ordoxEZeCPOHxzsOMPV1eJlzgTvlFJ/3Aow== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 114672) `protect data_block rAex3cxN0Df9jMi9dmX0g1gJa624EQ1FGainl8mLpqPMvG+vmF3AVZRP/qKmiQtf3k4AlJ/mU/p7 LuYTHcm1VvXkpvTwAG7GZgg20Xy7AIRnIRmYZ0pwb4hrmxtO1xBrAb1V+u8Ak3vUuL1H+5e9cl0I eaG8KLLyTeRaLGnDL4MAbUWD5I6eYQdIuHP9socC8oLKckFxZii8W1z4Kk5iALWA+QRb48cG3rME vlZC5tRDwLrGj3LB6dol4gQhu029nGhvBNtpqBIV7vt50YWAykf4WwsKgaNSi6rFXJAByhPnEWvt 8zK+pVYdSLrVo7TkSa3WRG9+Bhqjruk/jwaw3Aw7cZ1nZFr88lAjucqcxocnRIAx5ueNJkQKDhM6 I8EA1+t1EhfEfSrSUc19VvZ6FV0IT6nl2jv3gMHEQUc0RG16S/JjKgVza0QTRXdrDbVvvAZeikYn pP9YTtBRxVp4oqSWgdnhWJIQpc+bE4JBJQapX8P5b7XP51V7tUv+ILaVoEPpeBPsWw2r10KIhw/d c45ruw5sxZ/kF0GSZpIjkTBdL6iypiaSF/UgUCuIp/SWA1zXGioByXP9pWC84C2BFlMGV3mgUxVF lFBsABWKoB7lcRdzb9pfkzIFOSB/dzXC9LX9E79a8CsLCsJyvwtyCmwNuv5PZP9ZkoXCxidVTxGR QxXfVAB5AQDjYP/9ElOCWzVVWO5a5HeSZkb+AKmgJOH6aB/XlClMatq9XrGghpCBiiM1KQOA59o2 FxAJbTyCpBWygvlPuGHcCcqy/Qe/Bsq+C3q80S+TdLX24yLrG7LYy6fQFMqSBUBZeVDJIMOlObxW WKNIZ8AKYxGgMYebqEizMOBqcj1PFCTj7/dSU2BnNuZlTAEu/YayJEUiWtmo9uzUC9Gl2NGRK4yK 2uDV5k4Zf3oSI1Q9X4cF9xtALsGKIiPf1Swq458aR/+5whYumECWiHVJ8RPr6cIx+HtE8vo6s+Sw JvOWPjupYFP/CLiFnrrRUrdFRNwnNdhnbUaX/kIvz+kOvYZeHB6T8NffQDaZuoqDeTqyO0tfV7r8 gNljILbJ4YCqTbrPa2s4JAx+eIm7iFGzI9QECXGtURG2yXd1px4GEXK7IQMt3UlxsT80kIy9rHEK rcz68Wex85JBOG9QzGhf2GGEEkZ00bPJ8i++FIo2Az3H7PPtokcs+3MkKEuxYm/Y4XV/yGTT5H7p dBtGVFmMSGvB3B4nhYoN0wSrNIkHsEb0iUJrOEWXJ71WAWJ6Ym4kwi6PNNdqOAQH+nTfTrdQRH/C 8zX93m6cix1p/jZ8lTtPkkGfOg6j5NEPJbhZF3hvl8uN8JByF+YMFLSfsUgp6UHJCW1EowLfhYA6 c6ADo9DJNVjlR/XQIKwZZiIXIZEIkZUrX/HT61t0m3AWaIl79J+J/cJcx72AcmXvI1JT6jkCgYTj whLOK0jgLefi/UYczUxOGzwH0SiAK0c8W9akppq/+GXnNVvkEJKru54Kgll90vSIZ4zxi5/OTl+w sfyvcc8689qS4FtFQIQZ3hRi33U3SWhkqlC3z0qhFW0ETlpfxBFzO24aJSNHDRSoLBQMWyehHfoN brPz+kvqf+dx3MV/8YCpSRUFiGowuVDEq6f8eJ60iLpI4PMaBVLbTNMo3JLG4UcjCUsO9bQk3ckX lJpEjntPwaao1b9PyZmnvEleulQJw3kxBPzbtJotjRtHNa/2wQ9ruSwtKGOEewhUC8OU8rw/PAj6 SLv3j/nZfDZ1Ynrj6iKnuEFx0zEiqN2cSB1v/GJ6CYSPtQADRkhXEo0tJcmo1s5hfjw+eqBGy/xb PgPhCSypJiAiBHFfqiErdXtgeZSv1Oj0NdVlPCyzKO/priHWk3D0LcoeeY1EkKElbIbo30M7zNoh xfsgHni2J4WzwTCpJf4mMwCIt6aLaAA0KDWcghPQLCfLHlji6hxkoO5k7SWidUuwSnwqB6SV9lFL e4jFCkAP9S1sl2Pp6Bu4xuoB4s6b/W986YAXrEwybnnj3nswQfuSH2wT8zrQkvMu1J8HKnHlz1Nu rGUUyBJmTwdd0w6OUfsdvQDQ7H/n3/CoANr2y1At+D3wUULOC4kUZa3qKpXV0wF3xjv95ehiKKNt 3Zw7Y/TMPe3wDNhYsOMQgvEGFN2/gDELl1yGBTjWyBgtbLmNjycxPDQT7LPj2OE5RRzTR+CUHAf0 GCmRVMe2BSNTZtnDuR+LhXJrhy4eAarOeoVgOXAm7jfplfJ5hdJGBPCYUUTCO04EPN4me2Y205e4 TIZvtL2nX1Dp/Ewt5Anl/XV5jq6vzMWyERJ2gUIgRvmN4DX3icrPjgmumetYHo7WA2yEPyTq2S+U RrcpKh2alr+O6laGMO9gzIVz4lbHLdWqD5rktM+hbycSSgw5EiWaQVBrCtGyKVTVXMrhstfAwv5/ 4afMV8KfCmlUpMGfXS7PDfc0nWe3BG3YDi4K0cWE1DTC5fnpwjhuG8GN3KL3q/fOEiVsYsRfVTXa rWVAaFI+ixdB/7VGCzFg6Mmr90yaTxWzaXYZfoLr4A++BEg7V2l3vOSScINTMrCbw8OI26tkRzda LHC+DM9Jc0sSZp8wYDd1VKBI38fT3xa+5DJ6bEtjX0zBBXbtioQOytQTc8yxZL336kPtyO7VkR+1 Rzj2pAJmA+K0GcyfAF7U2dcF3QfIhIFN++bj57a7U+gDTfArLXwUraH1X7oL2BDOBYPN3KLHqdK+ vVgtn49GDEIAxsyY5fIxrEAScZsMLeXCQfgnlAbHv+BtucCCTxETJz0t39Y/Vgj4QQzHOXu+U9eg 5ZAhq53Uhjlunceonu/sj5deILSJRas5/LzMW69oi9Xep64aPElaF9+vpZXF3WLsnnHR9xH8qj3F tml3X9H+crRwwGsZy/YklKFkwFdmrJZ8+MriejgvUjxCwvPqT0QgP3/mi1zZQfhPBd4xMJF34QAm 81Sjb1w7R9Es1RwsmRG5yK2E1s09k7E0Y8ypQjDoVi6MSwCVCWkGKFg9tnZ+1H50xUe4JokAMbyV i0nMzOyV18RKZ8bt0tFX+NyDnTbPEUolaz1zVt768Mf9uc3nk0TrQDbkjAas373WNxRWP4BgsE6/ LmOASnwt4Z5RcWjyz2usMY0I4ehCEgT4lKxECXyLFNCSNKCoplWK2ycLOLPUYcrPKheYXWsM7DYi kIaS1M5LQN9veO6XJgK4yldcCpygstmdBWqMudNcSldy1MhjHJrXQIzpRTLSwhg3jlyKWJrdyXr9 c2dSqepFoeyPAgizmLBU1daiLr3d1YNR8AoYnpqX65JH5ypACX3m4r7jm+l0ZWfaCUYEOrdQYX2m Ou96sg6sRKbCJaa8m40V8KVG6+xNu0w2bs9kSGz6cc4mj4pHelvpr0fCDBV20LaUDmFGP1Lkcbk8 2s/XRgvd+RboL374Ejmk57BdVU27muTO5MTv32DkkaoTRhAhyI+KT4z4vEbAdceNU7NjZ3BUPDQq jaD1taxjCkHXTst583tsVKdKpcMtvMQzgFwuAa+hGSI4ALYj9ajkiFLkPfZla8EpX4qLWMK3D8GV RAKzNJvDzLEiOFXyDK1iRX2mN3yU0YWVECWxl2O1+pt2N1OtLrLLUyMjzzJSED/ANYHM3TO5+zjw BK4vMWu2piGJml9oMXzHS16OXx1CQ09lkynvjBVH7ve0lurDcm0prV4c8QU+FSuvSaUk06Ud1saw TdnL9vvarX3iUXxzOawMmXs0F7y2n7NIkuERNNEK2yiElU9aNp3ZWrz94BVWW6eTKhjPc/xjNVv9 aI5V+X+yf8LD6iJF1lU/veN+kMRCm0gCcOMBENcosvl4UTfUhkO3Lh8C5HqaOVZKPQ6nl/PYs9qO bCnIiIEvSObEs9jVL9bvQCMOTWS+jbh3BPAF7kYQYneQjfHSqTNI+nc1FoHgAaHIlv6ZHpuWtl1s /3vOlwirzuOr6LYfPZjhwnrvDKEx2eoShy4ucRPS7P8EsXmLvnsvFCnX5BENfTxSCJojHL4kqBbs gMcT04Vocslsf30isMRAskmgCPvMvSwuToAO7Eer7PmeWJxFOQvfCHcExC4CSaCbQKr7m6j7MQpy LRCOq5Iwz8KLzZbQPYTU7YTKZDK2QHtLgaI/6cHE+VWa/nDpwRSJH4kmNC9rqBl5GZgAbhKB3HE2 wIUCBY++3ZXwE9iomkERnH66gZdEWozt5iDhiU9y9aIX/D9CmfK6NC85axhe90BFb6VL+JQs0mBm p6oSrbsQmhK009J/9UA0HAlQHI77NGKWGWKBuwOLeg2Pzfn0riEYNfkSZvaz3H2WpgeH7GSjpqPk M5ifa/41u4ovcw2T4yC9VMVkz7oeFnKieF5la9y9oHKvdxADEg960yh/aZl25zMp1u5uWzgv1p/1 EIa9u2bXMpr95A1nTBEnkORN9V8e3XOU9RoGNGiKkPxELbhWqunv8+n9ztANOPm1U+9hbeSE5BaT 0KNAB56FUm0bplwGwzox0Up+AUMoX6Bg4ITwJk/FBbqylRvTMUXGGoMNjjkPD1nHEeSL1srohGt7 FhYfu/OGAL2ZO/xRNeaQQR+w+WPr5h0L0GapV03IHd/jKXjcnhYVDEhSXMTiCNHfozkmqQZ5oCNR BAsgdyYMmLp2EVGuSvVGrowXMZHpdeSYhYyFmlHa9NYMeU1MbElr9CkVvb1dMzblPbTEX8wSGLqq CBGMfo1iMR8wbNLCq3vh5fnVe7QwrvWPu7fsYCiUFb13RetkoaXk69taRddDfw4TMJacEIcEj3M4 SuWjuL8QIavWQC3zAW2A923L60vJQxOE27AgnUa/vhMDsQOIUASxwZbZHydwjhwY8JaLqcAMTKQT AEG1Ln47vT3Rg+XBK6lyQwpq1NvD38s1HI102MEX97W7AjfNsTA11Ymr4yfMcVKWXL36xPfbAWZU hWMx8/jubCENdt98ojyijWzFi+ZfRdBFhn8UDTZ4Zu+SN9XhH4sTZmw8UFvbQqrTmEfT/J2QyzKQ PPS+t09Rmi2cMJ1Ylgw3GqFYeNxhmCC8QCS+Eis/2gwXn/b6QBDYlNuwtzPy6PRAAxnX1nmj9OhF 21hil+CIaqJLoY52iPcBopEtsuB9U3yFfKEST5esP7hNcsJOCc5BJAT1rEkm/463birDKSc5mUXU 8QthxDGJ8YLb6TroDaajC4jNVNhyqnyXyCmSGngszSM+sqcBMUxr5LoOb1WXsWYbmVFhorcjroa2 dGRAnczPtnJUrm9Cr499qTQUWDc1NMqnbdhxDHsY4KEfYZ1JbJmdxaV9V3EAAesRnXIT4A6/RvYH GoVGmQuPrDcaMYajA2qtXhdsTYF6ySoSiSIf/tVkb7HeWSMw8gqm25hQz9LTiu3Lj4IYXlMlQ7m7 2s2z2Mzl9ts73VVA6EgQ7v/N1Dfwr+fnrnmjxfjQuGcnc7CKIVr7boNghMqLp1AZ9KUJE5MLewM8 FjUyj74dGjvLt2yBWxxvSlrrG3LgFBgS1hJbem9Xdz1ge4iQ934n2pRZbqqFbeCTyXn6XEeJzcvY eqxzlsG7xsWgxzSguz7ALCCTuEeKtWARDxFN2P2xrmKM+edqwlfAc0wAg5r6rjzwvaE6Wgsben+8 8DOCy61gH7jGJYf9AEqjEd+kIRn6uWoVKciIuK+HXi7rZR5GleEEn5nL9QPDQHDA76pWOrwvlYTY /hRzVYnYyMAMjWZbyQiI3JnGm8lGCOrL4gagYrgZ/LLfHNgeFSy1JkUg/hF3WqOZ/gKDSMYcfgWh Hqx9SASYuJS2qc3iDqa1p0I6BHki9LwJm0ajWPzgNFw0TAnEFAECVyHIX+s69sUG7UJ+/h6gL9Md 6nvfumR2z7nnvQ6Jrrierdv9F3kY8mtz0mxRegHVxWdBQqpeIcp1LUArliH/ftUtYL8R6m0VYp01 t8PpBleyZG40sohtQu+0x2VCv/kS8jYYGFgJ8GZ8tPOOc61gByOkLG7Nna9q+9R/UQweEupQsVWg Sw5xwzdlMCOSToK4tG/7f9/FP+CDwPqvh8hxuP+ETpxz5nVdqVX3E67mfXfXx0aca1kMFfPB+/iu ypAWDvB7rnD1j/3wlKfHiJFGlQxC2fdv1ByNg6T11uh2Ho7khMZ92RdhJzwIHKMmawhUknwK2rAB KtWJxWBoW219cYDCH6Dn8EZbXR/xo/2++KhpgYvIDJ15qNQpmHIxu1rHRe0LDBi3v9XnofjcTdb0 MAskO/rxgouyrw4SeZTzSJEKZSINAFdYb2dvttFOR6at6ptygrW5bI0YwG+tC3s9biVLx7Ro3FCt ZzzjwY+4yVYeEU5U0rVSN089D+v4wTa+65sZs8vzC27mr46YsA7eGdj5DwNcYfmCtYpgCv9KjiBJ JBL3re3DIdd/uPlIAlLxa/BbZTqgygx693FakPhzm6eUv2uQoPPfxnsG+/0xFNcKG7dQjucO3wLa UXXUSihpp4PFPNQeBU5DvxIqNqvv10coLLrATBROGyfRCt9BDHaclprep5cI1fmG8HA9YOti0E4D kci/7NpxVhivznPaoBXJZNH+39MrPqUEeYW1/5dXKt7aME2yWaWbbatOT+tFB8Jy6ooqbCvX9sC3 jrGO9UNXLixuw9sOctHVAOG5ZxvfiJfAtnY+TSxnPbZkU6CvbrVxCRcfutx3l+yL1340+4OoQxOh PqzcdOL6fe0FeBolAHpV3kDeKRuh0F8gDzR6L28DiwSMRuA8lrkhc8QHh1BfTQKv4FqBc7/3TNsE 4k61o7mk46riGeZb+3Erzfqhi2U1U6INbvttDoYGa4jFySiCVxyuwCu76Prtt+kSP2c615CaiQ1N sDQFQ5ndka/xJeiVj05K2fSoIRk4vPnPVz2cqXKlDLKMx641HQGk1xrlaCa3Y5be/OnCawsdu9Ph LmchalmyjxkzacQgfx/alrcoOVMrr8GC2vlP/6RO8nCyKOlG/Yk/Hvaz3d4epObSP5SNVXWct+ls sbSPqZFklfixh//ddEykQPbmwYQ7cg4AWm8n8XGqUCGhvkY+H2rZj7PmfVUq+8LDzrAFpsdZrJco jb+MWIH9Hk3CNdTQ5ZIjEo+g+tDnKHTm2gOLGIxgmCUrCmR3kdBM/jM1i0Htb8jT3JfjyYWUJXaI U4KWbsTrF9hVBMpW+OgUGjhjof8qf5uOELacCW9tpA98djnMUkP7GhQv6enQzIpRsxYCVSPp7F2Z x0DrhDeFvQ4kLyuzDw36zVhNVCG8gGtqNR2sO+iC1vAl39uM/kUDoVm4JYYPUb9d0P+o/IbvAiQj mHPHLuu/k6SlZeU4wNjP2dwSOISeKTrkVTyaRrPuImbo1h1GW9j1g25PunUm5qwGwsqhAwPR+wa1 94WVKmgcyeyiDZ19jm6iRWLiIUmsZGG6RKeTHJXi7C7okdVpSv2DjokCC0rto2CjnXT4HK86xYth AQ8xOnMgzNOw7NBIAXRHOxz9wi+7FAzROLfcFmfqLJWC4LepNohCb5f/y3b/e9ZLTUiMpwbyiQch OU9EAjYF+rfIOl9YOqDZP+BKpF3appuSV3Z/czfYNkbgHwGtOofukFpMIH1vuPfMxOftnHbkrsH1 rzx9GKKnEtngznxTdptMvMzJ2J8iUd+VOsFR5zwxTYe8yLskFoukIJAezgYyo5zvIgdxI7gFOJb2 dHIuNXF4BPBWmRXo86ph9pqW5i845Y+N+TmPzLYTcTwCpY2/s7K6ss/81AIBeoyH8vhZHzMiE6gh /KUcxmRxrIYSZ0Ms6i+qae9oNrvdB+TCLffXVqgNsutclUr9kvHv0SUMMDy6h6uYloCN3Y0AuVGZ Y1mQULBdkGBW4/mcwjm/m2iMxvsf1ofZvLX+kdQvYWF1F8kBb+k9LHzCvMAEOaexQE3zL9wDZLED MtSI1Zasm2OkLi22XOrmtza2LGtDoosbBULZydKMz2/Be+h+o1sIYrqqIV/ApymtSmtgOZUkFTgC 7rLPBXOlS7eDodjezgVxh37QcMHocMDFrqVs/tQZUSuCAvLTlbI/vy4LrNMd+DRCECX9rP3ngG0Q 2sSfJQTm8N0vzrk1WgeBHBskXGvNtesAkOJkkJO0NnC1/nJ/wL6OJP7BeK8usj0LjDK5ZJtzW06A ++2Tsfv3F457pSvOknvxvM9HPnGq003mMCK4rjXQXakvf4snH7i9pbPPFjA5tYQblQ6KNNgYOJ6e trHmiSuecvG37Mg/CD1Yofjxf2Y9kBICZJTt+69HDLYb6fZfkJFiu/Ugnk6OqAXP6OloLsT0Txvw uKe3HcuLFTeckFck64IAZsqGPs3bePeYUuJX4YtBHLVKhKzk2VKCLPHbPKLdxsZbiCPvEvEyLCvf 6Ngl3StnCHVWsq042pKu21y74HGtym8FX22/dQteJ/L1i8kUfMLyqhOF4tMCmg1i1e+rYvqgDw2N WzTWtdGraXJcqQU/usdwaEci3H6GLAHVnalos/7vHwxso2hyO1SHbdvCyyIBrsLM51nv/AcwqQZC WVPJV8dunBdBXiQCdN8YV2Gka64kHgGvHKiri3bkAsZ8n5AZeCxFtiqIoX7QTdHQcJwbtsSxF777 UMfCBYQqIuT9Q+cQP6xPqOu1ajiHbx045IEmJKSY2e2t7Ov64Agh6qLv+VrQ3QXwcHZRlZCwrkbY KpVjP5Ys4lo/yUmyPWzRo/Sgyhi/x2bxEGAGFrmIOyHGuOsU9IWLjnckdhoAYN73kt6A10Gf1mG3 MtxA4SDS5Rftb1h+br261w4qvIk+9uIkPWYPObzUAa5+vjogcZbpsI945Ht6/VS+CG+7v7BASs5x vwE4KkZUpD6CuQNb6UD9l5Uxq//lEsJEimYtlYi5GVCxmCDyT6EyH+TWGJ99ZzLzcry/eC6jC3G5 XwGXOeyfkn0lLx+tOiU3phoWuDldCCcWQn7eaXPxOiqrI55y8eKO2RxMAUqHBY66kdXcXfJel6hl yXOIsneXIRl72XJIviJbmSO1+htIe5EmZD7ohFnPpfV16CwdejDjNjjfCR6kWwRUGsMpS5bD4BYB eaYJDeY1tjYM7m6gwubNcJlQ+u/6hHHfoqjih3atOqr0N62JWyE0fivrwSNvYH9G5AG+UkB5G6j8 v98RRRrL/MDMrE/gUdYBEPXRs37v1slzms1OHwyeh6c9WHHmCCHVyLTHdjkpEEJp+zRFy+65Azmr pyxdKtIxJKAwmm2v+FzufvvICPTm6mJkR7JcoAL0YvEiGCNxLGzHchIMI+OBGEhXqvTUebq7XAx8 DMkOLfQYWeA4FTA6Ak2p0GZw6vRgS+NrwA0+uwdNgKut9qkumP3upr51BcF3sFtq5sN3jZ74J8Zm RvganlGsGd5FGNDRF3yJwMa7EmPdGYJAxZZaj3oALQ5cPjo+XfuqQgT5V6Lqi46b6L6nDLuS0QON mcs853kTcrK5S+eZmRxK8no6IDOa6C4d5ANz7np4oErLGhOhFHrCwk5xavL0zmNE8rHJWu2LB/hL Pem4/ZZA1uO+3bZd9TbtiByJ8E/KLY6xXMwqJDbQNQbUKah3HSNrBdkXpna6irNX+W9akgnuxAqm fbL4zfFMN4jOS4KDZZCHekINZQOtc3K4f5l35SXxMMZCgJ4e1HSRr+huSXNLS4wDd8Y9UPYSdhCc FBEKnVm0Fv+RORTWShiLjKXpqkwC32FVwJImFumeXsLNE7Qa6D8NymYCvo/mcN4qvbBF3nlk53LC 5mYPKpJZ/hHCAUPn52iIAh6Y92OO9wxb02mlnnlaAMfsf2VNzpZsYtK3xF4ycgRoSVuBfEmeKdFZ GFjY33NrX/4EDIQGm8fGrAm8flTJscz6L122ap9uEIRix/zePlWA8CiZWE5EFtz8Le05b9jQfyTg S2Jr18PPiaCJ8T6Vf83sIS+MxpC8PGvyHll591cNyYDa5h4j3v6IuaUkLPlNg5gq8QFbqqaa/kl3 tKnFMQjTb+zvbsSrD0j2oH0+mo0f9kH0u3du11SA1fZfkCi69pDM9EU+0/2fDqqmjk7t2SJ+wc0b D2PksD8QqFp0tlfMp/vt30x6mcWFrNys8Qdk/k6+e/7hcD5QP9mgtavn/0gnhKG2Vd9sl9D59aQz 9U+ybaFU9XlRfaEhekTchOFcbd0/eOQd7BOtpnYrMCczmbfHxBPmC9pbAM5TZCAIPWkPgol7Or87 hf4wDNLiHVK64SnS/oqMrgD1QrTZTFq13RQmqrIGl/vkwqud94kQBRuZond8z4Sqlo64GISnNf7Z jsfV0/4EXS0uOtP0JcrfhkfZCIVJOjxQz5hMt8IvsrM5rcWFGCcIKSQPg9nxwMNK3OLUR//G5ppw tb5VwlhYNOKvKXLLJFh/P1xkC+O6D8aB3IFuF3TgcqT4lp4DaCbuqn+rVzok1mslsvj3REj8l/lM nCbNlP7EqDn+S5wXhXu9IJtzmmmVbs2yxBSIcq2f/jM9LDwBJdrH8rnQXcWJVnrqUWPrVjknGoGK irp0Yv16nlWXVgBIKzBniSCBy1RjndBp1pOPrJt9eRYPwnGxubSg1OsGnbFKmgBFY0kBvS3zkAHB FTnPpO3HATdjJRjLaxB5U0z3LcriWbKGYAe8LRrB0rcqk91dogopsqqMC4DIqdhqYQoz6MPNa33K WK/avofbf9nrk9R/xiOwhxJheRIDH2lGelC5cYY960Xxjlv0zoOwgrg3n0r0RFT1npcVykjdVRco XscmLF86y18iRBfMU/cG3o8oSnJaLH7vZb8aDSNi9SrBb2aQ0zHOFDtWp9xZNyXFNcvM2NyZy15t 1ZOTHJgnJvNSIpP3y4fc2/kCleeUanY+4W2FkaPh/Vs45VbR4DuthC8DzfJ2CoR4oUqWMUYQlfWz HWF+p008dlvmZP/2ISkTopDLsRpwj2tKi5/rrXwqhW/TmnP08MDrjHcb6s6evYCIVHH6LHIwQg9l UvaZUJ8VNr9gE/IitgIf7rRoZfQ9EaCnPDcbJo6pEzJWRif7YnO8M6FuT4MTxA4+7RgqrduZbK3p 3dHrRLEdphaPDZrXM/nZeknC0OpTYX84XqueFo93KMPtL9CZ/fMu6rNqnIkBjlBdR5QZe6VGWi+7 S20TPcgEmHHaO298Cxz+tviZPKMNjyMHEU94BLza5VcpHydZsF7fEgkJelitZZfZz1TUO3GGX7PV hY38S8xEumfITbqdmJb9CIO2P+JN1zXXJRpuTo5kYENetUCyrHIEvDaDYInTjAjc5fIpogWkhKZk OfJlnm5rHJrw40/bwmDxQxrpAqM3vtJdX5joC6mAVhcybRs09EREv56VgPQEhMC7sHx0pkrx8KrH wOpUTeJNj9g2GKTPZxqqj0kBJODpO9MxFeWfmAXyiXwzjxPiEB8c+o5e0FEqZRnq+MYoPGMtvB11 rjQaRa0//bK2a/c4q+QDdN2YqTHNHqx+LbRxwIJ1aznjEk7IZKQI43Q9bIMnBfLXQUqULs+HJhfo BPqoEhNZ8uTCofHfjT7qFPgnV3RiQjPeXKoJt9UrJFGscUek3owNdn3ER01a/8yAEKZW1blOyZhj NQXShnXbhA0wlCBLa4LAmko+5dn2ZA2jofKGIBdrPVyf7JHnSMjMEPsU/dboxLkfPsSQGDHvvsq8 glRfrnv39Cxl3oGRC0s5B0M3W7N1N+Jkwm4Q5chLe2ArU6u9F7KcpA2bMtlqbC1gTdhUXx1Liknp s4FAVLTHcLq+Yvwrx/emvcSnW6XF/CZNQ3JG0L5c0+q3PBAIw1aIx87Mb4P9t4YlXACyNXpGcnsm 6It9WRNKA5mjfcyH746oiFnAXD6uFLqDTMEsq7VCj5PGIJst9q49LEEWQfdsTQxINtSvRV799tJg Gnio8bmnu3ccvQEAEG6jpX1Czjow/696lyXVNp3wZ9LhRADfc8+FsOf+wCmxJj6FDT3bSQhQ/g+x oyWhaaeMp47WTLcp/KIVMl9ubiEwDobmQFrMFZXOlActsenRr89BXhw1sgOwNy2k8Gkjf59lFE90 1oc/Ee3wqQ5vMvYwawEBIDucAP4TTvgbGPvbe2h2n2rqSnPNqZIAmjSLVKZfcEIRskgbQPxkaY3o 5N4MhMIC+wrEtI0kN4G3fvkKyTlytwwBxmxlpzWIJjTQ1+TooHQVc5BaWiTUFeQtt8CF86s9XiPK IM7RCFimIko/G5CL4BMPeLlqiYzvBeoTQiXgnLczJkaFqKG/hDeBP3XSErT+GoQOikn6aSnRp345 GMTxXkBTfzdLZh5jPwWwXjGFNaHzVQjBPxf8kd0G+auOa5Gwlk8zcbc8PFSfU6qYVnyOMSR/ZLkP SsBspPS3+pGGVMKwozDsHYy4iPkvYH+4dJIO4yFw18z5EcVDhZSlLZHFFFLIC5Ckhzd8W8kmgan4 uW6LgyJ9oxo/SNpQZNxjsLTuF2cHglMswyG2IST3Eyd8ZUZJoeVt8GqcRzdYl3D3uuLmLWnrxsvj tgwhVxIBuiASomBoEsosWuZdl6o2LJ5nxPZQCCaLb905so5VilG1egfkAwviH20hsa9heUZnjcvu YPh9yOcyIyVJ8sscIN7oapyDHmFZPXP8lQ5ScWT6dfhUiXkG1+mbYVoSFD/DLovgUwjFxhrStspv UkaRVVuJZnVsVQAG57cT9+yU+T443J+uZklIWXpc1xykwt8wxjB7UWZUtqbAuNwj4iVNBJilvfyf ZTKTyeaLxXmW8GiD2wULNFbl3xlxaDmYOD1cpt4NPj+QPQU8/tizk/umBBHKh58M6GVq59vaVPhE hVQ2gTwDtDHNfxsU2ocuC6folykdNBGL2IKAFYnbkL7qLHMI2dhO9epa1Je0qUOewx3C3+YqSVbf QXj8vhZFDF12JM6b6B+RIbu0dckcN4nxTBGX3+BzqYzToBnM6Wxdi3UCYI61NrVyE8auF5IALDiz NgOLTUOGdwQY/6jYsxFxX84Vsb9iZLLJ1F9R780hXgKmrLy/cO8Pj9QwgrqDiIkQ2A5kzTYMKGta +bKO5OkPeuFrftb/NdkUH1Opyqbomq3hKmwt0+AoilYYxBo1Mxz+L6xAkO8Zqi5pDpafiWCp19cE 1ZnQkfMK47P5QOAh100OUOiw6xbFzz+VI3aYCZnHTJhs/LFytb2iTBIzgcOLwEl5bYtZl8M1D+vb P1jXBuX/7qJ+9EqsdcwkZ60sex+yYtORTa+Kyw2HLon9DnV4A/tIMslyg/s8yMMmmBQgVZs5z7q6 7fJpv25MJuqNefny2BT3J0Hf8aQRAiOBnhaTKfzmY4Yq6rP4/1pPGHPP5Ob8RsuRtg/yVdna7bdz on7AaPOxbenCQwsXxPwKZJuR436IYBqz2YqA4WCsB05DkSdUHhXg7D9kpGHjpbNKMBzefxvIaeRA aBVvjbKAocHNOZLaz2uSkBHo8rJLbab932ymqgJrzauwbrpTCw5WuLmBj2N7m8r43CA4a4E1CPS6 QxhpH29bh82jRNDDgXBxDxFsS4WaS3d/Yw7j23bP4X4n4JVC5b7kfAI1p2Tk4wdyb6Sd0Z4hhsOJ atjHrYr9StlpKdaJY9dkwLBw94QL6f2YfwpQNZnqlIXzCo72h6l8zSE4Hnq5A5v1AamHcbheZzp9 0SBxMk4HZlrFA5MWqphZHDxl0GehzZpRbVCt3P3UyBNBZW755nikbd424tes+hIbtTkdBEsEOK/K LoMDVFP7LJ8PLFZi9clFI5DdNVsCy3PZGYFCmP8LvI4Cc4bNTqq0qGves1aW7nLzJ9/R2DL8Tjdh hhEX6ZqgCJD7WkH4JrWcpumwBiChBDn9RaH/lOrPwVYeUoWuFYLMEuLb+BD8h8y0O4d3XCD3UHkw ci2R3swrDKI7M1iChTTextDhc+NDgxAGKIHHV0iXvfdK7fvms40VRCicZPHbf7qp6ytuw4T/HhZ/ OmCGsySDCoSNxxYkIlnH5lkkj5OgTjumoJbD2+AD4RYIzDbdVQwXkHv/ygoNuvRLdUneCvBQ0oWb rMco/Uwr7HWx3KrDmyG2HGDz2me1BbDiUD7tUReDnr2ENgNkR3XCj0qMkAk2R5jM3FiMpeF3LlJo FCi2GctyzBUUok5mDAxeWKca61e/ndYh1dbn8xgzl4bbMxiTsPGjGdct18cH3Qs/SbxhdsLkzcz6 kMoHoyj+hd/Uj8bwmFEjCUfKWL42nxcCpUgekqDMSRI4nYM0f7kibKhHpqDUZD8AA50NkMoXqge/ Zvypwbx9mVVomNCTECT9Ksj8NZK59FgBIxL08kMLZdeJWPf3YRN2+oxfdtML4Zl/fqnTPPhPxo3s 4PwLSIHeLL91JlGQUheJA30qEmTejtJIKxYSSCUTeGL3J10uNDLnN08LjJgpd1ORgGeJrOygy8gM nQIHX6A4ojggUWOWSacj4CkwVKWXjL1vUakhIqq91yHHA8rUmdVrlaBEwTxm4rtkaveny4IXcF4u 5Km7SnwXozAPh4wScwJWKMXsB1PCxs38seEfnu3y2Y+bflx7nBoAwBG7kaWfgr/rc/tKOtAFLmFs cZHnlZwwudEGmS1XfcopNcfH/Ce8h4Swl8L5Z8aS9hZdcH9DGFoqnU++9cdjnvufAKFYo+bNWy9e OJ39Lfub+tWvnStlUHRF6b1wcy1Ir1PCTPp903h50gO4sy8fXyCXQq6QC65IVrsBXm3StghyjxTe 5afOvWiYR9FF2JH/k8aI/5iVRx9JJmr15LKqr/Kz7+in22kE9+KpJWCNPtHAxaqIMRfvvCLEW1Nm /vp0Whm6t6x0wIrRI8HS643HC1NEw9CgXYDcjj26MSmxjLXf0vfN5zUkl5fTOUz23XfY6bLWUlnq sIiO5fQmxAbuR4mI2DI7l75Af5ZS85kHlADWpwo/zOiqBJfTkzAfo9BheAU/OQDB6otAHN9igId/ pNU4ZvuW0LNU0AWQ2wL4mc4Lifj6DZ+SVjnmWl9gmNPOJ47N/bPV/BwMLQQtFYmvlPNEosleutOW 4bPGzHb1LGbTZovrHpcGTMeCicmFWCtr0xZUfzjWt9im3jgTJLZ9KCTJIncSjoIzYOBfDfi1CWJ4 FpXp1coWppyKwzMWuT9wYQbLOLRDj2OpYmFq5tRZoKL41h6lps07rzE8/ZFBYqY++GGRtWajOt0e vTU3Zxm09B/DfJY4IijcTBt2EufcIxfqQ0+yVYWT3+mWyZUBf586pwwBX6EK7FY20f3J4mP3VviF IkGfOVnsZJui1+B2Gi4dqOZnhA8aMOVmT7tZ6ofKUUxz2dY1tkc46kMN5Z6brNKyDewEc3KxcOEn iSgiOjFxWvFJlnRVlY2lco+bKMUixdej03B77c4zRlCf4xEmTQcOIwMFCkYmugOwOEwfQoFeqCP+ /0tZzkGt6ln9rQCvwXD+57JuPt6OJEk5ns/tnX+TTUu9zwA5VSVvzaIAuJvRHSnPvJ/yhVsBOucL Z8fGXxVvjYb4Dsp/GoACmn92ztteQWSoZmNJI4O0ZI9X8ycHtXvDtRuuB8UM7J9UTxb1i9kIGcuM 4lFFM+BgwhRvijX97r2xA9rI8TCHri7WTuDbbM+KWNjLjc1LRZAKNnb534Ksp4ryMpC2dlvVEv/w dODbivdS+j1pFzGrbdezN1E2ZYlP5lado3I9tHNiQIALUDbMWqSmQmIt8D/Gbx3W7mtXJEyUDSv2 +WOpi5XaKWkhlAkBnxzahKuRJan/iiVA/IOWH2ou4L9HP5zSapi0ePfVq7+bZGkv3XwZ0APXk+S7 /N6tCnOKkLLzPhBrCxMzq/ykSxI+fA1GEkLLInlx7ZpoYlXVd2/vNrkNfvXYyQgXuQPgoGJGJ5fN ZKo8Znwdu/2CTl7uDxx1s0N9NHGVSo1g1gvVYLCyCPGTwiPRRSKe1ccCp2A6kBgR9TU9piHSThfB SOzIwjNhfY+CtsjoADa+UlN/iaRjRw3lA1usY/dNOJiL/xAqACd33AR3rwjfKL/7n+qKVteXyOgt P7+5rn1KIalgELv/d7IyBQ4/2rsKffObk6JEde7dvWRAadMAZhh+6I16v67PVJofXqxTp+nLDpSh ++a9uuiHMXpnM+aeM88V1zApOhwNMeCJaFxLjI6GZmCVIriXUVO9A3WtyjJGfn6V+Yzy8bYVd5EE +zN8fI2nOI0mHFZVqHkgs8/7CnW/+LPuMyq6NiJ2L1Em8HSd4j7S0B6OClUu/FxF5gz1ls4Lmll0 o2phPzq7h9XI/oiDdnhtP5NVrqtDR1e2auHaTRdVwGYi6R5F42f1Ctx52exIfJWBcdCuIolCeS7t F9HprX9w69PjtH7ipg4sAL40DZQJ69Od5Hjhsf8ty6X0h87C2YEsQ1PVMB+Kb1iZOkWjfE2kHTa2 llxIav9/+TH807hfqgq9pfqrEUmyuTnzpuF286XJg95w1C43LTEZQh5xe5miPtyqGSV5KiUHEMoD QJCM7U4Kb13m09XwpRMIym4o4nmZgC8jKx+NsZ/sBzndk4Al8R7deMonG28x5MN+f9WcvtMqoluu YU4SsYeO0WmkJgxgYngjNvMgAz5ktYO0kEWfzwG3H8JkcdWMa3sb3MOF6OYiIvZilIVgH4fYRmnQ sCGfVqtwgZc4ASbd2imX878qJT+08hJ42OZGF+KovzDmjM6WAmibzW9xqC9aYTSMNXlvgvmCQSVg b/0oHfkzMehlOOxCFo5+G2z1tu3smUG77nekxfoRSEqiTDE7fNPq+m0XAeUIIxbIYnpKJhIxM4Hb WJwTZq0njC/BTbFvwC4C60hnolFWZufVVUwpr50oAJnJrPUn5vo1I9BgtXt619iqtf/018PGf61l N528QLFlrPPByPeZWVTamMr6+v/cl4+t68HsYYUEulcNFyxxSIrZFE6wE/2iB3NvvCmLkTduGYc+ oCINUezs7o03DkZUjKjkemVumOttIfXxGYwZUWWBfCIjanC687f1WPug9IxNEDKOkfKJTBIkFHV8 OWHv8CutNU0lXrZ5EE2m/amzK2OZysjTZDvK+7L7ToL1G8Ss+I8cWDTRRVGKR66bDth5sc2je/fB 9Zc2joQvOGk99Tiq9i+DZLPGSN6fktBmCTjXlOq0OpEkbKFZnINVFvKL+gN8yxqIA0XAQbKlKAP9 00BlcbQ4OTcfOyDQ2UNe12p1eQNkzIVH1/mYOmEtWjQNiITVXabCB3HYbFbwACZgJjJgDl5XtT// pNO/54XdXnmpKKlLKCIqDh8tXxs8cQK29BQ1OpNzhHi7mZbPE2zjL8eHCGm3L0mHWEFO45DDrtt+ Y3Gbi2LXd1jvPGX9hcH3HbWKSfNd7ReTnCuUWoMzUuiR36KZERZ5J0oB+6pDjHhpNZzCZWgsb426 mMv20R12mCwPG2PSJ2XlERt4f9pkGZLIpJFowEXGKvYbYLyHpcrzc3OZRe754Yh7723rFBlu86RN rj9wtiPMRgrxheq8runfq2PAYQ+KtUzGFiV45Hs8T6Jz+fbE8JtUmeIenW5vis8sk5xs6sB14r7f PAcU9gSv43VCFxuoG2bW+QG8cffFavGb8f1yYTpIjffr3R6klTuRKUR7MbWiUhHRIBcJimfMalsO rfbpW726AKSm1L0VgfjincHkxqzb/Oyp7LsnDmcoTE7It71cLdo1PV64j3SDqhNKif3jXWFrWqNs CJuk26ZQWKDVc+lvpKSUHOhOjo6ZVJp02nKbSK50q1u9Fyie/t0Y+pS302OP262n6Cb873aaRWnP lx3CDKVmw548mEuqMeS3/tTqUuFtpToKqwvnfmqwKRa3QxW3u2kYpuoY0PrzywGqwwm4zbmI2MDG Q/fGYp3X7gXah9kPNTeCy7/oeY4X0tfbmWdT6y9r1UcL6dRlP0/+19vOqsf2bmxMhMiz9CllWh7s ZxTIPQJkkEzDNU0GbKb8uygACXpqk39TxVbt+D1YeoaFlVUD673uXCuO7Q2h9/1zIUm9vMFDpjRb jh2jYf8pyzXGsCMzKc6Wv8uQZ2aDvDDt0hy6luglFAR7FzPazy76x8kw8lt1f9HgHFUo06atwPvl bkaE8Q3Rtd1Xo24ygsuizb1KMosM58R3Lw2WFT5S+Ca4QWjmd7NVGlLEbhafJL6R5bwniBiO1Yy0 vJ4l9tGS5mV/DlXPxbX8lQyn2ps/98+F0/55iBm/Z+qBZd79BnOwjR4IveNOaHg+eItBw6yaKF0U OmsRfvRYyMVDkZQOjc28qf1v5ZZ4D3Itm6rQ6hlSrcQzejOgMAJCdPZI1dhCgl+FIncRo12V0r2Q ebWWwrS0HeAkxh69g75xHYUKvoUImygTlP6KZyrJXkBF8fmty9l7Jif3nFK4FRtt5iDZbML75xbc lW/OK94s426QGf3tXYDMwtKcHlFYl0fnaqlbt5D1RklXci26cGSbbXI2kLChH951Fv82bYatNnvV lRkmIHRPfurseYRpiDUEfNds5JEZOK8o1ge8fSgASzQp7uS+DUR6LvBTBvbmMVYfkScj5rVtr460 qdZ6mz2p8g03cumh1QC4ycOxhpTshJDx/txZVKcjU/2uiujEhP4z+b9Un4oLjo4bMunJ1aYgD/aV Q0dZBTKDDgknZrwP++wyfeW+8vJeZ5uxNIu9yo9YogCwPuyCeJcX93wRBg978oUnZqsX8RuwBpBa IYbheIR1RSHrqS3Ix5bc4V0FSH19V8L0cj1VG3HAR7GdkntcirieGSqc4IxlBIFbWishy+c52ZvP VNfw9dcMlLjbh3DF8NQLL8Weob5YhbeeI1OjxNc1MJIdwQG3DFxm/DqGA1wUNnM3kT8ZA/NOjE7p 7sxFgT/gUm49sjUzPVz9aHLzTfON3M92ukeDAv15haHv9kp8Jc7dvr/t/TqDV3B77mppAR4NgAgi Kof96Aj9bA2mZXNPFtrlE4JY24GD6UMFUPAxX/TAeGNNq/2mHMHxc7B+qBMR2gtX5ShzLlpL00g3 SyRqIjgqR6n/yL33v6xn52FyxhGVJeUT0ifh9VqqDLrqDgbl23kGxzBnsoqA8QRBBQR2Xm2+vH95 ANHrLnTpBOz88DAX95M8ESaziBLSACogxep5fC0TZ2wZqCrUG8iWgwT1hzSUzgTfVpHy32g7snhO rrSWzQf640XLQIndCXvmg9VHZWNXOwGs4I3KVArUDkTVGOI8XaBcXa4hLggWtoQRupLe7kJJj4hK 2H8163kHytSFQBx/sX+i4Btn98CVTLKbeMBRLAwuMVVUZlbpC3V+zwIBaeC3V+Gf6MmeWE9PKgyL U+p3MAdzt5l/S3luAUpCu15rumQz5KFkDJiB1wkGDid074r3dGRYiGmL/x2E+3G+8HqAJ86Yz5pR 3yfN4AIp2k54yT+ko1I3tocW3Fx/hVvcgSgv74ScPMInUfzop1M6daEx+RGNZxE5PXkIGQNbZe92 2PKdy3oYUspFlCi3BuzXOSjwZncBgj9VCu7+tfDOBCw+XRmrlFMgmJ9G9TONQhex/6lF9QWFKllb NSAM/U7AXmjJOlDHrz9LhTwTPbOk9n7bSKo2CKh7iI7hOvq2wi5y/NZoZ+ESgJgl+7cavBBh8JjP SnOruSr6U0Isz3Xy5EFuI6ILZJwA+cEChDdAolbihB5BbS+OCW4UPy2UX0mRkil9zn2gi1uAImyu qk/Agvv4iK1tZzoygA6sHMjn2urxMuOBGZWU5LudBc1tO5rQmEKIAMIhcoeVr4DTe5s973IA7wtQ MQwf96/FuOjeJLH1aLt2jfOnE9XOD2taB5sFWAG5IPHVTvYUZBvbn/5wgRZZaY/LVX8kRhD3C3c/ mSlzwYyqMw5P6Pj9T4Jq0OZcdC6+kyYGSbjmWi7GtiQZG9PeRbkJihYZDDPmj2FVOekkDmH6X/Bq Qu5mJWsz0IkQQJTIverMF9QctkQRrdIoTWSo5HopevwhyR0/yjg/KQbT5piUObMUdaDXsPouBMeS 7dgAkP1/IqlVegg6B87foFPy6aYHPqXEcEcS/b7Kpd5kAjkQASM5XP90h3kWsZ9hf/smQPInhE8n ec+7AcL8bkV/jKVG0ojub9lLOP2zQo1am+yANT2L2sAhW6qmvbvpGVVADCzNY1A8fbFPNlBeTYwM gjPVEGJNamDlxq//ZgKrEpoywbyA34x1xR20NetvpH56NfrDQijGmxr+hsFbPEvi3hkjb5HZbzhh BY89EBNKG2g9k5u30hUdpfgZQIryllUWwHxef5QYnfv2+cuzMvpr4m2H876hKhS9le1YQc1m1wFh iWgB8+DYVzwEG27tkvmC+HMwSoHgWzplLefAqvdSaVtqQXJbBT75XaeL5UIPFlgsELImbo5oHWkp 08NLxtKf4XOAQ9Li6K6ELSXAZFeGOanSAJSvoJl5NZsD76m0uN5jNu8tO28iMBDafbnXGNRk+Umm YYSEfsTzcF4d6pM1weWMToayPjHQssftV6610h5iH+m4IkdX1ya4BygV+tA9cVLjRG8CKqAS5YDe NzPpPQST3X69XNTQeVQeiAvvNxNzaRfYdmIHfPvSdR4v2C7qVt80I8/ta9tZiXfPXH/nKu9+8lLl 73s67xUlBwrvoQheYb3D4RsVvi1lPqXGqjtdphpcHctG/0zbjQxEKzm1yISziTZyH7iP22xcU857 QHvEkbsK2Zgi57K5BoQJVullhlAPqvkiSzv1R+TxyqbXm1y5rdWfl8FuPgU+FPVyztmReeCAfA5y PznuulNl71VYnNB6zNaeUj8Ff+6bh159PnDS5O7zEgVjAYHanDfKHdFblg+oey2zPDx/FMU6VZaY F6JzEx/UOlBBjGAFgxAzyJWmsFZSk8/erN0jqrgwrZVzOncM4VA5JmEQiaRRDrw0jLr4CA/XVxqQ bZFTPb7YgBMXD5uxylZl4bSiHeaTM+Jfh23gPQjVhvIefdeH/68f6UXxv4xEQLnxHWiNplMzErvM 8z72gIqGmXDV79rSC+v7yD/H+QmEXTTEdRxU9k/pYQKylDErhBUh+h418XOlg3IX48g1ObcVE+/q c8Ys2ZMHlDoYrrJ9FP/fOEpYV3sn3GLafFKtElCuxzgn81csIMdV48U4UVkse3FppOJzJ+TvPzDn ZRklFSeVbDiPmawOSJ+tSVc5S7fuYdi/uORUzhn8BWByKabU1FITYyvcB72uF0e1E1oVt8wCvSea +0K+ij6fsFZZoxWEOVoBeFWkRm9Huy/laOXc33vQNVycLGO6Itwt6p+DzaWOT45IBSdtHafqJtKF DCbBibgBAR51DLtW6FzyXIikxlKiGTLs4jZ1j/80mOrcYCzBhFHD1oZirI2l14N5G7YAI+7sh4Ur Gb06hG9YB4JrH8GMAla0krqK48EDvQTkQqmVEUg995XTLNJyFRqIKJA4xR3z3Z0lLhwBmo+lTkav 98xORnrUdj/0dbS8/eUZWQerUsAa0xfizI8LIcyqOoRZFMnMiJ2zYilc9tqaFZKtXi6cwRIGxtrv dxawvaXmSBqGW1LBraPTbON0C/CImHR2fLuLdwS+npciP0KoR8rzprDTlQZLuumaHFWEgLvujMVL vOS0G7ThgGnDFVF3ZiOImAMqw0pI955dQZalXlNiaWf57hrgNzW06wJXgiAdcSewzxguzOdqjdLN Of6iayDQzNuK+e3K+SgITy8mp3ka8/UlipmVa7Ti9yBPN0pd69taTyUTitIee1l+dcRWs8CR77js AgWSvYBdNlm1sXqASc2Ne4h/4Zntx7k45/6A2d9JDLVa2G0kORsZLdFE0THG2hoat/7jY4dKQw97 ukyOK+lcLUABzCNYp7h7RddNlgrCigmpgac2E/0g+UiY1M0L4+wKaOMboGwAsAlwGukh/xpUpS4f ZnTBiC8mFzITLJ1zV++p8XiFNnhhrmIOXKHUDTvFtKxTvmOiAfp9c8Gg4oWO/zqNb1PEtaUL4eia ygIw1qRvae9GO3jSVhIMmCzBPhNd0ETQyXhA+HBdfB/5oiYdQ72L4Vsu1k2OTqzwwR4SZ0bHIIc0 alvDmn0AJOEZkC3TxJopiyH/VAQMWcQ6w/fRbRyqMasgs/LDFpZb98clt26Oek/qGPZt8b3Mszwd zP1VH+rw0/uQiZaOntkzDDlHZ3Ejr3pxKaFG0g5sfd6Gwnbk02K1CxlUVCgS1JZZ10Y/gLEVZ1bY zo5TokXi1r0XduyO3EMKESSnVTtMgej+2R2kpak607jjLvoLi4A8j7Gd1MAc9JnUfBnpXlIdJgPc AgQMnNXSWWelxkQSXdcSW64nLHYVvs5zFZlA2MvQRtlrdcp8EgZcKOGy+6YKJaW+haQdxcdjpdSB aezaYYofcwuWijAevZgNP0Vh32IKHN9z+7klRur3BEe3CoWV1ptr8jZe6U5FWxCKa4lhgj8dpnsd ThEY9DB56R4wFntujvOZuqhVD/m+Wx1Hx5cFDpjBz7kftzEmgYbEciwX3mnQdA8xqJkLKL0YNOdx o2XWtlMgjX3XsHRjCuWR9xJvJwttv+aQBZqMaAc4GXr5VHE9saw9otavZh+VtEzNsewMvkY2qEu5 +qxat8Ebt33XCfWzc32yFWb8mz1yLsxM6QGyckV0ticQB6jMLMdCQRmunabHl9s37t3WNTl/6AN+ 9YI9hWqZIkJtSzEhf9vkKrMzBF5oKhJcETE5Bw2iqumEgIjEatYQIztBISZtqIqyBErrwbPdXxuJ wLrQodtX9meGUNHeVtDG8Iae01vjfvviPkx93Kef2yy+l5iiz64jlkOIIggbehN5G3LPkpoSbIBu EYzCJizdPV9UoJAiaYP9PjiLTM1VmN+TeDryTu1vd3j30iBWYkf2uLbCj0+J1RextIZX+5Pw6pT6 3o9uJ/jOm4F5PckAoxa+hiDyL5hirRmQoCuT5SJx0XeQvCrh5+OpPbQU+ASv6c2L6D55P83VgIxh qH1qX9pctzofY8/V6g/ZAevljhF8Wo4CtL49lJxpMZR8eAdNWBGrgy0tAU63bs332bTilyq/d9aI FoZcrzz+bMGW21k1IC8pMH8yLmL2/LW42TQ9cW6Crf5O0soYk4oS+HzecAxX+/+3MG98Tj7T1cTD bbxIOaur254SNkZ2hFXmSYPnc4LwUGBt/S7DiSyzAh/EijqE5JQ48OZZ/DokKpDKN8Q+XUgfXL0e ojHDl5dKOXyVF3dZj3ijbaqIYjjDn0S3kUUwt7bl4lVzJ5FbdBsByzFbBKtoIl6g3Zilppagecc4 pZgLF8zx1eR0mJPttlR3PkGMajxj9IGnyP7/9BMVGRbel3/FcvWOAUVXAPbNwsE+L1BGztxkkFfk rHEgdJHmfjuqXk4DLuklYscidcqQ7kniLCINRHC7cGjAlKzB5GsY8pm8Xsyd1jk76Uq9JWlPlnHF pEoMdaBAhqOkdokdv0P+NQbNbknCnhUwRtDhmGBj6kOAPesBcnNX1alb/Sw+Y6OYuypV+RXH8AUT wn7rfXcjoysfootnu6jHYzRErKImZE6iSwnNRCqpwT0Nz2dhhVGJcghKaTnv1skzoSy1BC1piRPO wxGeL/uZId13a4hlqAg2l8YrbRawevk5jfWOPltwHqtnUDxtLqB3/fTPtZci/RBeKQ2lXT6reilG lMxUsb/PAN/CnuxGZW0LhkwCWvKcvQZmImrIiAsVxigqoaUQ9SJOwyKXEuG106AAoQ9s6kDIl3Ay cgqVzgPwE0+Lv3a89TNDdFqaKijHfpdUyjV1QOZGvfXskN6ub8FXg9aFcyvwuuSy1OjG1JX3s9jO tz2cyqyuQD0oLZSn+2H2roEadaQw9aB2Isfmx3hqKjNF4K081in8OwSwGmkxBNCIzeT0fJ8rN3gu 4mlkEcaNbecLdLP1NYOnThcifjQkRoA3Tnm797IsGrrgfP89f9XDaDKSwdqMG7B3pV+fbHCmYL1k C6hj5N+8jZXvZcTuueZPTf79xY1ef4dk/T+bYfNT0rrolZZjadJXzcuBlIfBQEUM/Mi2j6hg9Am8 dmcgZg/gKphu2q8MDlW4p+IM3p9GBiXgGzqPYx/d17+6aHhbjSv+Y6+bZZTMeRRKCP684Kl0RVz/ rth+hCqiF37hsrUwTX7tYv6E1KqYuVVCotCg81+tC2QbHfglqSfO+nmMC40giyBrcnx46miXrHT2 lGWrchx6NEnRCYj3mXBVJGhUKuULj79YSJwYyku3bRKgG9QlvJ7tZwXHNIW2/eJmKUokkzQeIY6r Gt9+5kfLkG3YcIHt36ZJstKDLv1QZAbt43tiRIBT52TGUyBXciwLzAMEwzcvtBg2cCer+GS+cUEc HH3v0y6JOucpdnBAFNwKqy75mSTOrEjlYIJ5UjztjYJcJT05/Hr/4Q3AI3DDeHFNQv0tOMemY0pO xVMiWfBPbU0pLUn+5HQtUYTDgzv48aOtcsEbVcVTn3DmQILxYuzfnIolkEkv9Oa5fvPF1zAcSLeX 6HxQLSpX1Bhg110PHSKP/7v0ZwsYhlx2Gt5UqhX4HJ5tTWIW0/4GxXz1nbfiG6qK92EILQ290xJy yavd1uLcRWWRrb9Jk/+o/ldGkDthUZtZGtSgmmft+ngZaNWHk7seoUKK1N7QX1salJNYhTzTN1TL EJ0m8t6hlh5mHIblCQYyK772xEbenbKFpQPB0VG7ILPTcbaKE8WtlBfaIvRxFK1DH1w5ybXbcM9Y ZCL/8d4ZrCscjswNr0EHqdHB4zypA4eYRGBRk7mBJkAW1aFkPr4T3X97z3VX95IY2yV9lSYkTyKs JATyiDEq4KDQSDe2MweD6j/K/grdL+rsbjy3ZsMB5o/4X93XaA1PFmGPhbot7e5d+dqrzFdFh6Ga 8K9QvI2t/0p9iIGon6+fieEmzxM7X8xVvViJiMs+A6GlqK52cExBy5oIw+UM60cq+s34Z92NHbEs LH0ZWKt706xhD93rMvgCjowZjBHZ+WpErb6xRnejgBJu1h84KK3lp4J1SsBh4v2v2Q8i6vtMaCkr df5d5QV9CP5NFfYFvwqBBklItXkDmRI7tkVF16kFaax3CBiGfITaHZ/yeQTJcJpmZO+qH2gHPAQE bu3QjchKs1fk8/OmXSMoEisEEGplTMEYml53Ngs4FNwsn0/Gqox+AsKZrXXJjMpyEi0KQD7VwL+3 REJB8/t2IgqPHJqr0Jxsqyix1z5+00Ze1aWJT4DzmBbP04+i4m5w3C8kVpAMUf67n1TYcxfWNgGO 1bY13w35TwII++mT89HzUGMyb6YDJL2cIqRZwCdleKM2NjIDWpqMojebzM6LTJciHFetuwgIOFBl AnNL2Mlsw6bg30y1Z5lyLN+ib0WkzxRGwODpGfvGt+8xRGli9Ok+3Y4AfQSSVeL2yhuQV5lV6K/Y rtXhI4Ez9IOLL1ymRPDMx3r/HGDaeoWuF4Pvei6CygU6XvXN9PsQYA+b9Z/NcdiUZhwqZheUNa3n Se91rKlRb7proIdG3PsPTUf34HiQzD9MxNvfQpq67M1021rXEKkiMHzBc065xNmYF/QLExLofjB7 PiuLB73McXNCxMVZxZW6rrW0XPGsX2+a5EE+kEJ4T4he2FLUunuzKJoY0At81q+Sv0XJz3a2N5h2 SFCm6NJ50Xb6+YRuxe6AVf0aFzhXqPrFFjsVQqDMYqLUJKT1WOTjU3kStZqld/MvreFMzFrUC11y utG0pON6BLX6sNj2Ro5XRr+7yozAhK7bPlZYaLKlyfix+kZZGOXLZQwmtqCk1LtbAEi2zszSRoTd 7D0hhJ/6uGGhROAb/Qcdn7MMTJ+jIbGk9/jsFsrfXIAOt1hW+2jrGrPIhEOfD1xQJc1Nt2yRXrC1 icKdbsBWULN3G+dwayhr1R7oiZ90ceRkQK9u7tKdXZuCLs0taQj315vvwG00zPxpbiuRzt0Stnfo WrBLe7erSMtcZ4yfSGrGc2YKhWgaBz7Xgndswzu6k5C/nPh9YtxYV1YI8KghJyPVu5rzCt/L1Kuy kIfUMDo1nIAQX35S5xL3QxW+0cndK10rA6unfydWXqM1QNvb+eTP2n7MsffMk4mS7KmXfodu72O5 tU0qKVkFztu6ePwhdsogYi9ZOG0l1M/5HHDtlkn78gGXxC28FTprbVBeluZpZrWZPdybOVcSaLlR 4hxifW/q7Lq1b2pcJasz7bARrMhfqDt/wjZaY/S8Q/xpxyyDMfv6MLkG53GGOZx1nsQ3XNXiy4p2 /+LExABXLUhp3rSbhsGk4qUMiPEKT738MhSgXXtjkjmAXTLzrjXdS4Ocxr+FuouHaXG9ilttEUZE qVgzMI0ACf0RJXPQURH5nBp0Yb056MQQumnOCxSbAldCpxrTerDdWnlPEuE0RV0yAspwKI/3qChk pfRI7ZYLSmDBeLmHQiRsRjdzht3PHaTXH6vW88CGCFFeGpfiAwAZxuDhRx6nvN5b5Kcx1dLsu+13 NCZOHYzWnM6qCVSryT9wRDaGHFiINdrvw3rIZMONvlQP7CSUEzXKHaRnpM/9Y17k2oVA//H0Igyb UPc9jsTaen/0+UHeBJkMO5plGYq74S6XEVHd49akd0FWzJ7XYhkxMb1v37um2TCiU915dBsC4amq JSCJ3b2QYjlVEtKHwYC2QPQkyOyCLhyo/wfX/ZrqhGfFYuuR8UeLIffcgbykSVQUzWuARleXyw8m xVWnvRIlYDRGfORYCpzVssQQinsav6EjSHEFdXC9pacncBat+jCJ8X1CiJC930r2aNbV7i5lL8fK PiqczzdVLa0BRWN4rMyvpMahcHWZjw+wJ/X77GUSDelEqyLZKiRzMSaZCYlYHRFK7qR7UCtX+sc6 +kKIQkbi49hnI8qylgAY8zM8y8aQdTI9NTI95959tgXWnlFtoK3Yo0+aat+TmQNkQgLmxPNAJ0wd Tq9K8z8cV9ZnL1tugK6pQ0tpFLRKOnN7veWzjySIo8qHfKKCwfC8RnfLw8ncHT55BM2SkIp1BYQY Cgu8AGlL+0QbKpepBEY3XoWuJk4MuaX3rrIiikd1Wq+cxyVsGolBydW++G6dlN/WYIa+FA0S/H7F JpszuZzt0+1Skaa3/oMBKh07jY+CZsOSQkWal+2Dr0VWHdkO9yffoz/cyhpkHAZZ/uy0QjmSCLIN ewJeP8o5q9W96e3Zr7WYj++1Ufavwo4OcScjlYD7TSNohp3jwtFmbusw7THUnUY6oG1llFaq32en UOeQVHG3HtB9obL8y0p8kOEm45lPthd58jtR2nnCyGlWyyxF3IGiORhqxGFGzcYnGpVXMFn7f3hR ZikCVGe3/0zq+XNrMqB+uBt3qezOi6CYJNw/8EqUxWhWccswzafBe/lOK5+gfMY5kXvATAHjEQTd YutIWs6dqzBWWyFpIkwJ13D71WayKBUz6Sm6NNrcVBCWJyOFKzawxn0sABUHQOaKlBcfkfknTuKs A8T186VyL3AQOElAgrKt5016Z7Abv694vLm7TbbjjV0utv84UjXjux9dQsanB88+wWi+xCG0DNwk foSDCLEABqDUOmhn8nbfr/1i9BDUVtpUDdioTHWogrH6Ro6wbGdtDlmKpnqFqYUyPFMNBWBP/bQv T2lIwZo+eiYFBJEWPQWz1tX+fcXe8UKNJ0ecCco8UCPKTKxw0UJjLEv1h/lLG8MEklAUka0486DU betn1jkco2/5+KFgUbXWBKtSujGmH04ynXW6v8i3EJbHwAiR9VaOAlpoid72TaykqY8PtaFJhO8Z 5iV74lJskmPyVIo/zHX7UrnyqfVXhGj9RKVVJcwo5Fp2Q6FGRROUQTkkYPES/Oxjx4Z9Zu6cmqtZ Tufss3qHUZzO25faHZKokqE5hzEnb+rw2A5xjhgVPfEMhjD1RlOUzDb5yGKo0YUidDOkIRfMD97/ tvCjmUKYZ90RAT61o8ULrYF0jBdKrvoVRfQr41HmMtUu0hSTzGoIdAV/1DN6e/KeDvNdGCebMonL ZfGZoBAD2fiHkCAdT0rQvjxqAeDN8Jh2sHqAA0v5gzPH3oR8WYnFbqdusU6yez39z9GIp7TwT27/ JErf2DN7y9rk28gA6zRRF2IEwtNGqGTTg+AJhucVyg80z2BmLSfJcyngUC1J+1IaUlsUqHQSrYCY DCWeZqnqyNZpEkD/5M+Bie2ucvzh954OKmNA6CQ24J2dv2BD10XSkKtM/6BUn8lLMN5oJ+DX/16W h1tjSv+aAJbPXF4IdpG5+XTboEu3tWwi9wsapWwGiZcXLhiUYxkwoiA53a3pMN4PK4rDKyyGice8 /UHoO3D8tOLpGpxa3i/DBgeEkzJa7j5PREh8jIE4nYtAd16LtXa/C77GJeeRgshXxGCvvRIaaWWn Npxih5CwAtXUlMYaoPAQzWibVsSkDXdUb890k32DoJdChOfQK8aaeQbqBiFXnJq18ZpgwOvV8pAD Rdvr/EXctrOCGdhtW2dzZ8wKAIFdfqPyLRx0bNwyegfwjexZoPm1oyeVLGN0rLMJ3i/26TTX02fa kr4BNNbd1fiP+Xu7YIYnNrtvbYjzyh5twkkJxnR5c3MXb0U+TaFwmvSLTX465DRXqN9OT40naSBB mOx7byzETjnhwSaP7SpgNoy9LdUhXZdg5HbAYKGvAyoYUKiTUUBxPqbW7ZfeRMlA1+hjrMh94bvK l8fiafV+/DHmvCaf3RAoAc+FsFXhO0Fy1Ejf3z2+Ns4Ezi/K72TzVbtka3e8vtgmUmAtFiUto6kX CPh6SPlcSQcFsUY4BOAVEoTv0sqdv3fPaQz4ljJcLm18muNlvLPHGm0VX2cqKD5VRyIkL++oi7OC 9eiyj7b80zSg1hDzP1SN1wUK+k2yYD8Akrk1NHd9GZUpgPzGVZKXhOUobvW2niAMLJSpJZtQG1vd BBaCl5Tdn6CFVtlTD1kG8sFs5DbI/CmuDfvQMO4Kztn54aUtQhTGE5QehrIud3TtuTOWnuAKc/Rv Ctq161HqdUZ9Zkh7KwnESgAUF2NPyl0uqlcwr1Sb4noGmCdwpWvQDWPRJllcWSOuhgzWtTWlmqIC Ysl2BgSznBcHkAXkmeDkJzxjoMSgDY7Z/KpudufHm3lrzuaeg/z3A49yJIeFElM5zd/wtlhHBxMf G+C+jVCD1je6jPmmiyJdvOmAws7Mbfyz/X/NPZfzmJKpLnAQH+nYOrjAAkSzyFxeNNj3wgyC3pKr kFWYcFkGBmvZHOZR3GFmgRLIF6kZ/CDgeNuDMYTzpT0VyNFySD3g+CmiWDlFzZPMSgTOxkpKUr+o 1ivl0ibZwpbV+0iAODcxpoXBQhl6SGRMISg8lAJ/u702ZqWMrpBK3VvycVZ73AHmSTJVqueesLBE xJAiviZMDyUsZpLc0Ydwb9KWGlqyh8bRbBkGVidW6NUL10GkBb7cgVnsxQaqEU78H8KZrc/39RBr zgm+UWrpA5HF0cZptvTIFMhzyDrkvStubfDDPUn5SKZFYPQRC0bKgcXQEEonXuKGDBZ7jL13mx4K Ga9m8+d5piSiblI7mU/tWU09B1ZJ4pg51Y1YSa/BtEitM8m3yaVC0HXWC+hD+weWC0gVmEt6fB4k B6Xo7t+DcLbFiSu8KUiCt0luqpAPirwvPpQgmQwLqZUFN1Hk+wH2COvws5cBwUhAyfAf9SOM9Dp3 KSVwM0NOaZEV8hDpNSANSNGiF4RVyOi3eaxanG/k4eHoBsqXLxE47WdlxX+0o0B+DROtVEAFkUFZ roFDQXu77onItAc5AzbCjW9JzO3NselJ6pqBHB1hAYd2GnWMvHAG0PbEdpzyA0QEUU1391IPXOra n3150g8Vbw9FnbAeqVTRYQYofL8+31APct07kENCbU9Ly0fG5lhmlrJzE+6aG7jVCGlu24ifSF/n MEcj5GqmhWAkFMZhzdxEiUn/FW81mM7ZoKdvCuUWuiCa2F/t9Qk7kGWIml4/EpREeCD2dqek2T25 OxFX+l9gD7NuTsHaM5T8Tu0OHwGtUVir/gdgPV/MMv+iSz/PRgWzPD5JcuzlhCwqePFSheacBZB1 hRQNOYx8DLA06eu48EEMTBABVAlTGI7O1Fv2tFkhmKhucMk1DnKFouh8FHr1344HfsXkmoZldla1 jhGpQBEZpfW3NQAonB33W3EeAkQ34QrFGg+DI+y3TNA7m37+35s7iNIciEuBjYpsCH1tHvOCjH0f /MPuncM8q+1QaIv7g7yt2pm+GvqVpPj++iHWcI4aTnsw3YGbbM0nwDApbjxMGS9duC8bmNv60QVn IIBf6jDuQ7Igpz7bc90UZl8bQHqp5qCPtKYx+uk7+Y4uFuFblQ3a8Tm6Fhf1uvMhTsatZ1q2CthH qiW5kZYQcaSVScaleH++mVWMk7JdupH+1YJi8gOZEj+u0syBev+3l7Wft9RJFbHCfrkQpdqtyInC iqNFC4+2p51jfQ+fXEYO2ntTfs64X7jkF83LA/2jInZssEidY5sBAJN0EJYbrV6wlN9BXW83/uWT 7dLQTYK1kiN+V02XFLQmpenRXvsziB2eLlhLiPrVap+wB2dDakuBfeSL5oIHUaxJpVz7QTIRQ+tx CSnfyzyJ2HkElWObQAvfSA5ia2Sa3NbsKpzL6kRIGkajqZClXk6oRxw0IMwImbkAJQYnbZdS5/Wm KgAP9sUEqpVgLUjmTA2i3zMuG88SxlV2iwEo0DARt7KxVlbSf/tcVq3I+LJBqnWusCxSFbolqt8O LPEuWJwXZMcfQKhU1bV5YfxkKss7KYFC6N6P1ryaAZXrRlF2BloPsBNpi58wk7sHAQAZRd6MIDtM F4HuuXLhpa0b56cyY9ebSeVtl9pSWQxcEGHp70tOgQcTM6Hm7cCX49HUjodZb4ZMTHil5Oo/nMXA HfaYqFipkqXyN3qpdPp1e8xQlVvMkJ8chMaUr/EJ12HfXrXjE6tWgIMr0nvPA47IRXto8JI9kkUY rs4O22VGVfU6RXl6dTQ9x+XkNXqZWBfYVZhawzknaAx7hR1FRh7VGAoehd4aVLGnJVM3uUrgacB2 Kmci6jcILJWRr2p8eNBLY6bTIUnAxk0wmiNb7QDq5z3d/yN3O8L8LQ4t5gKNHcgOlQaCNBqyVUb4 N3bi+Iets/lpKkWswJ9TyGaIV+TSc/YGIE69orHSXERNB1G1qNjEJcc1IojlKVy6I1LkzODuCAO3 911qqM5EmWB37lslN16/kCo5XU9pX6sfNAmCDWWqYDp1twnkERk1jeMUlfhK36+qC+GRYazF79yl ZX7z19dm0mm1C8rY8YeKh2BkevOqGyHo72WydXeyMo2yC91rX+5pG7CiVPeA0dz3nVBJlH9pNV1Y rypynA29tytPOoHCi6zbCdMz3LxQ7mzMyXN4JVOlfgUobte6K/13LG18GIOO/M967JwO0mMWRWXm gdJHZ25rdIgKgaIt53jANyfwTePlScVmClxwGbkld6ycy2/IOfDrkh3/36zwhMD/UXZCVDWrYhPR AFy641zZlEJeCp1oXS5YAnXBMXX+YD+PGJpchdYlQyFzpOewkdec46+zGNX+v9pIUvAI2bmNtpzA LgF5XBykM8UCJ9c99Wn4SqWpBBw8ogAfEOshOlDMYPEGJt0WB1Pbgjh6X523Dk91ej0oLPpUubL3 60ZVm8NZtfLNqbP/vMPAo5QdXzceb3FKvvBY3UaLTFk1s85ZsAv4f5v7LtsERBcGJ+lMiVssdffi 1RdyTnYWkjjVA4GVXbXZJDNN6RG7wOKShug9KUQjW4840wE7/QJbOXLMOe9aHeqSE+rYJttylByN tM3mxVtsZLsvxQO1UuhEjx0dEMwaTA3tT+3DUyjc+Ka/gbr1F+g8dko8gHWRYj9L16VqHdFQ++Sl kaDcTA71jJozi/w1Az5rw/1/VKm8IldCsgSZoxx14Y4rBIkAR30abIkmsVb8nRWyu1EmaUifEApG LeTyhmPOc4IuT4e557OaVZtF8oY6X6H2pA5w+7w8t3ZFTEeU69JGSAqsFmwN5UJb6bDVBDVJ3xzr I63Oe/Sk2rBqaep5GLvgQDICnnAEoiBYzVwMd8vCFXllGEVf0NJcYbfBBeUL6U2i0IbO/Nd4dJfp Hkt9YltTADdpZOd6/D+MibNbqIwH47RfGULp8Pptw4Zt4W/u0ww6DMEbvMjLFqffjcdMIDvxNtDa htCEFqiPUXj+kRkfuggs6/LDAy5/Z4CaxbmlglTLvFj+QTTJq8aIUNbpm3YFCNuLicAteZf4iJP/ YdCGRPaPPdT7WwxTXnpzgSpIF+MhTAcP2mJCIZlhURXKHVtQ9bWGGEI/Ozd4JjTz8/52O54/s7SJ kIXlplqvCSIiaUbFq7lsj6pEruHm+LrsiSCyFQ3l9Ep+EMUXNDWfkDTAtVIwQEd9F4+kSIlfENMh c7gJcKK6zXT3p/VewtsXeuPTc4htOfrGeW+aP5IgW9TDcMb3erm/Hyu/GSzn2UzELOavJugaGEq+ 7WlZQFh0+KeKQcw6XTrWrmE2SpkxCBsq3JhrNXaWZWjNUgnpcylUCENdnqP91zRsIoOI9quMkM26 3tBsm3keLyCYnReJGEa3J4R0+yU7LTO4lD1/Ql5jETtcKI9sz4JyPIjqJzJhuLbhNF1UxIFrNYb+ qUYhd1xbfX10t3UaZfv8dffN8LwZrBfcF+AI9XPDEhlN7rBlUNH9W0wpBQfkChJb4cq4Ru+gT/t+ skmKPDSgDk8t9SFL6wuuwMRzqjnoPXws44C8RExIMDqlh9i6h9RFROc5KaRhW5GR4+eGwshlJwwV 8Zk1c5dOVgPnY3RCKILB+zZOa88EYB8b97/McyJ6N+xdIEImcmmk/1UnmwzseZNA2gu/GSRHSfYr z8q/Xs1zhOAIT3lQ+693lfApAT9M7JLzb6Mn7fb4S8ckQwphoU7HsfiZfeDM4jlqHY/l+Bgm65q3 CA4+WtQ2oMRQ3fzQ3cFgmn7HCzA9fI/tWp1eY2DS0JQWxWWVSdwjgDwyfPQuDjq+9AjcYdpTV4gr aeY7BIxjUKGSClDnDRKIgU1fKDJ0rY2KhEEwoVeHg0L3sdR505mnkUdHtTr1ge/uRja5hWgyOPmR Z6RMgtMV3fBX00CBGiaR8OX6Cy19mTTegplNJ/IqRrZwwGbQDUcPsnmhHio0OMrLab0bLJmxbI4s 4jGSDe5UOhkQGgBw54wYOiHv76o2iihtZIV0I/+wh1a82+PkoxVLlTUAgebEf8mrY+yiYsMIrk5o RMfo7VpIfvTf+mxCSXVdqT4ZGymm7qeaCeWxIxDNLL5ktgxMyJQHVZA1rDwaOFaD7fFaWsVClkrS z9yxWexry6A5KJ+kL0PrIX9OnGf9Ry7IiXdetetvIEMT+AiEL0b5BjG42eKnxHthzc8hXdDCE+oO sAehvOHJHq7mU6lwjafAqeASsSqL5p0IjP/SuurlZPRwzhLMRqj1ym3yvqd3lB/8FfrRaO+Uq5Co V4p+va66TkxD0Dl5yQt9m2uXT18+IEUZ/jJIexHZoDpZ1c15xvmiKGm/9VdT4zv38+mDJfUKOygA FMYK6kWy3Mfoj0YmxQPszD+e+UzX1xHnhbxBw1lAfyUF/MYBXHEAhupC/K7Xt3x+Ng4gEjMZ741a lSWQvhm45M3gw8esm5u8nnuUDevLIhoxGkQLY76YiABWvtN5us7FPe9QzMfitNZETTtA8u19+RBu yEqU9QndhOdIooTwkyoXYcLp6fxQ+HT3kV6SZex5DC4+UADWgRWElNEHtrASaqnrDz4xkO/8Fy8Y vPps/kliu9i5j+DyDFwLyVLMKJcBTU1Mx5+0hdhH99SxU8ZN/7BYwc2ZR9BJQMHZhmWZ8A7drP4W ZjiVdGMKPtbG+uvKDW4TZP5OLwXOOgXuJOcRFSY++bZsKKn59PdZGZpTFsyNem506T5Ab+/APpg8 wfXK3HU4+ReWtO38VeI315sFLznW47sNEA56WHOLCylK5Tsp0523n9zHf8Wr4OkJG8ZpeJJLgZof ZxCZxh8g9wH6wX0LDuV6Rj7aWNNHrsi8V/R3sIms+/C65YP4BcGQMwunYNMEJ5trbrNVARFFfcpC f212Bv6DN2jiUAqVuqIYbdHk69XQSEEKWGFOaA8phknjv/aXo9Sv36uZF4JuduQ+Fr6fYgecaar6 GfNy8n3R0nPlgmBDRqmxpp2/zz3AOCW86/qyTu7lBC5amQG9lCS2rrOa0C9ODZhGXbhi6tFczqfk 3dGm8tTyL5gBukEzxRSnfo1jCyBsNA9UHzElAuyC0GAihFnyUI7H9ZlczprAi0MndkN5/p3NpLJu c7WUZz46607Fuj8bxEwO7UPUi/SWemakpr96gWPpa+jPIJM7PWgCdZ//stV46+IcMnC7/iqfShWz k1420SOJ0dAYsOig2LYMDS3VRbXMzx8So4VM7skKNzMhmcFi2iFw+Ln4aAeEz++QrmsHB7b+s82t ZoTwpGVjIrxzuM8zVd19PywwKwgQnCBMnKHZA1uFGo7gI3cF+lL/t3FqO67qnZygrHLgKPjhWHet U4qpUZ7gbyzTZAue+IqHaJkIxusr4uDpDL2jWDjbk3YOcvALOO771ty+D2DlaaGLM8rPcvf/RxZq xcJaAFDel+DcZ+IPuxPX73E5oTB7qay1Ac+3Amcm22BgOfl+BEcGCV7X2Rr0I+2D7gMyrUE+vVh5 6ylbUc/p1QXIsy9rhhHWhP0IA9YZTyAZkVOo9lM2KM9fi1omAqmXQvbLdmlC+rlmuovwmr6/1Q0z BayoUFUuYK5nqEPQ2lrvvzT1xPndEf+n9W76Sbp7hCr5s7U6Jtyj6fWwkIv4E52epL2HAJGJDKK3 urM/4FVzkpJh/V9L9k/W5BK2i57yoaLTXAu6FubzJcnER38VAj62gtGduG3Qpk5xf01Ui5T19Uos 4nMdSv3dWsUc9XAS040RPqwIIoJiBD1BCPcrTgY0V3gdYeFRm49WuDxJJ28fv3r8A4gNEq0eAf0b IA02J3OHLSPMWCq6Vt7H4khehyFC2Enc1tPUKdA9bcZTNO/d7gl91lOfAvUsznYwfMey7mkyqWKv /LSC3gxbUYs5sFAW4qR/Y+attzmhIOXOxSRKZ4TCoQNhMAK85wpnpfuvrWfmVxpaJ/7JcR3hPBHl PfC/l1EkuE4WgfOoQbcVDpg3H8tuyF02BEOMaa2LgNkn5toQbm9lgeXcK50M32rRiQTyNVHYr0QR hE9WSP+AHzWrJQFxws31uFUituXD4djhsyHT9RgqxBS4O9fKQyqQFsEaH0D2Ezrvume0snzILKyH VFRlNAi+6fQ6d4t/20NBnOQAtkKRyHnOkPokg8g18kbTeKesysTt1OiLgmSMG5WFSo1tqllvsuV+ m9cIYgTTtvHl86JDPwjEWxv3WikjqTnwdgyo3zEqHEDCwF/fgC4/dDA3qsn3yhEqMuXSLN/SI98D LQ1N8ubnmbEm0d8VzMPJLktOFwHhxOrJIGsq3jalwKggEOmXtExc78foB4Zl4X92Xk8MXmNHrxQv 1sV9AwTu7AuON7O8Rxu4L1o13lO3oowOuE6ylpWAfaLmJ/lkc9NRdXR60FDz0LYNNyPStqRdmk4p RTDnotptb+nhJoP2T+/zUrL+DDZzC6dv8kR7B1LKzZU7sTjmQujlOIZAE/+/iYCym7DayQ5fZpUr 8e8+pU6+Epg4gfE9AIKLI6QvMeEs9LJQ1eFxQaHDvXLuVLC8OjSiZGtkKmWRaxy3rzjpwHK+z02w X9CjEdeW6RUQLCfS9i6II2KsnkVR277pJ+tncZozTYHmn1Tm+h1IzkprX+tvr9EvmQSwvanx+8QP S/ecc0VZiQ595sZ6eFyxkw64cyILYfJ6I6syccTWdJZY4ELpUtt5YHxbFd6l2Ez+4lDN2xk3q1a3 apliUWnaovMIczCRikoFUsa3rv5cTnmMiqKKKOR4p+4mVK955UHGO/3+2BBHT0vbJxLJ3YUiEWLk RWaapyMob0v+s1NHBCQhK82bjRoqZ2ZLZorCOWknlUxR3UxS4o9omHFZMEGdIumKxq6wx0HtZumN BFfb7tfJI4JNNvh2anvDxbukOi+Kqs31uU98qYdLnjb3S9waOFpUSLG/KnC0FkrrAPRUG9NsjcDE S64ixMUIfZUrO4yiq9bszWqNP/QPAXHN5EZwUtvrovj869wkrfTQ8CcOM+tQkncqmW2klrv7Rgci OIT0vyhAgN+J4Z+JZ/Cd2YFcpoOnbbJ7MHfxH2zTPbWrBSYjva7fJoZNI5+68B3ajRd50zzd4hQc iL07iTfQ3fdFwLYB2BjoPfVI+eYQC/KQ+uQqr/jvprzKguPBo70v0+5MWW0jMxPSE+tvbnICstLt NmsGl3gIo98hIjyIcASZJsgSOLaIFUn2yN6McXiriC/8xj38itDEnHPTsrPgvL7ny7TuK2eLo8Ke A94FV3xt2p1a8nTpTjRskem0+PjUeVcCVqE96kyRsieixGyBxu3FxYVPLJUatolyE/Xb5U5hOMJW wWe5xcxRWr6LYmRtn7005JAKILaVGnsF1jf0WKZuzcUM5JFhE1iEkZVqiIiqt6vx5zzXBk5Dkt/p spTHuiRzPt0JRpREt8k9Z/FhY/Vcix9Z5yhjIjJJIqwqWCM5SLO273XZ1WVsbScdelZ19Sf0zPmw 6dGXN5gIflPmMKBkYUPGgEV6nrqRqfG+Y3JQjcWRIbCtFtxLOLBIbaMkvNLePZQtlAczCYN7Zqbq Hl+CaY4QULN/tjFAEWr3K1aBjR/bwOqXdDOZlK6g3guaGUPxCZOZJG2hKh34r1P8Cgjocr8GCdYb EmUWanmsB9NkuKGC5i8cX0AqS86E7VjGdmrAYurm8WadoDEJ/SMEJYiRErSzPoyW/4km20Jl82p2 CWsDbNbxDAxewb6jRIcJD9sfuDqlNh2EKFcfKwJ0hBTgCUF7hL2NT6nw94HyKVJAiIfRTIH2UFdL qWTpra96OugxJ76xik3mHDR+OcQ4TvQLPAALTiMw5Kc5mSx/HnTpZR5y9bC0W2EGZr77A8vD2v/x pVBrR7CF84pEqbufCll2pY4xedJNoS80HE/i5cYS0lC9EdF69aUP4HmpSSRoqy7qEfKqcXeYFjqE wtSU5wU+AZStQtw50n8/uWbAe13A+EN5eihOoNXEv8I4E99c6RjYWkO25o0lLQi2hkTosOmv/j9Y E8oF+K2RG+c7jmRmjfakXVp3jbbkPLH7njAZv2Ix+WhjMIJqXMGUHPL9C645G4FXp6wIHRkdMEiH DzA12GPVaHKq0hLsswU6dGuhtDmcSOwzYCiDTYuie3CW36IKNKprx/yKpXRmc2TEoi/zxbnZbHaM RyyZDAQxlIFysOuOjfLDJzbkqsV0q/xJc3ALUIjMUXLb7/JkwX8jRS+rs81485Nzpt1+8Baw4qmR ETHiFC7DtD+8Q9CssBf4YYhrwvkZFX5raboCYbIX5oMOYy49G/hSEke1cN4MfFBfIS4hszWtxhpT 6PqIENzYQg2mwe+GjEkC3jVCIA/lQJbTyMwK6Uh6Na8cYkgbULowWW6n9PsV7mgIlRPER2uvNh8A 256BpdxohnRaGqHc6t2X9rdq2XHIdedzO8BULN6aYfhL55CtMX1CY5/2w1/tDtLzpJ2W/QyGXmTL lQ0Pes4iE7hSZ1iTX94MAs0pobzMvMgqyBfS+1TRpbUySegqf9Bs5SMW813sLRQKR5Mb5XHfH459 L2FSJVc/oG/chrcid8u1m102H1vhxAo+CjxtXG72qNRvCVLZxiMyUMjGO3p5JtcOM6riZVKhC2X+ wyyvqsgE6vDYiWtjAQplZHmAStVhxeM6QNX/KNb0pA2tM6XiP01YKLtDxypYOoSyaugRde9VhX4t Hd7G+JSu3StdCdpxTXCVVRQzOwDPfZz7N9aUe865phy4u/pXyVUM9OP8F2DpaS9SsMp8nHBQm4wV fn3nywZDYUy6gN86M9dkjDlezwbllKbVo12BWMYFhIyWuMsNUEd9fCnzSo4ro3xBlg97u4963bKB PtZUa+H0q4cqkpVbnS+8IQLmy/veKCfGdp5iAgsaUyNzpE3KBNt/IGxeaWEU0YuAZaGH5kmM8Cqp T3ZyAETdvUuvU17sToBBhabtbRl9AjQwWkAFePEUWddXUIRAxox4OFe+WAgSVP0NPIeRaIWPrwG6 SNWY0tOy27wzpliEIeE2U6ooqGNDt1N2QMaya2n+ay0hfrlID5/iKOREYFgGmYrk7sPkSAhsuseg UkUsntQGOdcuFkPrk1WwtD0q6IIZu4P34zd9yplo0WxqrNUFs56uVoMRWK8fGN0Z1JMKmdoJ0lbg ACsjn0bzDuXrIrI7IBu5LsbGWsqslhwXRTcOM9+TNb6JihPuEIenEWzMak6oHbvRJPUh2JPuJm/n dwTK1Td647HGGgvvygWZj6ulayoFILnTtEVd5Vv1l/1llX/DVb4nfMkrnXGYLrvBIZ2+EHok8YOc 8NSrkfHYcmfouny7/e0iFOFRtrr/uFkxp3I3RIGjmzHT2hk97pce8CJVgD2SBPQoK9KxCfDVPEEp sBFAx5AiZSIOtnencgfOkxhy5wbDWYKx4yNBG09cPVqs1cNfca6FbfTzwhVO9wp7DmiIBpqqIBFG /evN0HsP7M2In3KfWqksvm2t850asD/DEK14+S/dkl8Juf5XBZtjhwHcRdydNxmMxSRGi5epTLUk MgR7S3N1o7zrE+mv7KwLUWjgdmMdZHfr85kq/F0MkJ9OX22ezu7/2UOzlu7jwZGmNuKdsYDjGJTV DkQ6Lt8e4y3UYoE9q2NJ7H/znwVFKMeCV9J+DJZAFhg0R2b4JiH3JRP0sf0vurLags8t9YvRfrSl Rw8Ok71XrPC2DCbMh5EbmLymDLc8cXolEEXbVGt6Np5dMDZV+O14qNMd3KG62HMB8/ArqkPkRq1I ZTZ/M9T5Mw3WFmQZJYJLtb+9C4dBc2KlXL/RPwQyFKmc2BZwXo9VzT7gvf9lmOYUN+JGfjtZg8VA /knZIxyRBZl2cSyZP03FF/QiU0jy4cOHdqvWSwYhnxV4dnA76Ln8lztvEuldYTdAyFtNFzZxVh/r IlP34YnaC9UzYlcIqIPRaT0gXb2yLa1l8SINnGUMqG/5bqXt19Yrob97iLhBN9sg9pZWkIANEN9o 506zYJiPFqBUcgNq9U9GJ9DjeypQHXcIyXKxXfQxJQ5+saNdQy5/tyFd+6loPCV7Zk+Uny9eRPk6 UaJ+xhSiL1Y5eCxReEwRnjyAa7AROMF/WJ3M3yWQPqFeED+y/tIJ1TSa3768pEDeotBQ36g7qAOH cowmXinSF/PfxNmQMTK8NPYAgNNHtbHMZ3mA3eFCIu157GBblMuHtvBGVyMlPCDoiHUM8ifnPdIO TGYvmXpTh7qn8yvi1XdJu/B5ENlh17VEz/cualnO/4eV6a9DW+/kmbRYFm6rv/e34kJvgtG/hBq4 oL16REkgGA0pfwx/EWWqGZ6VRrW+MCJ41NUJtJgrXokoJmh1FA7xADpFRcvW4ayBtJuEYHDLvekl nurlpEX/plZcS49sJ2Zm6YGyTxO+rl7VknB1UyzNtg+RLAA6JjgvQ6umiq2bjp8kbickmIr5qc7L eoaKrp39Uu8on22ZTFp/dciSvH5AKqxC4C1uLagKpiSwyaCu668pa5xt9VbXJAwQs8Rm06+V7e75 HSouRm+Op2HrhQ+HjKsEvRek+i4042kTwbJV2oCbbo6U09MnHynFBjw7swMf0rSpi6LNcX+JDjzA YORuCSKS/O022NRLgIKdAbiqX3WyBDli/57ZFi0fk3QdWSBpB30LrE/a0VI7vwJYNrTdW411bIqZ Zy98/wnahfubWGMzIYA0rEp+USnhdFmgjGnzYKrispGKqZqIiDf4OMeGfwQyF6sfhuXvlSHUSH6y s53HAecLErfuDsqO8RjQoDsAtBNXt82EmhFvTxCRb5S55Z9sFA/qDeDsLJ4sUP1x64zxPCYvp6vv vPaDS3Ajouw+O0cYloKPo18/5erl3FvDdVRaQLEDPHmdH2VbNQk86wYiH3ez2FY3jJvbcGu01zUZ S9jvB8A40Ty6Abmp0N2y1XKF4EZd37Jc3Z9yrYVV3I0PO+6qslAKnr9aBmDXhM+zFnpvBcHTCMEl EI7mLGLnVcPhmrwPe9kOAWZaCr5f2+oWTi4fkxR74MGevy9+6d3fzyI+F8ltZdbu80vmEUhfm6n8 GjM51Q9RaxfaC/vb/rJnuC1Zkt88T+tKCyjSlqfyFxPrhCnteq0bZM5zK+Ux3dlZnauyag7oRX5L NYowOPhxLnm04Rxr3+h+a3eIItgq27aaCYOLnDFQJDqd6Vl8zXvIByB0vdPhAuIQ7dYYhXBY8SkI V/MC/5KMO6bwDPI8Mm5DY23nRcpsx80JySLxZTrgeeKk20aVh4/KqM6iyHLhLuL1lcj5uWkURtq+ YEVmRc/9tXaznKJlQNxWTJfJ5kcMqrtsUOprjlFSBDlh3PH5PhRztyWnMnyHhQ2/x+V1hX2Mw+Fd FaG3WkP8EybTbQz+9H1KPdrwKJicmUSd/I+UVq88MUL4FdkYdLZzTq0CgKh9fBWzAMAyIqF6gIue 7qR+dX03qWLHq+FkxnbKGvj9x9CcxeWh+OPGZR/+HNQiOOxvT+YhArdcsteFM90Jwroe7fDx7PJY hXy82c/HgmOsI43ytdskVVlBKi/LCqPCIeVSNaInidPLEEOWw+ccIOQzm46mciNKtKdgc43N7Zum GuY26Pd561nMUgKI/171xgvksjjSaVuwoLxNd/mK8mkpiFms/Yu/4TuA9yLK6OitznVKsdWnKzX1 u7fDQyZYbT45C2amnftbBTg4AQOGCuYrjVhdS6X0ZjOmYHCsaLPwnl6yfsIxM88+v6gSDk8wQ/5C uuFKbLvjAgSWBK2rikMtHUYZJKHTFHkvGv7TFdMRzZy0h0/CM2D08jpfGICifKQhPSjEsjGAGTOf 7mUnaH3ZH4kHHc/l8ZP3UY//d7eiInd/yOL1apgIkmrx+0sL6Dx/06bFrfEP0m1+xRrOe6Ve+Dpo Y3toEJ1ClLofLRbTVdYsRuouzQRn44/3BJ8dYNePB7VKbvSKgl9y+RPcu9CnAP0tZRS6vOXx/Sjx ABS6A2wrC1DwcTzZhrdTxxQ9BjDieFH4xIXWRz7UPpoknuv0JL7k93fwfg6verNKjSgNmGUGkqg5 OWxD007azqbHbX/F1pPXF4RrLOY0OdyDVBkZ3MbIXkwRbl/q6xV2IrhrFhd8ZTMu3vZR/UPqcRgL d0JitahRHEYOaevY3jqgIBeTVA44cds2VPIWTpTf5zm+HYoFWctdL7rYJMTvzn7h7xi82fPyeOHZ SS8CLKgKxYPyubbHDOGOaLy35U8x8URLKI8TB14ZFhOOqChbdp1t/mMpgzhMvmR4ta4vDc1BmWUY RFKbbcAHfhKh6uORqM9N8BullRs139cz6pNPZ60H0+HuRnV4O4NBNqPftIrs6yb/oJzJ4Fw0zSL3 VQ7zP1v+Qzl44T2elSMaTNvFZbgWXghuJ1mdwHwI9YOUW/cWY6pHvBbD2v2Taie/9ZHs7+ns52iQ g/yCpr6d7ncAb0XOwEDFZAgsfxsGer1uueVFA+po+57tqojsCR7p1TkaTDp4sOjyJM2nFxzL5/Cx DCPPX9eGJAf2KNoQV8OlCJC9EyJjzvKqeApV0sPLi5y0mgYpezPvM+gzsHhpxDAC3Y6ustFBX+Xq fpj+bUq96pXCc8u6LKX1exPHyTGkR16kAcrM/tAL/08a0nFM5L4uSZMLMTpTZly0DKhJZ8h1+x6B 5DMpQ9fDOqQgHT7hAFFvTi65PEvVZQomHmamgwIRkJqgS8XcCYAcuTDBBU0rfPElibABDev/fTeb jH8InJwgknaqiN4EeOtx+IKLHtjOlUlDqiCrfPqtp4EZE7pm1B2SM2yrx10CfJ7ys/ME81bnRhAf Qe8UGv/RWwlXyGrd6i3XCCrCDKt6vQSVZlD8SeOyB2HHcG90e36tAJ9cCIafmWe3KYslNkh5E5Ja t4nrlaZowF/HuXSaZCTY5xgVhZFvvZjp1ZXFIha0lTeZ2M4/CmQWBu5c+CCMPD017Osx+KPDNsrP R2WygELQzqT/8SIFPxSRUjd0QgJY9JLOhb3UQZin/qMNqchu/9Wv0HoDjflePElPHyEdk9GYhzXp RD4NH/DJ9xqGhjlp1dUnMzUhLIJGfsnVYEX7YxjDigQJp08nFdcBy/1jTPSBCUc/I6KYqvPlZXcv xqedn0oSYIzHWc2Xex5K/Mnw5UkSssAHfVFWOvQooX01KSW85rGMZC12DMeqP+qNUxv+sbZvceED /6Xhl3Mk/U2AUx2GklEiSrnwEQTzwviZWE5LlTHyFkcavp7hFPmvhKs18mj0ucN9w5eNige/CCb+ XnTGvIJfMylpuqHqJqqya3sqgUleCQMV4KIugFRBQdDy/S0FqtwpQNvr8Ex+VIWhDyBObhAMIMOR NRHN6LM75NT8lBgnjftUxwHLj85zeJHBrPW1BYu01Z/rC+fKgKGfv+Egqe+0cLcCo1PnL4QtAOJp GP2bWrcFjoQAjt85AWbka9SOVK4juO0kggky3513ogcxc044qH0g84Zne9QQrKusHaabUZsmEaYc ilV6fxf0hgGHylak4FdSezEQJkcaT9sNbdJlUCtXZ/DxPvjdYluYCpIKeWl8WwnjtmNwwXQJYMYa fPySnpKn/rBNNpzcJCTK/D6BPO0MM428ajeaRzGnIMAcvoOslOB0U1SOySEpr2VIJxIhMem6zgyV tdCyg5YJKDepIpYbzDMHcoO1etJFpAKaMMwjlnUVgYJWtMa7gt3am4wXhUdK09NQilSAYH7Hkx/A HiqKQo2F27AnJz58PKcWPQ56lOm9T1Iyprv38+R0jrUQ1OzyFIMcFamAV4Zw8tiN3xw7idaUK+OX dwDR37t3z3X8Oi0Ze3JPMLoqzP1yU3YECle5FgcODaRZHS3n3UxpBJ6iRiRM/35MxjDNmxCce32u fn8/DBKLtMszFft7RIMVT+uMlSrGRFy4o+xxuviDVzWyzrSD4rf1uOYbkMiMVjmiP+XJLoacz0MT FZLcGupK60QGW7ROuj2SlQ8yMlVdNHNvlH/SbLdZwXAnSUQ8P4COPLHu/4VExcMRrYuf5hmaVTGg /63/vaurEkHdQLQVNWag/dHkmv8Ia6c5nExohjefPN0DeitKNOkO85aol0IcQ0J+kkc8JucQ3dZl qDA/sMlRMSf6CN34J/FQURJGrHO9IjnlwwDJCsLkq/ohbksEke24ZpjmY7MucPB8kWDfM7Co/7em tBGHFlUvtVxBfHLm2nE5NCfOac2f4jaF0cUgARnY66HWgYS9RV7HzRv/zS/aR58FcPkG6rFVkFXS A4pHAazell64AgUWrSZpZWdz8PFLgS4VciJjmWkttTOlJOHBQv2w/vDvRGduFnDPPCwqEYEn3w9/ xxQnTYeyVtyCfl71OYkkmqnRxHbLMgcULzF4H2FhPB9tSKiR/MeUS4OhdDJ9kRhYXVi4/Tvln7za ztMW2JdsqKuZpYemB11Mfw8gqquk9U5uzaS4BP1T9M/h7sDpjNAWMnIYVwSAKHzRWaIC3vZ7Nc+j jUdqSctkTHroacSEuOBUQh37WCBBH62Zc09wxkV/b7uxWo0/ue6KzmWyDq+SyFXsLS+fqXASnJnk qOOpPa5vD1XX71O26pKZWEQPa0T7R/R/5jkSduMIX5+G96SQDXqXNUGdjMGO9C1fYp43f8friDx8 4JIcwT4wuor/08fy0DhjqYu2koebYr1btzmCcPeDQUf7xt2UdU9r5WxObev5qbAwVoYxV8dNZm9n UYzKCZhRL5X6a3VDHwal83guPsDiHCwn4VrXDFESfeed0Y9x4vR4kZPx6BfyL0qJocPdqyp6+elc aCS7zV3O9KAJroBfcb8qViAjAlrO3nFUl08E5ZpoK70cLOL6rq2RLxbAECjDr6VGEZS7u9DWsp3X BvbMKHmuWsA7fxNPwZGrdms0xc0QWv27zyyQWfaj+iwYowYsJPAMeKD4P+xJrS9uiLiAY0/HQfvo AL7pC7/mqPzsky5hR2j4nWk0f+eZ9aUrFuvDVMWswUkqqykjCkItQKM0Z3yTILXpe2fjD8+lYWhG qljBN/sPoa2R/WEmXNNkk2oHUgbLgG+gJUjZ91B8KQnzmd7pJ5oKsszYHIbh5LXu6pL19RxTFmgW Yw0TVR3FC+i17Vz6Ul+YHK9Dp/OulU20lsRjDh+Obm4b+v6DmLp93bmY5w3GXKc/rDC53cxtABZg wLWcZpcLlj6PRcisPpZQmUNdH+EaYB0sQnK7JnZJg14awvHNwyUHrzRqU+KWWWJpdAawd6FVq6kQ jbruvwpmaM/NiK1bR/Q6fzz3c8uazNq+6S+6mAqOMMttnMGRUAUaGxN5GyHHQ66MFgUgk6rVZdnH AE58G9spQZ0o9mWK7DWU5GQCfHfdEwveNWJ16S42LQqS/6QDElR1OmUJqxhLO+etZAjuhBguavNg vfGej1v5KWL4tUY/WHRudGWQ2RAgVqvEfZIWv4UR/zUemqmhIE3oRhXl0Qr7bELgeVlL9YauK+yD Njy5VhWCmr7fTKlxAZhDY937Udx3w0QAED2AqOJX8P/ZhdZiE/4EiItzmaNR+hFF1UJoEBmsHPqH POVRHJlDxJ75EW6T+FhY+u9NmwxAYphhB8jLmquuqvuroYlvn98+Yw0HZLQgE7L30AYWOD1uOVZe B2DR79o9bH13qIc9WO/01ejSog98yul7HxOIiBvZNNqAKO+a8hoSAqZKIuIbsrAffpQVmkLNd/oy AKISiTy5cksdj8XDdFrgdLYM4s+hC5LdTPkV35wwK5WKSFlVFlgM3sdfjI2tMcSqO7d8y4SWSSKO 5BN1qdBgX0Oq6N6VL6XnnRtLs73uEIFzdvPFk1scLQT8rZCVjWzbzT9MPXWHxCZnkI9MoNBWGHYr k63b4gPE2AptRomt3l7lJ+d27D4N9aMCE9dRIfxi2+kb5i2hWCeDUKM8sXHcqfZ69LRLg48ACvq9 xEHhCLN50I7W/GI+hMwaJxEBhZDlJ3OvVuKIvi6UysME6p6pUwgW55MvQqBtlBSgndFp/1Gsm1sa tljmuROAd2eEIxUWsTeZ5nDTwcxpyD71S34G46AZqK4wz+SjbXSSdH32thTpInQFGvxoOyRYSq+N NbJ22C4CZgWgz8qa5ZZ32T4t3ewetyb88BtDQ675vU/RI+d+tQlwNXnhk2udgUeGgGz66mpzzk9L 92p+48qF4gXi4CNivUUVYnAW2OtcUMb1CpcVUInSXwlTlj0wA96VrPj5Wv2LMoTNG+ng2pbYUAS2 yPH2ZJZMQlAzMCz+oMD4kHWyJqUxUBIO2+0CejcF07b3UvRi3QtL2g3ybSzFtDwvRcF1Pmc9Uiwn Zv7HjGi6KcHlPaAf1gvzlePh21ZKBkSO78S+8jFgmsCP8/ov0+2VczMXagtVOIKsnggAGFiEhO3C gOx+Xc7m5pPLcz7HYM0/v/W/2kbYJwPr8XEKhjHU+m7Gr6r74L3FS78DLkwktte0II189BQ4HJQc 7DO9P2+YJWL4nf3vHk8e5iweCTF7hXro0ZGMqTH7XN7V5E4VM8RT9ZWmzUkryomKdXbqAkdexpy/ PyKOJrbQuHyUzxQOtGIA2IgtX3WQleFetcQuqOSybYyXHzzgTKqHJM7Pp49f8O0yv+Ga5CS6+Xj8 uCO3Nq/N6Enu9BiSqT2FCrcO+63vBpe8y+bpRCslrmMKe9ooMaotSXGmrtC6JHxN4UaVDbRkvhD4 9ozZd4qJmgJbeskR6iSeLNj5LY/1MtSFhvAnkYYwHNUB4CGHpBWBsVrAnrAHVcvPe0rpQneLTzJ9 m8F/m2XjqzcQzXxcKMXpmxGUxy6J3eMm4YfTY1iqofY+FlF1Wl7XmiZZR00wyyyna8WmFdJpnlX4 jzjBDKpPdx8wesZ+qBK5C/Jj0T6qBF5xGAvrCXuIyY0ZkKjNKEr1+aJZSdeR7RNQ5qwgYIivmpoQ p26vIKoBvcRRyaGOS/apgDjBGoi0M9P5zR3J5E3Zg5rwQDn/VaWzX3gZynedGljtPgzAcanhdpLQ 5L+SUdmrg9tzLchOIYbRJRbc8eT6+B2HMsZPa29v8AxHCivhPCaSohna7Z5jpKBs4JzCkU3vgJGh qM/ZwIZ1k/b/Nfh7RxtcmvcSs2iomVuLRY8mIgzE3phdmuAX+OAN8IBUziAApd6lO1eHrpy37GsE gt7FP29cd607hwkTn5ZW2Jw5yjXMBh1qkhiQNLmwXRH0oHUzVrhPa2x1D9ZGRCgT9a0pwcXRPH3Q TO1Pwn0VkqwD30TuVqWCMF6EW/q1ITpQbFatojA3lm8HXDN9E+DEKyYx7oFt3xVXukyD0hVpGqdt 9TOr1qAnw/DRks5kwtaJC77o6PRkFzA3bOlU5KiqC0+3WS+CRW+/mpKZgmDEbzAHManaFYimo59s ECH4Xc6HjNR2ih3sqTKkrqt6XpBlEnEKzFFLsx1ETpezxTCi37Kq0LwnroIJ80j1Uq++HAYgOrS0 BZk4F9UEJ2Y6aWyikPz9QJTTwcNZEhQgtQy5d+R5dslKgKy/U4jB/KcgYziTsGF39rZZH/fD9/fy 0xUXbUS+8ZFCii3uicdDzFhVQdVKjXjh3CurQsRJ+pmRPy54p4NsD1cJtHLV+F/Jco17Nq5DRxXo gWGviLVkpHygIsRriPxrn6JSLyFsz/pAMdtxleTy5nCePl14YMsOXX+l2bnFE6ZJ+lN8GEpN1gMs 2DY6xnQ9vWCT24SAT4lPlgV5dkPADqCcyGAecSZWcsoBfLyfUHl9gxmg/obhoBKDwzGtZub9mmRG wTmCU3FaiCJx1rmPxG3Qw0p4JmyvHbRQUOWNbyl7E06L5fC+gtySrCrP7wHrJsoc/BpyN6XXHdAA tiQU2SnjwQijTHlvhW3PzfyUZ7q3UkfEdSE4SouMx/x0EG7QmniUlOyXXAr7Qf98vkHeiaVS76Kx wU+M8tu7cHZRRX5V0N0StsLrRsSw2Dcbwu8RU1SuwXZrjRwDisj3J0eQlWpW/J8TP5AgDCU42iEv ryrQdyEn4KozYCCd2YaHsY9UsbdGUvSJNcs5SOk04PilwZB3UEjh38hBsMO6pRqILD7EhP20bZno j4lHdLBC431JqYLM4Np5jnLtWO/brEp1YusvneH78RRINJ2/T1IMlxaL02bkKwLpLuLFV7i/2VjN FfRESX4WZv9iR8f9Bsv3k/jAdW3DLIeYpBUM4l6fhqvlcMUNtAPny7YQ9/enNMt3nn3bXMcGaAIN kF3Oi9IBFlL8JymzNGM4F6BwiOhO+eT5Gl6aDRE8e2TMrPIqhVA9Sl0I5Ts9ADiWmhVQUAiKJPCE nRlxKwXOfvkaJW29MeQUVeMchHUP30d5M8mQivPhDAUVzNBL5OfOYFkqsa39wRQb6b860TCW79Xi LdySeGbInueOm7HcKeFOIrqh4Riszgst9bvwh/0sS270JbOeqmN/HD1BRu0+RIPxL6WQIIvFUxpE rwVngWeU54B6bPa13AbyNm9fFN4/dhoH1dF2NqHgrpPGfEnR2lO4y6dFlU2Jmd3kGVZvKdlkr4dl 1UtNtyLwe3OtOieL1ZD08kWXG1cZAe5M7H/AAAAjwOmCEerD/bF3xNwRuq7Quuc/Q3Tnl6a/a+Kg 0M5uOeAC1wX2W4jUBvt7Q9eVSKloime0O1uYj7JfF2HiPdTYNjOgPMRD+QIFk2X+Oohi6OLlMbfl u/fJhJOi1O5fKEiZj4T44kO4XI/lcpYc+DlRit984iDpnOvewexar7zASrvHOzWhyAcn2vp8qq4u Re0LswWo48B/+Gl0Cot7PkQvG9yS8lY8uy55MBF6KxuZ4vD+kXUm76wjQeYjlTMbWWeTKZiny48M ZL2A1MKAsfj9vrqundJF4izAJ1QtST06b4FBj7/VZuFTEZrHcZMz4Rq4i4yUYhioE1UlhJwDqjU+ eWoSIexmnpKsz1KrsEuMbo4HSg5G8B6pVK1jSpJgFQpakJANsCwfGoQQnqCbdTanB7PyD6xC1RYo GK2kcdtI89gr2FBkyLe0xvs4xByIBEIdOorzlJ6CtqCjtvtNe/NrhWUP1siHfZaBVRFJ9GArtc1R /T7etJ/wupMjcTK6+bi+VP5m9cma8mHFgdXYgwnSMneQBwWwuKXf68pwsFbZ100l1J/86SmcNmzH 9lgPWqdU7egZ3cG0fnrjgq/rBQ3htHbZxakZst0oqef0lVrSUFQVDuB/BJs1TilQnKzOtBZzvZqc BoxWB0XV1Dv5972lKhzZ2NyPYVsLjpMxfIny+aulSolVTwFG0X1Sj9smExgLLOI6dD6xsi7I3Rkf UwyaMjxXspllVRAJb1XTHrcw2ImkYdpdHsPX1vIoehoQx+6nhoo26BJHUwLVCsDbxs9xxKrkQpIS EnEkBpIdDzy1iAqDELF6FGq6Sg+aaQbPmPUjKBe5uMr6tCt2yr/M9seajvpi8HNcsgL5XfHQMKbU uQcx552Rdr5YUWrOH7xYci+/Ra0tN/0b+vLKBnW4WPkgGAkHyxNw8PA5igS8Rzwg/oJGEH/HFPNQ 4oV50hQocrQQZVGmBKcq3eEZF1jyZTO0tLV9zal3ATyGkDaL96zEis6SQ4WY8kEl2LpmPw+lg+t8 H5m4g55MvvOkLnfPGAjDXupeFrE466dOtCw4qxLBNRbsENDj1XFe9Re/9iuntaSVJ+3hpDSheLR/ TbwNfrQDLrkoeOxXtd7Tm42RdSydNsE5VVKO28cg16m7X0rD18lJycnNKT9A+I+kYRRcCWT4b0+H w2h7MkJwBRuk9QAJ/h2NIL3EUVWxeNOCx8ORxFICj58szy2lv45lxaQVxUtXW9QZulrV2oQZxIWs RQpJiDifekRSytDlk/7Ng/RWFHQUPDjTmCF+QeLZQ8Fq0kYhrrQFT3Efh5Dfb5f86M+LShSQi3gx fNYOkm5sPY394WEIKkxpSg7lP/nM5rPJ1ZDYwHgKw0m1B+/zdOLd2rAsPHVBwm5mmuuUrh2h3/My +ZAczG1lBvDeqyHtZNpIYbblvY7CoHP2qWJHdtOyaQBrGASsa4BOLbyN1RG6GVBHVipvX6w5a/5F +rlOqaLO2AzMGwJw3YOXkZsWXULmK5Ld5CjgKVRgtkx4pv4BJH73E2RYp+K1lm8RTBDw1Qovup0R J7TSFi3p+uGsZboDAPcexNuQsyKLnVzNTlhFR2dVnnIUfBBaIoUsUtLk/LDsQ8gI4zWqQhdGcDR5 o4XZhZEkTBs6MtcZSZRVkntvVQRIhV7gnNO3GS6VpaokQu1qjFNEY++Ib00xpXkiRkP9qyBupgb0 XN6WU/fcE4kTIb44A69ZM8mYzuAI3/9lSIGCBUpi78a6OYeazAwrf2cjTWk+7XRQuDbScNwmaD/7 s48K0Nr7FQvNe1+Uttvs7q6uzv01umrOBg4IJ9IQgRagQMJlOnY2dWPSqi5PIM6lL/Uh7CCzcMLt hM9VRd4hAChFlwNkj44IBzJJhUBqR5MIe5wPcEyWWijnmIPjpChehzhKx6hMuT5E6clqik+1BO9G 1GlOh06K8yfeHq4pQCxjPHAJnlsv8ir6fktJiwqiSWz8jqWlXxg66fLw13AhdT+l8GDWgtH37y/P 61Ni5hn3zlNDkey+vEyuG0f6bCKaTGlHMZZ1VBp3vGHcZwmpxIx0t2RNs3t88qN0x7n0NGJN6B3d QFjvegB2BOYvwPlRblQl6aD2OzO2gj1tyELSWo+4S0jbt3NxauDGqFR3JK3+aq4cNh88vGA2f7FC nCqQ3Mt05zZbIzRFbd1F2YM2dSbQE5NedB9oeANiR4/IVYPtGpfmC7CRcIRoOJSvNpJkzHlNOjGF W8hBhVE3QmtHtONRROq1APyCq1voMAyBEpepRxVLIxBIxQ/68HpJD8+2NYYSEJQo336lSAPsEGHg 7mIEPMAwhPpLTjO673nM6QhY7YxjoNY5zTpyrUmI6I0VDQymZwtQD94RwAYtlGuVt/d9UXLUyO51 sUnW+rgZ/+q5SoWHt4gzHPtwBAyHEDd3KjjrNeyohgisKbdlobpYE2Vtcjt93d9T7PkrNHOBbCQp tiOymbxoIL1r9pkmPNAWa+VReekmBhhMILUvYC70H8Dh1brBi4KTmtXnXIO5xkjpAPOsXvZbKhs4 tnvQCCsPYi/OTC4wk+A9RIpyqTigxkWoyObxWU4FQ6JSTLT6XTM0rJHZBmGQ0Js9o8pa9g3xep++ pCAjMaLp7bYTddx8BxSh62TYPJoqvvoYVaAGoKPAEr5tGMNez+P0NKeugmKGal/PIKk8+jMIUSE5 M2jDu6iDQmSxMCTGL3UYrJ9JS1he4v08+Z2ZJXYDBHhiWS7wI/mNT4J89C9lTz/TSlZXc53XrySV L2NcnfHdW1AaiHgbG+eqZbEOKosc1YDcbyr7LgA6B80IqTmm5VA4moqZjW/6MgDHfqOEynR7GwAY pa9svL7rEf0Hey3f95v05BWd6xcaWI7piXmM4Ost3KopANbB3ElXgt/V8IdQOHBAnq+Ka9HaAAZF JNFzWKW3dAakGeEDheV/RrbfvvrrJUzicj+/HN3Eg8OjzQPpeD25Xi/6+TW7o3FmziH3mb0iyMda rBe+r/1/9z7dUwrbN5yorB1lBlekKToeLbAypBK9BXlHibYn8dayIYaOkJZ/P5j9MaRLQvDKcALd jA3rs0c3H/8wcjoUmOPbR8N/SxzH9YD92w/AiwNWIg64p+HCtE/p1G1RX2nlLnSA8EvDbQUYavlV y3dyz65lLcnfLuI4YxgJ6MhNMiPGX1ZQ+qdz6myw8woV/rPYmvi9qaH7YF9zqiwjDSbBO8bhuuvP Vh5ulfudoA8kg0+JfscGbpEwo2aYG9IGznJ3K88fKl1r16Fw8y2pbQaTSBNhh7yScVUnfZlzLv/C zBS6HDTZjD5YiEcfa4vGEsqp0+us/6jWkNOvMkY++LWNEAFwMSQj6jaUAT/KiJ2R6NLJsZwv9QCh FzUA7B/SNAdEOCwc+n1bwpXT7cg7hVL+sXtPBK2zmCJVwDRKQHdfYqLe3ETnbqKgV58VSL8EOhn3 vBDFy04FUu80M5LFHERLQwqMxr953Xl8VVqxALnaZETygtxBjDjjcxNx111e3N7+UJMy2hF4NtJR X44SQIcvgV5hFcvwLFZ+KuWjva9bAdS8IcDxL+gxxLBk0CaKJEjihleOO+uMbGh3rGtFCMerSGVV sgYY7mgjm7Rf5gEzjkxV2oUob5ML7NP5ce+3snTsUqBQgR22rxZdv3fjhUskaLw2SXURDG/Q592o jvZ6HQekQNtnSCI8T4L4bQTck6FsfBkuNRgM5GufS1Jcr0ufiDaWQ02JXI67qhwm8eTPGzMg3FFU gLZwQYjc17yX/ihewiw5Zbc1Uj7EzDPFA5vil9H/UYP/h1WAPBsRDmoKt5hTYHE2IxIBh7EdfSUp Drx5OsMQU0v2qN074kaSPUKI6mLGHkmiuRdatbgmP19Gf7TT9TberrhBFniKSU/4azZ7/caK13Rj yn7H7uEYW54Rgd3VsAh/Ig6ECL9RFV6/GUYUf93D+mV6TThca3NO4iBVc1YbSk2lHpGnX10gUe9/ HPq/Iq6F/5fYlbsGxXytRukF7sEg14FFSIXSLHpWQL+BUWUkpdAmkeJfiO0owFamM7A2WzT0t4X4 2/vzfHqo/Q694xxsxx8NocH7iwxaBl9w7xlSeZsZmJrTGKyhgUZGGBZLaAFy5SYHv4zEdqbkg9Ye YPbGSnJjnI4M0/zfuBEsURWD0SFH0/cce/jewJBgHKNTu7kJx0Doq9TkbVAWiD8noPm3xFiesXxg 5zSvKoS7jnzjmKF1brTn4evrJSsEIuqDth5bhiHRy0GkjCmnhnKgjztFfW7lPoqEmxY2k/cr8wNs JJdEs9dEFIWxZMrLPGX3BNk1keM9nAGFc5t94ozgzz2utR9irC1Lrvp+vwoCL/6if5a8PA5vjPT0 4Xc4ZnqU7zWP5NCB197khlai8ezql6M7A55/d5VbA1D5oOvId8cB/0rtLUY/lMmgb00fRfgduukS FDCWybdUu8Lbu4t33BcaEnFxUJwiDluX8NmJv5HtRdfgGbOTqdKDCKBYlkdryps/Gsn8ewGfSmzN vzNYaKyzPYpmq0g6w3gu08D4r8V+RXh32kfoKgzGQtYvbt9igNHVy9eNzUuBjdxVeGel28ydZhwO Vu9ELtVlnLnp6iSU11rgGR6ayUGSZnPWhgfvEOZTjmhyJjIoWf0qZLTtBH3faXjxsuESJ3YrnJjA 8IJ5lix0Cx5ukSV/tQcinFhiSR/C0xtfuMOC7EM9ae1bVLdsUv8mW1g5zy0w73PhqjEodekcxhpm AU1G5//6QzjAUg31dLxeBQ1ctd94XajmixWF4LIgA/nJKEv6uYlstWQyph9iCHxQWMX1i68AyB5i xn+gFQoIXG+J+adT94DbHy7t29CFNavDWnSJdc3JHlixmyf5nNJupuT1tGQj9/oBIpWe/EcfHfio Juvacmh9Xr5eOOGF58Lgz0y2SNfX13JUUcS0PNFLGmEPT3YFhITrPvEJzwoOG12WYeBNSwT1KbwE NSfS8R0g+F8y3PARq7UPpETc5dKmu1r7ApV3JL1/UNYM/5SKaTXSwWKdRmVAl67JszSjCp/Nj6g8 bbXnrDSYHeYP1MbXdzNBu4AVmWCffJSjc9fr5ZN/gouU9IOAeSOWDqzHw/WRPcYQHFsh2x44ZDug kFh3aXW6O2gvKcNfS9Jt+3yadz45inNS2c1qcpU71tZlaVKwKbQGhwiQvCXiPxL1glfoUd+ceVup 7DVaTag43V8fQWaYL2LRUNKLDSo4jyh03St0OBXH6+muck3VCcC7O4DbNds8hgN9zefr/WO87cpS cw9TEU1PUquDgu7kPvok3PUmTHf3MTz++SLFt7Hodbx6pJWZ92Bkw99ZA+Rk9K3CQGQAS0VZu0uy wZo07a1UqRVBMdyhAwetGIgVMhifa1ELsKYQ1veuigthitUs+7lJtcP6ATPSZnatJMvzsJ4onIKq I7/Dz+uV6svBs3iPAIIqJ5jznTp9+zI16Fwaa64/I4gFyH4ObozTX/2nO3CZ25i6fNMbP1zPiN65 egQuiNnrkydOh0UI4JEQxSqaxxZuxwzCDZCB/rNAz5apl8XUyf7eao06nRUFdTxZ2M6yEhrch7Yh +u1wymoDeGxJh/HDrcFS0KiFTN2RRVdAkuf6r19L34reMINA/lA+95XLvqw6VaShB0ra6nTQhbZd An+GqkrhCH1usAOsdCqT7+sQWiOZPeRoJnhJAKUzyLdqjLmpN8VZXr0mlP9Hh9ot0hX4mU/LxJTr 09VJq8VXa12XFH2LyJoZO5L1/v6ur5HaJ9FpqTPq07GIsFqvsddU4YTJuvyBY9MCb4M/kit//0wO 0sqvEUDJmgZfqtx93AeGBIULGHIgJsp16EHjC+Cnk79qaqHfDMAC47plzaE0fQPM07a3fcI/RxM2 I3yl0LXs6sDTaqwCLp1bsyQaOBK9ukym8lKbKffGPzi5V5vI1MqK+m7xJaP4c+kX1FP7kEgIplH5 vt77JRQc58ranvdTZ8t4KHrN6ZYAiIvLgVaijyoLfGTebhW1qO/LqJFX6IZ4/OiziP6/ID/XvdwL q9n+OoS566yLcLUzCgxU7LGbbmEJ4nKhyl9MfYgImZ653UCccDo8QJbpBq0Fnw38zP3J71R0BWr7 q5mLC8ZdLUhcBUUTePRZC+TmmhIjhYU0hY8oTYUU2MEO2SyJHB1H5NCGtrpuoLPV7Xex/vfVHnZ8 nSjIbbBuO9cS0BFnaSuaG21UJftiXg6t6e8h6Os4ciU2cvzNVmQdz7C/1X/QVb31CcQVqYANVsSx DxGZCOkLx/BKOF1ssnJq8JMuWhX6UukK2Q5bvWiIUmzC7e7fSDxapFW7yiFhXDAWsYgEruIcHONz qoQkPo/+91gKbURDQLCR9jeGtRaZMaqHsoLy2p9lQv5MqpAkcp078pRxRcUSk81aK+D8FlF1A/ZU lAciCVzDUT/Rnx2CdBP19CklKHkB2xE2Acz6dM87EL/ZOngEdz1ZJZRVaB7uRewk4TpMygKV9IDn SMOXIiMg5Xhaip/wPwZvWI57zZmW/OOiPOgN5Qki9y/cq2dCqbyMKW2YB/4TPFwr6zKSsmwL2blm LR1YQj1GhJqLMFpbvVsfL18FrdYTXg+UGaIniap5IzYlE3kaDXVDJSdg++pArTXhUntb2+IUXsyt 3dEKSjbYF7galhPDW08gx1iF7UtvY6+GPxcgk95oJw82QDcxKDxI4HD0ZD0uzm/7ziqlshA3seOW hdm43aOmOxd/2hezM63GCAQyf62E5EY9gPNDaE7jPImsqTxH8X/EESMsLIEbBA6JqWlRJLM1dVGO pQ6I0rbNE1l7hTbAYKqAhAwrynU1FmVtQIyXq2V5vnaYwlfTNzti0bYBOqE7edvZ6oCHsCIYx7Fq EZRRhPLlY/rNI0UoRJP5iMe/PKctv+bjELtasK3u5iLKo/STX7rQ74CwblgMHZA+D7fzv/ZgmAoT Mv9sgwVlXrYIU0BtrqF5l/3c0tCLprJpEje/pqxMI/yfnjQVc/zMNe1BHL9ODAbAUe5dT7ZG+0Xv Vvw6OIrRB85/1bk4RdbHQ2udicL7kxoebUUGQREwI9n4X+T17z0kbJ4E5ZVTuZhkeOBy6wa3GPJG I9naCj+ZtAYxxKHPEmisUs7Ot4MeP6IgjMBf3B2E9HAvqfRJW5DLCasiMgHqO6drZ9Qu2RIGrxgf nJllq+0uffyW/3QnXkFctK7AgBYU1WXz0gc9ZP9sidsJLGPVBpg2wpF9OnL9O3f0Yo40Q0VjskGE KxHX94nXAfYAyGOoxuhMw/oKTIycyGyPCeuH9hccu6tXIPA7riSFYgcykBHTi+6FsPokJhTmozSx r+/MOhkScs+h5YxVsTLvXL2q/hiZd46fntkFoLZ0euMu266oqjoe78i5mZL4RJXob+bSu/qZ1ZyE DdaycXQjyyqxaO04gp5qqN0Ra3/RowPZOyDwtjqJ7ZWyoEP1U10QEKcxwtdNGB2MxPSZH9n5DHRn U/Tbo9pijVjj391Ux/Mm1oSObWp/yaiZAwWS/CpuU7fgVxr/glkrPX+MS69B/WrrRhxxT52cRvz5 XMTnB3cao2+4oRb+dg0XkDBWxd2E/FP5WHpmLyknTqAgD3JSP7ruNulx1tWVGqeEYBljWCdTtuLw mpz5xISpRSM83l5D9CF2h9nqC14hHXwjSSiGEAdibyQ7xDha25FOmXE7SFYbeJ69IuzPaQHi3lvM lT9zhJzQkoF5yW/RQG337n2JocG4caCIIG2xs/QRkONc3eSuRwu2gnrNGDelm9EUQ4qsfsiVuOjx xW+gbITpotOP9Q6zB1ZLFaWpP1//ynSwZP3O240aZQ+SKQnlj1CSXSa9PJQx/4hsrohmruoTjKUR r06xnYi5AqZCC/Y9d2UJp4ul9CjUAq7221+9dZ3tdR3Thg66gg/vtseULpnq/M0Xv+8psJwle7kP CtGic0Mb0lJI5l3Kesr73Le6E5E/TYZj3mLJ7+jWQDya2FHsW4oJnRhFfBPBOfUhNl2SRDA1DU1d EveJ3HFtAtLmeDwmP+JFlnsd+UJHoo5Q3e/POoEWoZqTk7KmyadAl3DhbyC5gmTutyLwWt3XlkR3 eHzPcxeNRYL3pP7q95U+v7Fo6yx2JlYAS+E99xNJjSb4uRQ1vzUp5KQ4wt/7AgBlWPMUf+NeeQP7 z+qJ4hA5OOiuCCM97re6Q1sgRlJ+LgCfnG6vVmCIShHj+y7pmVDf4coJocyyZasF3vOqS7aLFwV1 YRlJTw8DfKupjkfEw5mn0Bcafe9RP3rzib44JsSU5PMJSOBE54XHhXX6aYz6+HQpmZUatltfgia0 30J09ljD7HuS6iyVD8CxmVbAvl0XZhDpWrTrIUwpVtz/hehMFR9ELcu5ffBD2ZMsTyFOQT5EmH6k xKM+AlFRKJ2/aA9Y2lqNVMubew9MlqkVNw7eXereTzqZ25UJ74piNyxs460DB3A0C9cSZsM/sm2Q /TORz/ialjivbQ51sPlh8sZFwqxjy5yE8iuESf0NFCqS7zx28YhjA+MmaOpWqgVh9ttvGJ91mOh+ cuGljqKXq2g7MlxwPSpHIRIWTjfdbxAoYr5lpyFgTJIRe3YQByw7KRXOo9gXtupgER1YDim9XR+T 3xl5zqbRfHQmivQswnmldB6n5BCDzIXGNbkG04xZwwX3RmwcHjG88RHZfzO7Dx5uNdSH53V0jkZ4 f7zAjfeEGAzYiA7P2cIgEHu0KmPwyN/+5eUPgR0pBIsbzk00YXiCbTwuVhK5WKCMTslVygL9ujYO RK0YX1RP554d0MxVq5EdqMBr5R1wfJJWQpP0e5jQHk1RdB2amBNY38QbqwO/OHhiXwGY0duv5jSn rD5dLWOHap5lJ3KJmx1Fc4n0UuziD+ATLLeZQzHxU+uw1rDdvHtZNfMuCrOnkmqJ6JIyKxmcBCWW jO8J4EFgBh4Qf8Ca3RXomv7sD9rglRneqMWgXhhMOZiHExgvobpHHvDMccI0wPezcqOqaTrfKsFT nMycYZW2vgzViufrBhW7mANHVt/imZC/zRRJsEJr5oGHVyF54Ujo7BK1Ji6jqXEVUTDWI4iJ/vM/ pdZkvOF5vriN/NddPPr66LvVbW/v7Tm2chnVx5B7PvYGIT4BtoYIYuHB2vMSza0iChNVdkEd3gij CIYUeHesDC2RHlDgXc9Gl1Fpz5yy6RaCWI/8GFDdXDYZWqRFV8bYk/fwjMoVTRSo9dprd79l9/Cp wsE9wE54WceMzGvO6qZrreCd9QCuWlic4FmPEWQQM+/0pR7fThpKfrev3F6BYcjka6UUefx67qM+ 6kNm4NjF1Xg3UibUs2VF9EsgpA0yTGPtMXYfiOcgyILe+KN6tfRfhpwhzyH9Z1cqI6KKOIVWqH0v KhIfofJMO/xzeKgAvukQxnCzWL+9I93GSvx19V5koTC239tbjW4xn2Hdy3oTGxu219aa5TEi18+C 8xYpwP/qmpj7rcmDPCSUoSmPphlxoMs5s6slQg+0askOYOEtT8vUYjXiPZoZB+5HB06nU677TPeQ D+cdLVDIhnh9qrnRtb8uKnF7Uc5xlsDXyLZbn4IwvbQVgXsiV4l9bSKSGiHoFAEE6DhUD8wHjGIN +PXAXPIensq/tqxdX1RhaG+9m3WobEtIZ4m72waY6vlkYj5nCB7kl7U3SeM2DTRqVTTtMJEFr21T /u+V8zgsbDDzBQka9rjfInS87HfUEE+kdi29CdiNt6TDHzlX8OERfwPtgBADltJgYbC7ioQ9qBtk /GMJB0rqDYnZclBKquTF9T860lz0niX+1mtSQM00OEVVfThAlpgo9WEYSe1G97rymmnwOHqBikRt AGc1pYasmgBcfX6maocYaN6rlXETwlH7BEce+sdpScXEGE3yM7v1NO8tfUjNd2xj77QsTX0zVnaH XwtqNye9/fM1pef1GpsFwQIDqcFGRv5vLhCwZ9qbWRRPN2A/h54Jje1y5t/QjWgL1kaGxqwv4WGt RCVg9aGgD29gI028j0ARs9R9Wx+PxSfP7Pkpnh8fOl51uLCQX5SCTr5mGkd9dm9RTtFTR0wINvgX hpEdhu4qSLfIta14WhoV96Z1FXQCqzWW5TKINpvzD4lD4UX915JHGkKus5kdYHUWdMnx1T7KStgy GgVapCkHZeULwayoYBAELPvmAILx/RpgbphNan2usqk1nqW+TY9H/aMXOXPO3i6/6jZkCETgwuIF NQb9DznnuuNsK8eoq5WaPX+XQBHInA9ANvwsrutYhnF4cTZq79MjoI0aJCiMFbIkYIzCkcNSCIwj blKQQVN7kl7Xe41GRJeQbKNXL2/BvX0p9tf4PRlKEjOmBb8VK5rbYN7wOFA7I+6zULMiJyg3b9R4 l3IvOVDuJFF1g2D1CIV2wBVJsnMgOBjdnGlHKfDFxFup0xyxim4f7mXCD0WjcoB1d0OqgfMpIgPQ I66V6K1Gi9Kavx0xpm8m4WwoP9AGT2wZCCXpn3goSEeAgmyLPJEDu4RtrMTJLYWAh8/7H6SNuTDm aW7x4uswM8TfSj3Jg5o2ELjAoNnrWQtggga1LS2AQKHvUpHEPxqGEj1Uxuc0KdF9k+PLLKoZnfAh 1rdc+0mE6RMAvgCjLwB2M5hJkoq73tVaLmkwoqr7WBlLOdWQYMD7/fALOa2GlvdtRwQJEJZgotjv hG95gA1+UrhqWDFeGV1HZqttZXfgUmgnGLLBPzr+veRY3C/iKozvH91ZUkOcCgcBvJ9/iNXeQHoc tpKwCqeHBxYj+cnE2RDlym+e0HhSyaNMNycxKxAdJs9PMMMozG3Engeqvbjr5CDtwClGX0FUgTln A3EzGFBqtk2y7UzwOmy7DnhfFjoB1QlZEQXuwzqTyL43veNJir9y/QRiHvAxvvUzUqfCeXs1wv/d lrNAG3PQ/vEgAFaZif+k4Pwp039BLIJqYDS0dnFjggBnpBqHFIwVvvFgxzBwybsJBk66ccRB/e1i HYHO8MriNDEr66vBfFhwpdYoiyIOayNGCvpwgv/3NOcowPkJK1wu8StfbqjXv1M85PCLAfGEjIcB gHtdGD+ubUWmdg31mzLq7TyugkWnN/ZNXVxvLmwO/D5WvqNmh6cz4lr5vih9BsR2zmgQs5EUG5tr HblOa4glMX5oTa7G8Nh1QKZyrTwo1UV7J/11GBFd2mgvxWOxkOTx32t92SKcrKfUymvC2JbaN6Y3 FZqqqamzieKRg5y/QvVntyoSxVAz2t/y9VebZkBOqBUHQeMqUJrBxobdgulJdxPjuT/IJ4ETlOH5 ZtBSzMPT/84nSCpdr5TJ640eZ9TTtyanGSOolNa9zmICE2WdgQVj7XBE0Pe1z1bARnh7RfjHZNBD zyNXPhrZ4uF0cnpGTTUtSyPFxSBfBOYyfKrJsk6vk5yltV3edjqzUNRrhbukUHouU+EZyfURTDNB pUyBvx5p2wdKkk7cb7hCY529AhlRAN2PvL8lXLJqXBNm9wEupwq29iJc9tqX5Yn5O/V/CClB0B63 Ap8X0p8P3F2vEljipz1P2BH8hMWY+jXi7NCwjzn1w/53YGbpaJz0uL2ORLBUZMFeVV0yuLJmL/6p aDELj3A+NaNYFmEbuYK0tmFLHyIQeE4MdfsTgHaCcA+mO6i1pVbhDJ+f1rIA6YXXgYJjnfCWGeqQ p0A045wcFc2x1S61DNTcU+WYsI9JGTO2a44mwHsz+OWGBTcm+P7BNXPyxcsjjyMmbnIkbgz46Skf s/zro5Lp9gCzeHYcmkk5NKFHwIRkwJOQotVPddc9lsicpGwzPKk9nJ7Iu2o08z8dwlYcW0Lx+ktQ 6ZsJy3bgqXRyL9Fod/1J7oYT0NemwMCvIA4nKZCzXfQLpJHc8e1LzW1hljAAl04EGYLgt54RRPYY qHsE5hzVWvB6dHksAqdQk/pt+6BVhS2Eh8U0j/XvaNSCIk6gC91Upe2O+LHgTbMm1ng7mOdFoObM vsXfyN4O+kTvnye6bI/tIpRrrdwTNvSWDkUKGWTPJENXcqSvBVUDuPgZF87y8W4P/6W177xIVWad /tmdB0ldVeeDOq2D8wkhd25sdjPUjJVmJ+41Z/F0aCqR/H5FpRLYdQ/jrEI7WtINN2iybqPnyrgJ YQgkAvgZ7nssf84gFJOrq5YCGPjldF5Sg9aAa+/cLnBRqFjnl01zgnL+0F1LrHZlTlIecVJ6hTAV YGupwEIGY7ss4oWx7M0xvaTjRfr/bCEsS10zGyokfYo0gH6NL5d1QzfuQl9oUj5qRv/BKo9iWLaj yDSWEOp61RlvXKsMpoXSGjgblyV8VIEwwcxWxVNe8nBmYSQ2kXXpnOxRejWC2Tgq1PrSA98ZlNQF +ebI0zZtwPKc/o9uaSfgDZZdMFgioTptwDzcKkehRuBusqilhdXnAXgebaeXb02SUC+kKvlGaJRr D5JLl/WzGIv87y60qc0xLfNiU3MqH74dLjuw68RIOcFl8gW89bsrWffxSCO6selqX+0LlWMQaCR5 btRau18MEpcBaK9zWgXDq9V8EnGeacm+w7K/dRKd6k0JEfJF1PCKsjb8gTJNbb5c0bkwdPlml+Nx xb0o55iyvQCxoSM4vH2wkEodYVXtlylBdApkTg9q5NSsllj7tq7chOuqGn10/zxzAN0AXsSUcigp d4Ah/KZJNSp2Lc8f76rhGZjVkiM23Z6sP94CE17xU8My3tKqnZMBVi+LW3y47q1ZzM9uDifMf6AN PT+9GVtL/5o7mafAFELofM5h+h7JfNEEi2DkSuIGUnwZ50NX0s3fv0te+39xjoQWy9EZqH17+xKG 9uaGT4m+3vezZLcAeQ/epXToKRkacgITTqpzB4BsdymipAwRrW92Q+l0edJoTuvMwNtsGUNrlVYw AgwXJmZ/0a3maP952rZo1m7ZmwcDVEP488WLpfiVccFBJjRJpZPS1oXm7JdiyXtFVas0ZlLJbToS uFzhpYVpcK0OwFf6TzbTV/T62ZqW8hejR5VvRQi15erU/RiDm/MQS3CIkcIciqR/sFWmefm83PSD sgUukDtzYWUGtRYNoJw5Z6Ci263PievavvF6tGDbUpiOMMyylo/7Gk4lgRHVt+8n7spPoiuccd9I Lc+iVNsbOUK/rT2cgMYD8NKt1PqmOHTcj5+BprxjNAomv9jJQIixpTGoMeyyFx9DSElmQLS/KJtH C6PDVgEOxzeEy1O+0A750VDLcFamHHYjrtysXgmTfSPHTUj12LuCprzZ5mDdasZymWdhbNf5h5TW 5XaAyS0RGLjZ1YA3NcBQ/RDE0ffQGFoYNVMMWlzG1SXq7RQDQuOrlPjihijrkmhzwwiAms+NuFXS X9wjWDGd43yfVgtpVHfyaq1dQxq4YjlRTXOY6W5V3nHlNnAe89fJ1vXHmbNwCDirBVSo/BEB9k7N 9gKIXT9Ov1Rc3/1W0Qat1iK4gimg1s0LWiOEbTb7o8/BQ5v4IHfNdJkZxeYwT6pTzxj4eiJVzKic OaKZQJ/iSiCTGq/WdnDsS7rg5kkcij9d9xIgejrHuqdh5vMdv8RMHt6NDTxfoyUvCHUX/5xHoh47 4UXyuHhOPxDtMbfTG+H+DJOdnF2RSgV53oisrX7L4G8EQ18r/j8mIg1X8JL/QklBYY1G1JGKkx+L RxzH0dPdc0PnJIHYLki0tbHCdjaw0MNyjJrxecLzjzduWGX/Rd0ft2FUR+t0qBcg2EzwR1MSSZWJ opClvqWBmd/o/Rr2bYyQ8gqFHfAi3a2L+P9OdP78VvGLOxuZmkfZPwwXVanBKqAIZCJSXNXLKiUo y7wWFVWukK6LhZWdjuqLZLIBL2sdZHgedd9YJudmrrdFBOlmD/RTWfQeCI3uD6qzKiXGsmQ1v/Zj ixFv3dJuJF5REEA3jYG4iXMPk5lFZFZg1U6O8rKNRCVZJqXne0ND1NzE6U6lgCJjw1Ryc9WF4Rgr 1FHVww3AUDgELiV8qY9NfFOVgZOGE75YeKxTI+Hb9zT4OFX3XWaky3PDqwUskK6M7fUKny0gg9bm ZWUWhcK/h1hVTDfmNFqizugF2z56/R9sR1iNw7Ysm6J4worclhhTs/2J+ysIAL4fFIaJrAlkBskC /tsBnHM1bXADH0mM0in0DP72gkCNNQxscfxMMKVzqdQYTbNIWpGbF4HLyc9BTiI5thlsvibNCN/9 hCz/kvdYEEP+mzgrhYvqjOP9NGXRUqlolHgYiw+qe5zyjhrFw8smdHrhMSsse83pngv+GIqMGb12 p0+HIntyBZYSqidpEpGNEDLa/9DFwW3Jg0EHWxAln9ivO3LNVoRb4WkZKD9DI4ObSoq9yKGHilXQ pLJGafUcLcVDiRg1pGqYTgJJ+Urh0ZXOwUALCUNmAxYNXHrSi3tJw//KshQ1AsIzMZ15CsKXU/Dv SlbqJD2Is16SHMn9vR/gKsEgAzA+NL8W5SMAnzRpoCLtZpipmva0BEPZRY81X7h+XULrxdv2GtVr 0dUahxg3xXUXim2nkBBXDFS7HNrXv71T0+9ziYOSIkyO0uiwJqFU0iDIUQMzWDb0gWx4ID/RBgFv 1ovmCcQrzsc3/IqaPyS9dsDSIj2Uek1qKi6oKTv34XY0U5hqUbDxT2Yq2CPKrbCOOTLroaPhL198 FGKkEx7lR36sfiMgJLgAb304r0bYFJER8+h2KtoUOgBV7j42a4AHtlQr0jmXDepQOfbkqxgxkj5h Op6gl4d56MSkNpICpXPAcDLSl+2jehdPceoSwSya70y1VbW75r02rNIpHM+puUg7gNQjkJhJ8bT/ ugtfY906lTz7ShbdRD2/uBsc7aFrxYhyjayfuDhEzJ+jvY9XQsEksKndTKhOy9B6Ek6EzMeIdAVg qSYtKsSjiTZrkJTLDmA+MKqTLXcUZFg+Q+xmRkL7lVdVA/wHHKOpxZybS6AKe76b+7nIKvrcP6rp VQd5M3HBp8n3w8lT8mtBABI4u1pCWeWxBzLqUtWWY1t6TrEsD62sLR9cUz7QI7lzMb8dwPIwZLSa BObH1WVFmDGBtsLjifo9DJQFPCg00RATJFkBDEcVANr3MmikcwQdCSBVUEqj8hKsIChNUMwLQTJ4 ZPm0g0xsoLvSFKu/Unr8x5oHnTsrEnvRVGVKAemMGJUmxgGyq4Y6tk9GhK0lX8a6PwMiz5l+l5kU Devo8LVZ2ojg2DgEkYb3EcX4/o6H3wJO4pL8ZN5yi9rsCIuGHlcMcRWACpxn8GVbIaXKCNFztHgC /oCwKbGz/r9crseNiGCDkdsrfFEhhkAyvpfjvimsyWHiljov1Tp2mDGyXBACbj0mxa4QDnqh+tBr OY1twL7qQfdE3bropxoOpjyhyjebzUvIU80wzo16I93hst5avWJPEgi0ofj8Vvcv3An6ewCck+he NM0EyYuQI4jEzRnl2q2azAppy1KVUg7i/dOARpYpbsRIG9g6QbiF0xid/iigpzU7OK77eG8QIZox +znM033zRtjZKfwDAUz9krRL2T0KV8r1KzDyZI0FNHfLdctspNmdcAHCugzaUD9I+Ki9Tl/C8AGx NBjkrQZ7pSRvO5QYFhfvO3GeDidINF3uVVh3nhD0C1ABoBWSs3QX1XhaMSXPdXXiD52Rq/4QYRZ3 afvBkyM4CkwDVoDiJKqeOo4hCzW//tMegFj+ovduh3NRICZa/JF5V2t+UCmTyCrgivw+dwSldIEf SiVM4nfQjSmPxB8yy1Fd3XnZE3j/+YKJti2yh3UDCibeUgePxYK3z2/nUrW6BZ4KDTlrEvrVhb88 JY4ogYgfXXcPgdcEMonMBCuzGHxEPAmWu0nOYzFbPzetNKXRHnKM2qLtscRRnq6ME/c48jIBOIhE UtuP0e3FhxQVNFF2LvA+d7AD6K5X92C4kKuPe+0DmNvIJaNPJx5dcb9nEAYLQ2+knLVdvpg81qHV zZghAw6KQU7kPlL64PWNiN5qrN/nTEfmOs2/H0hdcH97Jl9Fy4Kb6VGJ6pNi1GvvfLb8U8J10fqu SAcxMQEVCllHz02GuzRgafTrR+RSf+S+Z8gt+PfBJww56QhLotPhfPZ5mRN5LGBD0BoNrXnhf7fk iyFSzLklgFhEvMgb2NjzAC2ng60AZbyq68oHoLEvY1AbDWqi/U7fGUfiv+m159LY4gVz7FslFB/l /W3XX0TSLiwAuV44P/tykbT19YcO/Zs6+G/rdPtsaubWSGHu2abXT1SR1yRHcKdWQhOIRFSgVxRx BbNqhMcbAHq4kH+p7l4lHnfRAeyAYcIW+GS+V9VuhhvU2AtKyDkSHPV40asxLXGX+n0ezShGD40b y2dtmSzKnClrTybxl8jlNB0Wb7NlMoh08+ucrnpEy9v2OtDA/CZQQuqX9CMyHWyFZ+Onn0wP+MPp D/apoDiyXK8AJ5JFVDEpr2ay0YTU7PmAVqIIoKq90XIg0a83kvNCzsWDCrxnMX265dslGNPK34CW bzhPs8RcPhxQqQW2k8JqaKoD8kq9ddguRBxfA04UtMdj6ioAJjkeP2/DWvCUP4FzvcjIbV9D7ziO Xzg0kkEP0k2kN/+I9fF0N4/2LKJdl0JGdcoDAUWPkIHutiQLALX4iK0kNcTHqiyiMR0Cij+f8tQ9 PqOqO3m4GY0jR3q4fUh0y5PIhD6y3A2o0jpuln23XE7cW5rTYeCL9CCVFVI5sQ+dYyUcW8OM5DGL T4L9BMYv38VwdhrEC6FRyTmoj/KZcdCW4g0A0oZwRhDysvcLJMZWBHqsLigIGbFTUtKg2PyZ/k6j XRRzjv54g/TstGTp+NY6Xhq+d8wbSG68cgpbGPAzyfSgJxXrIu2u5jrU1hK9qWc+KOxuqDM5VTG/ SDOu6c3JywZ4K9/ilUyOCVzpLdwRDYB41XM7J0E2t6/PA9YtsxxcyW8K8iSzmbZKncpxHsQO4z8h wJomd/ogQbDr2pcI4kYYNjkM/heYz5OhBjuMLMybYfAWoAoPQV5MdtymszGWwoVZPaIOC89Cvo7h lk2AMYXEAukKVBWFASY2oYjjL1IiU2xqOJ4uXdDYFIQQFlicLm+PUVAKaJS+67f/LnMTrTqXGXS4 WfhbFeiOQpPjBPzHvxfbNOranopgw9bhp0QV/84jZac/b+d0XquG4+FKeIRZdcYtPKjV05xCjzco dO2ZadxRGAC9iTDXB3MhxO1Ei1hoHpWRZLMjMj/SISvKz9QWaZQrt4qphwuWQzEdHyCQ0meKNjTt 6i+YQuzCzrPLy+BkMeYhsfflzY9M58Ma+j1lR0dzHiOf59lmZ9D2ca50yAGa0SmwY0Uav5xfBHOi yRf2vPG4MzKLrHsPTc5RCcLi7oBS0SGByH9BRqY6g9NPi0KOBa6gANAREVKGQMNzuauCqT03qnEG Aw9wInV6SLagYtHAVYo+ul+7awwBwXZa/NXBqoK+H5ZbgV19QOBxhpOOD5FkohbgvEzLekYsh71I 77Ac+pa/Xc3ZGkWfEPcqtO1n+Qt/5ZXC0nQoStpmIh4N94NjUyquJZVoWvbwc73SnnXbSJePXRrG QM/kEmeFBrrdm8EwLA4VhUQidPsxja+6v1ft1/rqO67V9BZUvlGfHtrehWU6g+/ImDEpGCGWsl2t nqiwRRfuJxCaGG1nUW3mEBlOh63gxpp5qlY1e31W+NCPBg8390BJ2D6TT5NJO0CmDpUrv1gDdrLn i7aEGgv9pLZcLxl0gZB1rbHj/5hFqsN1p3kiLQq9gYm4gFvsHrM6QWMjy4CBOa5xkPR9sS2/BxtF eSj5Wubx/hENvDpYixFTUmV+qeTkwFmiopEkANdL7uVoLoy4jOO6ZhLU7KSRY2O0cssh9QtKDy1A S7GLmGfmCr3BSMWD2mUt09xEKdu8pSfSmnTW1cx0ojDKxlvpq5f79EvTicgOe6wj1eCGXP0l1guL h3xJ8Un5LJKpkEQMao/CgnGWhVudsrV3y+nsCoy1P1O5gLOVpKx9bVET5XKEQCzQLkyl2yVEDoPG gaPVSs1MlzBdpKXrmpaSXpJDIjDnZaeyKjFC0bOj57OJEPqa4E9GK1Z9gJKfx7/uh8S9aDyOzYtB +IOjb2N1WD1ca5q9ny2yx+7zeMZwc2r7x1sAW0Y9VmGupnKHIPdSAFD5cdHcoh1Zd/HOwCqI8U9G rRHDVTzIMcaZHHI78iSPfnO7ip3Pv+U3gxJJsoJ6hlBDpclwEniKyd4VPAQ8yindj7WSkex7rAw+ qUoeSJc5m6/ZKMRr6nKf59S48Q2WL3jV5rexDp7pDQaAsxnw+D4VgwQdzLmx4LrJWEzVrT80VFUm 96t8fZO5ljIj16mdWn7U2X1JjxrdPYyA23/dGP7/6Qb5UeJ16iYXAsMi5HVXOIEPfsUE4W/8DFMO SXE4KLoOl66ADea6h9HCbCsaY6iBThJRPwPOpkUZnTx6EAY6to6xJCh8J8WX9gJqkwqoWTdFds8B y6ztSp9gLCyLLk5mghyJg3lusGrv5/LZ1Wh1By1kcb/mg20Nr1pQkAZ4r8JFElwLLs58YFuKKQDV DL6QitiTn//RAQ8t72kDzCuDiAgQk/Y9iSm0hJ3ADID7EtX3BhDBLsZsVq/kbBI6YySK6pt+p0qX KgVGKAPO9tUMczIbn/BxaSSkJ9Z8AB/ENq1ndHldrirNlNIqJc46aPGV9TauexEyAv51FCxQ27r9 wtcnpi8SDPRAvCPjN7UrKS8yloh7hcjde05kgMcVoHqa8WhiRP2ulmEuGxE21gruclUp9BIHwGP0 XhLJbKcThkIfLhlGBsUKOqL5xfjKL0aFyfccUeL/I2fBUlOHKLp7NmEJsGXS7D1OQ6FQWLns2US5 NvyEcckqqNX3NefwSa5Bidf6tOmKgR1yzRNpEoZ/BWwA294iLdv6b/0hBGj7x6qXyea35OpcEV/r dwtq2/pasMA6XCoIuYJfAVNKCOwkzYXddG04nPftHZICIhi6ATQSTySjyFC9aQADZHvSVlerojBI OuuI9CvEr6LOsPCKOjys1vP7Nn5RRqoqFd2Y34NDt7vrS/OH4YtXfsv7Zc1XZVKoZ2u8iiDRCTb5 9YGN0AVdt+gGjiNl7J1t7EoVCLcAGiktdnfpxJVl0VpWZbCz/50Z4LcMpUsVHzOBr7IrFjMLL2Nm 9lTntj9P4giwA6XChkeVSmYsgs2GBikLXb0MBL2hfxpu2MbTZxanDOqyxUIDPJ90qVrYJrZqAlKC 9Ocm8iH1vOhr6PmyvlTaUbNqSiqLGYOCMLaE6tpJSVTO+zrwIIJ8Z9U5tukRRIXVzkMPDBfJ6ORL nUCsy1B1nrtG2Br+KUSRnl2kKozVaWwmfzolssN82dNv2LYSj1vS1W8Nhk8LQUI6gFbufGgOslJc ueS2YM3OetUxMcTD1zVZXc3obeiOScOFxP8QpzVnFMwWnsRlFUIj1k4tAmFYaesY+9t9wYA0x6fP /sU0ldNJ0WxVxDw6VxBYw0KhluTJHYUP6j29pmB7+CdXEN6FkBbaeiZ8+V9p72XogLg5GjPhO51K w3+3UrTEMoyYd6eI2Vpk1EtfTn7A5HY1p9RyLPpiT5XwKIdor072ZluqBxqJ5WWjUMPMMjIwxkZn dsVNeSsTK6Wm0AF1DA6pk3dLsX9dkPtkkoTAB9AmoFm+lNFBYO1Ypjd/BgJBo5IG3fEPleHnT9MG EoCysvi1kN2/H4m3LcHNZx3GlhcOsO/PXp8MTA0YEMwCPjJxsv6zGPRRF9OrM9gQ14WAnaCCVJ65 Gq5OhfN1KAVOTTt0benH8SrFDJXmCPbNZm8c/QUcevkoRjByNZpmQBezCgUsRStA3ReRtsMVIX0X tmZRN7JGdwCoahcKUigbf8vcuEMTCVMKTRYqI6NoPxr2UM7CjiNvs0GjVJxXIIOQicmFne7CXyoi uRilLpIzicYgfEnTLgvBJxCwya/OSpB0rxQAYXY0YF6ycbDaFb8NVh9sajCgc/++QX+vjgO/Gg0u QXb2pNn2Qqb3OYQz43ssYXHLuP5QiL1C6VIDJvGPPFd1p1aVerUcCKCUveD7nBO9XRzA/X5+Gje9 LLaMxyoO1iVkz01oijer4rVzWfUvJ1FXQ+7BVWn3fiv2ZgRILA5CYrES56pfblR3q/25Gij9gT8S H/uLBkZPqlJ9HWi4uF361GYQJqkGCxf1w5AU6CeZ9ZcivDcRSZYBQ9bb0eSoyuEmANMuTrIgd00k FEpIyMaKoZkN+4LoM4/fgYkLGOLQef8CWhOcSnZSu3plmm2vbf7K23dBdPfis8no7eiKiC7nMYuj UgHNf5NXNzNNbgTP1UMgLVa6q8BHeNgYCAX3sDWF1Gr4jedFa6XdSnvvS9q/DQzkA7J3mnEMv9an y+VwStrBNZX/ZmWh+Mmv3eOuhjVQS3AJANySYtNCfx1+4aEGmFaRW8TW77JZMJfF41Y0Vek6D2+2 aYGod1i9YG+qwrT7IapZHkM4Ro6/SeDhfst+ThUxM+wXar1FbFDGWCXNBHSfhC1ST/hq4Bth6+rr 4rVwAq4U+bWQkX8uV8xJie5xEVqf6GzybUP/LB2yTocSqF7qAxo1GfmpUK6ycG5rVQhndeefTApH dZ7Br4navjEpBJGphC4rpJxtDClnUMk8g1NbY+O/mf9/6dUENfxVI73T7S08uwRMQhe4wF5MMOmE 3E0Zkq+FUe3HSiB9Rka9b8TvWm2t36Tskm/1jfFNpE4MQt2IqiBKCoIlQz/Y7/c2eU7IIVr+7BjQ eHi2qveEofRE47Bioy/KGyno21uiRVchTi/ekICpWDUQEL0oHFE49aVuH8C4YhoEEHicDWcuNsq9 yda7LNCfiKU85w6AeoOtz69u89xicwf7delD6Qyi77JwKKS3iyVtwPDg1JZG3V8zwTxCCkVRA3tr +9dhL9m/r4QkPXlmtzQ/B4xrcfALEbTShrBxxHoYopTzjNwNhYdGkpHMlwKO9h/0OTJ2aELlg3W7 sqpVIdbgEA+dKhfoitgk5uHwHH6lbJaK3pSF5Li0Q2GTlfvpDV4n60++eYLzQS38QTGfFsB74NCD 21PNTyAj7AeX+IU/NIAM8ei6PmV0MFBTUupTOdoSKmqV6cRJboLfLAZ8k97wcHBOJeLjdhlVovu0 pRaysAxy4xdr/HUaGR2255sWd4mi0eIJmV3jY/8lppQvQ/lgXI00AxDMdm1LXhuHbGYw3ovB/8lF aY3FaPZcUB1+bAS6bwu+yfoEfeXhOgqxnM1kcmTBtcbEuMNfO0o8eSvlV/TkLGXT3hvJidmWmPy0 fNQ5Jg3W2A8EMoz/a6iZg2GwYWczhIau6scpfL4QhCLkdloKThrbPYRJGqx5TVyO4u7/9Zo6elMv v81tak5RE7jCUiEGBY3GRk1m6dsLJhl7lYoMW7aGRFqQGuX1swl/eKHDtfXQuvN55Ajn+y2rAdb9 LoCJ3j5fhVw27YMKKoasdPMJ3J9lFlTy8STYzfCRkh9K4N4e/8gA6w0HGHgkfdLnaM+O0oTtBXAC y2PoG6IPZRYogX7cAkQVUYogp7TvIGbEEMF0r0/Vh2Ncm0gIzZV5OX3ccwoXcYaWPjLiL4lJkKij YdU6ndPc6ukycIPEUqdo4JqsXgv2U+qQy316JtzQF8hNA/TmpRUOsBKd/+LXfqbnPj3iovacvw54 x040NgVfw2EaU4hURx3KqIRsYEmVkXlhb0TQpooh8HgMns+wEOCFYC0rytnErYrbMtg+9+p/GkF0 Dc4cLkSi2BFxX6KfL2vSBTBKLdO8R9mWeYPL+WSZNwW/kqGIuKDQ6OWKvzvlvTHXc/KMkPwrGXMW VXZ4FPqog3wCkllneA7yR/7AGDF3vwRoHpzCctK+jqoaZDFuwFBWTUnEfsHT1AeZZcwx5LK8UIqw MsyIzpU0qtXkyT/C4M13XMgMdEqCJ/WhjzqBCJCYrTmj+83YH1WHZQdMf+778ooY8OjizmLHUyJP XdHeof4AYwcWrhahU+lMVLAfL58d4uob7YxIfaqsuxNzcJVG3UGWwlwAPAJ2ikCw6ZGRmeXx0Ci6 qcmxYQ8AFwr6IHW8B1laBzRv+FNIFmRm/o1YJ3BbcyfTEkRcl9BC9abo1YD/VNJcWD1sHTBZ2TA3 lKIUBmYRIY1y3mVcT6edtUnLi2/840kWYzJDcv+1BvAg4SHlBPqooQDzIDQst5KxqgABZegy8/NJ LWMlm99SVM8ZRa0W/55AAXr06PPXutP81UuRHkgtCYei2PI1eMp8jzM29C2WvIX67MfDuD2Fd4kG uU12IYdp+HFn4BUWmhF3LJPjrh3rSPVtFLivPBtXIKArDDMzjd32HpwX1QmJXwK69rhO1IHCdxqJ seaWnuMedlDbxj6x3Z/oqVAb6O+JuFwfgD1LoQelO2JXJIlgh2rpJkHNE56BLQ6w4MHkgoWRYlya 6E83JXSUBRde12N7Cj43lDdCBoGGBlt6lf78uZ07szl1tRlbUsoxvZnBG0P1pBnRzXuuilCYgKBr KALMPiDW/mgcsGQVM41VNtzLA/Kn/uEUSV5+BYoYNn88R4EL43Bkzn53XdjaTUvvhF1Eu5Hei3Ze QkR4tyT0Q7/dAnhNXXkRX+cPGfoefEp/7O+KFW3RzdiINRpVpTlck1+qpwZqhxgsz5ZOxnCStTyO cOfqjHcsyOQ3pFDI12YfY96wr3XDmZEhI5Q2vhAchuhAv3rOCA4cVIw3Da8YDVMRa1qCGQDnLVcf p3xsgmKbQOEFRCF1eW2tvgyBvP0AM9Id5PbwMJoOcTemxbSRAzmjB4wB9HwwwFrhH8H5YYmAc/ZX ZQvMvQ+FIqo1yTVsF2MWlLanoLLgA/sNh8H7cutNC3eU1Nbbadg7XAR4ufmEDh4u32If++IOdesQ o3zRwcTO1zjGh7FpW+0PHf95LpqNntzj0/XXkdRzFr/eGPrutKLdhsSw/5nnh6xEoLzxXuW5eae3 Yf4FWpRt7lGBEPtgHAAq73qTrDRHqqX4Zy3YDmzdFDypJjK7pu9chj1xZi5WYT//TFCrwh5xVvWF HsPAXAZBYbpV3xS+VCZXtTsVIFn3aQ9EgzBSn15VxeKgYGrbUaTYJLnhnnhE1OdTbEgifzy4e0kt IKPzQhTzVoyNMOvzUKkcpaABlj7BREIiligv7qFj7g7hsCnnr+4ZbEZxp9eZaEYfyR53nLW6FPTe aQdOoAXuu5P/M49iI3z2rz8tvl9GXI7CFLxYKEUzl6XI4WietjoE/gt51zgNEoyRrfvbaj/eUf1K R5vRPiP+AqjhFQYddWQ6fVSxDIIahFspIOyeXXdCjYonf5368NrgopvRNnuvfvtK9F1rtcYGgCTi DSQlynmAuDygTKVDv04eLVKwibvguAwJS9f+GNMUQxsQDkUuK0v3oGd4J6pqc8YkeaGUMEt2kY+A lTnyKOmLToSUuMD53VS1jP8auyEU6aJsTIaCT6a/MUlNfSU5dyQHtcycjWKdZq1JQFduQ+XDt8vt qcyT1qYOH/kpR39JMLYUt2w/FxX2rA57UgkE+hT6RIes9n5EZLBitkum7M1yTeXZfaJldleKqLz0 J9SK0z4RywMi8BXrbu6dzo7ceXJyaf/AOOLkfycQQdZmaUdxOqwVzKwkqGFdDOTbyQDnLjqu++p1 OgcVI6ZiNm2xNyd2vj2qJw4U91WccaflU/0PEK5R0z3P+TI0aodBR6stYoX98+9NgimLJVaNg4wM zThUpam7KqooAI4dxsd7AL2MumSlY7A378bziAJ9jOohQjdnFHPVLiaNqOBPTo7c16UHEbBHjZJj NlpkTrTj+Xuwiwjpputrw/SdqSuMOBWgA9+Q8VLHHobWQCqa48YYByq2VrhUKOOWntNbYt+dcx1/ 8GiVEPGQMtvlwN5gBX3mpym3y4JOsMDKq8618dsrrHuAuj9ZjFkmMBCtDS6M3tRWaEY1clZc762I uq7ZqqmC/wSZlB19AbmQDqyaG1WbvW2NcYteCpSJLwul4pFuLM/3KcVWDWA7EUslJBweYIopMRWn 0dsRJnIZBtodgDtU3w0JoP2+U8LnU1JbBI1YhA0EDlRpEL7vAJksZNh6VrU/PF5Qdo2RNM4jr8OS ChT/M20rq85RMKTqGuzlJVGlX+7DXmcnTRayRexBZiXUcrhXEL1PkkfQiBHsf5f87yeDxqIcZydF KTuMuLIA2KgsD9pj0FEiX6wkKolq8MqG9xvanjP5MOypJ6rbGPCM4zMKzXYm14WWMwkzdx9CmCi9 bu1bxwXbZBRDpAsIjLbjeEl4uYyliK6Nviln7ivy02Bkdm2XqIgRPkary4YWfs6HfJEyfhKgB1SD nQ9BGR4xzaNX9JDgIrz46ddAB5yk9LumUCJhNLm+W/oUhgJiOt9FN3kSwuQCHc1nNpWkgxjO+IJj 7ro/YpmReHVVkFsnjH9NrfYjag0qKvfKVqOGMui/ymGuD8EfbWYWha0TbLg1dRpRLpSDgGFcm5mU 8lXufU8F0fmxOX9SYxRP0UvmuCF+//LE42egBOZsJXhRW9OtJa01vYxQkz6RxfF8bffAp+SFcSOZ jqU5N9BSYVEAAOj7eTosetHSBMOXjePsk2kOTV7wG22XxWnIA7AXI+4lNYghaU7GDiJFpmjyPL2Y SUoarcot5gTYgDkXKHf0RVdrDhAG2cx7rFMxSr+a+lEMCjvt4mXqahAb32226E6N9IEUlF2+a+SZ xNVG6CAR/+MEeINY61dlVvtsqLT3pCrSPKHuCPHKEeDF3EfPYysrY092yZqgWm0aouL0/h1LSwxq 9j37M8+5KFoPEwp4vc0XC6GWnD9y4UHC6JaiD8YvwojyzfAGTm4KyfnEGjp2BvjKoIobbXsRGlR9 b6P4MSWLtmSx2MEgA3fSXyMV0uRtDjrUV9jrXviDK1XukegFtKIMgmougtpTDMjuUPSRZ/KT5rKL 1nuKbDlLdDbAVKMP6bYPK+1nrmskQBHwAzkEgRatC6d2zzqrtS4nRcYvs5sd1ylxxJ1DEHwd8IAn flb+ugm7Ju7SRr1SZ4Ff8MHTfmdMv+ETgA60j5X/DeG766/d+oQqSQBcVymfcb89+OpbIYXwfnMO noz42dvMvEzfFrkcOvb3EnaXDoha/n1NOIWEnZsicIwPa5dDu33OoY0tRW0n/M3TCGp3VfdC3fuI W156MtoMBnnQ9hEfcothwJTFpPFUV5NWiHHsHb4lqF30lKaAuz4gQKyzX+3fKqcrYO5SdwgSFPZ0 24rWPv16uEYW2qKZaAp8aAV7Ou1v+O6hoGbTvF7fKT94L4ryGTqla0RvmeVzJVVDZTF5t+HvM5w/ TmWXsIs+JtOXRIgiAMFRbrvPp+uuE93ndTiGCoFkcy54uruVNbnrShw1Ur3WWARPsr3yxP6klUUu MTQILVkWCzNvpWEzhD68/OKDBIrGC3drC9nycry1mNlW3c1emj2aOVH3s7eU063d97HEvW+h3+7l FEk1QWoPPeEhfNe54Q7cNr6UeuI7HnTMVOoTBPEDBGPWSCVfJzmJ6g21zSlN/DkaMuqSgKHPDAoO MCXiLsuTcr68655oR7oTht4Cn6A80h5lpdDCF4EW/kFS4PlT5tjRNNLJW1TstRIV5mZwNpPTSgAV +UZbd/WsIiRuaMKLdtdADiM5IiutS7mXDsKyXp1s+lRok7uwMXVx9dDdJmQYu/+hfTt8PLktFA+p p/Y5/2L1ZEUfjoqYiuNgdSzm2F2CY8uPBpXAyJgoU8ogH/oadTx6rlwzIKm4tBx4Db8ceaqreWsP nqC7FO0O9GPghZS8RXg21WiMgiA04skMMLAaggSPn4XcM3yIgIwOUMkBO6WvBYXYqoF31ch+WB3+ 7yIkN/hw0EvoJ5YbyDMzXtKBdtwwmRs5lbJwyrzhxckUhD3kIKA737W4tWVn6BX7Zkhde+0PMM+3 NHoUpkyhwK5r7mg2k+0V6nWEjEV3a7FivEEH/Z41nkYTmGeEkR6lF++RufRGCeg2rU4lONX35Ets KK21zjmucoqJRsUD7nW18+394EuTy987ZpqaTsAq6gizR3c7SpPoYyImssaSnMeb/9KyKj8hM5N2 rwtqRo40y/qbyo0gUBb795FIuW5h5aAdOmiMIC+oSP5lRUI5FnCnc5kaLTeMblVZB09MTSQhn+vW xt3CLZC+nxGWUwbQEVAUB7EQ1CgLpPlgSRXMCOdilWoJ5Fp6nncsVud0BkSvNxJwqfUFD5B46q/v dvUlBWhxXoRkaL2bJjhLsLDrpj5txCeqO7M9F1d0IisyuYvg4sSq9LHkvFMxFxI6JvmQWlrrfouG Vi99zGneWZ9Mp6BcYpWVUUsgq+YyjPzl8e/vaLSj5syiOmXhOImqgBokmxjXr7iKnP0He57E2PHn 9rEsjgwoLyB+0LXNXCCdbY2FkW+j0caEpOmBD7qdW5Rb378RmYVxRvglIMa3YE7FpAviED2A2oh8 P4xa0QKNoh8KiWLE+PzE2LWjTJG+o7iP4/VVbA60EmCBvQFOFUuhx+L2/6mjlegF7lc5CTUULjg5 tv/jd437+cm5SSxFf5CDfW0n6yjTwpnkubR32Moz+QSw4aEIfYn7k7PMgIb3t8VmHmOxaemXK6kX i7JBS4sGKFlzjGP7luoo3SvRbvo4ktpnye/OD0XR7DPb9ogeEua3YYiYgCA74o75IKuEfoMCCRcb /WuZDfc8popsPRWwNy8gDznewieS3t+T3glivfVIuKGn8+TcIOhC5k4z3hGOUIhaRohpCpc7k2SC LdR++ahrAaDnp4nrv8fehUpYGdxBxraQ324JBo4dMc9UnrHHZ5SCc0I2D9Dhns2QBhIvb7vgKEo+ IcnvVeI0GcGm+yPrQIfNefLvIeQiWMZYopCEKT03VFq57zdApxRb+VtZOLXRoAQGlWifuuMjPNr8 yA1mmk2hTA1Mbw1l7CsDdOwDcRfhWfs7SQ02nvpkW23gxkp7RUgsNrA/d3VIx8krk48EfLKlYSy5 b0iNG6iOHbXA80WWyky89JQMNti6JrnOyIajGiBGCLqZAZQUPI3mPfd58xy/dngdduuLD73qfdlR KGSrqptd8oqfenIjeSI2P+jyk+xXNahPu+rJJw+kiSWm18UdJx2l67d31VGUSlnuATHji29et4IA bRlvI2XiVDRSPpERhXaPRgYE5Ju6MJ1uKeYKjS1gW0SJ4qFdJzjOlJEZn32k5l51vDE+2utgA9lr EONEkbKK7FyuYjpo3qiKyCFnkoK+zc89r8C1Vhg5oPgiE5jZfp0YeJ0FJBfirWn2sugf0D0UbbrW 4fFIuHBck1n3t8ZhiyNg/zSPNyV5CmFl7S5dXtBhzFHa/uegxoHbF/W9gpkg8vIdqKX9ke5f5h1p YuHkIKPRMQBx+k0ZLSMqqkZznJyd8d6V0v7ElMG2DNrTDe2zgkTWlojQ9gysuNrzO5GaDREeiZyC wUVgpBVga33HP2bosI30yJ7/nCjbrPOxRLqmPlz9xjmE2Lr0n79/yCg8I/IVNGbSZuJMzWHSCI42 50zTmDYEBSnHoGLm/+xFvX/YcVBx6wnDKtBmQ9LBNG4m8La4tIvoQxIABDgfyJfljE1KhSL3Bfxu cj8bEpb+LUSfqQKzOLY7pAlZLRE/cAOVQGz8GW0fRu3Thk0T9rLSWvn0EJUU7EBMG8zP7g2MIee5 0Y8fp0q5YPDHqnhvGo/PXghxVYtWU55VM4LHUU2yLwmi2H0wdpWh3kmt/cXfcKTe7KRNTRgA6NFY uNqLpLZzlFLbf+/hhccVaj6y4mw7PO1kWGzH1gP9ku1d+/ZHwZ/FxH309crmVFkDqj1DNv/3+kjV jV/PREKs0y8UZ4vIubZnOHT820Ol8i9GCGG24m/ZkhTZDV0twV7pfrreWXraXWPutcI8+vQSz3iN 0m6ktg5PNMCRuGJtV6WOuKUM6w+Fm6kg0TH28iZLEnlytCdfUjRvxrZNT5/LoGTre3ZtSlp9/NVH YF6U1hlFJ50b7xYP5mBjTUy+iURIuvytVPPQcx1dO5El6ukO9EXHaAPAnJxp/lF2nyPagXGJabez 2Nk24R4M46e1xudgdg39pEjTLSRXQr5WGMYHg469EGQcbqVCcE6fG4i8juhKTa5tJ5eJprfN3Hu2 jO3LO6iy8emnYn2MNznuSeQJwsMOeJXpM03HuC1FA8z3OdJO+I5JVmPQfC52/xhFu+FQR67F9brF i7ZRGzQOYKSK5tv9wX4Yu/oofPQD2a22Y23c9W8m/tZ7vFhvivs0Cy04k+trlfe1EdLn/trUPXfv 8yiKtJZSiLdfqOvI/CbktNadpJlbmWdY90QiAxPxqe2kXAz0REIcyaFTt2R99mJC7TzSmqgDLTsq +1OHsRQbWEH0s7OkJC23rRXwlspDHXUry994UsiEp3F4T+3ruGSGN4c0lPgX0KENE/jGo2VCnwRi M/RXpACytdcwCRFbR4kaTW0Jn6TMAa3QjBxXdrOUxsK0ojinwd4ifi3hmMQS69vzlxLyKXCsgm9p smFhmTybbMgtVQVuFnlUfyJViPVNt90CDtRkGiLScZWuXJjoNJ7w9ZyIvSJw428ixEVn3SDvQ/8n stN1g2owCvZgSPR8NnXdLaEZfLViL8ZEDc5Ji1Rpsk1BbLnRd5IYEntrXROnc8AEDY2YWLmamIgO MFW8bSy96TwAMtBlNJSyuh8W23MZrnUcBnad8l5TWcRtydbCzJuXEQ9PzsU2bv/yAutpcgfqFsFg Mjj0mlEu7l1yiDbF/PuTd53d+m5jgwRnOF+mesTWsMYSoFdCV3sdx3Dx1p2OvQOaLp6a0VCcwTsP ebAI4vMF8pz252tNaYd1QRENdtLNQnVR/U1+BJIoxCkR8epTZ0YT9mpKXb+g53R1Ay4aCB5h0mSR Q1rMQ0IYJuZ3Tmhsm/H+vj/u8ZknO609Fjn/nsER3Wrv61CaI302c8OR7al1HTrtFTNSkOhLfCqk GOm/kFqT/AKDcgiMQgkmg5cCALl4Ax3thStkfK3krRpZxQs5ivhRVpt6IgszoEUkKHL3OC0xyYAf 8YaA9dVDAWiRB49Qjij+TiOOnBfR4C1sHp+MJKOuAHJCuPxEMZ/cMHUDH3skAPeBYPTRXthssa4q 1MnABOM0HbOZ5yfDH/DN53JSGrwTidDiJ2ujdGig6RrWO6u04n0DbRPOv0ZBzbEy8ILbYywYZ+yK n5a821dUIjLYSpz5wmOflYPMyAXSl0BjlxnGlIcpqTrJA4yX/dMuRAPgz9NUPulyNRUOKolLRI3L nAWatyeMA6pgBIunN8aCvJDHQsHBnEnHSw/lOVjTLAVazI8fgHCiX99+SLwqM6R6xd+Um2lR8PA0 epMPrRIdt6G1lwSeAjm+FP3ZRbMoyHOmKa0m9MFmlJ35+aEDipmXIMakM113x3hZ0rKMCP9960Fa RZbZUCAnzAli8NWNlpZ7QTwtgVx1UUD6oDSwJIzA4jkkKz66hcUA0MBzhwrA6gQ/0wxZTNuqepas 5HCMwgu/F3dcGisKdCQdwlsrJNrTcsO7ik6xuBwnysrrLS8hMZT1mJDzkC+xSUxgkezYKeUNZgXJ /xgNqdQibY98UQtYBhJepVsAtYSdSTqMpswF0Vmx+sOENEyE6j20TbFegwazWU6OZbPncLQe+JTH HnbIyWaFxx/pUHLo7Y6Vb123RJ1GUJZTLDmK04ylgcN1NMQsYeRT+IDNYksKicQxZXGRYj22QQ4J 1Juw95AQA78i3UqhrGhA1oo01nGRu5OtLOw8uAuc5GBbn/u5PFDlrSg4wWelBdEstRsCg6UiPrDh fsuGHn4MpnOkwb2bxjqQ5z1RqIgRnz/KGS5/qD4eCdBOkGCSZMC8t6XzrsR0Pr28B0akXBZXKNuU tMRBrLQyVadsEY/F2wz0raNnR5eQSTagek9fdjB2FRTMCv7Opgzsk3fc6iA6lL9/uEYFYRtSdZKU JPxVF0lNbm7pb3QEM49jVhGzvspjzxBTH80L12JOhHYGkV8KfjE2ClMhbLBEEFc/marS0W/2HcfG aKAL9Ns7//RlzvgPutPPpJLfpaAckvQ60Rfmn+Im+UCdVykkFn/trrUVxmFm9Gn98vZYqleR0uxb XESXhxWtfbGJ0+vWt+D9pI5BOpsBHfFSYpiayqsQ/PZPRd1vFLtJZV++mV8Yb90/zfxOWCiXXKiw QjTfHiD/eqpeJtxVPts/Cow++JedeaG4OsgUIE9Ql61lq1HjMQkjNcsERV5i1rlPk/k8a6s7O1bb nf+I0nLKOT2iFmDcnYoQhM/XXnnASTXEp7gnOhw7c6q9vb4mriZAGorPhs/TUrIIMedYno1Jp+CP 9/J6pW5Ll5BUtkOULa85wM3joDriAcDFtLlJq0zR+DSy6vQzi59axBU01+4f/hGV1pITeIzg1YMS PTlHdpIglrPXKVPG661nOGTx7tDxV7MNRo9/5QRKx2JePFqx886o9GoLbTaXuXX9lQP/v4XOEzh0 +4iHJosrNXTzm5zMUlh6/0wDHad4E1AB4o9K/P7BBN/0772Wfv0Rs/4rKnVP49RFtWAbpy+Ql+/E /SYWO5nV2blgHzm8Js6rgksgG2bC4pq1bh96+sI+CXfaDmGuXbBCwSy7LfcZz9b1PV+npOT/FMfv Zblp0OyWhBpluZTEls4bAYyG4B7tc4PMDgS1NMklA5XsbwRti3C0uMcuMABTPy5KxdKT7LPE+Iw4 utwzh7rQWWY5fxn9jZF76m3t3WbMqtr3xsEYCb8STTKJgYkcHsm+fRVoNrvp2mnDebAIZeSwSD1i 5mIRF4NFRFv5j6uL4VzQsyqfLCWQOHMArqrHNH70DmPWDyf8FJnQ+zlT0I37wpDGYUqFt6EXEB0E 6nwVB/uVSMjE4KllY3OCu7DV3pKyhf5kwvWlQ6gIVOKHNfugU47rCU0ZoS9MQ3fFHYAyiOTBcrc6 FfCFOwKnqK/apIdyIvU6CCGfU4O7yJpv9ZGmK1CmD37lPJk8YnbwSzBIWyIdB/eIAkoxZTP88nhL AvGv+BU3KSpy1Eix8mUgGsMwpMxocCOFllavb7p/SSJyjoIeRDyXvE0WU/4tvf+u88IKSC+exL88 RvulRCpri7VIirr188WvE/msp6FnpsFSi+WymwpYGyx80iipvkcYZCGTV1Jif6CG9/OlpSOsXo9t jVkL0XFtzy/n5WyQARKwQbtz+VpgpQ5gea/RNjdVslTyAyR4/d8s/OX2AjgXiqHBdfjid5Kzd3G4 juJ2gsgVfhNRu3qfn2EShuhwS0atoyrB0q3SZ+XaCLDS2QlvJC7tH13aJD8en52TqjJUy+n1KmTA bPnKJgGhkkSGKz/M3uAHGDaNBk7cgIi+Ff3pSlRY5TZOlYRqs8YI87vnEX2LzSP+i4U2Qkd3Vd6Y 8MGyh/AT95DBJyV0zqYZnS/vk7w9YYHGZBORGPEt89YGf/ux4U5mGTc2Drl2QrerAT41cNVmzHA6 E+4pL/heNsKoIUAShdw3OdQmjdQJN/nmpS+TQiGplSd2kJ6XYxoulPVRWhk8Vny1FnwZFlVDXAoC aX6dd1Hz4Td2+3e8K+kaWv4KdoTjO4xhXArqrQn1J+8qBjlEu+6xDiW6Eo4wlBha5XbxIlDYAj4O kALVKq01bUTjNSYAme9VGgLFHaLhsuUB2FijmrCnf3+nlr7Yx4tY9kyhM05jRyKhtILCCrcazkzU SLnzu3zXBtw8+hM46FnN7eTZdlu54f5vucmoRr7NTRJkyUXq6/+XkrM5jiqcKhpjsIKsaDnfnZ+m Rkto9zUwnxfW1CoZ8OnlKj8/vsLeYfGJ2jShymxAR1cbnF+Vdu8ROHsH4KjvjI2B4pFBp4WCrJpg CcoOuekZGBvkXuQbXzj0csUrIKEmLuDbTp0gQxJ153Iqmma6oemrwoFyJ4Yy2lnNa8YcG4j8ymVy v3LBhLt6AsLcXV1e+N74BjHuqo5tTClAlz33KUtS95yZbshTetGvhyTBGot1dtRHtLrIL6avygPv VxQWAluZE5/c8INXZQI565xPmOdtZoPWyJazLESjc89diwe4+nk3B7KSmq1BGB6EjcjGUVl044sj 7Wtkb5OMat4q+s2lciuC7zh/zs5vhEI7TKR4hhecaBz+YSWXub+04OGIjayHAIykZWwOcvr9LzrM RP+UdKOsmEE9cNc64UckDH9+dpsKeBFiIGemVQhZtNFD6Cly4ilrOYAfjXMC2b3pBoCpQgsQTtSc YC6JxRhfrjPHACxDhXby5reVMzowpH6rkiBl09rZbYwnGxNuhwGfJdw7CLbu4NsjSjFwuizYhVPO 69dNk/FqZb84SSvH94IsT2gZgdY7eiYfFqurYBJnD4G8i8OIgkPa4c+E0aIQfEeueH9D4NN0vMrz +XOM1StYbYAEah+m54MAtgA3DFTyY+pPXVZWsIkRttT5C1J50xo8oeXtojwLKwslUtqcf1Rz15oJ wf+cRL/GTeoiehjyrhP6VEJJ7EuS5x+fKhrLKoHzym+kNEd9jP9a7ivM2I+x1TvUCf6yzvFxaczV ToKxnxhLtNMWjLWNj2EOvBR1ahB+Te9G20UCAK4wMgi+4rpVtisSWGbkpqD6/3jzvXYuX3EKhX0M ckH11sD+CzND9BBBaVf0RD260rvNmCu0Jp3mLclXBtUAFNy9RpSJwAOd5oLDaG7zngp7fOkZ+iHT Zy+Ul4TzdTlK3y+EFWVczkYBpbM0bEPj5XcQaacFrWx34UK8+EB/JIZWSHb0WpjTEu4lLjzAOigc wv1Gmq/KxvKaQ81exfIkgXhBVKOtJZTFMQv2W1c3lOgrhbwzLarT+nh7HXYEy1mXu0u/q2Th9xF2 mB3cxpCOmbpZBmmSyz0PZJkDijAGPd5WMJ933HOiUDLsblvFbh5gmQZz/zdFb7bW3OIuw9kfVnDe 5nEGi5NNzUXcqt/MO80IIGr6R3wGD9iqZY9dwbZtVVByNtbnsGTdS3C0svynaAZy1eeZUZL2Dfq+ gdIJXVIArfoV2WwnmGCSwCmME+L/KMY87tj/JhrOhoK1oDfhcuFQ1VwGlxJzwfnquwDt6/GxHLqI m1nCTubTUtbocAy+7jDu5r/AnqcPqCFHaHjQIEL1pm2Fx7dQUijNoPiZc0Gy2eM1hO3dugwrGCVb +VHKWtpLE6NvUdj9JYP1CsmXE/LyugN/kFsCsCR+M6oU0hIE+p6LRV2VwhDiUa/oX2U7g90h0XJe RUHN+akE7Xc4q0wWng/sBbxqby4WsJRbQlWnFQvE7XnJRJrfTxUpq0A778pSSNRFEfEcg4PE/fLJ VRmEm+/tcmRs+bW0wHEzLHeDLPvvE91UiwtBrWWpNuccTFnmwI94HRRjbUgQNaEOB2FX6NguiF5D PSqL05oo28pUMFa4CEozs9tkeuyhTlR79hNDvyk/ordJ0oh3kNzQfQFaVNvA5iqMWmeymzYttPAI jFYwYidmc+Qyl+XHapcqSsUNUfPf8JwwnsabPDnvR1Um21RPRfhbGAWyeTdEPCTkguWEY83sJ689 2oK08zT7uebA77pbH0g7WNn9h5Ygn2jbBKFOskjp2BQMEOoO7X1IRCYoDqU2Jue7vtdh5IRVajQB +x6Vl7/4vGOmpuJk5pWnF7ou00DZWGT5zm2Ar1P1vHhabx1iW76nGFNbRW8NBwlHxudSaVqxsir6 4sC6mWLOZPxJVGdvNdKlqnBXMp2MPwq+FosIn8zFu2QHOW71aWBifenVsylA5RsK/flj/GYh9egG dOgQRyIMSKuAlpicN1ZIZWiCH6YZyMIn8ieAhMZJ3O68/jHHtvn5u3PKtA7sYva320g/WLhLZGTJ m2Bq9JFeGgaOakQbYqXNllMijOrL7S92yGR5+DxIMfCnrAIqMDq56Sd9eqfd5bAcCwRG1PzMlNob oVm6D333YOr4XEHSNRUjp3lTRkgcFVFy3lztN7k8+u7+k0g+Ya63GR56TOHRrd3/9iIhT25BZb+w Y+HJbBXb1lA/31GNerGW750LzonDdl7C+LgOA+eaYynm8e0Z+HeRsixeyL3FxdWpUOy3qw9rMyzN 8L7QKj3uVuH8GXZvywHdkyjLL8zfEOMQp+7g9498zeicb66WLsRR9FemW7h7hIInsWAUiemS/Mrd tHxOjW0i7VW7Qr8ylbM6vL0NDRbHOTdu2Qmj5Tt4i0N8Tr+htVKWlNW/9HMUNENJ+BdH6MsPvmIh s8Pm9FPjXiYQn30Othgbau4W/B0a+PBLmS/Jm4U4ilKx7nEzxAf/eKLWGcGWZAjFTVbQpmKIAcYp xSUndcJITdGXNanSiTBaP9nsTE2XsUnDoczLIlJi8N5h5Yn6DBykyms7Z/kIxilHQdHHDX56nKQN K31IDM6an7rYHBCvBss5mx82D/iihOf8uEZnivtpMALT7FIGqq8rkNZBNn5C1smltPJXG/iGXpkB nebr71Vg7GSV7xer8y6qUQ3IFA6GIGiTpW7tS19adGLlZcLqMBMPcYc1b12/TgL+bfFTydHdevzo nft1vyjPSkwlF9YW8a0O/Gkjg2cgDr9r1VYfpy0zpQw67vnRDHqjlxciiILayYeDgjDVYqRtkbdu lxh5hlApGfFishyGOFGGi0DNeDrhjXokf9TtPPR2BZzoIeKzOy+fULyObHtZEAkWwCT9pZRwafK8 WMhvUrc1HxG/C/lEQ2Q2TCYN+68/SsvTeJR/fVqaMRXb3LbN51EnTNuszM9twHzpTX64WrXmcnfk /0FI43M1M8w60cOoC/dsVqtI3SVDwKPcq4rSw/VOzdIhfqIZ4HE0BI2rlUd+Ue3/vP8NYfsX/hC6 OWv84lVR6cWD/iAyDdx4OhJRuI7Xu6I/E1ceNd7YauWjqfuVKaX6JxnCpqDTQL7ZQXse5fkfxd+P fwneUGqOsg5ThqmZBwT6BSeTVSvnZiYynDnBZiWEIMaZSBKFdbvIn0EPtPjRldSxZ6fQlhr9q1yt GW+p8I31mF0wt56CdBTo/3g9tVbf0RkLQkksRAJAXU7ZUiaLxrvbPfaqyGrBHTOOEVh5BFDpMxjw TwRLdzet/ORUfpDQF6QSedZTrd6xHq+IPBFgF6DCqEn5JhL5wr22Q0Xtu53x0w76UaNfHrdF4qZs QvGnx4N4waLPM4vgHwOIBZio59Zoc4NS7Kt013BY17dIwwEpcLrza8WQUhJsqEvofhFiOtiUlBPS hsn8BAp7KvzjMGJ0WvNgMR5UbQioX1qynI4FRzfTsR0TcA4YNWh/NbqhXR5kfnWrHMb9zO3O0VVi bPvERBd+Y+EFsIL/fQyWsq1LfD1BaiSRko/24qnw0k4IMzADAXf3SR5G7HsUvuTPr1KNz+OFdWPi JZB9oE9/JUvW35rvX9VzDj5Mtea0hzLN4pMWlFKyNICGe0shB4jbxzDxw4y5yIF7eYoy4PMq2ANo c5VvbK3WFk7HzPlVkCkIqcEu91vQRrBLlfq3WNYv/MFgyYKEmi4F5XiZi5kgSh+B0Wzl8gwKifiw ePQH1aakfi9ztBc2OG89s4C8kCGmdFw6RP/FttDTryZ0MAxXv1TwsOoi29zcSzWE39LZauu/NywG +L/DFAqvyHe9aCpXeOf2+5FsG7IWoOWGozz2RzpXDNC3hgQHM1Km+CZuk29SKZwC+gN4qzz09zHL p6cW+h4SWEb51rAGVaF/51aASHS7yKbh7noxG67a4UcBuyDvyxWwvOALDGziVNhVzQYMVc8C/Pdb 11PSahZ7h0AbDNUVLhyspSQxXnKyEFHn9hX1VEdtzcOG3X8YJ2NyG0HYkUn8vPeAP4EVMpAx9HAV xMePVGrhzyVwCsSJC5H50pKIzagvB7h2Ec9VLUfqVJ8uAttv5UIyxLvkD4N7jkLP+SknqBPNoNAl xGjjbVRvH+uCwhSQ2tnJf0hYWZp+EavtfwmIExaLGSIty7miqrRsorr2F/X6csa7E/lb73GMdpr1 Czvqxw+m1SvoBy5A8SoeZTmevUSAePfX6gpN20zqDe7Jbkq8SaqAmtZYMV9uOkqYcJ8yKckp3/GT yxdIiTaSSlReSfpm2hyXu36ibvfUaAR4TK1LEA3EIpaTSUQjsAP7kEaGSA4tVbslQeltNc2hOufC a88et76s9D9Cp+9pepKOZuHUO6GGhxTtHvQVd2Pb/ahg6VwqITUGvta6kZSy9FZ2OQWdCULLF6Rq x448GujnsuNC3XF/yPkZhc36ae3e7i122Yw4xz+GBwTtscgWkWG/+92VaycKE0tDG477sJqAJ0da 009DQJf5jK0YAjs75HRZ2/WeHGDT5irwCAmw4h5EeU7LBCtRO8iEb1gTnWzfUSchgwoRI4G5q3Uv 6YVYxBpV2iet005dbjaqoOuNxc9zbFv0MkVTjj8YPmkCzqyzgvNI6kSwXP0GcecKoQAeayzxr9je qEqi5XK36VyEtqcmxAw6CNf1x1oFShr9j1YND3i6L6sfBNDINwABj0MQNcC4T8OwKIWlod+dz9EH b7Nf1i2u1vLFNRoxIWCfiAzgd+hBz87BpVI0xj+lzW2IE4sCgNBjf03BzhLzAWoqm3i4B1dqcxjE yo8FJQEXy2v29mkABMEwOq5wVK63/m9EQquVCXGi0v/+APWg1a3laNNjB6M4gmnuz8aToP12CiwH HoktlLmhvAXp1xiqd08mj8nda2VEGQM5/LM+e0HHZbkFUUuizdL4Y01eVO47LW66WfvAcQq63CZJ k9ynUFaSNMAonYyTeQw6wpHin+qVRKc9N4IWqvfS0OkHPVW9Ul5rWn9MWPNK9cIhrBmqcNKxYNDy 7a1rRPzxpUuUR2suBoVbMiUgPaW9vangZ3CBwOVUnunQquQXXM4VlsTVlCTtmQ0Sx5d7F0caapgk rly4vfEwAPqjtpSpIpN2fvHt+rlfIxo3mm4tYeshOwhHVWMNUfzjW0L90LYppogYXAbqatd3Bznf Tbg3/LQC9/Gjo/4NBTD+OMwXDivjCQfKDnaH8SO1150u9fp7n8c8wbYDcCzdUvQy6puVaBel2tyL EG9mKrRCnRoMadtFO7Bdun+5vpNibeamS41bjpBe7kIFmZpA5euWAQDlOLqpzw03bQJ+tTXknCi3 PbUw9mgFNhr+J1JcBK7w19DcUwvT6W2V4sl5Jh0YcranaRF7GGMzqJAaxgaCFmbXG2GMgCAbKTgA ok1sEWPclgMG/HOtYubmT7wGD2ebCPSjby3I7Z39xuXCpeCNkdJm1DFnfUn480nEkE67vBFZu/hW 6SyFAdXzIMDPpourYD3dyvbvmzEP18HYqyPPQbkVM1aihg2eaou9SZnG8nPinwBDPu/8mzZHRCm9 ncYdEsBbZgh5hVAisEAZ3yu2AU4FVVRD/gwe92fV1J9VoNVjv8pWN5rlhnIloCksBV4neQyQN8M/ scEh0weOscftAcHEQ0+taI04vZ4VfK3pUnGvHyM3jh/jc8950uL5cL+hjb/Etk+op3h5xL1Fo7v8 F/ifKHOdLqQbGLNQgpnRyhbgbRXfvmNQZKsrIa+nK61jupO16YumtZgDvWbEfPAMenP2kaSEMSqd 73hBCMc0WTgtmjGA8sDfb/MR5nG8/pFR44ff2HDqEndQqEb9OfLBvYJQRoaI9sQBqnPExJXnZREl oK67Lg+dDX+YmVNi5/JGuzwUDL06qOCUaKil8WbrvOrQMpJjwT9t3d1JPgwpY33Lh65dxDbnuthD ih/r8/gohw+ZHhceFdLGY5b9HmTHtU5caWf2GkBjN3aoaLhSJ84uehnktu/yc5GYHXfAi7x3TM3k KZxaLbMkF1+k6UZGh6xcyc9uWnYesPFWgqq04HaQVuImU9ansKqsSavvZdE1qLrWBHcQSwnmT8JO 47jqlkR643iTVetks9k/jWn6cNi3ZcKTNd8jrICviCxWGyMraXv6zY+KO6/XjMRmiW4QnWwI59nf s0gBogi/0ApOngRjHkWt4WndCxkTEfUn/EoO3gKxPCo4hviKbVPlgPeh4zwDN4zy/mL9rM1PnvG5 qMh08Yyo2hEMIbOHF6yzOIUGdnwivLkG+0tiWXjOtnL3KT6oaSrJjkDcToZkYOIWOINdZFxKmzE1 HSjtOVAKsTzELNrAkmB7TpNWmrkuNktNj1bk1Cb6yw2iFWlP9YspLiyu+VM3hYpcqmWh8BG07TlG /HH03Y6HXC7o2et5k3JLuWyGBF2/obYb6gHZhy9FQFnfgcOGBNVQO5rZOOsUNNl9GVJP/ww50JPg OvxvUOJBYPsCV9qkmmrzH7/18LxCAlqwpBVv8dzEF9DicZjaDX2/o0HR0dojbU2lxPMSgHpFcfXa eL7HxB5ri4pib1oMZa1r1d+MPTTKMNAP017uuB2Ih9+Sp5tD7hi95I9mkZ14Wt0SCFBqHiJCrWx8 hElEqOnyum2a/q0PNtplFSu8x/ZQBrv/zvRdKwv59Zv/7W38OOhj0b11s1QfyDsnVsPZxAXN63ow ScaWFhDB77rHGC1os4/AmAayYTCa2Cu6vzq7fzCS3elBB1VY6Bqn/x3xpHoRZlbxrJbJXUpav/+J hm8cXtlT0pQjqrsopTM095gw+dDUMa3hrOO0S+PMWsLtgMvfw13PuY7Dh+1QqUhzClMetBEUqk2s RYzJm/mHFGfkL72iagTmV8apvl/Hpw7xxXU+XJM/iOvHuYM67LwxAGFkBiZz5CCAwLf8Lh6nPD9L IJPt+u2jNHCj2MjQPrvTYBEN+YxFd+CVf+BMJ/OoQZm9PAsRS/1JJpibVxEEAv3TpWL+G62DvLzk k7cQH0MsvYUrIwQhn+WgddJnJ8X/8foyoLlqOgdK/N8zI5UsV/i8uXReEmO4mteFK2SGZqlYR0C2 EmQJ4YtlsfJlTeVQQc1M+1CvKrwn2jVBwhnF9Fk3Uu7rWXNioDJd3mTPwqTnGJg2gHydxHQ1DKNj 3WXEZXHVgivQGqDqJH8/YI1H9skkJhNUhydrKMye42rywQgU8f1/aS7ynSHM9yHm9I9SGnfuuKWi 8VPT+AurUkjGii+EWgSTntRh/DfMZT3CXIYhkU8QwuC3uKdjL2Pfxx1sd7203Ls650eWtMVJt5+f /Bn8+BJXwW+T/k/2SREl0rh4IiZmR7KQXY3es70TuvnGICLq1p/ryvpUI6QuMZENzIsGAtttAwIv EG/mGcJ6dH0lfCXlpjD0BXQvJFixBuEKq4FNIOTWV02AE0/ABJZWV5jFsYT09Box8JB7LmnkdMFa wbtdDO/zYVAV5EDIppsFN6eDVi6OZ/ObZuPMT6BDijMfj33y8DU0Xj20126+ZnlNuXH2ncS/zixZ XFmcJtOBqJSCmTCI7oEylsDWQST5xP+EN6rcepBey0vNLnnMSeuZMqN7qJbHpCXukynlaYVF3Jw3 e66EnVv2b2JJGUKJlRv/RraqK3Yls2cRIHNjIuLH1iY7zrd4yhXXPuuDmiPzG3nYmxejlrT/0Uew 2xtiRQIMwkvZcuTsuX5v6CJ3DWsxkuJJIrlA+LbC7eujMH6Y4j2eA+yzkhEMxhZVM0UU56gVYfGl l+QhJeD69Jqod7VFzkhxo30dqFImPJUGWUYOvWUwT4M6a0UToZdxoBFGU9DmAstnchVNAfDnKqRe 3z9Flzc0lbwjVEhi7UtwGJ0CaWmyw7nRPfdiPmLi8sp06ME9IGs1EcHDp0NdzRQ8s1AW+r2L9lmA NwZ9hCryXvqS06GH9uwzMBtEEDUyXL4bNx/krCxyn9epHyP0ixjQUQByDkLTxjQHNeRugzwNg5LG lOw8d6G8caQkCLnfO7KG/AiCm74mjYzZ71v/S2kLkUS3XNitxk7XAtddFreakU0vs9I4/+P3vz70 5jpeNE8qv0Erbqvuw6rcdAKeKIpyM46y+y6b/d6ie6BAc6eJug45xsGqgarctumeSgfUUqZBBl/w Uca4p1gdpLX22oq/orxZ66VlOorxtxzXMkY8RouQEwKqBmPgg13O7a5NLhbOasFYrZGtynGpA3XZ AG2xbyi52DyxRsWL61cUGGwkIGRGTSx3y4YSAdilSVyb5qPKOJMq0bO+He6MX86r4HiqWnVYNP9N y0hjhsJ2xhzqOTgYduCM0Ss7xdoZEK9vH6W11Ae9BCEYRUt92BvOvFP95V9NlOGP8D43g+K9rCJD MFbCFOxNTmpwNcyEW7zaDp25IdyaxVaT9bwksae2zbLcL0nbzXQlzBnRUqUdIScvgB2zub/HsicO nXtewAFx3MGitp+VuqtCB8HwAq1A7FQZvpW8WTXTsk/wPL8vdpi6WRtXo0B/G1pXWlZn3o6q5B1g ZYCInouf0m65vbOWZPSkTCnuTV5uEQ7UE3btBCPM6MCnzypx7uIUqEBGzjo7O8P2u09ahCRotety pVnu2MS70lrAGcOYLlg3oNzxPOjpyn59jWnCUaMtR886g/7V4VXjSZT/WTSPNjH7pCNM1dViRpLV 5Ich8ZiZktns0AAH+7QARtOalatTTyxMBvOJ1O8rl7PQOIphxsyIOyia6G3pRYE8z/M+p0RA1T3E m11MCVNqwv3Vg4rrPz1atCBDZUp85y5gCgWi2Nq1Co+idUXdL5IAsk2QEtnVQtENg2cpfzpewgak RpKVa9blf6ayBjVxg14/OuZLcSYSBVEv595tmwQKj8bSwwoB/hMEVs6CNLgOsamkaFJ9On1XKQjf Ay2P6fN2GOfurIB+208yovCq9ra2nk5aPgdHNaP0sApYvRF2vDcNoBuV5AitxOpqMdzDlMXc26gf zKVBvFOcTwf2PtbRQhH0Tw8jB5Q7HqSqz+CvVD3TPyYweE3navVHQzBKHCACPzFGnt4vlF0Ealk/ sUchZS4MQvHo/D/R6BEXQrKrkynNUVRxEv+eiweLjjq33zmr5olOMUSjmeKYF2nkQb20WnZCdlbi eRocEijsuWYIqTVuj0ZQdqsFT3RKOBoQ6CKNBLK6F0+QY3Ak6NJsT0mDW9rWL1LejSsC/s6nuxQH LLWtCcE7MXBitx+UuxxrFdqU+HN809jZmZcph78whnS67Y1mjTtri/ZWus6vhUmrnDrk280V/9Gw ZanrTR4KzaGFHab1xYkYUPV47/k7dGUJ9vhgHXcHyIRLAerOfxU6r7D5BOZpJEdHPtg+9v5uFjCb l1jrDVeWTsUySA8hg0i+pqXNU4T4oLvwPIkYfBIREbKjDX9IXMww0n/gbL9Adfnst/g0PKzRHb2f aufnn5b7giiSOrHPmXxLXrG/USHKJcNeSwH92bGa8n1QoZxaSmBjLZYj1gSY0U/N7lmBmpqUpmMI eqi3TQi+HRatwvQyoqFhAQQq1cbpHLcJjS8AHVH+lqEbUqDfEZ/0QUU0DIE6b3CMCeAv8+o6iWaR j/1oQ6PHtH9hK9DaJYYO3L+WMpncMLxGAtIFuWN/4XrsXIo4vo2UJNenD6CE8JftFR8cOeFO2Vxj qDyS5r8HI5YFQNB1td2x/ieUMhqm45qr6MVhXIfML5YSaKc4ic28ILfK5cy6JdXqIfmJp3v6jVe/ MTu76cle6Ggdod2DAYRnx+DU1tEjhKOr/2m2EcVB0oVEahLW1/+Hxfxo9bwNqKsbifcaJ2OwmoaL +Vj/eF7FwB7Vc5cV+XuthTxRehyl+dLzcFarg3rNS0a3Qsfeku7F+n8IDIaKUim6HP4nPKAc28gF T5JU19rg7o439dB+WcVA7PJy3UpO8h2hAkzmXWqA3kdip1YTpSyYL5knTkIuSlODTYj18g80CxOr yhD1bdKnckfS4sUli8tlukOXLcrfUbsBBu25JwYRMQuF7GkZKCCc8C54ojvls8rYzJwh5lkT2aT/ a1fsrpHl9789rFXPQhx69ghrmdnqEjHv+qqJQWjEumQvir6DrnoHXZjcDIlkJz87TNo16rVXpC2J CKccGiJLyDTVJKsgAd/HibW85VD6Ls6WrX6thoJf8KQ7SbxzahTCwSLG5QWLszDH6jIB7pSwNAzR stv+wMMHGNfiuq+bfYVwkXZAPA8EjuehZ7Z1BnvzkKKU329/zzNGQVD1AbibHdUlWSrJUWCdnjc7 YlRdQxP0g24wd8u3V6/P/103GkdVnOeCpQ55KqkcIfrsLbHvNu4LaVx/xcGb/ODiLpmAyJbODlT6 AonPdODtFwGIUkZ3AYlyRH9TXIHSKslnhZrfNmAwZDUk5ofuRSeDchbn5UBpiw5AbyB4ttmj5P0i NbuRxGYS66+CayH3XaB3b5ZjwRXayfZWGwuC2UCafcn35QhXMJs3XibdGtaIDXkNeGy7w1iQM1bY guvhSGbXgFmNP0LwbeC8sXqe+62es6l/gJqpAmykurocBewEVVMaAj206XoGSemEYvm1/SQb9tay 2a8YGF6NaWmkYMhjiKNPmq9hXiIulFdTz/mxe8C1Wl+yKmoOFvwBplgZwi2Scgu4/kSmIYqRyVpM vJ6mIQbaRxtLoKcIz1HZj94ZNKThrB+HDwjMR6Vj3oxVFCQ5e7Jde0ULW0pUXmpeO8ioZePQUf1G ZwFszZvhCPi4kdcQEOImFvbjHtzK0k8MS5qlUnIyeb++idPgadqhzyQCJtkjMORA+6JbEl7uBTaU rFM7INLNL1KMKDJpUEzWSjJop8XCOsCUIkwEZKBQLpomgtghrpt5UnbNpeUb+EewPvXFLnzzwn5b vslsoBgsnH/M6gUQe4seezEE0SEGEUMqpuMeHeR0ZPYPh6zfHyoUJJdKQqRaegVsqVnU3La5adt0 b3LMs+vRv29rjqfTKFcPMYQZptOCJPzKQkGsmmqxH88jdUUrKnqa5dCS/TlHij7ZWGt40uldOLrz hkUeoxfyUxDUnnyOOves5yo2swtXxraHUOky9gWk1LO9yU8r/fvdqkK0S92t1X3d3wE8AxezrYlT f+XfynhqL9mrFmKHhba7VFQ1RKER5O50G1SkXrr/kskE9dkIT3HQ1BGG/5wYU2hGpsyDp+A1jOe5 9p//dZtXNzZI7uwdtNVJVipkW5Gr73wUAkx6goasgz/CD/FZGfWc6LJ14W9D9ROIRrlvgahcjigH srDQWNHxUNl58Fyj2K+0y4V3hzfCLtkPgZvrJdnb1eJO6ZiYR1NU8IjJw3Tn0MuF3aghalkaZgmU AGf8L9MDQtD5gpVt1wCm0ffx1UEAXY0u8opCgjPskifSoQ6GlM3yEqaAclmywvaHHVIznNzTCTho oCRa8PaBKpiZTDdWo/Bbxp+HznZ7NYg44udDxJ0l/ocV8MzE0MSlXtUwgWX8HZY6SmmEkvSJ1Qwl /DOfELKQaCilBpa0OlnJPWsXljA3c5cZ1mOcNh4/geIYaRVa7nkc5X+PnMRFflsEWfUeqX2EwpDW xFu0Gs5NNWehGDN0I0UlMJhg5jjYJq3icA/fmGMpTosEoFemA8mdF2FaPQ330YRegnQ9d/JUAb26 a0lAPotlHsazP0tq7FbCCnSqgyAUq79J3hhbTy63oi5pmWssHcfeGuiCHl68sZhI6YZu4ldj0dM6 Avn3QII0kLRju/X8esL70NV0HYBnoOCC28le3xyX83t4saRTPC+jMyDf6z9y+sS9EweNgWvtvjah mvxXsKN/O4dNLY2ESTllWwfUXHmB/yRVQKibKatCqaXErPuUVeiAhmJVw3GIS2KUcjhYm7knnN1t WnV+SjgnjnZk7SO1xutqICI/Qg56ikA0upse223wndfmK6xfIVUMVVDC34Cfl4yecjsiQCgqAkhY VQiNYMNwvrO/QTnDVA0Utas0gtI+yd/iX6j94If7e6eOPXddoSifQbSD8dh45HCJzYy8yxOZxhQb DMYHw0VFeY49s48cMtAzn3mgvD4D+sUn/6mK7/W0BV9vUPDQmsvK92g6Sp43Ti8tzndPvNGlzQsW AIKiuuPMTkr51jpvH7tBMTBqEdRDuXD5UuZvU0U2GxAd52BpYNtcdh8pdg+FlIxMCw70tTBWdjD2 ANy+w4FbHRqpY4Xve4oAEjDIy7VI3jVM7VGe9wbBg1gX7uIxdMXIAjWseXzc3k82HhCB4LRM1CRg 7BvHbfhyOzejJrRBhbqVcctv1LIfivOzza7JI/WmlW0CCMMq8m5C7PR0GDTRBGeW+YTFZkg6sL4I aRRFrQw6qWbrm3jjzAkXndoTndWm60kLV1MENqXX24peHDOIXYQM9rXTYtnF2zNetHsrcc7grQF7 hNg5iYX61pXa4LWj/HIZCMfVGApxyT1frMzMJsSGSAcDeA/jVe5kaVUE4WJa5zlBPFDsXtw0YKjU ixL1E0GgdcI+ahiTTsN0wkkQ5lvV1kLYLt7Y3xmj8meqyS3GesCPurM1CpoIXLpddeshv9n+jlrV qiB/FYNodrH2ZwSKeMdeFDa4sMdrIeS5T2HS199TrSxWPOF7xSLzDaHpNp+QDfxoLiOs/TBdOnQ+ C+O4YwCvEJDhfkf/ApiqHyAFSR60/Y/GfIQbXYAqwDbP5Htgxt2AocfljOBSEUa9N+FwbnfgTbja Id/NlYbY2+yl96Fa2uQykBcB6SbZd51DJGpTPPhvZhXyxnUTvul7c4S4wFjwBUhKz5DpxFbvICW3 QGqMucnJkW8ELt5gR2U44L744a630yXEkaaB/P9tzeM520KnOx1xMPmXOih69w5Kyjz6gfHFBlGq Ry5WlWtY4edmjkkbYl2m3HeAv7l9rr0hv+6Zb+nFhqIjc4u+mDw7BuV7enp7q2ACQOJZdNeNCLOF l3gHl48hZV3rjkMtMnZBgczLe0769PFZ6t/Ay1aL04EbcKiY4Hj9k9fV4oLWaYg5NsAI2vuxRLgB R7bW0ozGa9gMiPme9rxnoCEzguB1Rlp15WDc6llnmx4q1fljnLldU/HtV8wgAy8+vy74raqFkP9Z MI8AmDGkCNni0ZC+mEnbE5mQ9v4a9PCeEC1uIZBtl7PjdcsX6nYd43NkhGXaroOv1O3UbPlHA/A9 kA93BI/wHc6MfrLmAhxGZm7sfgaHMAtxwvSw6QjtjzuuL6TPoHqHdEUWmYVlZXwXqVjlFz2Yt33z 7t9Vt7j4B8JUEc932MnfTBLNP+0HGx+VnVRXVfoK+vhtdJa+8Y7voYqLh2wNoZ8Uz7NbgaAnmRwQ 4lFBWjGw7rQ1Mp1L/z+d29GSUd+wl1nIcfy59bv2u26Lqqq7eDp/KKyzHFEMZXXbcJzI/mOdgs3v oH/Sh+Hi/d/8SpIbOBrf95jnCFmItNHyYiZPY4Sy75JBw6I4V/3DzEgjpY4+CfrD50FJF0/Fes5K xLt2pHKU260ex+507O2Klg2XzySOGQY0fNhjUUGYDV4A7vjyjzRHCRQJ53CALqE2EyU3DmjOsWJz nnBAbOX7hm46iYPoICe8Tb5Fz76dvfg7FYtZ21SrOAAHu4i7LjZdZwanejRVLwvwCF1J0nD04k19 9B36Ij6y5j0y+awl5f0446XGxemSpflKjO/RK8KfEUaP3JoHFEgmtbwGnLLe6W4wRt3VAj/TykxF oHDBuuXZ5AHUUMcXb0VjQJPcc5mVlbamcijOeVNkXpA+7Gxm87Kq+ucZYx2fB6jAgAvsZ4hNfmXt QsHVoYSn7IQMUDWYbDVrSUG8R6SXW7ZokDO15EBORZ+8CnwxC3IQiy54t88+oesaxizeSPqUg2TA fQh/SfHbA4g4nFqM0UgBv3x7+eitAuUdVuZ/7yvCD1u+LvFLa9rcgVpNV8j6BOJJGa2pszw0tZCV heh5PyO4RKSGCABJeQo56KaPy/wA0SKwrwjzUl9zpz2tEzpypWdI5C9tG8ZFGyZ9jj6F6Fwov0Zd GBvuS7l8+MahxvcK/DXz63FIonQq5XaGGlJjjlcibVgo7/p0LR4qICAqfA8q1CZErRd6vEtwdyHv 3BJ90z0LqREeXioknkp80XwPmczZaB/gOkE9nh4GnM+VExnNxbIyc7JkZqWz+5HvNKvIyIsKgAzy iw4p5NtQblaSV481v2FvzInugUEU6xV1Cr89TY5H1kjnY3vVhsrigU08yQThvWc8Du1bwsTqMR62 GNRnxYkCoRUdG3Fyn+DtiS9DDFRpX4KdqxGqjeBoQ+0QjlAR+06KPXezOtYmtIwMaLTySuTWgL0M q9DMDNv85Ch/1eacGr4DEnRHUEvvr4zTQubeE6VTe1Qq46LbF4j0QMcXqq+mwHSp/ybM2r+ydpdt kT+vdew/UcTJMWi9jfmZ6eIKd+Dy8E7Qobi+2GUseAmrNXfakLbFih5f9dqhfYtCVEdwpplOubKd r67hPBeuWrFzsUM9/q9WzDuaS2LsFaTbF1MKlgK7SRBoSt2FtUW/XqbZphx9egffVOZm0BbQRY73 faw0doBXZkSyqacGGOcJQWTFMi/DOJutgNPWQ+f/LFCiiU5WzQmYufqhyssIWTdkXme9PBwFYWwV GSNkCoREN0Pt4DCbAKcksVoDVQ6PVNm8zigtJI3fKXZ5TG++aVxKQmr8TKhhP6594uU57VEh/a3C fAj3dethhe5cQQXLgL0CADpD/fZyVEfwsOP0BwOMqePL/1bcRK//7bBayV9C2NZw0MdIMDg2kqKy xJlk+vDdTjfHF8sKzP8E3T1n6TjVwZAhQi6OnngUQrmo0zTqwh29+dAs0AC0cwmXZyvEhxqVo3yV uRai7APK8mA59/JzbvocHLlt7cCZXZTfYpmaSMqD05v0lsRx9han6qb2MedySMA+YtSM5DMpUioR G6ZNrx+TWPrrnHnb3zNp8ktWs4W2vkjsVl2g0cxLA9N/jccGin3vYfjahgmiLU32cZ7hpvYcT78o gYpbzZtAQqzeWYFX3XLkhNGOMR5vdYR6KiwHkDa8rPgGbrhMeYyX2rwTJsbUH+JK37O6F+humDsl ub3UsGbpTJ+s+J0ZoJHr2fqGrfW8vI/2wZ7797q0ECxD/VyggcW8ORNbHQV5Q0UaOww+W3VCmskm 9pXG5I0FkTzpLRx85TYa3z5le6JtCk5UUZa0XDebLUNFDXi+8ED/GMPuBRrhzMB8BA+WQ7Ciiob0 VS/wNCiYgcWt2UlM+m390VSUofmk0uKB+Rj+aGpaLGILHpaOL6dd0fXgRsj2jSYgmfh9wS8SzPTg MWfK9e3oNeQAshh0Vw2hvrGBPAqxsoY0vNrsPhZK9Pzi41UpO+4YhUw3LxwdnKOy6eE3SoGt9oHM GAeGq+u/GzYYCF/NIYL5UqBzWY5r2ba8ATEXLXvZJDB6QMhWh402JoBLqbmTOs/NNah1jPadsyUq gFTx6HjTHSIsPH4wn0SC6AMwj0hvVC9HDRbaLOlJRB/6WRkba5UH7RkZpgGkG/AqM33/LN22jRbw Sl6700QmqL05yXjcbbyn3EgZtPBc+3OLPv5pHDXO1BHhQNoDOZqAtfAmS4AdIP+Y4wyr8KA8dHKk BkX4xtLHybq4Mag/LV/y92eootnAxqdXqnpp2YccVIqRGHzi+txuJNcn9MvYla5x7p2+lV0OJD9W Px8SKKhSbquPELETW4WWf7oL3ZFuM7gd7eScB/2ZpjrdIzFyHc60VHAPBWAcpr1AoEinFSWrtu1b dSf1f50E28vC6rgitlBGtftAvEWaefRpPB0L3qeNVD2aoOX6gd3KccOk8+ggYTEBFwTQRSqbzzhW baztSRzRxl9of2RHwgIuc/X4QKk6pXoZf9qIcCxi8W8uPKoLD2MyELa8euNrvW6aYE7VU08Npq9x CqLmQzuYoe7VyG/JUjMVZ2zoD0Am1ifS0GwfogVK3qzHsroQotIJ2b/GDCl13d0lhDyXcfIukAnp r75BhjlXnRQ/E/4zmWnak1HmYEGSvVJZYopcZ1CU9fxptKlegSbmM1evTI0qBizGPKz058BxaeCw OQjPVCWi421vaYnYNOw0RHr5aCbF6GxWKi74ZbHzL+Oh3eZr/OKlzKaXKlHdiHxegcgnU+5z+3vN 0t+Pv5QPSzKT99GqukLBBGvYmnPQQzcCwsP3YfAtmV+sLrtRLtni3czMNfheTNcmvEtXXexvNk/d ERPkq0byWRMdJvB1jW48XP6zGtm9izG62GKV2yHxrokw/OLi6al5VVwt3aaHqqvWDoNfhzqdNJ93 y25wd6LwHKynH7ak8dQD1iG+nssUJ3efgGcesR+4fxW/+u76eCnUM4i/dk+DtBRueTQIJfHieRyZ 6A18/G4PFW/eGeGFf9ei1G64d0veCqSs5C+qow3mMeYqtRZFh7joePRhKcAfjyPU2Fz12sQ8iauz JXkadA9hjWvHWczKjoV2CRP4bnHfSgyXBLMfPFFmvXELJOHen4yerAubQeGYa1JTxm8/VTquMmjW Hh7FprDCx29XyEbxtv+T2POmxUoU5aJdllc9ncE9IAcPTmgwF7tRzhVcEZ1B62WnPfLjvE/l5mJM yY1OS5tyYbqW+Y4CtcXQehJvToN5WPjYTaNBCfUodvsOwBA5fdDKpELir4G2hXlyUia0A7ad+Xt6 HYhbL8iv0q+hNnrwN6UDhNm/NMdjkzagUTSLDH3CAc/iXHyp1amMwLo/EZp9wRfztzT2GOFObstg iPt0YLmSM71xmZt4DKPS0s1n9fgSGrCnduMrU4dMrs2msloD6OkF0QyZmNDgNm7gjekbbzNF4kcU dw1NNig2CfqY0NbSByRR0KT9k32gg6pHznUmUp/RWjOsHo+rrjZiee+XLH2mu0dkH7d+kaezF9iz DPI4rgGt2G4WTKjAHJHt1rttj5Z7GoksRsgfo3XplUBH8/H72D6wP58nVgZmCW9RruZ7ALwrn3hL iyU009PlBNcLwh3uIe2944BCxBRM3sbcPQVTeZRh94pY/Fw7S3hkSoEY9VhybbIXqGJQCpwI7Qm7 TJIL2UvXldoFtmiyTn9UqSOaP2fBxZl67EUTm1EoqUqMsXcWNGQYwNWUVznzO/CQtUqyKcf+Hdv/ TKM0xPBXMcvnyDjIeqQ/jmJy2xoVq/3YdEpPI7dKCuRiBstUFuljp1r+W/iGKvS0BF/uwYch7tIL 8OiA4XoUdLsrlw0wY05FCqHJlJ4vq9CQpNHdaQZSfTyQzFfePMBpl7x2iYJGOE4a6rwbpTPJbawA 8WouAmTIy4bdF3CuT/lWJ//5QocGe6y0uRxhxRZ1ws7HicoZNw2xlHlMdJsAOyWm/zHBBCBXaGwg arLT6v4QbSxyFmyWDDIgPbleP3OdKaILxzywmceZARa89CSGrlR8AUlQHDTgyE1ed6WYuqEKcq5A KjObORxABjcAwL6ZIxzHxAsu3sE2y6nZMeJ7sKnXhV1air48+g6xXETAgiLfEdUeu4K2lFC5f2sG J1s39L0WwQJamBwlp77LCv3EeVCEo1Mkwk4B6rVTg1mew+q+gGvZph4eLr3/cmcEq+llFYVEIDtb I0ismkgIOQyzcVdHa9ce4Y2DVP6cXLKmatNXDQDSQyTlYwBt0MalJQaBemhx7klI6fEtpk3E48kP BW5d+v8Kydyahd9rtAnob5W7iECMbFo68xY84aQWCeeIYCXsC7FO5YE1nGMZpZRKbNDWWiFWd6Ru W70rgOjwRwJMVduKuBtNjsSAxAvuBbk7ee9Y8WJ4IHf/DsKFx+sB8BGbl241B3xkcJaYzAONUh3I gHa2glNiGp39uz2HmpTeKCcROzP75xD9fWLtNwVK8NGZ6WAzWopwqjOoUvM3UfUBjkjHRdPr2noR mNt0aU0MJ1fA5t2gnAbHcM3Q7GCzQh7TZhPDTCVT/Ck3QKgU1sKkeAOVJAzvTsoWWYEVItQYxfi5 W5cxg3SDosQEkwrRxMCJjjDOR7CI1Jr5NNwX0E9891sv0dMaMpS4lEd8AYzxsR3bNgWnorEkaq0V U/82cT51l6sUewSm/kS9zcnZ98iPuZl6q3Cts//9Ry0TJI9aMGs7nQiAWXSpGpnScc0nzaqcNJqr kz7yU7net4Yq0BRjMLK+/SUwzEtj5q2xefaWgEYoi6DykixcGN4N4HblX1R71efn46/Um4Z8Ei65 cExUZwRVxTIYAT+VJBasKIRs541HYix6G4/ksuR+n71RLZ9wlFuyGhVQHhi64aeBkJfaIHHNkzM3 YinooaGktv9X35BJD/rzlfrG4HO+LblRTCb1fRpSi11qiEIJCL7RVSWAyyyN3KLKCoUjyLmCpiJV zpdZsD93fa+7duMn2vmuawVtnN5aHUVJE5A75KX4MzucoBQOaVkMaBGTjzBGCiX3Fydvja4vFRxb nsXn8fsphfepfcmuGOjAVUKc1Z1NUIpvDy5951CVaJbDN05Ev0hcMwv5T4+WM1ec4tKPDKlXAKLY m8mvQlUfJtPyW+Ao0rkKxM5QDSO+YqCUoPZqjInSBDg6mVo8RgivMJC0XZVA9pvepz4eCS573//j uvxbkbLS4VuikiNH9g2QvMCU8mzXj4L0T5vYHdc+/leI7qLCkGsJNjdIz5UJvUscPxq0UBW8iqFJ xKacS3W4083g21Nw/flfY1Whw/B6uHLpRMyDagqe/ifr89ev7+Gtz0BBRXLvQQ5OAPrV1n9ufaf/ j2UARfxDAvChnon9XiCSyd7s29KM2JwJzgyClKHJts0ihUs2x388oA9lKpKTTlMbmN0CSDBDvWZB OIhBqgkn5iLlyvvEWIY9sMdCJoN6WMF/IqTvP0Hbz3vgYYYHnjJqYU4bJyTDZz6E7xHGSsCH5HV8 zw5eF9gi/uByZW0upNj7P8grLoJq8WeWzL+b6/0S+D8FI/duyrCWnsH9luxvh7Z0no2I4VOxHnDN YdOGsJoJkCpCDIX8E0PS72/YyEEVEB58u7isIWhncvM4k3rwAS/DtpjI9e/f8B2O7dao3gWwXizD sDTk0afFS8V8a6kIzuoRtUYOaqQW7/M7IyhgOuweTI+U2BjXHtRMMQ4QHhq9DsuCCHt06klMDZ/r feKihvRlrel1M5At661nbTXzSn+IUQ4iB/cUtzIbbZ2yy6nAAI1jjZav5f7RtPW0Zo8k6XlxpOS9 0mDTijne7GK765nvC8/JDVmyR/nqp1YeAgdOPF6kF6Mwp2+i3oYmz+HjBGLtbotwrDGKkZwGPi9g tij6TMIKP/5BUJDtSaMzakQ8AAaXXDcezaBezM5XlsvCH6yVG1e6xRHNG0Ax5ho15XLmPYncayaZ nRKO73yWLWIAkjKaPHM2gtzY/Ihi6IzY+yxchFVpN2Fr3WLkrA3Bz9hT8JBVGDZI/SjbYMwjXGPG 3fwODjP7HyhBBNZJdYxjSdLERI+fAWrB5bLH7SziOXTbvIgFUsfG/uZ2xQC2JI8EV253/ROvjp0V Orwd3NUSCWdyUjBFk9TAfSNG1u+QJWhOc6vyPt2qdk4JY8hMiqFJ09YtcUhHWwxza3ysyjkIl9Zu 5pPx3RaZU7IRZJiTbMvTzCw8MlbU26/K0bKzjVRZGX34N/9gTXCs1LkKATHejP8WDyd73wR/zWgr oF7rqgw4bUwlEq3bbpr0k9nEwVXEKpwd4XIm2qR/pIYFGXPnF16x0fcRtuHC9D71JkeuQS9gJO/x uQ0vixUxa//AQWNQhv2nltaOO0O5YxF+13iS/Byl6GYm4NNAQ0lT73ktTlvhPvTmTRcYfWhotgec 9P9tzxQwhIDh/gqPgPLNQQ+ERzMYekHt2P1TJr1izPwUVeVEk42mmUBs/W/G07mYY8PO/CY5rEJt P7bIddZ2PtCbRKCKPT8D7I0AgZ0Pfi1Fc8mN7IX3xmu0UH4wr4YEiRMpQIEu+GD3g7OvDsmAPX5l A8bAstxUueFVC32sQHkK3J89ytQXn0QTQb7U6qow95DBkent1E6LGi5b74WZq2o4m74au412D3Kr NIqMbHE5YgN4jrIJVZ5GCtsLEh8jXA6FZpe5bHwdURZNNXuu5hCna0yLMBaZebq1ffh9UBVupisX kkFdPj21ZU5KAuRWK+FS6RBtkN0htn001uR8xUE/MvDVSE9tJ7dYQd1RN2YXYvb9zNubXstBfB7u yn2Bu1uhS9A5nEY13wOUJSjqMa4zw4nz1vcvpXRv1GXpl8JVjv+P9HMUCb9d+Rd+jRK/NhKcHGCP uwtcVTu+isS2a0uyxXafI84/ayeEaL/qh/toDkJY+9pCHLqXkzpyWpQs7NmBM1iRJxdzGT91uH/b jDPL0zk3ZX+Ip5/QUL3Nsu6a5amSRr+TDBMc2LyLZTmTAl/tS4c7dTA1F+3f/IVqWaaAsKKAtWSm nJemQZb98UIjIN5b0o1SuVjJ4mz/tzkdfEq6FJMkc/dGhTor5n0YG/3xgvq0GsC8N7qRZ6FTenv3 2Q2EY1ooFCpCRQTwmoDem9kn1P0i1Y7LiyMH8Ik4Jj+AkLYdcq+MZM6vlQ88DfIj5iY1KuVUZYMX 53aaXQskY8yhjEB4kbTwnOM5zeucuCShoFxQ0UDo/cJxYYtw9qTLFhLWo/FBmqCTKKyxNfUsZShH b1oAMtBQyqVM58OwqFjI0M6hCsRsmZILftFtjVID1XsSpnCrlgFhsN6pLt5JIOyWgGCEJvVFzpst aRMV7/s2ORdRXF+MV+Z74yFJq8wdx3N11eQmzgSG6MOz2hxExAd4rSWPoqv6jqdPgDex6YYtrakI KMy+DOL3ZQGya4b0Y6bIu4vGyDr32uBPJBN9Y47vRNF/OYgn1Bro9QNjFLUjYBajWaGBj276QUpL jUvNEvgZW/71ABbsrZCYr90II2hK5Dd//Z/9+Wlav8ibtK/tjBeYp8pJGrr3CFmiLgK8pzAeey+G NLD3OqFaJ6h8S8mEmoD7zIr9sXnx3o+RWSrX3Ph2W2SZolXgbArjbQTj2w1zFwfElw84j/HARcOS Wxmfu0OBRSv+wvLdLbLv0JteJrWDxc0oFZmiIt5MiMEomWUfhptVxFvwnbTRo4tzo9wAGtNHCy01 Fdfj7LdY/4dma7kRVvWRK+vkjPcEw8Ei97WWzTNLbQMg9unyUOoQdV1nwS+0ljV5MQYhR79fskvG 7QsGLjtecl/d63iM6ZwP/1mppehoDTpy+EgldkfSjxuFCwliRcVaGfJ/Y1GU7RsD9h5NAg1FjTzR Y0jiqVpstd3KaGLyg/vfod/LYEOdIcemrF39ugh6TIr/GBDpB+23FqlhbXNlcN0fZEwHN65T/mpf rflqBH07qSQfcCH7C9kZaAOrUzOkhQtvcidaceM8AZRzOC9e2wGhWI9Ff4HMY1FEnwwdFL88MiAf V1pxkl1OV8+dFYvHkM458BX7uttvSqOnsV1zhvfQiQiTeBNCNLOVbNy81jlVir38mYBZhr9rS8xI ZFeZMgcqFBpuF67j+mnRhy1xiEicfaMINK8L1fK2+28hi9QZJc6Gs2AY8Ui5olnAoBZoBdb2XbLm rW1EO2qjDAAquL1zpZpF+kylLjtNNdQ3r9C8O5jP+ohSPZu9fAGgVUfoEzzT+lE/yowTUlAvenk8 bqDK5PaZKKeZYoWGkjGmgbhBn8k9H3+0vo7n5+89feFH8WIrrSWqROnLHhuY2PU3uoo88zaFUUbi VTycW++gry0j6f0HPS2SzagSGq4CE43CuaQ66yafsByNnFU2jUEKPiq8ZZz9aSIzVdXLXaXg8ePV 7UK/3tk/n01if1CNSqCNcqThBU6wGPv8gKQquqeATy9SeONAVog2no1Sq2IAL2/ATAgWoHClFCFr qHzBUbbHxZexogEY1P6UJkaZ/7nHo+gxLyJ52iNBbQ88ANr3h4ya4V+vNVsChWk8afZqOYXCkp5V N1IKos4CZFWTsghuNXn0AV56x6sqsSY+e7LovmdPLBJllqyTXtjQQ4hXv0b2bRzHnrGuGcMZF+Bm TGjD8jzorvnsEb9Psy3tQOYffVRRQJJPQJYf3ke3eZWDtd242zRv6ZMSnnFliHKpPJOdUAaw5PIv WN88jveQ+zmSzMkqktz2u+U9EtfnU3qzNAURwMUSQ0lX3/g7ZEF8lQluhtdF/7LTNzaubhA06g3H 02UEyhBozJnhecsGpWwwelRxa393M9adK4Zajn8uvdd4JS4VXyx26szoJtFR0nDpyEwbF/antV0G X8BTtnxZg8Ckbm4L58tQTA3GCHYutll9IZfZaePu+5Pa7BnMZyMr8vQ6TueFB4r1CzpSxHMUL895 0b6OJZPGQeEo3PPADeto8GHcemhTGMlW+T/J8ixChwDRD2qLhEjaRSERFEfPZb+eUj+U35oaXlmg ka/9wHgk0kuyqFrEVHRvdxWiURYzfYjpFOcCafQ5WszX4QsUOtbhx0xCN9sv1qOn0s21xKlC8bVl hjssxrVOsysc66TBs/Y790whVjAEVl2eu0tLn9MCtlgrJHyMsM5AgfyfmjILNgO2oOoO7QPcLmWA R3GT0mtP6pVzE4kgkDjfAQ68KOUj9OkuaFF6jIQm2qgpape01PV0rMpmYtHBFZeunBRv0XScXya/ jLMBCEOo2znV6cxlyQkXKods12I6wNrw5uBy8f4MEQ0Nx05q8HMJ6VzjhRY3Qq+zc1A/WPbk2f00 BboqM0W6MTzPqoWxrEkNW9Fgi3ceF8lqWGaT5qgnAyKD8+wDKR1mUAIw2PkhsE3iLENEkLvliR1z e8fHDSRpZ82UjUudV8NL/v1bH416BtnMsuQ26N79LadWBzKNYj+IHqOFri0LdmQFKvGrnn1bvslA 9Z/DPpt3ji1Y9Ix/FBLC6bshDCxHHnex/OiHLLX8CQESYY1WcQedx0u21Z91nuorUc4B31qDKUkh h63qDEsqP78EkwVjGqGJUTbVY/sL25k7+PfXG/qc9MLVu+QHvtSGiJAOOO6be2RUkZZMQnewWFk1 WYFikYw4ga1o4EUkPoopZQAP+C9skR+tCCcGFZkkyd+RtcRWA35PFpKY3/MuA3JeB6Ad02q5iHJk duqQSDfELuo2l3N786ak/vttg/oTHqHc29iYpE4xohh2C0GCl5m50ufGXM1tMgXBQ774rT5aEE9b tsPxYQ1SJlwZ1cChf9f7QpDQcqWu/MErRfG4Lam1ZBGubG6puwYPXiw+IL0KH+xg7b/utydaAsAJ ACl3dinfkqpebn/uJuOAX/91+dVlmE7ulMzfjshkQ86QsPbEoq2+HZJmi9e5jO3zJhIn/gP4iREG zMPrzxPzRTGPCz1I8A2hC7wNOPCtaR7krYFJ4RgRf+N+GGc7g//cRlzVaWDVnzazWkD/dfcc6UwA f1FIbfMBCEQ5PW/ry31/Zpu4rfmPz9OcNJHXwCs00ZjaAOUNPCICbuDnUNXdRjOob7C/WLxCuq5Z PDNj3TlVTWqlHgZ5g+tFgws9E6jqBNhZYWSlcpHkFbZ+zfEWnmd/3Bd+knkitHAXzSlzrzZfxZSF C6pdsbSvcUCLFd4hEE6LTAOO9VlcE86jQa5xV4MkKZwQvuLrUffaMgYA1M6YoKa9m3dRUb+nivzk xMwDzN2NG8kxcqN0kK/WvSiHOfs3EaibTFn0ipKrRtuD1bFW1Ql818fww2KSJv66D9w4Fy7jHigE reueXeNgS9MrSOBteSDtWtNbUFQHMBJrdxVxHN1R2W32KORaXnAAx/fnxtIS+USwsfPc5IMOeEsv lMK6y+b2NRyVFeAuWVHr2ljwLsp8K7vVkhNKak4pRL4N4Ehis5ShtP+1+Y2AFHh2gRFKPgoruDyZ Cg7jaEG3n+i84Z0OCEOMr+z9+Sm7JzLMbUB0LcdZLAKt7hcqg47SjbP1C6Oaj2HP6XY524yjGhfc UakNkkSofyoVOsRRNHhzj2qw3dGbDmJqgyUTSnzj8oi34Sj8xz0zXaDyQCAep59xPIrh3VG4bHIk tdnU5K9/9u/va7i07HlApaxQxnC6oDvV/M884hJ1nJgpDTtx07bdOZLDNveg7AQBW2q/olD+/6I5 fD8zAIYC/mtC2NF/GmkTutGDy8R3yGRftD/FI/3v/Iwn6y6MTd0m38qhlg4d96z0IEqU31Y2ISWV Q/A4XRG/8JHOiF8EAfJ3JTJz8f9iInVmTJyCZUQyrBARtAPShQbu1th0DyPnQQwFsZwe6cuJpcut e3/M4OuCnXkPeOhiOCmN6j8P6Ip6nXKRq6jqVGTH8DzvfZvXjs4CrC0ppNNM8VyL+5Szo2sU4Vx9 w5/7JtxTBVE4HHWe2cnhCXYUeBLjrWXJOZLQhc9Xf1Y6LUQuatpLcXtvZdnjUPvU711hy8FLgieg co3oVMfCT4+kPRF5oCj+0QQKmiNELdjffAJ14e4HyUqEhV5eViKOBLt3xM43bb45h2y+PzlEOBjf jvSDzl4EqaQegy89wPe8z+ALTZYcmxK+BeQPLLVlsgYN2vXO3yD/jM7VVzw9Tfm7fX9A+99cUgZW bAwWhpL9h6Jc0f5+2g5O419q/N2ikrrmP+yPFb0JpnBT4TzYIUuSl0GIuNQvChGpQOmnLluCn4uc B9kKq0uFPBqUssezlvqnqamtjFFrvf/WtFOlyZx0YCJAXSJhi9S+66MO82uFCCi6Qbci+Y2ow3BL 0Wc2L3a+37oKcZ3mRkdyxiMhaKMpHJmhyDCCe37DTO9c6oTXzn7wgvvDsjIBERg9UNZx2Iatp97i sL1DdgeoqZ+psV8Y9VJQseWV4d2FEgQbXTT2ZJ8KGCEY4TEp+JNFiz/hnxQbVij0fw9eb1bFaZbd v0YsG2T1iwwLFP9AO2TI3x3hSALnU0/kDpj+Z7UFhdtQYV9mjp8NOd2g/KSu4ieS1mnGQPUdFyZQ OtRiJF77xY2F1rUC7dHG05NVa0MHGJOm1xGRrUgeOzCwuljYCeSFEBEuoWQ9w0TW+60YtVOvRqZQ /D0wE0/XF1q8QPMHJttPyYjVDhIl7ztOYw9+3snvCc7b3vjjnT7KFEUUMuMr6dVQqrtzSs0qIjDg GMr3hqnvQPZujwtJceWw4gblqmIr8uXMuXhNzbvzr+tlr55rjpjeVbYgE7FrKB8YMKOPwWMNHi8X 5VVhncoXGC6aGZa6kX1yA5EN/drT/uy6mYFYPap9cXbxAYOl5cIUSnzp+sPNHG9Xbum22wewc4q6 pPGCZUOTooeZEc0wqdUZT3NZQVwKBH6Yz4Hm5UXUrHa5Ed1v+DHyRZ3kDsBPkl67kpITp4Xk5/ht FjBbQL64sPY2IfY6kBO8Ugb2HhMqoEieoXY3OpvZgL8Z3D9sQc9DiLS3hVrTmQT21tcobSvrqZec lccQ5ys4+TnQ1jByFWtOPmUOsSOd9vts6OFbg4GaWAvuPwfCAB89gLbVyTbfvitp2ONx8J6qhhTY 0YVSv+BL8hpWHqpHHDnIfYyuWJJn2yCtCaQ4siX+hhtMqyZMERMTA1obWkO76oyCZB1+WoKWrXHu BmtizPcAcRqtJV0a26weS7p/cXE9iBavXJRDWaJOgyBpwyhR670cuV1aP6hlkeXRlFG+yRYrOFWI 8ktu4xY91lxJWJnKDQAAYhV/TJc84FJxJ9GW5JZ1uLOEViIOB+NxS3z6DUAyga+UV95++vR5p3BN KX3LVflft7UFs9waf3xvCD2YzVv2SmfPeiEzb9CVJ6BI72r2GZC8h9ID5WwDXRF1p4H/y1R/ppA8 Flp7Kbdh5xE/3yIak7VKgHGRlJFmwg85ETZk6nwkWNy4q0BqThXu5bUQIRwR9SQijjv++GYBE5g6 8AG9TOUuuQDgvY/OaoG8vqwRNmgA3ZFAgogbmJdEhX2drfNZM9kHBoyIjHYKpXgUdbOf2sD7j3LZ QDucdQI9qCng4MEHKn1mY0vmwbbAM4EYpHhTnFT2VUy+H5zPyUzrvyF0Mfc2wVXmXvLCGzyT52JR 1HMOJgx2PQv2rX7o5z7Pbhk3yYeZ80c+RAr0oxFYxKBK6Jev/6+NuXaKjkcBoZm9koyLudQiXS3e bWzNin2CnUZeRVAg32A9FtcWSAXcYvInh4r8eiLBuN0yzQ/2qk8q8TfFrMOQz5NGTi6T/KV9HOJ+ HDP+8UsSCHV1kYfXdxbnI7R2nDzsZjjT9DsvNUjfwNIosrTVbNwo2B60Q944RoVoocqhcKeyj4xs YVezvPbDy4Cwveq26QM/zROBBRK7Yfw/VLzOTVf7uhnN+HIxAbwhUiype/Cv7DOvRiV/06xJA9W9 XBzkn3POjZ+9liiJikNw4HB1DJ+fPduV3l2dW1pi3J+qE4oUkzMAdbh07kpvdBDGtjg4UlsLa/l2 tcq2E22nu1qnQV+kpHZUmfN4a7JPV6aXbWG+1s4Hl1m0RDZh+4gcxwXkHvhNFCcbN3rm+ru/vTq3 /gvbhqSRidYFSY6iCWBA+c/smqNSj+gJoNf4joOIaAKAUQdRyWrEoCas01H6cWgaoWI0ojdHuvt8 mSSjCJF6vCMFe0e3niSI0Mj0jHeqJR+sFBBWiVyzdyJmam1eP1Kca1q12UOSNcFfSGuazVyoCqzi ZdBJXv0C0GoK9LLjlXcCo/RWYUTFPTXr9PErU862kiC5Jun5KVqSttuacqugMjf3mMZEeod1ejH7 xaWnv8UA53feg/130kP7TK+38PmlXvBumJQIK6CGQt9T8wOya8EqRO89fGvdzeAkUquXwJUtPeK9 JF4ca0pzbrgl0HDdGgHRJBaWlSmgQ8eH29g0npIADuhbpO6camsahibpo6uwNNk3PnO+7sXKr/DJ JAGp/QC4bFfG9F4XtfLuwZSo6f6w8l3M4kpQiVwqTSdiYtOFwJMK+X9Xgczf77D5w1kKsJ5KD2y0 19aZqp8V42WP/sQtOJ/DL5bYoQGT96y2iMQqSjXapvXCLj9ZSzQH5I3ecaFyPWbdVYno7L6yzrsM BFHlr73QeZzv0b4jjAE2VYApCCs/bLE0/XjaidJG1bl07JehHsQUc6y8naP7NJnS7Uk0q1b4b0pf QR+LTj0DnJleM/OGON8WjHDRxfjLciZ3K4leUyrD/16i/jhScVhexpwKPGVkMdH4UIfpdAs4kuRt w5zXumlNnTX5Lbd8pYJiJGqnXcsFsk/K8+Ks8UDhZg7AIyIzs6yds49ivsURdxMz7p2gCnjldm4a jPBBpB6xlzUBXZ9zrUcSu4CX1buYsfRtk+Y//qlj5ElXKO/ik3tVDfkldjM4hWmXW0K1L7mS3YZp B929V4IVNOH2Vq3ygy0ZW7GRsVq8V9+qcrqn8d4UfOm7o/KxUy1p/g3CrHxQVozsK7VQul4iycuq 09qeP8aDI1hulrBP/NnWwdLxGTOQFt18xT/RpaPj/ZArhdQHJSPzTqprRMzJ5hOmv8iMP1dQwF+8 9PzVB1PdlTD93/krhLK5WdvLeMiM2AnYLYA7i/7IjinapMymXdJLbdwlQZagphYnz/+2qG3M+tML lI823YqTPtbFAmG7IfyobOEy2KudAneo+NU8EwPkr07INwM5cV/45vPI4ABhlfvALD5iU+v4mX2X HdBxxbUtGtkSeVH0M0LPTcMHtUt4BjRtLrA0JAWmU/MT/3x/B4O76tCQlCfa4cALKvP/Cz6xVOd0 6G++0wy3aHLhlNcf81USWcqtN7ZXYLKyydSHqq6ym7Pzd61W8LQOCoSlJ29ocm6vo8lb7THYOdR2 3NSfk588KVI/uwhV7ncJQFHI+Lvla73eidQY1vv4BflkuJjtOAcPhB4/pBw+88ZJo3hrphRJJ0GO i48AIWiNFKW5bt7OXtT3/FWpyDqLx6pc5hiNqEID7RuKemgq7vzLVH67w59P58Ce9g22NA72zscz u8UckZPl5sK96hQhvTZ47H92b1VmMZbXLSKoUAUlL/5FLkpo+7P2eoHZk9peOwO0l+hYfhsc+zjK Mzm3ymrRPvyoLDkJQNxjXjJe3AJNOCTB4v34sV08ej4SOJ0/1p8zsv7tN/t7j3+YKLPwFa86NyyR Us4Gxn+K9xfO582CgwKyMpdbWXmSqJIVaegZooiUzvLT627w9LDXj2Lz1pGSiT6KZYxQhG63U1FR zQ2iJRZcbSvaU1OS4kQcsXMWt/8GoVxxtw3lyrn+xcLU/NZ5zRNpUob6T66oCGXc+rwbFB8OOtDt JWza9IyEnARG0zTx1tUBrVmiU3bsfCCYTer2jPxl5v2E8gSMNtqSN0cc5axAIBpnZsiumiX2IEfh HVXrLPBmPQIom0HYvXJyq1lLdtJ+R57dxKu4eVMovBG2a8RJKqc4BFm205Fhd+Vp4zsj6jj5dkWo tQtvpJuSLFpOegU/6nTsy5Q/EccKbSbImVKuFyhdcKAkQH3dFXpsmHGFkXoJDyCyqs9uX9qpvSZD a6TZLd0gh+HMdIoDASdBDKuqSiHshF7NbJx/8hONLjJ1D0T7yLe5e2cjxcyG/Oj9ubJnT4ArE4Tc ERCIJV4MvfZLsZhuZTrOLpW0LuJJ3W1lwNcK8oxjltDsp4syyhTip7hGHNXT1CDUMPMRHXMLI68U arN9WTwTcXFQTh/zbwnyQloWWCY82hLT4WdLOrwqxpLcl7F8Bi6WnW7En89dcomvYxrHczGZSQMx JhCWjiwUtvdKRFP038Bx2z73eEyVtMs8tQvoPl4bQJSUIwtNDlh7qxlxTn7gMxGZfeR1Y4KabJya NXc2WIcNAsfa9YaMeQtPtfF+2V+8WfoHppCuvUpCailqlWYA3ciUSY2MwdNpLwt6pcvXYbnHyP+J NY7z7t2sYylJEq4kKbffGQrmJi6dYfux39SqEOXXlhg+G4bFkhVDOopQKCOlZwms5Pmbgdg4RTOw BTXzxrchKtxDImd1Vfd7ka66O5kqb0YT8mO0ysCW9IX0LEXL/2z1SeR04b5vga44UptgjBLFOjVu Cdiml8OSUaCrULs6TGITp+FOFjSZEKNnWrXSxHuObJfc54lMtx4fXC+VvjEb6yFSnigSeKvo3FJT Wmwwg6wzY8hAsYa+Yugcx9ueWIpwEC3IZWkXxCG4MmiuBNqfhx4IfkFS2v9ymvkOO+I16GpwAc4c NqkVZI6BBB3fmUiGsnTLXhcS1tj0uYgzs1h0XYDXUrGXGmo1zdNp6ncasms0uMXhU7+n0xQC01Lb 65gAmT5d1EGkdJGODgoRo2gsQdhaKJ6JiKvwrFNrWU9ZDSyGQCuNekuJfPdKbH1ujBDa/63q3CS+ g0lLqC69ccKxs49O6cNLp4HYU0Z2m52/jXRemvmHkTB8Q5Fgz/wwHlmvZYr3iz4WxK9IIRxNQIPw x0uqrdmWigzsQLymwXu9YNs9wB/Lb+3khH9bAm6CEw9yJ+ldneQl4NhaTQXhL1SsUj4uZdqARrDR jOdgbWeomchdD9t49oPELmYrqzABPCKnSVZWviOe+TxIrbVjGNz10weeHxrdvx31nGbR4PuVt8Tj 0G4rJJ4RRiLTvCmwUTpzkemxvBshSMnazQ6YMLbZJ84WlMqUGfWyUOJF8DTEoKvdZXXpPbgFOt92 hvSHYXVIxARTUyM9oE/sO25CPsY4LeCCfw8ZLPgZh7rxTTzmPXDq7Mt9bdeeUnpSNfmTgwLjMid6 EkP/00N9RvshvmVpSvB2HHHgQPGO/1r+7VQqw0cTHyfp0BXx/qfNY2tUImT6KuuJRWUFqRNIJ15Y M2t1I+c4RTTsVpu01YHQoQOCaIUtiMuGqb+0NUGfjMFdh+In2mTWAYVxkMy7AXfebkpTsp6Fnx6e N69JWrQ1Lo+Drhf8H2KUVTY7p8NJUh8JXUBdPctQ/2tUVmrmexZYrUf51Etc/HcHNZOd+xXG/0cq g/Ew8B3wR+/FXFK3lzB9RA9poP2CQ/B1WSfLSFJPwQZYB7NaTYPFULJotahCASlgdgTSQrrT5m+j OQXGvnh9SsIXMGSbGs27c1XA+VJU/bJX+hkzKkWHfN2VtTG1SFxhDIO5uEQYwrcBjdJ45+u6K8iX 2xViWxF6p8yMiSVbRFQ5tEIcrFe4yT7YGs4V9238brlXmv8t3a3/PptoIJxiBuCpNyVYTqYKC/Y4 YKk8EdeOm+HVgMnom4UmuJtPhgbYRtoEVo+l6pfShmZT/osqe966kh97eglth6R7X4efrD4DNMwL wvOrx7r3Pc0QBTUvd6VVM8cH4MbM86AXQD9fyimbv9nw9tHXEPMV1pQYv7VNNt8fIaabdfHtjG6l c0ZyWDu1PP0DvIrBalZHwoGUeYlRYiZgJVejFNOOI/sr36PjQ9RVT0RgPidTRfeUTKYIejetGNz9 kXJO6IbRTerhct7oF0YHCOq0QwxD0YXWbrh49g4dJnkwlwB5HtINno/sdG7XI9SSRH+zLIlYYWkI FJcL7cqQrHbiHzuNzNTsChwn+B+P59VRkWjMKp/vtDlgaHQUVAFyppEXjAjlrau50npvQxyOseM9 ZnLah4oMGdv1Qm5PuP3bJ0wzFi5nYP/Bqc8y/TEVfaXEVJVJBkqab/zmqJYfVZGGXBuFeGsIsGsI KmxrkiiuRQ6WzSpGD/a4L1Npl5x88aHVG08WLDJ294+HayenlAqYTPu1S7ViCVzq8Rlg1KDM6S0F 5yT8x8J8a0zfiQTel+K9x2SzayoyAzf5nLsGGoa/xQjsvXT4DH5A9GiVNMOVsgVV64CYzdb6+mhJ 6/YkQtJ7iWsohlMY/iIbkGjha413Xtdncnp8OqGrejUaHeExkWQU6WDKObgMMPWa9TEFKf03fX3I QOpAJxnPN53XsXhGwNMeaKbeAq2M2a5ul3MVDcrA+JWLGyaRDS7WDqCuPcHAsQ1ccKS3Q4hK9JlO ukgiRTkIVSPPulgLU7nicARQpWWFI+IR79V7xjl0ivPuMIYicCKG6zbn4VKbPTAyftsn4HNieE4H AAhOdm32chF2ejSEeIl7fgiE0Jn7LfaE1n5Xsj7vO+UtV5fL3CXUuAIsG7mmfPEuHv46BgiD2Cm+ f74MWKhbJDqXXz1axZVKncO5Pqa7RlzFcAK9UquVDJ6t6YJMV52kIbwDAM4qKmzUlPG0J0hJjpVz fCCqUcVg1VAWzHl8uGq8ehwNnlJFnfvTeSbrlITHkK6p6lZRJZU2AkUWoVUMmsNzOPiwAM7/4GbT 2WC7XSGtzOKh9iMZUiLRcUg/WU9tesiwrJyKQS9KhbsX7CI1GR+brPR0Qs45taOahZfkOAmCvg4v NhCzXJ5NWD+biH74OyLciyf3vZ58RAjGGEqfR+7HHOYVoP4eak2km/1LW1UJlKRS1k3dppKBemvM zpiSVOmjBKcbFKZ5n6lRaFcpQ34n/3CCk4+a9F8U2fFaag57mskpFn5AU6U4rDa/60d3d4jNegUE REji4FWoqGTlwTE8oyCt8Y/FsZKUDfOLtmAG/p9Jisw37lYJmmeKvV+RRICY/fzxj3fR2H5NhRTQ JMX75fcghBO3gq8OO3US/T8YCHW2ejVMMaJv8oBDJM97OeSuU9+J+oKrCZ4cd6u3cDQwinTrxVKL HxsXGopdgqI0jQYbbpJSZxTv2JnLFf8hfA/opj0szPy73RSq0Dr0BvyroW/mNSWyWQgKv7s/ihu0 TyymFq6Alo2Xlv+8iE4gEMmYxUFZ1shMNKemq3cEtxbk/u92A8+jXwVov9oX79RhYmpQ6p6gKMNH KY+Y1mGnqp1R4dxJXytXXSwtwJjmZd9BIwC+z4F89A35+077A5JBK+JItVVVTEWerEDC3JI3Nipa nqbnV+slIP/rAK1i0jr3XPJG4dES0dC7ONQyfmczb8PKrda1NSJbMdRidiNGQFKdSsDupVZ4gT83 r3kmiqDYtZcj9DsAAkhxDLGyhhUNPDWT+yWYWAKIgwuDp3dtNS9gw6BT/E0B5zKm5OerxHMUddVt FaowqRliZ9H+t/QRAGNzwECMEwk0hhWd5zR5RlZZPEBQSurnkqxObCYFapmmN1lAraODiQR4p/Z6 j+NRY5OqDsM4R/bKuiFDhdTTu6JUdhdyHhR6qBllq4jIw7srumcBjXURc03wyXeL4NmGfleLl+P7 LxGRTX1upjg8Py3W3OTwflQzZs1ZI3F4H9hSxknXCaywio/c7l/BeV7jUg09OObGXmUOJ2LR6soa y54OFh1UhReqBC65K5eWXt68a01lEqYsCUJg+uVtQR7tHC3rED6wj4pOFMYJIgdqJsWq0nsKsuYB egeuuHcR/Hagk00RPJEFDKoLMn9ZCQoACa5vStK4ieZnAuCSkbKoODQCjMsYqCPyD8dgfY3avxaN 9xI6/gBZBCoHEjE6VjPkXWcVlTuCGhJfoC+tmdaKXsDZaxuaZooAJNDJ7De493i9DwrJ0yNNmVJT ObLf4uuBjTyR+WktbMwnA4Uz8B5SZtF9A+8o0chYtuWsmqBAmkQPzpgIHQYM4rpQRhJ2hr43s19n EzJ85M6YouMmVA6k+y608euViZQBns1ujtgm0UF+XCA0KK0eEwnqzs4F7+qkI8iFmE2XjiSRRZJ1 p6+FG/SRchRxwqaUfDd4pdRZ1aJKUynv8lMbLjGWafPRrlvltWfS3GWeNag0a94Y/tlKUNpq/Shv qpiqK72bd/kN6Yf2ANC+blg9h8PhgVUkem0XpWfp4pkeVHlK9pNP2QcYOk27EjSzywkGTtMTGsDU P7Fv9Bw3L5YWE8KXryIfpHRe3cEivvC2D2eI3YJGgxoNg+z4b5aPyhIJ3sYH2zuZBVuZxbfPF7nz 4zNmhsslkDzwD4ghFRgHRlfhMNhVXwv8JWd3FuZhGCMDMxc8f9kfHMsfiTTwzFxR1fKiAdlhu6bi L9oy09E708Ft2efSso9pSo/nrBEtyoni9q/dGAtb3dAV6r9E0SxB5N2Olr51K1nFFSXdZC3c54h8 erIhSfHBWlCt6vdaBIa0RwE6Le6MQMJjA+UJ9H40XWhmHd02eggWR1IoCYuZpL7J3qJi0i3xu6Dt aDKSiQxHf0KPBTHmtWzkFyhUpQcjMXZEXjm3XmhBQ+FPObmkLHOpbjKtnOdZKI1Kwc2t+unf1NE2 xdZEIWe7/a34X0TokW6+gcDq33B6GGNBsT+x2CZ1JDEE1hwbF/hn9i63yjlpaXoXEL6iIIHOgmER q0T+XppAx6anyRnyiU/ti3tEVR7TAM9uv1iTxyr0DSVhR9hiBpCsbGcfsnhYg14Vx6AW3apgeluV zaITFvxXc7QYNEn5ZMMZGKQtdss7y7yIz7uXM6lPMW0eCtkGdMjb8ebSJaFf3hxS/pgXk8FZGfG5 cpCtPNniYww1UhO5Bu/KlETXmGS6wQkxLbsUojMWNZXl1wDlu5XXSwq7tDLWNa2WoTFYdhvjTZaA 9kPNj+HBi5dYp8kr2d/jlqYMcsNeOljf7uoEftkfwRbsH+sflUBu8H7Bk3GQGMBoklVWddM65UUR n4teVaFE1+FUJUptYzh37KWy+QsxCYbPrLQEGtEQm4XmhgI6aAkVP9uCW1ZrjzCo6JmbCqfVAYmC NislAWE8sFUEQFZcpyyxtizj6IRxOK5Kl9rJECnNtA2jSjNOjVXfgjAH3WKCH8JmqJ31ulGA2rk/ cQA/q1FnxnrqPmTqEXWZcaEkdSzPP/C77qukgESUMGRdgHJLlJpWNV5NWs9v+XiEYIUcWYDwV6i+ Ap9tV12u3/cYUhn0mFgZQPkh5uEY9U2V3E4e5+sXISQ5QvIiSfwoPfWfI8axV8RcPZjUktviBYkh ClnqMOAhq1m5AzBCCcnOrXfMlMNXS1lw//y3RNG6rd0gqM7BnuoYCJ34ytoL1pA4nU6GhTeRLmiJ 1TxGNypzPISZSnfknikVN1a2lT4S00xuHudstTHgq9BeD+98GhdTLZ2bayMSAAwHFXjrBNIWjmcT FupJi8q3MnOPaUrnjtTSVNK3lj+uOC0qA243z/yMXiM6nDIeauKYYKObusN9dyp913mIPdBd7Z6s c3P3+Su+r8ZcQmnEiVEVdAoj9YzIOiqi2qcB3GvWZhXRQWmwQHPaN/U+tdA0hYVeYiQoxmZzJsS5 gijwmz7zLCcY1UNRzKDzjxzBiXOaty2UZ0+8pzVEJ4dNIHyGinxWu+9As/dI4viV+6Qm55hRi8cR mCKW8U3FBcWEXPJXkKVlY08ErXRmpGtvGHMWM4kb4E5R7VROu6gBfH4dKKX90jivwL4n6tRNBgSJ jBJieFdpdmixWH7EJicfyVBY63V8D6yZ6tzu2b/AqYnxVOTAON/IMeXBrAqs40F2x57BYV1BIkfZ GL2ERWLd9aHAH341uPQBJhNIrKlCwJdPbasVJy/7z+haLcNvcGW2NwDv1Zol+RoWjCtdJO6LMvVX BhxGdNkgc6Dn10VXsnyFoDdRkvQoK9WPmsvzL5u3JCZDt0jKDk+AwciNqX1Jryaa+4KMaL5/Wezh VjcUriT+hbyUqrmlf9aQrymCtrvbrrq+Zvvb60ovYxqGGeyHCfF8MrC/G37m4AXWHxkQfZzC1h1K XPy78k2gPuzTFpgKoidTYUmRGz834B+D/DvTmzUcipSwpLFyX0Omx95Z3rPZfCq6jfYoBPvxJcgc K3UjebAPlbuIt1TWAY2OowxCM0IXAzTzDiDQuZaPY/z6qMZPieneIXGryOIZUTh31YozDFClu8Pq BiXwDVcINEG5aTdjNb3moKo7ElfOQz0495v5HLj875CPRoFUUwk0Y5Egg41VCPNmdiPD2+h3p/vW DcqTY5qV/klHk8V5ejILkhmYeNIgndrXaQRfRVwEppwaTZLVhYtX2hcI1ATV0tMM20mJiCPcUpWY fiJdH0ee4SGoU5gIudnFn8P4oz36InVrzDgvka+zcBp6gb/VEWKidJ5zDJ2niA9qv7SY46cvCaht 50Ke6ItW9r56KJqBYCXMA0ImrT8Ti8NcwBej7SF7HfY3vBWYaZvzdx1ONVoVZvojaBJcOOZv4T0P oMmDUsiS0xCKrB7YIZr9un3jBtzUU7tKm+6xr347NjvULrqRuHYFRjxjXCjmqiAi9OCaWQYjdgSf yztMK/+5dXYk81E3J92Z4DsqW+F6Ndcsrk7k1XCxmBhZtJy5P6lSrOXJHqjWYTy1Ez9/u9TDhupI 7QNruEr4G0Ns+IlW1gCZEPGwLpFr57EH1NkrDqXk0OPrLjl8yNV3mztn91jFISscdsa+HhyrOwyF D2WMknxDLYi5gLcN40LlrDcvS2l7SWbf0KOX8/+oOLw0lOL7dy4Hu5gSW9FJvYFBjWx520lVlqBk kXDCfQrzT90qPF40BXf4bnLbTtG2B0jtr/8iqmHOYyOqXhCl/rwxT7HjP2TqzOg6NhGfkZqUhcU3 hwcmRUxlgXJVdZUquHeC5wV3OXcKjn1A1lVaiRgh2wb1HzyESrZ0Uu87RnzyCT+lytVtKRWg5o4C P+KyFEMz1nX71rPcYJc6dNCrObw19Py1ycCgvGAreB4hSymnJ73cdePPoUnNAEroW3A8t/ZjEJ63 ICIdPrUkpKjfazFjTmN/fInIg/x98nCnzOvSETDx+S2m6fNOi4QqdxUDIG5WvNjCLZkuCHMp+GIY unJt0VUlxwqm96zf7dDNKwdoqeh5uTjWdf8WfHXBHh6UfFmYfuivU0SqveAKltK54NSulnuTPN44 vZNpsA40eUFt7Y5v/sAXQ+pZRd8YMh+aa61UnQ/7UY2pxWxDX1JJgzAbgXRgrsJBVf0SSbQ6GFt4 1GWMZG+JS3Us6IH011uRtB55MUUqGgqdtLWn3YNxZL8GOMd9irqKSUPEygD9IDm+X4NB0dgnJgsv Maf+iU+XcAohmeDP6QO59Jd0Iuts9sv9VDof7+FXgu9yWXml+/Lok7ZDp+qMPldLloB5JXj47C15 6fDkhsHz7jzmIFby2VAytCvNJ2JhHAbneIa4jN1yBPxoZsM4ooxgGE2KifyQtM2ByhcH1m/er9+2 aTzzzdV1tcCB8wNE+k8CuVkOfEjJ18IIjNazkHz5ooelyqVGvrhFxKZMmdtvNNHgEfCddDyjoNpE u0ZYjUA8+h3Gg5QgTz+fnUfWC82I2BPR5CFeg39SzAzHf8Pq9XGyuLP3lfEqYz1lk3jNAz43KCPF IhQt1nP9kwwu+hfH+12xam16IjRAPGSPcuXV/0kDTcAyNLoGq9HzEDOU2Py9mChhzcF0gAPxYI3P 1RZgU5q/jMv+0H2Jq0AeJErLOxuOo8E6EbBHZOvBun7wAoPT45oaHDcLoQ1EN2k/MVL3pGE6UBUQ khC8JA6FhdPGmca9/7T/E+steOX+tJospig+Na1x5AcmhQeNONVciNs5+ayhO5AHYZo8gYMExo4A AsD3IpH+cME0CEi2pS1RVdtiB9AUTrUpFb5+cZfZCJH/Mk5eoGfweSGUJSheDUa9xxG1N4QavjL2 wTF6Qg6F0U+3RqANu6f+69TBV8DlUCCRHVOJsHxKtbSC3d5SIfdtyUgAEA349yK45oSibxJB8+No 0ycr57G1r90nhchHZ8egObnQlwdB20zY7faXilXPxWEWsioj5uOmI1pVzeXCx9JJV8PUKVgKoldT cyFSiJ8Du/Y1YZ8VaB5tSOj1rTHCE4EaknBThMvOWrIBC/vndgMxHQ98Nv3e5RWciBs5jOK+8oF9 Kz2Q62XYkIngt9gZd9oYdWOPyx9pXTBXW+uTc3GlL2G91gce5THnnmJ72r0Pf0SZpjX9VgqC8glh ZdHt33JNjQBrH9VKIfnYV6vDZ+ZjC56VMhkHRUIIop694fab42ntBW+xkdAXvW3vCo/uTsuJ1cWv bi/0U/CRM7meXPLXHCCCKRbQ8jTAYLEuxjWFXeR2lFt4z8ZETWAoMaaoyoQ2Hy2U4My5tvprJ7fW +yy9iD9n22BTRCJ5LUyLj3VB+7V/qBUqAjiA0g8na0QlSGbNd1niihdZ+IDDe7OpSQFGqwuQ7Ma5 mrvv9AGQGi0UKAgVKTv5Zun9n5oRuitPl3o+u1lGZzFIM58DkcE05Zz8b59olk3arn7f47CujOWi 5yvRNTTh8qJNUmdOsU/dRQ2XCOERpXa7brJUwmBS2tV25fVwTdMm5XGUCELVddlYED0+d30FTus9 VX93DuKlhks9iBv4NcRCe+X5KWLnqUnK7lqkxgjObWeLONFnnKANVnkxNWQi8Y+H73jfwVWyE40C iwcs49q2mAeQ+6yvF8+QLzhf17cF8yENRsJHTehN6cXHqhh4j6iZaS9vyjOWMxVf/IgNmjJz+6KW YeOxGB+ji5lNRIgTEA+Ar5JWBtZhvoHf7gPTkHI1B+cOIOmTaNuAGOgC2bSn03xYeplDBJ7IBQ6m ewWb9HCJWTUEWgkQS8EaVVTW8Xq7D9XvGVoQbwOaOjtGYVX5ugrZS6Y8GEezNV7VPgnKk+xTD1Ap ysT5F1FIV/JggGFwiU4cIWJuMoYEZwiYFhp3VeTfVGcRqjtYyICCtuSSEW5fiwx8kt2IdCRSWU79 FFBPayjxF1vLvburN+arCfeDzaA+CX+LRrAvzA81WRdi9A/6M3LV8d7SnDfFtzn4l0TI+q1YKmGG syZr6EQge2u2YS5FNsSISkYC6VBM1hqIriWwAGMLNoSjTpw1xjBjXX54038w8N73bhpzDrmR09p+ XR2iO05eKYwvRbjVM8FbeRWFYslALfCU8B7nFvzLjagl2Sncz5v/+UlwC1XE5FjrR7zyKZdH16CJ 3KNlVLE9zisYSf1vojkBgCl9xuwJ6N8NA4ZTknValuNsBMMoz79G/8ZktJW+nEMrXja32cF3kIEW S9FN88l77K9JS5HqiYyUFPKMYCun6PhtnEAQN0Qzc4mqUGtncblF1/t7yAT7JwdvQ+QL4NRQ48jC LuSqQo3N9zK8Qo511VYqttBzRSQCp2ME5gG7oLV25xt05STomnM9Y94MWHOFDvfNdsFzXuFhZ50a 2cLlZQe9b2V5l4UgjoTLJyAMcwfznFBIE0SKYqbej+K6P3nVht5GMMoer3jYq91czABICJKKexai 4FlQaG2kdxT6jQ2dOHN97IkcjPh/aLBxlUayL8QqqQsvhmP42d9LQ7bRbZdWf2NhlIx0XJmnRJrD Qy+MkNQ93/QFvms6j9LctUzmSdvkWeHPQLGzCC6oXz7AoAZxfMbGZRNwsIJxoU5P/4B5i81rOSm7 Nc437FvmCKkJtuPmyyWyPLN9DVUFYzuYNgYg8awRkuDOzPzWr6UrR9KnbZIyE/6BnZOBE4T42pds VHh8bslkWgV8gkSnyp5/AZl1VXWjuwpVkL+luLunKNYqgUQQh9PRSog9882prLcrUgPodK/yQBnz mMPI3jN4wJLcu8kygxcUpFzgtanneBHo2PWYHZn3Tm7ZmNWoku8JuIWlpQHm4/E4JPDtkkyTMsR0 7gWmq7N2atN73k3FaiJtyR3r/29g8DC6AvwG26M5S9ZgHUIsJp6OEPNF84cnBGFVQON/cO445Nzz ewHmBqrl2dLM6D8bisVvO1E35LN52GVAjt0XmAvTsJFgWEMPmlMRVw7seRyuyfjd9Ofdx8IZCcBY JftDBBXNLBDFIcRaZbT51QIqDTxP8MrIc1Lj5toNxxBspIHvyb8kwBWvbDH7XdOAo26FNZTvSaAy JvdjoL48UYrWWy/fKVDaudKTOShM1k8SH3Jlzk9uQFgkVesqISzfbyCxlGLLapz4VN0r4NZVmqCf RXK4iC3GsE9++KNeDUHDy1QMD330IBr//lMDedzMcQgwPmVWhYHcJKr5Z8JyzknN4kAPbkxCrDqZ 8Zp5hmcpjlT69Mj546qWkaH8oeaPl/3hWCU8so+j3zx7toMgll+H5NKU+b3Zv51wZthSsqGonzw2 iTLwvw+jD06pWGJTUQaPpaPY//nD2u5l3C5ESUBpmAXyKna0/iZ70b8/ZPyJkMP1LpvcWV4Gvjkt MIhnJnBEqM9VFiOzVOEQs7UEgJsBCjH2ai/jdgauaQKp8SMuVFT0OR+hZmQvehkx/97KkHcgrn52 tKiBjf1fSzguIJXQFZy+jsnawz5ohKBP/4sAYkf4JOi5VXySNNE57vDEBbJAZFs6bJ97waD1H1BU 5pPFNhFT2RFSogch0KzxV+t1itlnLhqFeGLGcKFKiUEZXohgE3WJIVrQ+/2GQue+g16uuf98+70N lcFz7bOB0sY1+EtfVuTvH+wmatD9+fOhIJrOshtdL4pNOhdCB5pM5chnLNgLnowp5ZV17WoJMYNn OtFBWweiRcyG2orbwhh5ZL7spcOfSWW+IufPTg9Ac+DOmBLHp+TBzjwKbU/WzH/r6uyCvZ/FycGq UDZDLpNWrg3l+jl7RTgaz4WXDiDfDkmObQvyjTWgevdFiYo7xeyHtQ8muLw/wTZe3tLZ8xkv/yS+ 56ZQiTxNPwI2ptX2m4r83XsSTiLEAVe2Im8tMhIJGbxiUGg10qSOpfx6sC5NSYlopAl9tgs9o1jU YQo9B/NAoiUVk0v5lwje8GjDFE0Q87e4saEcggchkIYHoyf99I/3mp+p/NiKx/kpoh4HB71BDrj0 5j3GDnBneT4Z45g/ACmMkD4dzrqRitESWH8SY9EtWDgOaeXk7xYgksNChbrZgsWW5ihHnsJiJ56N W00Iy2VeXgxDG8Re0B4DvFuIc4uurosGNbhBSOG76MwJYGfaWwTPJjvnI9xcj1OE10PFKQ9XVtkh qQ25iy74Vb2udakALvrdm01Dfyyktv0mAM7u3ycOjIpHUaoKUnFUMiwj+tD10wMIVxiNmynQHvgt x+LnGf4Y6YrivAF0DTNA+ZmXyID8XkFThaI0RnY2hnr7UljXFctGlOzSt8BqrgqLU3PaaFvWBNne 4N1hxymBUnWMcLBCWCg5vxSL/F+TPjYNPyVUp+2HIz5SYWug8GmJx4HIaacMwSi39PPqCvFjJbcJ shQ6U0WDGT5cCtrl7lXd5/nhnECraG2GjmGvfw+wLsE5SeN0I2NEcutPxzfGaD1RKUdBxDMMIN2Z 3rlQ/Vu9TIgzlSjGvqUwJxRe0rZ94XbhRcUxvbmNGhGczZk5adDF9GtVQQVcN/U2WKfUvajLK3fL Zlwo1T72Syg7BqEkLC1Czx9oQwl/TO/ZIkxAe+ZLWQO0CcwbBnMfWUk6ut1Mw3y66xKsnzJIi+Ia kzM1fLfUQqFjcyVDF35toVZKUQCO62YOPO25h4M7rhTlpBLoAFNndoNWQuOp8Xd7smsdcFYrjmAz lHeLdlZYy4DxlLtFesIur9qij1DwxvfHUdR9E0Jjfs+NcPToVEWdoMnCo+AwEemayqSZy2EteHnf AQWJjqeIYHMeUhF40PidQPYoTqm0zW2OVL3+DevrZmQutyKHPSkFBzm4EC9i7arJpSSkA8HJjEV2 4rjSVzpgxNTaxU/HaaLGNQ49AXP/yqvmAVqFfyfl2kCn/+NIU8cQtpJqwOZ1v5f49HOHMDaarISo SEQkm3uTv3hPT3UPsNscxrpO3m7IjKWxCvDRNaH4L6ZmIfVbWb3jRkZ9mb4/F+bBSE+QOIjTjW4D Wk5KRDxpSmdd5G+vm4JocQ9F3Cpkfet3gz0pv3laOU6/6eR33bl49dJBhqvwTzvIZYlx9kB79kFD QWJ5itnlQZEGena0rhzG1nrM+Oj3m3GRwIWTvvZCB/mVQl3/9mR8wQiTUwwjRJ8QKlWa4l0VM9+N b5DNwlZYvGidePcRco9c+umAx1IkAtPQCz505BxLvP4/Fuk0ZvHIFJ70BX7dPPnc7UDlG1y3Pb1b ldpvL7I9zYGEEgwSqUp2ZBbmjQTuIjQmVhz+xkY8jjOkmOOOaWk1nqeJV2emYe536tPKD1bq+chX jgCcYMhTpzI4dWcW9paKlrumkwsi2xzQtnRViKjJ9+6+w92qTQhPG8CGSH3I1wvd8nWbVKM4jaQD t3LEpFrqP2ziabRLVT+X7ThIviOn38fy+PhDe2Rq5K3O+JSWeCQBD6eTsmPzb7nvbdiEAeqiUMIW GJd2QKsBw+3DMeVTEzpbcvfkgar77Mm3vmLqVn9YZJ6Of8qMIiPgUW+G+3SRyO6pPbrBRUlZ4upC iztoz6aME1H7MxC1yB+vgTL7dgB7/tJiS5ek2Q354wDtD6S5p2bjbKh8wThDQNQx7L3vx4UxXJRF C+l17fy4rFyR8dE4xvOXzG89S8njFjMehUo/JEBePlkOktivXrzTBBOH+58PA0aA+hPzYs388rGy beXUSbZQT8okGWI13yU0WptVGY4x6TDr0SLF0IpOeUtkiNuU0aVcxWOF0VCw49ChQc2vpxs68Q/J s5++4HpaIpSjpwuqYjGtm4bl2xwL4WPhzpOizeRjDrK4l0ZZGgBHi3QliJ5LznD0nsFlsKkX87lp Sx18vFy3xVzQItkvaBZt39/pvL+AjZy7xmN6EFAmfXLjsnAkj81zsnZu2HyFTEeb85CMbVQ2+Jxh 37xCrTdonwpMMCgXveIwBoIf0O2iA2R2pwn9WE7C9E6iP25z+IbmCw62u78+LWl5bFOHzZ2cjYIY 5mYnvYW7MEXqYDOJFIjtjZd2tB32p1zsUIMuUo0M3FLFZm0HKApXmb2xT7ws3vScEIhUKyj6lIi7 BcWOgOb0D6pD1qnr/0/E56gRsFvmdZ1Eio+MNbcr+OaA71EFUeYJcvZs7imyz/yhS653QcQoIk8P ywkEyVblqNYReOVI3N0JSW8yiZt173uQgn5cEtDHJpoxmyHF8Id9WFyhG1lOQv0wPENknxwzQfLN uwFex3Xu+JNzRvNx+hPkkKNh8H+H6vmyBAEvRAOtw32jlV9lxegO9jheVK3j6ap2UnXUVCKSHzyZ MOIpp1a9gWwrDAfoNgEzGoLZu2YCCik1sSwortj3yly93RgK07IUgBBqVA5HTQMQNk4yLSz8oySg yr8X3VnsGDO77xMcGHgge81jLZVzoMcBoq9iqQJJJcTUo7vTdWkzv6qqX5AE6U2WWiovWBk+iWrz 52urRBvw31LuGh+lsmlMPY8chgXL3gMUI6vX9MX6YTgbyuSfyWfhZsvQPbx6mqqVy6TMC8SLMPpR gvT+T+yb1iP8wVVU7xOQGaLyw1bRZNJ2A6Wz1PyH8JyG7ks6sVrJnuTYRTnecdZTguLeOEzBFpn3 VsdTXNsDaSeAr5HzNyZk6MfK/cQ9gsVLbrKxZ3Sau+Wmf9fXax0kK3GEcwWSlKxgIBuN8jxhn1nz VM9bSdq4WXsi6N+zf4z+Llu8s0AGqRAnvAO3nA1EAOnvdi8mRVKhjPTm1aeOm91WZ9ItzDmX51Mw am618RnID4jiIeDgpa9/B1Sg1kJNNLSuogFBguKEQdX3VV/Jt10qu84u/p54BVay84UCdThWeXoG ViglgXFCG1Jam4KuCozGoHpgaRkQnsXPyQ0jd3kaCyc16yZ6JBIbLco3HyVpcsbovH7LdTrmbXLH XCKg2SbbsyggZSJZcyWGe5dwFaN5sd1xge68k47y4+iCKt5D9deri+IIFNuh9hu/6UdkPMpwmiYr o+mHOWJAFip0pmlbgGBiYGV8vt/uP3orZ5PZuIZHPu+uC/Nvm8qgsH0hqCi2fftLqXFb37E7j/i/ TNepqFMCFMsBAN+iVrnX8c4t8kDCY+2Y09tEXspg28U1ZoJy9jynhPE/ffSqFaBmg5nWOs2jHyGh i23HqL5iBAw9dOr9GgDyvbhVOVtjf16uueAAvONcYIG0Y7X3pxiw73CALpO55B98gIMh/WDFHaNU AgeBCASmcWkuKFhWyiO5BNMVekY/e2sf4cwGNThDsBBDl2ZHdE8fyeCcrVSrgiUnVAljp+CU0Vqx Ok6j44mmjW6/Fb0dB+D7UmvtUdbSHDJtWr9D8INC8grWOnUwTvvuIQIsJvrtvRXs4Vq1Skx9bGIK 8Pcrhm6t8Ii2lazWRO/5gfEulE2aQSOcleE4enbIgJ36veGKN9QJysewt9RldG+/Ib2PeS64gUFC s9VgRL7niKkSc+bkJ6HYnx4bmdQKK5jwJAdhSkJ0ftZiNeFmi8w+SBMVDoBgQx9b04fQYUk/XR7C 0Y9geujPO8DZmS1uYXuyNkOZ/gX/iyuK0pvxCgl+sGyElkbILjmVHCfkYUDUoDPVNiSY3IFlZK1M 1mWKX412Oww8TSNMqS8YNrSYFyttQ3Z1sBqJbZefU6meW4b4RUqfNyKT9qpgzC7++eVsHenchQTk eqmujzs+ySPtyoIzbR4LGpiQW3edZ1XIpDCqwC9fBGTQu/PmGrop4bOJ+ew5XVC+hva1BbXxTWUA 1UjqFsOgiU1eCK2NHjhbyjs2eJhDhpc8hG3r9eESkB9AAA4eeq4y7C0TTEtErcx7p1iF53h9nW5e AO/NpNJjm5QxC7r2vqgHrrEhKfK/fCmbfCrPxDOvBEJxoxK4C81CUI8SAhuRCRXLB04JSPk7fqwa OUQb9gfV7XjQl+3+sI3AQDXcDf3qKeJ6Cq6LzHxa7e5yjtTZ6ZW3oVDp4LAIsA9u5SP5/IvVn/P1 WNvac2aQAhPG5+wbTPeKWOiSKQpmLJHA7FqPRbOnDOjSLy34DPa3F/E74l2HzBlloNn0WT56t0rZ xuShqpCURRspL6tqv1gZmf0plhotMh0nXqH98hgF8CBF7+YOCQ/F2e9J+vqBuA3wlXI3K5UYXwpe 6L3DprqE8aJq1yTp5ba8NdhWJbxq+KRH+8Y6LFNC3euMa/sQnwEAEF9HdblwcKmohdTusXvG6sdy AH6xsomJWcBuCwRHHGYBXY0lLwLGG9Spt2VkbdD47ib77/PlI+zeXyM+hPbu+NKtoUom94Ma34pl gu4dG9Zg3uwSoOCVbziJkQpRfSRzeFihNNJbE20lj7p4O3w1snUUjUoEv/J5greqnf6rfmhCT5fp aOACXCXKeCp9eWxBX/KyQZhAL55f9b66/lgBnMU+QOEVToLjq+V1X/AmaKmG/PHo5vidY0ZRz6Zg /M6qPSfBJ0mP62ln1j0JydOnGIR/sS/mZzaDaoeyTG30fsyEmVLip4kofdXUxkWlSKjxZv/BwdVL 9ovHXhxBVMgGLu+PUjYCRORLOjagmZtI6AaiK/MZGwya8lP7Ief5N9lJ4z0T0rzPDTj244G3rONd 7MmWIelxy4yI36AGdrVHme6O+X4nPcSEIRicf9aDGuDKsidEMhiXP0pVXSv9uzWq0w4W4JQ1dMkt NQcF5I0TMyBXMdKmKPJeyt7md1Wnx6OBNCk89AdfPFOpcXqLmCXCfjtynd1UzivrBijWq98RCEKH 47xmREB1UTCkjf1GSns7wcqTfDth9TJrsLth/djMGtWiPav2oycv3PCRhbzpZZ9IkqdlILTEJHps 062Wcu96fR5E5bjxulVf8tYYowyJAcK626C8t3f9p5lRiiRNRvSHT/3JSxOe5QYTI97ZAQ8hOiVs PzMdY7CWM/0LMwfrpDrzgWMOmlghTrrWeuhpcfuQE0N1zCC0rrHyNNJ8oRsG/xOPhTFv4laKx1FK BvqQLbAZOqFvQt02gVe507/7G8ojsnzdGA6FclXPRZ3axEQwGp+M6tIkhxTe5m9mreDaeeUkkPlp Wkcdsl08hMkQd37Tf9ckeeyEZfX92O25lGpHT2KeI1Ih+jcjFXJEPD+fhqO8T79ydKPZxTA/Jyt0 LLKtxTFLFKTXyZ1GtG3q8gphmydJNFxVn9RcLufRGeEvRnWoIvuSwQNPYkmjruRhwZpD9wPO2lbe zVSzlvWipDHKiFkYCdZBAYllDEsTpvPXLWTX3BE4Fa72m5ynJMG9M+xhtu+GcofpTZ/O3hji47nj Uh4LLBtJVL+4g8fo+OXprCXnVbgpThIzAykSbL63rVhbQc0BRD/UJB2LfwJk8z+igRgRw1THWE3Q OsWDRScZnK6KqQz5jBf4NfQaC8yb4Lo8F3bvonCLMMZ2E5HETkGwQBUF/PQRNfovAfoVpLMXl7XK ZZWS5K6C+b7VJknzCW50QNW+PipBMHEdsOii48WUB4Cs+87iHG66Hr3tQ3ujG4bsKbkeXorKfk0l 3tecvUjMsrgIBQpfuVMBtdZS6RjHqqXj2QyDqhc7tkPbGITwJJc2oL0eij4GOjT4JYBJIE5sUMU0 wkCTWzGpj3mxrfYD3fuQKc6DCZGo61tU6MeMCGoTVf3OVNyCq0TFIzAmYbL7ynkO+SzNNmI3v6ZZ 3Wjj75ioXL7Ju+GaFVZNhuAN3wdDs/CH0yuDgNm3um276YJgiLEL/Qpt9Z+HhmhyFVC1jgY4uIYB Nv3fFyIXEcP6CdNmMkJGJwEqZ7oZxoNhtzXkWOx6ca2kZsA8wbE7U+fndz6d/AInwtgxfZVPUfYX 66pBlJaaWUP9SN0WN7RprGuthxQZZ4OB1Sq/EJ4kRptrHT6d96OtUXXenylGz15b0OpHovMc79jD vqwEEvkNs/KHu2J9SUIo9z2wXvRA+ShQsyhi9E6AUgwk+XWc6lu3cvG+w/dEkAs8Wrvs+ekgExjl EKlkMcvvcOmJvENpqd1NXtrYEWvDYtb/hPA0FJ77SFz3zOZ6Cw9c1MbA6kSNlpUwizvaTNNN736l DsHm2F6gvkm6y6J099Ix0e/CfJUl4877dT+C3LddYqHvT2bFQjrccVx7Mmxa4GRyLI6+NunWqsip 6a53hTGmGvqQxVvsxWKCxSPnFXX2wGOMUIqeogyRdHkdj/q5+30Pc1h5SnStAXWP0wlX9FZAZrZU QW8wiysf9MgGGcIkjGKvo4pnfQykDAohW3utUz7MVReMiNi5+puGUJ30CopDsBxzJo9dp2ntIzfK MxvKX4v3AJtvFSBR3S9GduOH5woZ083TSbAl2RtzNpXFyj6m8AzxL8qUAoR18RQ/kHhCtro2XRQJ 1PrORKMobo1wc6DqD2AE+yB6ktpYruJmFTC45Y+650DXrNCJ9PPjkeV6tTi8eVW3AIUntpdOBwN9 hgxa+aPCrGBB2mkhVs4ArR29bKipZ2XRlbfyEGZfOfH/Jd+rM+Py9SXADDpU73PXbbYxJ/FGLV/o zcw2rQlV7QE0MzuTZE8vSH8Tiay9RZyRU1U1xssKuQy1Hjf7pGN2/uk/HAHoTH7yFpty+EqnnX6C 1GwLn8lft6M4SVSKPRK09sktSG/6kq+a61YdsTv/ZnJuLhaSNCPf1zKwoPxiUSauduC9TAQehWL+ 0cYfdC1LWpBzfGWVGJ5k8xGJo3vM7KvqZtT8yJzBmawQbIcEOKriBCp0SNlNedj7sSeFh8wG3ODP s5SrfGKlrExSPUrVw30bjiMg0KsFCD/KsWjPt5MfvRJtUw5BEMRCFWaTrd2ifeg+Q8hx62tRU/FU AuSzpJfIxL9kQjIYW/RPq+wuH6AXmO6c8wS86eBTTKdNXBCqeF1YQ4ILeUh7zOYGQwa5Yy/xm3mi 3xTVqyCDHbDS3T7L+8yVeSXfo3CQpkOWSUxqmqDY4+uMnmzRINC6RPNtySx7vW1CLbcG/FC2PhjP rDYl9yMjvoSVoSuiIIA6pQLE+T6+RAKXglmIHm5rSOwG57xNhF+NGLlazBoSdZW97AX9fUijwJwx tXT5Mtz4xMDlAIqIgl8HBGJ/bTERwMum/6gveRdLvqQUdZ9Tiavpg2b3KIt72u9eKIB1KnXDobc/ ORBhSn3MWyg1pbfLrG+mFoIJML1VX/sB24B55MlPOnMDKN44T/xH/2zrS7sDQIqXbZ0HQ5IcL9Nb agL6JNPs4ie1efNNvb4FmPahUlPqcSmr27suv6ERQXb/MHGzP4Rvo+ujioxLboHDA3+J1YsM/Y1+ S47W45s1Zqo+hyHyOmoAnc1XQfkVHJ6Hv8AzVqJ5ZXlZ39/YaGtxG4uGLt0hBWfAadZASrv8Ae71 z5NRmjtWoyGPOLUvAiO0LHn7NK7T6+1fhFk9EhCO4VDBdsZmUltOaSjQHzUXBC5WS+5PyFEdi/xS sUhuboAkvcxrdaPxOHRdA+AZBZ3tNJDhGkbQeKWy9ob11CK83vmu+uUnZCxc2FnF2xOEh2Amf0Gx 0QlX9xTxFpVvICz3dHlAPZigBo8vMEUf5oZefp/InWeszxldCVfTFFcQnSr9py6EMTMELM18p8hd fS/O03u9CWyqFYBr417UcMNaj7IXjITiOj7XZDUq2iLpUWux2+vW7cMfcnLOS7YdtrSza36FCa1l o8n7olYWM+pmgcAcRGhKSln+PA/h6NHMlOc97Lo3WH4ZNECQoppmPZcpBNUKuHZjGpf7u+Xmb60G 1nCJDAynJ22PNS8o+296egVkERFjTVgOk7HPkL3y6tqofV3ip9mjqF8BFJSYGZkpzujU+gkuLlJR Rx1cz3vHKtPWso952vG+L40xjfnT7Asu9OyYWc6NLUnN1Av6BGfLqUW1H3J+yYKiQbCP6wjtIEq+ 3SxhQaxN8Ip1Hnz1Bpl/U2WtW7bJ8DcLsilBiaYRpj1gdeLIQS1y2vDK9P9pGllsDcm3aXqHVzNh NgkYxkdoMEPXLahrifbmG5hDlMmNwMkaf5OWZ3h2NqwI+04BrrE1rh7UiQ7DRI1aZ8HLrhcrAng1 P5OmvjG2DfVI2dDIblUOX1dGKKu5ndacO7JzjbRt+K5cccCMFogrTp3tWCF1IPnMw6AjGKtzeuO8 XIhx+gIjNaX4XuiQm6l8awYq5FzJzRWclrGJmiKO5eTKxeovXmzY3s5LmfPK0d/UZstlLWBloO0g FR9TDvgDCtt/EblgmjZMHI0n9ZCjPjOzyWGVjLAUPgJU2y79hB7ZihBgF856R/znbe+3LRkp6n9U EkvNTkVSWr14aLfZcpcTCOETEubzrZO7QYtbA2gNi1buTMkaSesbT/3AmZTWwCNFBpxc87wvTCy7 Q1IrOJj08EXr32gMb/7zqdXaUdJzsrIuT2/IEqmsJqzsIyE2QXLvbweLNzGRbF8R8FFQ69AZLTow pt6X1xho7kCUtDsFNFbB3zhhHNT4ozuVWlirtuE6yJ+esDx1OIO+/A9ggcleddOHp93CzAg6XC6i LB0QYO9uRZPmtPXoosqEUHNLZ5MIIizbnUEBt1yW8PANw6wE/o5EOfdieMBIxFh6fb5g/dxsxl/N mRMsjrWv4ghshBgP/GVdESXTMhwRRHsgVx/IP4W78hGsIXxAJX0s7PuEgycMaHrULYIEQ0tT2ulC xEDQwrjfFR8Xh24PvFpO8Noysv1mtCJoMirPPiMiNJ8D6JKkBTrFZ5sQkL6/up6JKYuEfZU7I2wW IhkUmmCxffxXeCxNWNMpBw8K88Tovip1Gjs9wQzhU0pyXm/JT5s53KJQm0eObLofljZHzUSjDO1h LbCCaGNOsgi4VxOBup8aJkx1ducqvdePZJdeiVlFrCHFe1PmUI1VAKUSzPG+Xf+bVWK+sihf09oK dg39AaWegwu5+xCY2W3KygTMZFgTdMf6R6UwETGCBF1ZxESJJ/qsEAuAb3750li/cWSKxe1Z3DDM FCMIzI/xRKC0vdudnANY+d0plPNw7D6r18/9kcnlHqP7fjJJTwhfgTDMB5iql4jI8nDIL8Sqhc9v 4kM7cD+A6B++fM3o56Uj+ptl683X6oC9pANedmODniQcSsfj8pz93kcPR9fHpLaQHlxa19KV8WHf TGValYABWaiZjcyFoNGmvmCkFnLEjh/zZAA4g5DzU8yo+zMN4zsRH4g/qWht43Ja9IdqaLCh2oxE 27E98DuojMw3r7Jry5IHrUkCo4s4Udqtj1iQdGPJmp31ct2vq7sKQPr//PN63Zkyd/iGXEqDmq1x KtZV721017UsWdWqIXU9rd/9zACJ49VQ59mkZ1XdJgWATX41W6nkOCq1oHBjOtS2eyoqhITgw6C5 50l0ZYfPpQkbssU/Y3t5lL7fOZsyZCEb4/TnOJ3qqZNIc3wFC9B7R89c9MxeDBt7+j6MF2E0aw92 Ou14nmPkYHt+nkfsfQioJYP89ja4SvGf/dR5dF9eexPC2Z87qpNMySqxNlToNW98fcP0JEq9xIBx vyIgZ+MmXFzPgDZKS1Yk1Vxl47/UXQuwxFiqzIUDrJEl5VNHJ9olOXxOS23tJVu70YYDFGLVeUnd Jjw919HMRMTmY9gtcSbdO6Ll6WRq7VD81tRI/AFxhPQ+4LQd8vnnRSW1+83Cs9ja8LZRHuuPMTDy 7zMW3OZVBnr10pwuxye3mcgpYiz7KxgSX9EDlUQ5QAlmqxSBBYGRJGKB/uy2ayupcFjrXQjRdmDJ kEHF6I+meoQahY7qtz/AHe4vICSWndUPUZgsCW8jMts5QgNoi1QjFQUT2G5oHkfy5v6l0ct7X3SC FnQs3MOyydHS7xmhyJJkHZbsmpau3CZPtq9GpZpLWzoYN1EI6Er2MsfXo66F/uAwVHeKbnhvfXW8 D1ejNpDGfK5mAB1hEyO5lSwO4ITowRVkrx+gI+co3VDmVKtvPYreeyCwjHlom4FzDpcyGaKiPzkh fvnA87k1taglOxWLUahP/Rsta376Th+GYmmrCIGfc4kNlOJ97YOPoHc23H3V15sPRTv8c8K1ULLO Ibu469IUOiAzL0ZHthxBYwGr9Zv//OsRqPuSVre1/0zA1BHDllpVtEvFczu97kGMFRiyVpYjVF5y 8P9i6o4WrYWq3asKAQYnzOG5kDiCeTatfAsppBbIXHd6D+5qVcmSzh6KF2iLSUDvhOSyT5eGPrU4 4n+/I/3PTzFO4xkO9wFfX95PDsDKZuld7T3TaPyYFwkW+Ua+6GlKRsvcSZNFqOGSWDNfty5rJJtj 60+Ad6MKR5QNko2oJ+p+Jxbn9BqWUm+kdYoaSsoRGRPP7NY0MxKLfLansZl+ps97W40PjGolni+5 dHCSsOvsux12LzCoWe575qYYNwpiFG5/iSRBA0ybWRAw+CuuEGfm2+RHShIrmQvE20KXltva7kHD ga41qZhCx3ToZZQ1sU+omVhHNSHPafwuDJq9JqkoMAWIPkmbML/JkRwgcLAoAIN+yTqNsLmBtBnC Nn0AXvzN4aKlRT80sHSkv5nvZmuxEqnVPsH8euCnlJS43LBUliK9N7O0RzlrbJwmMr40l2yZQPgr 0M/q0Gkive+QWVMC/ToW5j79sLEhuDa1b9tyg7ifbzBvrvfrJOBQFkY+rB1ro1bSa9h2hxwn4JZP XeE32gR9Y8YV+hKn6NuP8H2r5LrGt+1RWSlgwl+4Y1yZTBJM8X9mxP2k321zagDd2vJX2JuV9Q7I nBGxf3qGDvmSIq8IbYjWW7vw20t+PAdH7QS8ku/ifNHN8lfxw1tvCfUE6L2RcoevwKdwQee8rIrF oBfIwYnaXpkGlKH9hpfdjhbnlsmIfX/d3C1JyDBgAmcTXaZeUVdGeABeVac/yWvS6BM1Z1bjlfDW M5stt3SR3wgqkp2+rEH++KYeotIgUpy7g+kbqY28hbS2+m66zUXE4drg/fcYxNu0mWVJLyZLULW/ p7u5HUqrOJOJp+BZL4PhNke3cxKwiReFnNefTOEq/3F8ZU1qwp4svJdKnr4xopus8P/H0tomWufY W3hz9bTb+PP1khSMWIVhgWuFVjpKrEgZVdJtARUxuf3XiKWr4J/cGam0Utwj78YEjVWAJGFQM+/P kq+Wo2mgxQI8tiA5PJwluLjg3ITAKRwK3z4peU+SVIjCZsY1pI5SiePWAFIO7BODTDJ3nlaDBjOk 7eEFTYJ8go1fXeCgQcQs92umO13dcw93iE1217QjvpN7hpYim1D3K/rf+KxYQ/rGv3JY9GPqa3wu quoG2xRsU29PHeNwUqdpCUTna5l9s4L3RXPjVaPJvUZEWCaYsnG0czQ0WJM9fy0xH+3yCXK7aCx4 GAKb65veesdOIq9EAVRBJydsMwn27YBoQshYMZEM/YYGMsZeYLoNqv5bFrIVkEcoTuSuJvKqLFAk yE9zNVYEHm50vDSYQK8Dzx8B6sAYFAEfiG1rqiyemw97qf/045FM/ksQCkazofmRjMP5KD3NLEe1 6zAZsZ51W2MJK9AsRn9PTr/P1c0zAXLjT1Ws0EHMHkmDijZC+6dgDeTBkZ/OVHcuoHjHWXSjHMNQ urPD90Hn7HFFsNsq7TETKS8FpbLArY9aHVEPrTVKgplRt8qleb5eczgKQ2UWxB2LZGYL6RYINXtW YqeUytY3p5AlC1sc6ShMFH6UkjzbIFjNhzp5vKPJ3UTvsLD5ctjG/qLnJGg3aarKOyhID5iXggVV RkuYmImno2Zoc4sdJgUwIR1JbPtVXdEDKOHl3medHlt62jAZET95RfTeRZJPWGY2dN2IahbFzRIB n9r+B6unjtm1965EcDN5DHFAD5SzEeyqiFoxdhVQQjqCamkBDXB2xt758AZZ/vZb44Ssus/8vHtq vtrNvuNZCcDTAJGa3x3T+MNLC934E0HOuXgu9OXEPgkbECv9x4hVEBkBESyn2KWeg1Nqf3NDOTQS b+95EASQ8dN8rsDISSD0eTohxs3Ar1orM/VCGq3K07BiRMoxyPfC1ky00lioa4D/RjLYCFhWGc+Q q85bQe4vhZAoid4SlZ2DlCJytFeouPvMEmINARWh2/4Q3+7PGCeEoN4/aEF0qEhO0PevxOcHM2bt eFQNcK1s9fAfMfvWs5wE4hFhVL3y15fc6CNziLj2Diw9j+m98qrdEefMH06f45te7ohxVF4yG3Z8 2Rw3BviHbHl+AHH6roafTkFCtcglClieRZoSXKhTh51wtng4fpFLY40VCfA+UXpE3nhCKbdzwIMZ oIN2RFdhWrVgaGE9mGHRW6b9VmXeuQwfi7QlcxbF2x351VeLrDQcqXEKOOS1aA+GbKHFsm/yjAef EeibjAv1TFTRok7J5AV9kZ+Yz/tbsxBOf9iHmC8X6K8nh4aa8ixCyNo1Em1s+EU+9Zh5JlIgVoLW XuEnMlJKTcn0s5CO/c7u43qvBXfIZ7vv1Xfryt4sKKuOEgCwmguEz5xP3leeduJlDgRHWzzIo5aN sg4Dn+bYJYxgB56kLDInFH6e5UmDm4U1A+HDSdkcSHnIYd49CrdCqOOm0OqTO1XJFZKd9IWqXVzu PVaKVrbBIl/Q2OepATsO0xK6wg9ZQPus1KYiSGNsxZwf764N1pIQRqdo03qQU3tAPjZ/Bng/KN6f fSWikcyAOJORrPixu35HGepPKFcQD7z2Tu8gLQiRuU8zWpBrEYFmgtRKohcAokpYgQKpfEmH71ju 4EmLbBRlhTEgLy1UQL3jkGwGsVw9CCUQdDX/YeZHU99FlGavcjx+3C+9VT3DcsQw9Z3g7MCf9cUP n18rIcIifOxRDd7qsqC887JQ0r5fvF+6bHSPTq80js+Mrbd8Jzt57CaB+5F902yufv1Edog2A/A5 AtRbSmhextPnXXOHP04GDR/OgWHGboQJFhC4pEzTCB7Vg7Wbv4EuHOm/jeBslXQ7YqNhZ6vyMqDl IDzhq+2sDNPtgaqFd1ibs06Bsj+mESB9IWq5TN6JtoHqi/L/gPpkfD6m0Ha4RObP1FdeVbWVK3MF 1m+goUOZfT1CD/HDEXlP0ZsgwaXTxwQsxYuLQxWP2TUe0pCO9Y0UAAZ2Jgb6/MsfEBMr4han5fSR p+4no9FL/E6c/0RNriu8ZmD+uZP1d93U7zxiUPi034kO4lIQxmlSFkhDpaHSPaXQaTC0MzyZjT3l sqz+vmLcrik293tuUb/sC+ZGBxEl2WMJDF+JI/NK3mkB4iS+LI+CJ9bnh8r5cIZSwUe0+J1Dlr7V rnahBRcYt7e/jz575Z814+PbMu56o1bX3XvcGu70X88VxRIhdqyz7rO7Vm5a9odg/U26H9Mz7rYU cgrLukI7v0slmO1T8rS3Q1EhxK/GbcuGSu2pi7SnoFSvrDccy04bYsByAGnFUMDIghZ0evmQpQuh UA23g+TCxaFXQ0cVci985C2wdz9GhyVjQonZIRZ/kXDCSyASspLwGAMjUkjOUI4FxusoLs5TsuRn cJqDC5FXXuXuQyq5v0dI8zfLYfZWjmk9Xhc1RM2Sr1LtKbdQkPe5+0ruRVaVAHkV9Admsc69aVeI nvs99CADhOlf0ZnqOROyesCEjXMBUnnn8xyZYo+JTlYogRZBrYqQWlqf7L1zh1fCrs9i2mxNNPB0 DgvayyXkCKK8dA7XfIyztXmMebgYu+LBe5I81AQH4wB5bG67T4CUtFbRUvPHml5qi9Ub/x/WPsna XbCgtRhRfRr50DRCCgRYG7MR+HhNVwcTHYmnX9Fjkxnh9UvY8b6y0H7RlI/fNCPbhH5EK5v3dxZO pDYz/zVhHsmXlmZVz+yuCPMbCTpAEkx74YiXORIVIxBdkFgMrtTIxtRyl9Pc3JgQSHZ/N1x++fi8 PYGG2+HmJDZefLC0Q02luvUb9LRr9u7qUHpGCTW6jOFpq8naSMpH2bjC/U7NFy/TAN89l5MIxIqi 6pUfHOBQu3GkDlQ3z1zFqufGeJ/+xFD+EyBGwy57M1p8pWKTyWLMqL2JzdVJtKQUWG6WhNUbR92E 1QAxS2OKNXw9IhqRn+b5MPFml4XqubKaTt+yePZ2i7LgJp/6cEXu3hsczfFT9fhqHiV9P5T7Xu21 N68thlyF8Vcrg7FfRmfKrjTLQPjdKCrmQpuFpHo9PQFNqMSzBqS5Eici3b0EFcXNTCsHvmaY5BkC uiVGd58pzVt9tmkNwvBUhLYJ8I0aF2CmdRmlM94YtNFZ4OdVbehFNgMqUVSVmQeoSBGGJAsIOjHq JWgEMyuaCNAOC6IfVBQcoEe1XX37x7sPLEnzoRWFaM2OBw6qAERd0lQrlFb4ncPGDVRvA9Uit6yW 3EqqsZzOHBBwKb2nbTlWT4xjokUK119tE2CF+nsiS0LlVC3OFTgWmOkuIOyvaloaLnB02C+VA/7e x+pwRGNsRqgjmYvr9TFV0k4loyFYggDvq3hw8KH3w79d5WumtuY4AlA0Dm9DnqUmnj1Sa28OuCQs 5/HXJzjeO7RWNP+iXht8P/wqHww+V/T8n6rfp9k7XY4hxSo98WJbY89YHxBDvFxQhd5LZ7mbGHA4 ao5fiibT/meijumr/mPZlmBOhclP1ISzIan4p15s5u28H8HTsft0gTfJuW85P7EoaZg6wCNNpqMf 4rCrFpC5t4X6w8fYuxPpSmcjlGbcNis1xOGHm/dwdFwOMACghpIcn0IW/uz+wQA5IHj4gU/gnFjd Lstn8cnYumh+HUQd8exXqRHYZNIFLoAL8NdTKhHpFrK2Zb2CopFiw5l82TQKrZUIcTX1WWr52GUR 867LjZazXsKg2YyV/mt2WDmWXTJbTcRhTXjFvhF6/aGzkZvQ7s4DrigOmD4iXIR/iBdYlhR546tQ j8xhG4qbV9XkreA3A4VASHocRzGuUkWlIiDpSSbg54bvzhPCs8yZvKRaKN2jwRJH1MwVV/UrdNJP 1k3oP/K9S7jGbdDT/KNKiFIWHjQEXuKNVn9NrRBs0kTFUxmIvNdEkFgFheWpp4DrCuMI85EJEGYC CaECcsMlzvM1XFj80WG3DES2/NZVHUeeiRT1vjZbjeHY3WhaDsal32imnLPmAnQSuRYOzR+sydZa ungt6R/P+MRKV+5ruZrN6Eq/64PTQ8Eu4JS08grxBwSCAnxHP7EiDiVuzDKGWeCKC96otg+mmNMb LrcERmOq95ZSv59vaR9LvTj91hSajFllygTiqK5X4g1ycIvgonBFK1DtWuNX55maXV1E/O0p3SiN Hk5cM1igA8zXIqN6t2L5x1pQjhMGqcSlVqIJNlI6Y5zuW4VtWlfolPMJAljBtvoHTAI7pV6yvMPa uEDSKLMiB4LOdOtPwaj+sGfpqvDQgZoOQMx8kR+63jrMfisUeofFhOMLv58YFHo0EoMrT/D6XX4D GOXFGs2sSXxh96FDHrbXvDSNTne4j6GJNCtTpKj1sNFgdDFBpfX3mBTisDzG7MCEx0FkQyOumpwo 3Yi5fefJb8FCg9llmAK3CIib5vYhetjhnwMZOvDRcPZLIWYO+eAN3Y7cwGQYPyXRcxiOWyDqA1IY CJFGB0na8EiYCn6goaNHQ1rzMqpA7xYcHbqoFwD4reVZfS0KHdY2Kan9d2Uux0IsXJP/lopaeMm6 hybboErs0z/yl75SIv1EEhk41aYSCbGm2FOpBnBA9oDZlwkA39LbKWYBQj8szjvlo5IVJyqGsan8 W3JvXWQM7xbnTUvBVvMUelx7BMZBs2VT1pMruEVdnm9T6qGtYdufjXeI9HfiV4d/jlA/LRHSuoUi oBaBGhYdaaTnMs5EDR1IfcYHpjOBg8UH9IPFM3hXO3Zhfv7OvqR/A4qWJW1uCiFKmyPZFLohk71M M1srV57r8D7kiTRvFgBSHI6jOZpAtLNcbIH/YP27qKeOiALjn1FnzGIQ2DJ4IWbeHCifpz51onU2 tl2UQEP6XXrsBSWFErg+nKmbtcfq5ZNdGNLmPdk9jmFrkAlgxVrKhy2w2lcp6qXFqZUu+EvEsdj0 FijiIzgcTavlWY91nCIcj/H/UqG3FdOAZ6c9cNK5Q62NtWv64AAYdaYfkgetMiqYI+NGmVVouxZd TASrvjpt156nw1CxqsIWHU5z1Dq2TakyC8G7/dObhtUc2ckOIapBPavGER6hEb8O85uauR/Olmyb NLuJued56Y0w546o6mlYtULfPFqZM/kOmB8vcungL4JBC67NuPE1XJjmt3Sp7wx7P8YyH3v2+pwN mZeSD2aMkfvG7ITn78qRWXe/8FedS2tUkBuwNHFCaXOqbjIxa5sfwioiDrVVEZMviH0DzarvS8+4 Gr3y4HZTMZBhNzuv6+OSu/1eCoGU/FElWpvdXTh7zaC12i+U1VUREQELq6yPuSWZNcUrkf9YNNT/ 0mTl6p7r3Bb7spP2JnpD2IoHejW3gsulSsbp4c5OPyriYTpqR1ceLVMEOKN/dw7+qGR1IIiWQIEZ wKbqp5TpMXRfH5uk6X6soCBcRObIKNadzRZXsmN0QacepWl9OApAZhDF1AMdbIECyEftOW+LACKV 1CX9LVuLMIiRNSNWLf9U77gXGGKW1xZGTFONicLA+hXnKx+dBjYielNoT2EXsHYcVSywl6k6ZnmJ CwHEJVdeqp2Fsm+ZuARLiExOVimK6sWaDoytzJ7XWRjCv6rY8HoJ6EUYbS+HlnvYbWOsSG/wD8o0 2KpF+H1IFZVEKr1dt22ZMu/rUrcgDeZqRI3vRc5nW1Oq9zzfJ/pFLHiDbqj/bM1XAJMuBS6SWYw+ K76s5aSpBJUCMBSRz6/RTJ/rbt43SuuHdpDFAHonLOWx5f9NniIX02AtbPZJZj0ylRdoFQnGuWeH fgc3lkSCvX9AH/K1G9Z/h+WUNM5N+Zc9eBMS5Z18fRsLBv5ZR+DTZpzIGMweXv/TtHZWiFsITpnV ZlgTxWTV+yvUPg3VDZjfnQqdTQBiBOctPmAwdikIIPVPnRGkd0yGu8wnjw9O/86yhBIzFrpDv+AW gU2CleHdhWoiIBIgYuszPWZ51EiNLGxtLDoj7PBpUrIskabhs6Z2wOBjwOFtpMovtt1osOVTi5au I2XuZriYy2241HBDT7pGuWWDSRQXrV0OfyaxF5m6Zbb5zRaeY/yIGVRnk34IQ1EW9MCBx0QQ10/8 odcMiSqmYH8ztAggnRtz9CZoDrL0dCe+jfS50VZkrP8BXahbwEKYTjbK7JguYDQO5ZuNsSWu0GSy Qd2gNeKObAxiDgmcTrUy6nsfpYLSfUk/LI52r+PuEF9tAMEf+BjEcKMmV4F7Z0ClRo7ycUrqmoPL 6eSx+IhoM3sZjUG83ySDW3RUPOg4lLYm1Kd3bsSCFoQ3XN/N8vQKks+u6zQi03I8qLWXLFiY42Gc ZE/3v79gFlSPM9gIXhBqlryMASSdshkT8xdgbI+D1oqz/RMOSjrlc2SUSkBd5W67oO33bNSNXomI 6jwvDuhWfjnnoK/P7F1LoFCq01Oie7bQuGDPKcH8B4cykmt8jEBSilA6aKkpVrPjsR1Jkn+2lczR HxERwLMW7v4gnH8BTyg9GxZ0PwNcni0fS2WxeDUSWdKhSgyfBbCaYU2KKglj859A6dq801ZmM5ak k9/Db70aB/2e3tfVzSQ5QLM3EJbFnrhthmbkCzK844EHcZr7jhStbnfV8l4xk8lTKg916b6MA+Wq 7er/d03mL4ZlUbB9AqLDoRajGGIZA//Mj+tQXnx7c9ciVmyNhNMexF2yfeq2sD9BgVTCcZj0j7Vi EOMmERtIR2Y0HwsTrvM81078bbH/rBoUGMLv6ZSsteVZMa0aTm+400EU035ds/o8hHlCYlrgjOOh cG+KG9vIw7S8zdTR8kmrwCFEiSjl/yVpvcwZB+0DCtVAEN097hiFpfTxIo99MeYIYjYLVCtNWOEI Ag6Jwdcr9c3CDurJOh01ECPGLLjMdBjwwQ3FI45YYOEBaD96yY6nJbWV/hP6gsAwV3sbPhQZTpgl 53SBHD8tLFg8gNqnqC3wx7npoz1YOEsS7yXIvOEnMqiMm23KnMzcBqmVDRpbo27t3mJdpXWyak9D lPxW3DLvh3c5ngV0G1ea6XBylOfqC+OpLR0c7dv0o5wPHsOk6qJjUcaPlpOhRnrlYGyJG3nh3yMi aYnVbMXk9kS6VvHznVbc476Aip/+2DwmoZvfL22nnBvXAZtTCYoDkzqR9WPU2PbqOUy7BKJsAZ94 WMxzug2zPTDuDf3D/RFeuP3drCUBZQbId4FT9HgU2xsSnhiKAeUO9OMMU3lxjgz8JoM7Qh6nvV+Y RwKK9i/jeGZM40iIe0LVhO0Gadvx9ui6+QHcepnjrpNegqWZ+ZOzQ3zIn9/sSzakFj+ehXt4osZx LHUqk6jr62MCL/gpV995CUFwmBLq3QOenImKi6k5+GQ2Rstnq+lWMsYmF9NPQSN28mzbDecd68D3 /Wu3FJKGepe6xWH7paaACWjx/wN7swKb47wA4TwO0vGxrUeML/owVJldAY7pqxIaOMPmH2HnUejs W2RVP573yahxev1On3/1yX1VrzsNJufKuRjt3YFzUvm8MSlNgnSHroUhG0/LBOQplwGfCsuOfeAu o9l86lEKe0ts0O+IO6rknnQpM0vLoGxHpFrZzStukTCtuGiZ6HgLfwdzaDW7PHLwXlXR9ZEo2HAy 1zSUJ8yA14c0BSGlYJctJtbJJauwD8R9wspmx0JhPuTkzYKUKrmaXm1PkuEAM2BM4/IRj66lBfez v1wwjP+VbWC4lX36lX2Nbd8lrixAWHhwQsESkE5WhgkAYzZ7jIA1j6gAVi1N0wSkb0B0XjjKPgyX j7RJRf17fSBG6PGZVkBUJHkf7BhJI2ROj0SJgCngKt9aBqV4cFd4o3oqRDcEUjMifrLbn0EXw09w +PQGQMh8q1T0v/0pceymMdAwt49m+GrdgBFr+TIAE/sgAFfxkq6p3Q3bfqQa8jLD/6k31i+G9FbP AosTTbb0FUHnfbm8oXS8sXUPNLZiDpsGV4cDbg/I8BOkdajEJV2RCs9UL7cGOGPnrehcKyuacmWH NZGA1cQOsx3qDJO9F6gi435hd3oEEWh8E5dMPQ3qiK4Hcu5EPqlsJM6+3hv5P1vpa1wpb1yawZgy nRdZ04dPct0y/p5/AsQNrdCBTNDjNZZ3442v7uNwdZU+qWOg1KYDBADINsz8mJkqXQTAIIs7lE2f h91vZg61UGgv+mQowzmujfdFh6oh0zioy1MlfcmzPhzEboSX1mXewciPAuC/kcdfQIqRmbWWf4Mc GYas9jAMRe18qUwD37purd/AXc1ttLShnZoa7J0B/xuSQBGfuyHZelZx86VpPjGDxtjYoICyLT/1 JIgdPogs1wr4ewG4m9rMkYIdvNeKyWYCYFvvI53CsWr1hPWt13Isoz920802iuylEaJqI55cpYf+ LBhOVg+LovEMfc/Yb6C+PQF/f+muDkClNt2d5H4L+cGVCerhP62MD6dTpH5fbVx/qjSPeDHIF8HJ KQClEMTiIJNOenkeuIX/FDQA97GN+6VZcVdNOfgmSu89hML0LiUOFS72DNTtsvZxCm9aLuvXYYNb e3tth52I68Z6a7y3G7ahRjt/Y1H8EtpCBIEZ8LGpbuIzVDcveEAEAZhl2DVofZpG52/xK3tuzKqz FJNfgHmIQQoVoQ06qbbOClwlUT3bBPthTPmx0aej7axH8I6iagAPe/oJN9Q3KRVdugaf7hfD9dp3 x8J0nszZwKRsIma+h0syVN9N8cIK9y/9RfCSJF4+EUUDYhwW2Oj/AODkEaXvZA72jmImK1Gu0Qqa k3gXSWoxgMfIaV1v0BdylNAOifJDcbonyxvFEppi1rlFR7u6eJKnJmWCEPGzHQoKVBPAapR1Emdk 3GidpET3oq2015odk9sb47rg6EBtWVP6K0ZWf24wKl6ExdgxZfmyJKQbVxCCO3Fxmef+ZwvtiQdC 7fQOoaYZ9a8sWyD4xCUDGEdbSd2cwqctE5BBQvqFc0ZsJvKwO40L96CmKysHxW/O+3/QMdVeQpl1 jbxYPTiNT5SO1EEYiRy08wxHHv50bvlv7mlT3P3i/j6ug2WSpmMeSQ8xdEPwxXCa8wD56VREZwH2 YeoLs3mjEfT0t4u6g0r3ClkbjxlT3sp+m7uNGW28wnBUet2+fsO5f+Q1A9TAj9HQq5tzqL15HMcy XPbcWZiTbo72GyA6e25+pXqcJTdP3VzasepdBTKihO8Sp4PurD+Ay01YFu3Mq1ppTqCczCYIe9+X aLHtJGBZZJDu/ltRFFN9l4t5bYi/S7qaCq7xUv+hYa07G5JOdFzB89PLCKzE7qpswmFXYEZpjdxS LD8CA74vNz8AfhG0bmbIZLn75SsXuHbo8a5Ibnxf6PORdFxNIw/PpshbN0MMIAl+IdMNrGg8t7lM oa5fP2AiRxmCDn+nEVfwfyF7+AaVGBShnL0uS1kc/G6K4dxVFTGC3+Y7sVX6WnapPWeCBlmHULSJ zcOuoRjGlQKC5qJTMeK0WTmUwy89dXMdP2sLC0KyjR8p71gbVTycnQbjY13I2corRFvbLD9VKqGS xSqGYAacRmxZHhvEELR0LUC3oMIsw24idJIj/y4YP1XT9WSiaIDttQHK/R/vHkItrLS2zsznvNHS 6hAZdGDXKUegT4sZxBPOlbRy7KaGsQ56C9kwx7qITBlllDOchgkNy+3ua6O6fxVsD0y0C5L0Kdt/ B94zcHX5KTDqN3QrtanTpgpT0D3rstYAYgn3YrURx4uSIIpN20WnRL7XSoY4Eb9JTGVoTN0KJBse tG/u2LKUlPlP4iuQ7apFC56gjeJX5RjpyIFf1EMgqUIj8er+kzyEpCpOp3uKiK3ii+NjmC6V1QRf gnmiJDVsrZrSIowGWOsOCmvSdgIMSYr9hjzpyKPDSDqyCD/xn/RC/otRM/K0V/YE0BQEAwVzuTVh 0NwxgjFZIh/hbS50GTGunQyF9/YLDdpJSoSXnsOVRITLlLf3ZTRckZ0z/J6TP+c7UBC23CRI2mL2 okMREs/60OV6sc544VLPkoyihq/0OLx8OdadN+EpxNCpH5XM+iT7caRPKNXNfXXKto9uqhCGyC23 CEUs023f1ec9/56iAbJqRjoGJpIxiQC3oYdpQzaF59C1dFXPhBXEZF2bePy3M7t9d8yNJFRzDKQl 7Z5c+rWKC7UIe0XH+N8iTn+rcJuRzVFmghmLuJDArAhc5C0eWd3qFFte6kLJl6sD8sK4rYsfA5sd k8ApvBQzx2P4l4ySt8aup1EA5VeevZvSFJCshK/3O/lDzOCZk7cGms+i2e22j3DL17p+m96PRoXv yBhJ8Oo7FWbt5q0dJbnY7N/ue9l1nRjqGIGtyH21II6OSDVkTKmFtHjD5nH81NbzrR0nZMJ/wiPa SKAHqhZVB78UvHIUmd7n8AqZi8icUIU8XxWrE9jiPFu8+DjCwiy15kpeA1hYJfdIfZgzhycdAexW pfC1kd5iXmN66dvUsG6GCVehJ3vHbDgWMsfNz5Mog7b0op4/NTnQD9C3sBPlo0R/Yfct0kbyG6qB 1+IicjD6FaeL82C0Ea3GoC8twXxLb2hngp9Yi28UqWVUvnMM7lcrWK/2vcWpIizhV8+u4yZ05d6c hJEqguTCkT8NodntCAUS9UHuAKIOAd0tfB68zfgHQDFh0m/G/KD/fOeop4ygRq0Bw446BZXuCKzW p6rATpk1jpWhv+/mz1OZm0smwOOZVw5vmvo8I6zsyiXLxxcs2x60OvYyODet84BfzvfUTtCU+QC1 pjqaVfLOiW0MHaGOTRuMPFEXVPtYV2VmWlp9mFCIGs2/CfxR/lCFoql3MiWJbw2gyVa/KhV2fFXT SAIYqsZeUwAE5Hj+2qMF0MSLvkKjbjYMKbwEBIiaQob2RFbDHQGnA/e58oCK7VSOSIlxJdRY3rS7 Waa5ncyTDsYJ26S6pF2hBR7BEUTSv8uElCp3AtGJoLlqQMHuFNN9PnzioJVfgE2kuqFaaMGdOQ7K KfpYsH+CRyjKRBdSVfz224Pv8V7pYUMbZvlexsC5XVQGk1a1f0r9lJSXj8lBryXiWzYYSgj8yw4D 97J98hRRcjCIr2co6u14Oru6JbC57n1qqKbUnI4nzCJtGug/9f0tXbsS2OFOcOEIMtx+w/5YMK3r 1kWODPV9s5Jv5xpJ9f6hYuue+UxFsUD4Lmrkh0iY0U3q/qtnlHEHfnxx/o4U5NVVcZmiZMopcGh4 gTC/rqvT/n9Pcg+KiwOBSboGsgQO1IbQPWi7ATQh/2axmy+yphXghoWBzSkRsbl/5x93NIba+uRd SmGjWCfbdWjPkoUMvsnCMqCdmEkVjJ7s+heX5w36CeDr4fAyAEg3sL+7/GABVA/Ml+Xvjxz7kVmF wvLkn3IoxvXceJUCLdNedlFDDI0f0pt9lVAfBwWRR8+urRLFDi/1rj22zr0224esbfyTt3MQTxZz jCpjo1HU6dOYHxDqueIVp5mOMfOL3UaaIuckukeEnP8bLA49Mpp/QM80mzzNyRMGnWpupsJAEjAV Swu6e2LeS9uGAo1IQ021B9QzPF+4s0GSKYQqhzp/AN4XEDFitLoL0QvXqFaXSCYkj6pIWNrsx/98 /HuolTpoVt1xjgMEpkZOWWesXRIvRK+uQ8EgTrF8RXyktNMeKq+gv4Q5Uhi+qlcgnRRxDQBIGMhj hgAqvVCSwWEy4BxkPUvj8KOxsoiht63S6//8O3nwXL51hS3BbPyP+NlEM58Lp1q+WDJe/g0a0BcR SIguT2Z6nAblox5gV+H9aCKJabYLmw5mbCOMninRY7iHRqSaxJlmW8nBGBCtWTva+r8dezyYBwYM 3xavhOIdI9abXf3G4eYBx42mYb3GNGEOzKa6RpNA9T0tfwhgtlfhY2Kw3JAPMDy6WIc60l8kN8Zm L9id5zNccs/bk+EJa0BHdUrkbP/ucyjyCbJO8+mp7+aGxfXgtyyYKipxiN2UKnYk3KNHCOuUwGWP eWRP5KYgm7CyaBDAtSEhRvkHB/h8h7BGui8oAvudY3P7+ImQyC83HbpCp9i+zFxmOKDiPLGl06kQ 4hFjPDbi7bwJzUietoLfaZVvIgocUUcNoxzy8lxuEVbrF/gcc300eCWE0xFNvjBEENrkuav/+WE+ uXViLkCBclMLfLYtfKvg86fi5rjW5ulA0bpzw+JOFFn0g9ciNH7mMVonCR8T30/SRM8Lci1h8qJW 7u/AJ2X3qqlStv2IMOxIFhi7FmjMW1C/8rgnod2MxfWOdvzpqSNT8qLC84+ub6+bSt6Cf9bBnOn/ Lp5bnkhB3afY3aZt73/3uIT3m8oNwIowFwtwrHgtXgmDE6d6bvUCE4cYFWZPtLU/n0yIqOjoBc8Y 0yzuPu+mlj/dY5vOL42PEpgpL2BPRFyylLETmdEMuzQrc6ETTRUsnMGvCfwX38lklZhsUIoI5N6i mImBPZeGHfjYV14B/jZ4+H5R3V6sinxEK1V8ERE2B73K9HfAltUiVYqKRNymeCxSXp1jwtyYHA0U RVhWBjQuZdF1/ZukgOnIlHfB0NS742WvYugs6kHlNxna+z4K17GInQtew0gxlSmLQW+J2F21AhPL im5ZGMyeS9JMV1xS/RkuiSM0iKhX3FKc/WSl87O7yFUInGlJR2h6SvD+QFz1L5B18XnkXfaxmkA3 9s05KLHX4naR3kfyw137yFma5tqPp5mVtX05AJYqGL88doLvy8KwlTP1IYjNt7NRkAf0XVmxH18H y5IkYg9u+bMmRam1yrcOLakN0evUvfG1yjHc+BCfwSCjU/6XysQdamPD08CrAT5j77YBzBRxZRZ+ NQzutt2y6tdy9c7b22lHtNzcJ6j0Ei5fdUns17/0REX7RYdG7ye8rckTHn45T2BS8jDUuqbvHG4E grprYJ/F546FP4Jxm3w7nbAJutF8m7XN/XX85ZqUGwBGKk+uzQ2/6bw0s/imGLEXuvS7p+3tdXWq fwBgNqMoJvUiA1bRtdnY43SE3sFcSxCuc0qLkdE3tq0hv3M+8nzz74Favj0VaIqJP2ld8rujGTIA VtcUca/bAKYMZIqi72DpfDmxtDtlyg78do3YXwQywQ1deQHR5lhBWhvu2oL48trHRn99UqKrtaWC Wi9Frf5PRKzxC3fWIgdnQVCz9sWAiztJcIXoT3iWeiRnChXxsZLshjv1SEaKGkZrnRKQmNVeIMkW JcKN2tip1EovLArzrHRnpjeqV6Jggqr7oPPyeCy+L/rmrY0th4looY/9f5rGNRbNm/5QyM2pblPW SA93BG7d1our9YZfro/0zrZqPBMJuvE9BD1VB4B9f4+HD7jgbZblPSqYScGJLIL0SnQUglwr+rT6 UfGmXj3GKasjyOMfgbAp3kECovHxCNCUKB5rpuOLHOe8KFat9SLLoSNbEd8d0nx1ic8xsNm9YZsu Dggzhhuc0WR0JewZBXHcUMwSD79SmsbecvUHQeGJf4XMdSi0xkvGejHywgaql5XvWserwcFhoEev QLkkU95Jh150Yc1ktsEy/d0P7fgvMFkAbSizPjyLMQEk6Pj6/AALUXeR35DGRJLB6qD9MxQduN99 JSNizCdpxWQ74nng1MoD7zvu4UhRoO1C6BTLIYuKkWjDaO5vxvkhTe05vgwNu9lWcDuEqO1nGv1b tjmJ4PVC9Ew1L7fvgzpykaT6Y6rxJH2V/RbT3mYam0OpRoxrvV8GAifXq80Q2eMvswv2SKjolYIJ O4IkUe5Z70uFa3v0hJPF8pIyu7QGLTwylHNpGAcFo5yxiS4kjd/XmDEWOA1oW3scOlEmvyYazStm oH/bfoIDB+lAvPbJ6TGake8gKKKnC8rPh4sKUwkUBa82AN+BlMKtvdiyUNLQKvaJdApn3+DkGnId Ft5Egc0zGFbk1ANn9it6ssjnqjS6iFwhf3BYm1YtM8cTVAZyiq405tG2Lf8e52VZDTWF95pzuDS/ Ebtw3ftE9j/c+QVnkOQ9MqELzQzCfgn/iHBnoWwyhczOAisaGogPKTpUsQwtGI8HPY/elVBFyS61 AIonliieEZSx5kXruNn+OKmyTf6fQ+1kYjra8Jbb+4UKx2+gDA78zRWaYpFYp3eSA7VqB+IgGApE SSWBNpwsLyflqvypnB61LmiA33dQm192VDAgsRgP5sfP15K98oLOxJ7hHY8rnAphqrBcjugh8Vj2 eUh0YB4sZjIX10Xdb6rHmJssrdtVKM3lNFA26QzwZn8vk1LyebtAZnU3Fyy1x2R2NKjhaP5Upnti 0/tCBfj1xPfdx8FLT6JqBiwQxCFj9O2gIWDBAvi/6t4oEvlgMIe4r71jjBwRJYdSMsOSXDjYX7uS wZsxZ4xBW/kbibP+JJsQ0S3ycPMs8dYyqYF1J9xhV1pBkmfrA8bAcrad5PYCQv8Y5GfzGmfK5Jim 0UJGVeYM0Xb0nus+yqN8k/WYGqnRLApX5HSWj0IQt3w1Xfo32S42+D7+JeFw2uo9lEWengmvgocW +nWXMRdY7Zz6KCxxFo2Fn7nNNgYRBgCxSzGj7XUDed5Rkvh754TffQ6WfrcBRO1SLk469Zrwx0TE hVlp7lUoneYFrqlOVRwNNuYogaLm3f7K/S7/SiFYphjlHGyBpYqfZcOZIigI0Cpc1rZT6YfWydkN PH3TMginiQ4gSGjEDOnv7JxF1+FcnPpNEgatq1uTR2gnlOKtayNgXmvVEjyxLHBChADSAj8V0qEx EDX1oyXtWmkiL8783nb9xobnPsh3iqAr6mXpvX4iaqrmdONYX5zdOhpNSj8Wp+GAYNUjs+qVsGKP c13p0g973Ckcvgcs60SO40c/V2BxnEmrWFQhlUq19UhEpdSPjFLRt8RxE3oUMS1l3JenJ/s0RVjN 7+ketjfrFyjsp0grb3z1lNxp5cdk12yZwkBWdyuYyvXs8V4CmphfPvpP7cIpsgmSgXsvSyDmQhBe +RjWollPK93q7VIQSF9A60DOLTUym4pUkJUPAxfBpDtcc/qIkxDAQ+PbHxL5MpNIgpZGXzkrekJn tPAwpkUDhYbNRBjSUwAsFmOgViRZpTedVETMwcmP1QR3myojRwle6iAVdo9CSGrQefLfTnph2vDH B5YXf9tfBNbcdn6Pz5X417PV1Tu6DL8d7vRalzHhGt/LBGeZqMxvkxAb1x8CWrMfExqVcNWUuBAl gEIl8wuEoeDfgubE+5myWRuJHhz9JY7aJQNDSBiI7tV28eVu/3vCOY79a9qnO5njrpw4hNmp2FTh TTHnWdWq0vK4Z52JKjQI5vvr+Zelrz7eYveBsIHa9/VmqMD/c5TU18JQBhofcUwXHWQkqyHmhqhK 93I5m5SkH5Cl89OIUQY9+z3TOX6FRLYq3JSrCeyt4DGTMiJBmxaZrVB6Pk0rGKWuEqcWnwD9rlWT c5nndCS1lSVQ/92scdRnOpSFQF2zB1KbV6KpzCuaWLQOmLiKdJjpemg2lFTBnPlrGBpYqFJtEi6S wI2kVPDgyH9p0JRebx0EIPOt9l2l++lTSvR0DRLLOpUDjtrvJybAayy8qNL99Dr/Sfbr/RW6z0TM WbJsjS5F+zHoOoiu/6QjhurfFMboGInvj8uzv+7b4GQCL1saZHDu+QAUEt2CwrDcJLHQ3VawvZU9 UqTFVRp7Aw5pDxAfYcUanOcRFdIhAwKZVEe8mGcxicbS4GGB9LIcEUCp3cBtImeLpx7lDP0FAeAA CoEH484bg/Je3PJNfbhDm6qCJtvbt0JbvQwpcRk+kji4NDfaWZ7q4dMXofVUPPn0c0mQz5lp8lNA BCAgCIdCnass0IkBi4jPx+vDTBKbAN24mDRtN3Zdm0+IKiUK17fhFYIzbeOj9gsIgvJ8bFVvKEQw CCiFaHNi7nMDQ+nMVXJ9V2ZEqhCE/9lo+hcpis2Vv2zswQKEYUgZlX7eli9xrpqEiS8VgxMmpTRL jAglU/AUaBJdjAstfMwiz7TknDhTZihOx8p9kAnCaAjeJ3SbCz08aQzOcq7vx4U6vujKRlxCmoyD pimCVDs9QVR/dGCc3wQjhWuPxaTG2V91aXgo5WwJZJ2/1Riv1kXM0u5ZxesQmgOfX4Nh8/iZR9TE pp0NX9VZ3schMLdIHEHNGtDna3AnZB7R5l0hhAUUoFSXOUaf1Rw6dNzZZiWdXmfH9YcI1c9hWzYL /L28SzixwFg/R48bwTUn92wNOT4YiWXWHasSNTYFNcVlyHsfmBaFntDSgb8ZX2F45+Ed6PmpWHdq /S6OaZVLGMg378ag3cPbiuMWm//BQ4TNBJaVWlo7cD5BYR2muB+8gtAhyaL9wqHKGfbQycyJeW7F 65ZrycFaSG9XzQ1njbDwRdjW67OMS6M5JIfJ/hD6jB5tq0Z+OV5nqNaAg+sYd7jPxxmJFjyjMRRB xO6NdInk/Uw6/3aQezK8J7byYSLh98HT+uVaYdBwJXO1jUObFE3+WDalHYfIB8+H7ZdIME0J/5+G /1vYeHDFFBX282GxH2/AZZ3vqRFseBGs77y18coIBE4+jDwNV5Lh3uBt2sjir27mZ822f+iGvCmg Xp9DOKaO1Wopqk8YB5IJghJRYgy2XL30gu6eVuQNqG2Q2JmmqU5nH+b/5YS+2GOWtEQWfNHNyaX0 qTmwQvFNUzatnNpqgTEqkvlbwARd7GRNpnxp88+ptAroOkImu/Az3/zRkKWKK25PFiR4BGfD97sy k54uj4rxzxY2Ql2AM8bcRxbbg9iBeYKcqt3AvRYMxrgbxQHnjjTLiIXcAMnoC0l5TuLy1NBcRVU2 obEN9pVQAU8KnH1rD1wDpWBURZVK4njOB0L/jzrrUwMbqswf7Xh+3jfZiVw+LMIxWytPf0A4ZjhA WeYDKxUPYNTKWyWZ22g3aB2YV/G/bX0Hj2FeM8Gm8NW/QaIBE7psOVMBGZH9zbaKug/9SRvB3Pn1 g7nt21BKdHEhK0YMmQR9VLrYiZU9ZX2ZYxDpIEOmkSHc02VbN3bO01/lU0tA2ccwjAX7TrZlUO07 2ONHCoS2zb1sr0y72kgZuexznyXeTmiatSH4fydfvYcjJk39deHiL75x12A3vLSZxXS7QpKI1YPZ ldYnGNr0p1Axc05VRDlKaUtv5VQZep/Q5AoVwurP+0vtpvNDHLCcxWuM5CRGGhxrftEt6w+q2cOS ZaoucDFcbDQ1ZXsaFOkTXNhC7BoJqKywKHCJMbGiqmYTq62iQeZBCypBX6OWgTBYNdrM8o9HdeWk UbarKOwMW/IUCVg0PbQlKNHiURMSeL9LGf9kKQ/chAynKjVZrIN30dgLIorffz4cYqJ0H2q9c64z pL4u7WiMUZKfA5zN3YSrqSFWrXS+NWwvmP3oPoMZM6nWSiTAMOAgaZWJuaGaoGCFg3gkJkXOc4Z8 A3zjNn07BgwEh+kbiRrNk3x/4hha/HSz9s7zRw6mYFKOXXYpOc5riTREl1NqSP6RjsAQEo9e6lZd GM/tGre8K7xXizeBKC/8vTbdlZgeVgwMqTOApY/TmkIS1bfrQIGWQjgZ8jgEamSC2ykB6iEHkU+h PgytTKuw9PbmlzZrEe1KgHdvyXzfWm6XAiM38EF6HE033O0DGeeWfvdOEDwrdke58nWclj34cbnT C2ms5cGD0KN8CElQZylTjxnIzx0CYB6ZWR+30UsICDkzBIYVmnFk8FmM9+53g1GUywL4qW4le54N F3e/7F4Swz6h6FlKKmLxCb0cIsf3qiOaOJe7hBYitgX6kHVEt7VJ62YeByMDKCstvpom0XHsVBMj NkeHyCI/FZfg1kzDTBtVZ8OJecUF3GLcmxZ9bYBLHyx7XympUjhQoc3Y6QrMBqZILJkINTsBvspb PPaAXDULtWW+9yagaQUMFclvThJHraNn6xhev/hU7WaACR5ZLaPn+kkgHhdVqvPNUYRw6dd3mTDe SRCTMmMRXCQMCv2oNjjeK1EOKiyP0fQ3c31aJ2TArtY68U+GZM/waWT1ZhahVD73q6oHd2oJF4Rt FERSAVg6ahE9Hy2mmnPH8CI3C1iKb5Wyv1lyZ9Y8oA2AlShMAoIcZkcupXdcH9Lmj89TTPwDVzYK +1nxPSJjvc0G1/tWt10XDWQlmUWIEewvTDE2e4ZXjVQKILV8ir4YHw6T6Yba59ghbB0r/nICWZNg 47tozVMexCxoHPD9a7uJNYXbEeKa+4QJ45SKCm4Nv9GjaXH5ld1VQ0tbYPCFaRc1XpnWZNP8wTsy X7PICOG+yEYJzWp9h4V5knOT+Btz2MmT6EXoVVZKERJNJFAHC0wBEHN6tXJ0l6AVBpuNxmHrk2YV 5/GFu61y7i5OTiOVwqas1tsU85NYfyCy8xXmDiuWHXS6VfOzcm/GgDfMaDdOSktKv2lEm37WNpSh AuzH2gfSerboDJef0cZNLKk44Qx5cRH7PDPuA3Cpi0Qf8fhZ82VETd0dLRoHQaV6UpVc0n8XFBKw FZmjM04YHgnngj8Dj4ZDfq0qe7QFFSK+jWwKmkD1eKHMSJ22w6ru93KnmG6DAPLKpWCAqPJq2Mx2 2RaerjoS929P+iG5sM0Q6dEhKf2q/x3oNO2K5vz/FhkndPnItuxDd2/eifHHyvP9s5hGYr3pFtsR rLNHnFudtSn6PPh3sC81eULNuCPUMgDj6VOMdeER6WUVMeHHTRv69Cb3YvJ/h2sG0PuMj8rXPgp1 oIBUlq9THI9VoO1N5A3ArS0t2oPbM7DoNU7fznkNfTLR5mL1wZ2EsHsEkyAjX42+uOZVv2iuZcTO ZEcz0xl2p+6Gtv9Ck6RZ0LxGVBEAE8DI/uC28Tk3h5IwS/iOkQD+GzJBHMr8ZVWBeh76aptSH77x 2/g8TdBi7D4zjgQA7RP6DMkRDC7zxot51HaT6do/nYwDAMwB0iV921j0hUfaCnjr4yjQYY0nkftn OMneQ6zr4wUC7Cd0zfYuVDo/kzc/QZZVjgOwqjkG+B3ePTY8XSyYItUosiaCOpuMPbIwYwVU8ri0 Eu2hAjAqGBTQrcxXVss7A7txmvxd7SE5NJTJ+lm9TvhJIbF3h00363JuHhK16GktYJdGq3VJBVJM TrN+eByNB04ze08wVQrAcwr0z1PpnN0Y+5bTbyL4LcraBoOFo7MOdP6TqdLi/0eDWQnTzARVAc9/ LUnx/bb8dDrCmsy1SGu9i/2jg+7FAhAd0rgOKUS1psuUHiQruKCUBx/DPxHcR/M+RXOe9UkzFvGO OS0TTeDR840e7t3XvcbQdHT1SORgVWNJu6xL68p1RT55Ws8sCOMVuoCx9tPKpZCZCeh/LndXfvtC aB0beZ8hOOFRUlPMb26ApF95iFGFvtIHi+zdu4aXTNOuSsBL8BZzxPlbRzo1dotB4weVzXWLyxTV tF+alC868jycLJgFMNIEQiYOv4v5hYh88yD9VT2lUcag2o/0TcJPz1wjTytOQEIvHkikhoHyAi5N otMP8ZlYtgg9FliJPEV1VmJ2GhGBc1SipRe6o+q9I/1oexYAwB7WTj3HQLtMDlhHc+GP+0kNfLUW LYB5xQSCPDdHiwpEG1ErroGXfb05mQyrwJn6B4wcUjPXRDj5AilvZSsx8aFMFN4rlB31C9t7KCeR ZfFf3HdA+NMdS4PMxDrbNqmUjxaKfUe+bne0gUcjpmAMZ7+iEH9SK9oDIfw2G4PMkCyfEnPuy14X Wu351hLT5erN7Nx+YysYbYsW8EiTcHOE81abiONixbdBVCB8mWuVfK9MrPx2EsB1nomqOCq8koqm MnhVKlsqfZqljTeVulnYsRgHeMC7KxwcEt62jMgEy80/F/VEchcJ7O2QwTih330QLomdDyji3JHV gIpyhwjY0Vf/BR/h5iIWfU+ZP2BMY5J9hPTcwaJKubTun7xnoZw06krk6AtgaTM1itRopp1+FQM0 Z+w71oT2Ie79pLMif/G1/mQXoFfThGUbSs0vmyDEnIdB4VdEogqvCYPUnvMAYaxPaoxRPZh/Hh2e lDwEM9ILBFv+gEhbmmOlVkQ3STBUedWw5bsXr3Qx/Ip8RSydEhKljW86oBxgFcm32CO1zZs3AAp5 g8iAznr+Fh2fWQw6oo5VjPZw4XbSiKRr8zL4moBVImIjc7/5zph3qPhkgxvKZ2NQ5yF0h0Dk2tHN 4REoKxM6FsYAH6Iz9HSUFPVg7LDzmsTbubGiU6vto2LzUi8nFEWHKeysV1WUsrtJ1RDFBXCXUrbz igD02bQBMF7phZr6JM2EFb7I/bYs7T47VXAzHpgIJw9BN2i37DAzxNDEz4b8Xt56o8HTZUYwYHXL RjLSk6rnDGcw18cLPH1Ffz4uTroW1aTRgPE86KrfQjTTwuN1YHfnGtZrnGMjSUIKXeB9JgBUjL8C Cd5xKrMQotPJWHMac0x6R4nAJCB+jx3bk7Sm/hrPfRHNFyo5jjxPNQZ1jthim6uTjMCDwnmA1WuJ upLfvwGwXXDKihuRwzUSXE1ksyrYq+du/SZDQ8STl6Oxbl4wZjDBR0dgzNSg6v0mM/RE+ji+mt+C Jdw6IBG7ywAW4sXJSan/pATgwJaN98zXe4u5RgkrRRUPjq5VYMEscVkYO5C3dkLGM9ffgKVZJC+j PXF/HTsrBhxxjMBOEtbFPpwvOMLgw1FSdMMFdkwrFDTkYdQ5kJvWtZWVthpLssrT0icBHSbgxr4r pb3wX6G+lo6Ij0EvyRGTGF5pIZy9ruuHEJg0HclspDOZdd6n1X3AxGPBoipOkr6zaAWJXEaMZmre 6yrWEWHdFuQoCKJufq2sIFqjm0FxkGPlkZHpDeF+hQhxdvoNgBkfWU2ae2pEpUwn2RFeEhM4xz/R SLDx95FQkNqMhVjv16O+N+fDqIubfIyHuNU5OL0slCEowVJ/G+GXAgf9FaFAeinfJRMl+jTYq5pu WtROMUgHvdTzE1RGh/r26Mvfi0v/rRRdrV8TIP+AY+lV+AmgMSLq0kBbhwOWcu+miEx/gT4kSu97 gS3vv/7ZLZAK3kmLSinw795kQopVGIqu6SU/fImm616JCZKu7GIfsV7MnwFnrCRbfBWPdT8gvmTj znoYA+HOgQfzcqOuN+XUN64/L4eVqr9eBCCIfedLC0mESYduJ5n2B8m9L+6QRarnz18ptBeADAg8 xmVVaQc0ntLGiAPiBRX7Lnu1q6tco9SqYzBV54TBuD+Hx6A+LCFouhsCeE92U/egRXVeTX4q3pzC IqT1cWnh9zGS5iMHxqO8YBtEXWzcn6yLqKmW+8MABWcxbM6cV7T33D+tMs+MoILPrC2HitJoYjYr E9QBcttZ7lxCpAEgIwv44zSqAR2BSteUXKUu0V+yofNlXx6iiBIhQfItCyKElBsBiNY5QyRztujh 5aPNJtFCnyHvHDXgELy4n4BN+8rm4JLPv2pHb3FUtXt+5Uyde+ecs8OshA8GkcPyCTOTi7zPkhYE Y+KHYx3w0HvTH4f3isDsfTY5hZcCBGb/rbx8kdo+LmAUJb82qtVR3EpQ+5SsKbi3/jjM7NaIRTKG r197wFS+lpEi6ReTYm6ibqQvt1jDgRrMyZGbH8YnZhnUFgAyI8OC1ym8LhaBXyIixEZk+wPvjSJF 2rNOmlixj6Hpap2x8VMea4K7bYUUyBWJMwGh+f3JIEnOLwIhWnaTLSuf7nj1+vlWGeVcGKeLfHvm p8zr/V5IO03Wu7JYIKU1f/DXfPoAXSonqn2kkvyjQWuAWjsxpgPQ7x2+LNeDHufhEkm686XuEZg0 TlaM8rLVo5IsfE8K8K/YRkXxdaMsHHCkN54Db3TEqEWjzPdP6ynNOrgOWiPXUVvIGi4hfDtD7PYQ HWwkhcZX67jvHtfPJutTMu/btP0MSqJVHMylsO37OhpgRs8dXplT7hMp6BH3buF9ZyM9bK3WYUY6 spR5qzHeqK33eu30Zww8SgwYj63hKByC/+pRVSYX6syECmDEWyOqcnhL+1epjmaD2DWFz50JotLj pgUYj0ZxhVx3M+F92btwi965A+IIsOPK7ZGE0nLBuHTq23ah39DDe+GUA3wYDasnFWKYBtMiVvfH znM8he9++pBNGcqzrIK0agf47oshriUCyzn9KBjh07FY1kKqSTUtk5jIz82gNu1w1RBdPanKhkef 4Te6Uj3jaz7FMxaAbPrZtElnqbl1DABmXYKWr7qkIdwg3xVetc9cMlgkMJWUSWdcH54XNHLbTem4 +i1f6DxfO82YxJH2pxuIA1lf4kuA8707h8/pGBYQBoLk2pO+dwrgblPG7CPU6BrbnTvLuh2kf2z6 aTg6rq9viyeKs9hBQrRRde3GtjoJzdBcDbZd6KZn/NQV8LEFuAWRoFKXTxsF5OS3lWhtcqgkEJjs wWEmHQPR4mgYTj59ms722LO9MNamaYOIaVVVHbvX764BTekDt5m9t1QX0qeZGF34MPFzWtkoyALA ajeSqFdVwbFgzpxBJHMN2Va2iTSeluoZmJC9KYckKtQFet7eCCavyFgE0mWLhpdK6qefZGMQ5bZw nhnwk5SUFDieoqBXHySKlqLlitjE46KTDQqcdZ92Kxg5xw0uCdVIvV9JqBS8wifON69+2QmloHWJ fHRbaMKhuXM4x9izpVdjU53272olrdo8OHdglkRiP50ZmXCtK2f2ld8AxSKZfjZssJGWsVKy3yZJ GoKKKwvrLYDz0690LGx0JjvGsIY91rAzlPi/vBPQLKQikcezE0DOPb2XpSdGELTZ99HBaShsEEQa qURABkXu+2i1mf5D/uy8gPdYpjjQNDZOxGfAqR3XWHnGxbjtsDLvW3jz+6IWYt2etazqeF2SE8Zo qfzJV2vdWbt9/MIQ+7molgbwglXyRR8U4xbzqvwFIex43sVUzhFWtUvGzyd8hb5QkJSoYLCR74LY IUyEIlK1j4gywh2uwK7XwsCmxLFw0kpq/k8IoQvL55wfdCxocuwp57XobtxWlBJm7WK0kazvBFdY YG621ZeUwe8Z+2xjcm0sxA2OVtPjptuLKyINPGLz9g+8VOI7EZ+q04Kod/PT0y8v2+Daj2El+K8w LgsO4dKvRmU6CsyRB2Yv2sHyxMmSSsKiO8KE6ktH+Tkfz4WHTIHhG+PP2U/xcR/NIFM+hKxIiuoE +ptT+GS52cNp76fMoXKt4CNERfEzEyFqSIApXcHfDnFUkWFdf03xCRi35RHPphBO7NSn+9Vq1Knd 3qn6k+6KVLTR6AFRPISKz98ncgMuz8ONiKQ2OqhDKFT9oOrY93UuC6/igADj `protect end_protected
-------------------------------------------------------------------------------- -- PROJECT: PIPE MANIA - GAME FOR FPGA -------------------------------------------------------------------------------- -- NAME: PS2_RX -- AUTHORS: Jakub Cabal <[email protected]> -- LICENSE: The MIT License, please read LICENSE file -- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity PS2_RX is Port ( CLK : in std_logic; -- Vychozi hodinovy signal RST : in std_logic; -- Vychozi reset PS2C : in std_logic; -- Hodinovy signal z PS2 portu PS2D : in std_logic; -- Seriova vstupni data z PS2 portu PS2RX_DATA : out std_logic_vector(7 downto 0); -- Vystupni data PS2RX_VALID : out std_logic -- Data jsou pripravena na vycteni ); end PS2_RX; architecture FULL of PS2_RX is signal ps2_valid : std_logic; signal parity_valid : std_logic; signal parity_ctrl : std_logic; signal parity_ps2 : std_logic; signal ps2_bit_count : unsigned(3 downto 0); signal sig_ps2rx_data : std_logic_vector(7 downto 0); signal sig_ps2rx_data2 : std_logic_vector(7 downto 0); type state is (idle, dps, load); signal present_st : state; signal next_st : state; begin ---------------------------------------------------------------------------- -- FALLING EDGE DETECTOR OF PS/2 CLOCK ---------------------------------------------------------------------------- falling_edge_detector_i : entity work.FALLING_EDGE_DETECTOR port map( CLK => CLK, VSTUP => PS2C, VYSTUP => ps2_valid -- Pri sestupne hrane jsou validni data ); ---------------------------------------------------------------------------- -- PS2 RX FSM ---------------------------------------------------------------------------- fsm_reg : process (CLK, RST) begin if (RST = '1') then present_st <= idle; elsif (rising_edge(CLK)) then present_st <= next_st; end if; end process; -- Rozhodovaci cast stavoveho automatu process (present_st, PS2D, ps2_valid, ps2_bit_count) begin case present_st is when idle => if (ps2_valid = '1' AND PS2D = '0') then next_st <= dps; else next_st <= idle; end if; when dps => if (to_integer(ps2_bit_count) = 11) then next_st <= load; else next_st <= dps; end if; when load => next_st <= idle; end case; end process; -- Vystupni cast stavoveho automatu process (present_st, parity_valid) begin case present_st is when idle => PS2RX_VALID <= '0'; when dps => PS2RX_VALID <= '0'; when load => PS2RX_VALID <= parity_valid; end case; end process; ---------------------------------------------------------------------------- -- BIT COUNTER ---------------------------------------------------------------------------- bit_cnt_p : process (CLK, RST) begin if (RST = '1') then ps2_bit_count <= (others => '0'); elsif (rising_edge(CLK)) then if (to_integer(ps2_bit_count) = 11) then ps2_bit_count <= (others => '0'); elsif (ps2_valid = '1') then ps2_bit_count <= ps2_bit_count + 1; end if; end if; end process; ---------------------------------------------------------------------------- -- PS/2 DATA ---------------------------------------------------------------------------- process (CLK) begin if (rising_edge(CLK)) then if (ps2_valid = '1') then if (to_integer(ps2_bit_count) > 0 AND to_integer(ps2_bit_count) < 9) then sig_ps2rx_data(7 downto 0) <= PS2D & sig_ps2rx_data(7 downto 1); end if; end if; end if; end process; process (CLK) begin if (rising_edge(CLK)) then if (ps2_valid = '1') then if (to_integer(ps2_bit_count) = 9) then parity_ps2 <= PS2D; end if; end if; end if; end process; -- Propagace PS2 dat na vystup process (CLK) begin if (rising_edge(CLK)) then if (to_integer(ps2_bit_count) = 10) then sig_ps2rx_data2 <= sig_ps2rx_data; end if; end if; end process; PS2RX_DATA <= sig_ps2rx_data2; ---------------------------------------------------------------------------- -- DATA PARITY CHECK ---------------------------------------------------------------------------- parity_ctrl <= sig_ps2rx_data2(7) xor sig_ps2rx_data2(6) xor sig_ps2rx_data2(5) xor sig_ps2rx_data2(4) xor sig_ps2rx_data2(3) xor sig_ps2rx_data2(2) xor sig_ps2rx_data2(1) xor sig_ps2rx_data2(0) xor '1'; -- Kontrola parity process (CLK, RST) begin if (RST = '1') then parity_valid <= '0'; elsif (rising_edge(CLK)) then if (parity_ctrl = parity_ps2) then parity_valid <= '1'; else parity_valid <= '0'; end if; end if; end process; end FULL;
entity foo is end; architecture bar of foo is constant xA : std.standard.BOOLEAN; constant xB : BOOLEAN := FALSE; constant xC : BOOLEAN := TRUE; constant yA : std.standard.BOOLEAN_VECTOR; constant yB : BOOLEAN_VECTOR(0 to 1) := (FALSE, TRUE); begin end;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2237.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02237ent IS END c07s02b06x00p01n01i02237ent; ARCHITECTURE c07s02b06x00p01n01i02237arch OF c07s02b06x00p01n01i02237ent IS BEGIN TESTING: PROCESS -- array types. type MEMORY is array(INTEGER range <>) of BIT; variable MEMORYV : MEMORY( 0 to 31 ); variable k : integer; BEGIN k := MEMORYV mod MEMORYV; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02237 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02237arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2237.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02237ent IS END c07s02b06x00p01n01i02237ent; ARCHITECTURE c07s02b06x00p01n01i02237arch OF c07s02b06x00p01n01i02237ent IS BEGIN TESTING: PROCESS -- array types. type MEMORY is array(INTEGER range <>) of BIT; variable MEMORYV : MEMORY( 0 to 31 ); variable k : integer; BEGIN k := MEMORYV mod MEMORYV; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02237 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02237arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2237.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02237ent IS END c07s02b06x00p01n01i02237ent; ARCHITECTURE c07s02b06x00p01n01i02237arch OF c07s02b06x00p01n01i02237ent IS BEGIN TESTING: PROCESS -- array types. type MEMORY is array(INTEGER range <>) of BIT; variable MEMORYV : MEMORY( 0 to 31 ); variable k : integer; BEGIN k := MEMORYV mod MEMORYV; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02237 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02237arch;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -- Complete implementation of Patterson and Hennessy single cycle MIPS processor -- Copyright (C) 2015 Darci Luiz Tomasi Junior -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, version 3. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- Engineer: Darci Luiz Tomasi Junior -- E-mail: [email protected] -- Date : 01/07/2015 - 22:08 -- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY MAIN_PROCESSOR IS PORT( CLK : IN STD_LOGIC; RESET : IN STD_LOGIC ); END MAIN_PROCESSOR; ARCHITECTURE ARC_MAIN_PROCESSOR OF MAIN_PROCESSOR IS COMPONENT ADD_PC IS PORT( IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT ADD IS PORT( IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT AND_1 IS PORT( Branch : IN STD_LOGIC; IN_A : IN STD_LOGIC; OUT_A : OUT STD_LOGIC ); END COMPONENT; COMPONENT CONCAT IS PORT( IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT CTRL IS PORT( OPCode : IN STD_LOGIC_VECTOR(5 DOWNTO 0); RegDst : OUT STD_LOGIC; Jump : OUT STD_LOGIC; Branch : OUT STD_LOGIC; MemRead : OUT STD_LOGIC; MemtoReg : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); ALUOp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); MemWrite : OUT STD_LOGIC; ALUSrc : OUT STD_LOGIC; RegWrite : OUT STD_LOGIC ); END COMPONENT; COMPONENT EXTEND_SIGNAL IS PORT( IN_A : IN STD_LOGIC_VECTOR (15 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); END COMPONENT; COMPONENT INST IS PORT( IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT MEM IS PORT( CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; MemWrite : IN STD_LOGIC; MemRead : IN STD_LOGIC; IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT MX_1 IS PORT( RegDst : IN STD_LOGIC; IN_A : IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN_B : IN STD_LOGIC_VECTOR(4 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ); END COMPONENT; COMPONENT MX_2 IS PORT( AluSrc : IN STD_LOGIC; IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT MX_3 IS PORT( IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN_C : IN STD_LOGIC; OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT MX_4 IS PORT( Jump : IN STD_LOGIC; IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT MX_5 IS PORT( MemtoReg : IN STD_LOGIC_VECTOR(1 DOWNTO 0); IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN_C : IN STD_LOGIC_VECTOR(31 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT PC IS PORT( CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT REG IS PORT( CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; RegWrite : IN STD_LOGIC; IN_A : IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN_B : IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN_C : IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN_D : IN STD_LOGIC_VECTOR(31 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUT_B : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT SL_1 IS PORT( IN_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); END COMPONENT; COMPONENT SL_2 IS PORT( IN_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); END COMPONENT; COMPONENT SL_16 IS PORT( IN_A : IN STD_LOGIC_VECTOR (31 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); END COMPONENT; COMPONENT ULA_CTRL IS PORT ( ALUOp : IN STD_LOGIC_VECTOR (1 DOWNTO 0); IN_A : IN STD_LOGIC_VECTOR (5 DOWNTO 0); OUT_A : OUT STD_LOGIC_VECTOR (2 DOWNTO 0) ); END COMPONENT; COMPONENT ULA IS PORT( IN_A : IN STD_LOGIC_VECTOR (31 downto 0); --RS IN_B : IN STD_LOGIC_VECTOR (31 downto 0); --RT IN_C : IN STD_LOGIC_VECTOR (2 downto 0); OUT_A : OUT STD_LOGIC_VECTOR (31 downto 0); ZERO : OUT STD_LOGIC ); END COMPONENT; --ADD_PC SIGNAL S_ADD_PC_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0); --ADD SIGNAL S_ADD_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0); --AND_1 SIGNAL S_AND_1_OUT_A : STD_LOGIC; --CONCAT SIGNAL S_CONCAT_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0); --CTRL SIGNAL S_CTRL_RegDst : STD_LOGIC; SIGNAL S_CTRL_Jump : STD_LOGIC; SIGNAL S_CTRL_Branch : STD_LOGIC; SIGNAL S_CTRL_MemRead : STD_LOGIC; SIGNAL S_CTRL_MemtoReg : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL S_CTRL_ALUOp : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL S_CTRL_MemWrite : STD_LOGIC; SIGNAL S_CTRL_ALUSrc : STD_LOGIC; SIGNAL S_CTRL_RegWrite : STD_LOGIC; --INST SIGNAL S_INST_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0); --EXTEND_SIGNAL SIGNAL S_EXTEND_SIGNAL_OUT_A :STD_LOGIC_VECTOR (31 DOWNTO 0); --MEM SIGNAL S_MEM_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0); --MX_1 SIGNAL S_MX_1_OUT_A : STD_LOGIC_VECTOR(4 DOWNTO 0); --MX_2 SIGNAL S_MX_2_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0); --MX_3 SIGNAL S_MX_3_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0); --MX_4 SIGNAL S_MX_4_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0); --MX_5 SIGNAL S_MX_5_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0); --PC SIGNAL S_PC_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0); --REG SIGNAL S_REG_OUT_A : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL S_REG_OUT_B : STD_LOGIC_VECTOR(31 DOWNTO 0); --SL_1 SIGNAL S_SL_1_OUT_A : STD_LOGIC_VECTOR (31 DOWNTO 0); --SL_2 SIGNAL S_SL_2_OUT_A : STD_LOGIC_VECTOR (31 DOWNTO 0); --SL_16 SIGNAL S_SL_16_OUT_A : STD_LOGIC_VECTOR (31 DOWNTO 0); --ULA_CTRL SIGNAL S_ULA_CTRL_OUT_A : STD_LOGIC_VECTOR (2 DOWNTO 0); --ULA SIGNAL S_ULA_OUT_A : STD_LOGIC_VECTOR (31 downto 0); SIGNAL S_ULA_ZERO : STD_LOGIC; --DEMAIS SINAIS SIGNAL S_GERAL_OPCode : STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL S_GERAL_RS : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL S_GERAL_RT : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL S_GERAL_RD : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL S_GERAL_I_TYPE : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL S_GERAL_FUNCT : STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL S_GERAL_JUMP : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL S_GERAL_PC_4 : STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN S_GERAL_OPCode <= S_INST_OUT_A(31 DOWNTO 26); S_GERAL_RS <= S_INST_OUT_A(25 DOWNTO 21); S_GERAL_RT <= S_INST_OUT_A(20 DOWNTO 16); S_GERAL_RD <= S_INST_OUT_A(15 DOWNTO 11); S_GERAL_I_TYPE <= S_INST_OUT_A(15 DOWNTO 0); S_GERAL_FUNCT <= S_INST_OUT_A(5 DOWNTO 0); S_GERAL_JUMP <= S_INST_OUT_A(31 DOWNTO 0); S_GERAL_PC_4 <= S_ADD_PC_OUT_A(31 DOWNTO 0); C_PC : PC PORT MAP(CLK, RESET, S_MX_4_OUT_A, S_PC_OUT_A); C_ADD_PC : ADD_PC PORT MAP(S_PC_OUT_A, S_ADD_PC_OUT_A); C_INST : INST PORT MAP(S_PC_OUT_A, S_INST_OUT_A); C_SL_1 : SL_1 PORT MAP(S_GERAL_JUMP, S_SL_1_OUT_A); C_CTRL : CTRL PORT MAP(S_GERAL_OPCode, S_CTRL_RegDst, S_CTRL_Jump, S_CTRL_Branch, S_CTRL_MemRead, S_CTRL_MemtoReg, S_CTRL_ALUOp, S_CTRL_MemWrite, S_CTRL_ALUSrc, S_CTRL_RegWrite); C_CONCAT : CONCAT PORT MAP(S_SL_1_OUT_A, S_GERAL_PC_4, S_CONCAT_OUT_A); C_MX_1 : MX_1 PORT MAP(S_CTRL_RegDst, S_GERAL_RT, S_GERAL_RD, S_MX_1_OUT_A); C_SL_2 : SL_2 PORT MAP(S_EXTEND_SIGNAL_OUT_A, S_SL_2_OUT_A); C_SL_16 : SL_16 PORT MAP(S_EXTEND_SIGNAL_OUT_A, S_SL_16_OUT_A); C_REG : REG PORT MAP(CLK, RESET, S_CTRL_RegWrite, S_GERAL_RS, S_GERAL_RT, S_MX_1_OUT_A, S_MX_5_OUT_A, S_REG_OUT_A, S_REG_OUT_B); C_EXTEND_SIGNAL : EXTEND_SIGNAL PORT MAP(S_GERAL_I_TYPE, S_EXTEND_SIGNAL_OUT_A); C_ADD : ADD PORT MAP(S_ADD_PC_OUT_A, S_SL_2_OUT_A, S_ADD_OUT_A); C_ULA : ULA PORT MAP(S_REG_OUT_A, S_MX_2_OUT_A, S_ULA_CTRL_OUT_A, S_ULA_OUT_A, S_ULA_ZERO); C_MX_2 : MX_2 PORT MAP(S_CTRL_ALUSrc, S_REG_OUT_B, S_EXTEND_SIGNAL_OUT_A, S_MX_2_OUT_A); C_ULA_CTRL : ULA_CTRL PORT MAP(S_CTRL_ALUOp, S_GERAL_FUNCT, S_ULA_CTRL_OUT_A); C_MX_3 : MX_3 PORT MAP(S_ADD_PC_OUT_A, S_ADD_OUT_A, S_AND_1_OUT_A, S_MX_3_OUT_A); C_AND_1 : AND_1 PORT MAP(S_CTRL_Branch, S_ULA_ZERO, S_AND_1_OUT_A); C_MEM : MEM PORT MAP(CLK, RESET, S_CTRL_MemWrite, S_CTRL_MemRead, S_ULA_OUT_A, S_REG_OUT_B, S_MEM_OUT_A); C_MX_4 : MX_4 PORT MAP(S_CTRL_Jump, S_CONCAT_OUT_A, S_MX_3_OUT_A, S_MX_4_OUT_A); C_MX_5 : MX_5 PORT MAP(S_CTRL_MemtoReg, S_MEM_OUT_A, S_ULA_OUT_A, S_SL_16_OUT_A, S_MX_5_OUT_A); END ARC_MAIN_PROCESSOR;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0akrUk3wQb4EqzKkib7F59nSOOeoy+q3qc0fQDYykXO49Ll/FgY0ewL69TWySlFx1Cac/+BCy6vf iumuPLpTjOS55mFm1JTMxYzM9NsagXEQHLi1lEkcr65/dw7cjFH/RPICXrv18S5beJM408VyZvsr NCAeZ9gbVAaeGzkHq6VNPIh/P5GGGWEK3241GOn4p1v1t2GkteaDbOSjGK7wX7a4kTfRzrAH+xYH 86BcPdOp3oyEseFdQgL0BZboHxt4zJr0bXL7Ln+oOm7kGCKk4PXPdudDDSsXKQUPtDHqr2MHJwZk LDVjKe6pX7e2DnCF/lojAxyhWqtc4aJmRRvYWw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P2FMFi4MUNbCcmQEmOw8kkGKpCf5liEfyrVflbrNDPfCQyQhrfO1z3elwJF/eYuRk4Q8ng49IhJM QbJUTOajY+rTGsCSJpmNj13e1oNpCtCwEA2TBzHdzEyAxDwQ0hUh3ZqnFSNQ0MMnavo9wEIKRylK MAHL5TjDsmLJG1Zi4ZQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block GFuz3jjDcNus13vZfabnTsKTQz9Q9tOYpUUTv0v99miJHiWg9X4Bm37tDSsBPgge2ZWYV/fIZNhM o9RFowO2ZPIK8CdMOp5y1r9QlxbgxiEVYj1tH56LRgvbv2A1ghGFDDY3Qvyz5G2dmEuSZ/58uAtK A8Mm1zy2Ln16qChURWHrjkDuCcIOuGQ1GysEn2sqg3E/XWxojTbAmy+LaQrAOqIwoDTGFZ/Ek5fe 49U6fyDbugt8sjMOq32EEkOAQwWmc5uVOZWv3KIDCD6tRxPMIg8J9cwcCTEoanlasaaRs9KqN5go 7g24OWiCSjQz8Pf4KXR9USnCWt9Xh2mPsrZAPg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576) `protect data_block Im59AZ0tyI9QVvGpilKg9HEOiAHuKQ2NKYRjb1pd0X7WwD7SaI6W4ecFLl1slrZiOg38vNT2jeLC sUifOcYtYKBpwUhczYuM0NU8ofXJE+tVEcgK0WeUxBa3Nm3JxIY8ceE0NiVlhzqucj6Zs6YSrTVR IzoeekVAa08tJhIKjoAlFSa9wyTBR9RhdCoCDrL9mX0yChKzY08VowGrwE1Vx+je849cntpZtWLj UyErf3AoiR5zlyY6+F9+ZJu0iKZ5kSqPVAsIbJdASVNhiUP9Gb2tkTyXlEqtQ2Q7TdzbUXD1P+e4 RIW0EDv1PJV3dgWa35jqC7S/Abo4GdaYudtrFmvXPh15P2UAEcIkAL2sXmw9Cq9e2/B3fe2h2WHZ R6HRrugJiKb9Kz4zHzk0tE46PnEhGKJ3uPPTdumTTx0Jd9X3oCMvA/aBXYLuhkOXpwlU00ghdBZU Hn9nPe9Zr3JJ+jddZRs7qhIGWWbrBF0wXoikisln23kFC+AL+KHs1AxGfnJCltH9K2SkN1vgrg3Y E4eW7JQuIrHSKptWbTNSDTwyCpiUpFlOBRxz3JQqZkoSi7Q63rmxJmjre1xnMQDi+2F4PTZxCebB vT/Clet4j9ITo998fieOV305e2SMayJ8sOY9kIOju5cxqL1xjxVk0J6nQvYkGMgwWd84+nqKMDQz 1bx3tnOa79cF8e1MXUAtikBEn3lqLZMHaI5Bwbx7Etf4/S+QyIwrcAhl4FHKc5RYRPchLN54KOKX euUf+yQHDpRXmnhW3cI/7lZuUNLiHs33rZnSYUfp1Xr6zR/sZgQfFx+wWEZ+OCTLEyXq6qCxehKK duezfDNrScrAS0i2JoIAe4i9ZKUBysFPkAD7HB1sircS37ZiKPgpcpdJiQzQKdB8A/eUfSV+wUcB beubHqWWnfiLG42+Pm/ch9mX/4JcB763jWCEv4/J25vEG7R2xrWoZwfUKZv2M9PZKDY1ilna/ukW N5Ok3Z9MPcXgnkQe28lofLwhehMtMAzVga4/e0ohQx9YzZHPN1hzfyW8A/k9HZiWY5v0tB7AGxkn EruAVlGypO+UuTmayWJK2c9voLBVqfi8G+7+F+7PKZuyjIE62Vb3l8CFanvDr6S62IShU0gQ/xEc C3at4n1VQvcTLLqAAgj2ev3R+JRK7KuksWvR5bb0OxzCat7j50CsKkecb/LfHXlEXBymQFbRzQyz 4d2qN/xHwTrpuixP25+4xuVBDCStx+os8A6IZ5qMe+kXMzjPqP+oJdJ4q20qsddfvb2nvZ4gHoLQ NubwrmPtY356WeGGMnw9VHFc8OSs+MIEWQckOCjD5xhY7/LqUeui8Z1tIXvf0xS1RgLdzTRLWdRi q4WOPSla7ee7S7dVZYAS3ki4sfgP6PVIhLjVexJxiMg/QtebgO6+HhKTeCMVoSJA8oSTTczyaSCw SJqsZQpEKkN1Dm3F8IXAw+1yXZ6ROly7Z5BKBySqGuuexMEDibabYf9+FuElZll2TIK+s7UCTGFn nu56mztixpSo2nxIjDJO1WS63u8a29uMYCXqGn7Nz9BBUrdbNQX6EhWhxZlbFrecwYYwYQoDANvq lE6NhMmmqnIe3+SANBuo2572QPOzGOSVg5T+RGCfklwmzIn1WV9xHbI/yPJwr18TEt+PpGVq69Uc GzFNUYEG8KNUB6muas3VcKvNxEphXlR41nRbzZTcaqwKKTLfyuzKG1uII9ThR1Yzvz6kgulpA1EQ haJ5FWO6GJV7rXhSeBhKyG5EAUMRfcGkkuK5lsI1XYJZO5fJlKrkvMhrrDz+hMBjKnYWNoVNNIO0 uHjMWiUmuhXUif1KsOSbtWRGwdVsJigADeSYSgva8y2e4fVqkk5L2MAdj6BKueGLcxwboaodgZ+D 2QkfleRhz3zg8sy+CbLzaEFt1Fdo0HE9TPufWW6Mlw0RXqFxhqacm8lH1YF6IVXMwmLb89qp/LPc lEOJ977Ns11Ibpv0bBtmceaPPhPNcQw9d+1bNalzHZaYnJELuMM8vkq3K0jWaJq8uG8XUKdDsXya dh5HDBbZNOyD1MHPf74HB96huuOE/RRRA2OnlOx2RHx+oN9wFgA7/eHGylLsGs5xEZobwPAA/1xx hKkLtdnHto/XQ+hrMDGm1GmvQ17RriZ7o/qhfjaCm/R4qW9Tij4zUEmhA1486zZPGIbW7Y3V0SpB 97ll26rJpijNMTUcu7DysTPAkbWvP9R08XcDn0k4wP4GdtPh6lP2fwPUKvBuO298ExnPt+G/7pHB tKyIoB3T2/vLGoaW2/9EKFvs2JZZawize7NukAUFf24F6fp+QsXGVsRDh5ZhBBrD2wt/hvwi3hoj RoTuwtQuRagCJzB5ZD84Aqc6UV0R/PrNMXXm1VXot3HROrD0qTkEo+1BmwX1puEBpd7cs7VpIHTw hlw9PVHHQRgREJU0azV5978j2yK7wmdJ6Km9lbuGL1FUm7NewZjQP2bYCEM+l7Oft2STO7ndmFV8 9RelzQqOddxtZEDpCYZf2HrdDru6P+ohxrrR0SAcbThmi3neXkATR3D4r5BSAGT6s33hbjXtegHM NhDCfnU5xC9i77597wARVfxpethuKJ0euNZNhUtv+XFVWj8VlzL6GCyzqRZryB7MkTnfiWVTFeLi wwu9UVK9mcYLFi4Hlag/ssgdudHLnoqAys/MHb69RtYHQyn24Ex6bCST7gGoxRZGL+Mi3hTgP3aS uPI9zc2DzmBp4DC/Usb7Soo4lDgcI7ZVIH+IV8rSi8zP3bRQ1XWXUCcDKlRGboJIo+vuV4D5jZ6/ ZZ2QHvGGABNyrpOR7Gw+fiZsWWluXSrBQqvIef/xuOMNg0zIXpfHznRoJg5tzs8JL3B/CfepfFyx f2f5JepxChNszbF/R3/zbIGKQP1TyjSG6jIuwueid02fNy2ehbB55HmV/lGLa+/GJLZHVVIhbr3h oIRfWia2Bu+BaMRbL/asbTxUBW1Vvtj8uYUdbqDwMxXrGzWk/YHX3s77lfpNtDBGbqzz/v1bWYy0 ORCHZ+75I9jjqBFjpZryruTahI+MP6maNSapiCs/28mBwWDHZg9TFIb5DJSC72NoLzFm7yrBT0GL GBWFFv8C4lrAVZ5D2+r0Y4mySL0ZRUmDGJz5fI3wKm04eC/lDlS709Cm7xAfhFW0Tt8ql6lCZPry VjKzFVZjw5rv4G2uJ/pDjIIbDeB/fLy6HuOX6xqB24OdTnnpra3tRB2dXPD28sEFRGfpYFjk3ljs 22TipwAUaDVcOmm2vX90cT8fRLqGWaR3citIai/n67i9xU7aPLAquAC+U+X4yW415/IMKYJA6k4f PcoUxVFKrOEyzQuNWD7Kx5LY8Y6ey35mcQ253K7sYyUvCOi04NN0yNW3aXSfrOeam/QFmJo5FSAt zNkeSjI/5pFnqorgrDZdV2WHXsWZTjrEg3QjkWXazJQOVU+x1oJOQBlCDNmPm6haqNhtJ04K0+Ox YG5ewcaDne0fmK2RwjXTg4NxN6aNhwV1UHKHeksAKDSJbQd1Iim4VtZ7bhyOhYAAlO+7TOEHQqDP earFCGMB5PEfEDr2++UO7aDZQKSCMVtTekEojwpIojl5BeTUQslWSl33RjieWIJfrg/rr4EJ8vvL ov0TxeHW2fCCXEdzpUDGTcMSNbVg08dLabhZFPnYTsROCT1wJUVtYPf++PHW6YmKRYwBaYtjOUyZ JYr8UEb2dOQoFPB6bmPMZMoLTYnYZpsVkZAvBvf7NPnoI2bdRKxGRdTctgLC5JsUQ/JP9eLcnApx gLbVfI/O91X+DZJk5JDWmxpRw3n4gYz6iuFwPc4ZoMKxX5BpUVhgR9K2yfEWiIN6ukTZJF115k3R ipqV/yntBarqL56QDHKEeJyCCF/zMUefVjknln4DRHGqnkb0ulM+MVD5tzUKFymTfKrNd8DTu2Wz pxJXkm83EuisQ2IhuRrc3OQm4lWKDKDForm4hsWZWB0lK+piYakQDP1vKxeQOkklVqkmdbe6MffZ 3UX+1sN1OmJ8UKFaBeaEy3I/rJMqFBdJbFFLsTSjXJ9T5Jkl68DuQdfNbobPIHf3prEKWe5vdHZ4 P8TULZgji6zWcY0xo3VOsN6Gsh0E6nnnvDNBaoOlkX5qhjPe1Qh5wgFnn4pYDjgz4zYrhdCf5hxp EWMx/caiUeu2wAZpyMj//wRTbP/stCohT37t6skQnj7YlX+RUd/IDlHlvdJaBaq08+D/eU0hVFkT KmxKx2LooygZVZdONEdaBGfyq+15pnkYKBFB+mf2xVcrgGQUpUL0n+oAk60U0L8lxtO3H9nCF/ae XjTV7LEANAVByqSJUOnl1t2Q30zWE9bVi3NyMsCH+WnnRe5fnKmr72Les+4keDnQjubGxENAnJYq NnOS5YlfP33TzYF5QGgjtDwzJf9JFRBtAxEtU+kDZe53oCsJ77xZnhvpsQZduo3daAu3HAbKI8ZU pFUvjXgsiFtbqpVCdLy+kd6+voPN3GcqB7f/i0qVGN580FgyZNf2QvqULLMB9nOv06mGb4LFoPGr Lh806W+gQTM0P3smgwJede6pEIPsUpJpvVh8c3zCbfS473HwpBAY9m7m5OZ38UI0WVxHZ4oBeSKk rQDAyYRvWyG9dH9hXRXO+VCIVQJgKwWelfGAq7yPUeGyww5vmDaOo/3IGionUM3aLtGXNhb4jV1E QhosSqUH/X+IFYi1BCD6z/f5P7AdGEYwynl3ST54WrQFXhq/5IU2cRe7i1ySv3+Tr4hqnAv4XxYm ohawa15c7ppzhUU+i0W3iozD6QcOI2XHA6Tmp27BKHf7yC5Uze8d9gF1CLmJvCYJV3MiwsdiuPPK gWetq57i1quSzAKB1xFgPgzJhv162e23IOSsbDqTLbddcG8a+z8ooI3/rV2zekIIu3TN3x/Lg0Us s73lHmRzLqeSVuQaJw5ENLE+Pvf3oUVY30Uic4zRYd6ao8sNhHJByi7k/Co6kxVDp0+juqdlgocg Un/oSYtN1OXqnQJIoaVpgYRIXsSgkVyFBF4tI9zrDgWn1ERyELvHObAPeGzTjF7K/sabM/NA8dc8 UHv0BLoLsw5LEnSPFvcZuRydPWQ2SVROViOtwJV91U4JdV32PYbaBE9Rt4Wa9Bb6nvG/Y8kzIwfy JuKZ4e8TuPzC8LH4rP7T5/0MQX4N3z47Q4O0X9eqVq7RaGc3pO9rjnGKbqWgSuso8IVURzZilIbw ABkVOfyQWxYA8VWDkd6g2h6NQAruiGxjvciuZ3u3BPkbz0LSYHOlamv4DF3apsTCx8VXr5diqV9p RhLKEwa9t4YrqcxuVKp4mUz4CMmjDW6p54F9t3ZjMxhLlGCzCJbgtsrlcSLQ2mLJGeYFN6ywQf4b X0s1Q1hCD4mjaTiMmS7uKff+H9/ts+f/GGf+Qhb+Y6hqTHSyI596u9BFMRr+9iejaCSgQNFJ3wze jKcmbqMxcxQqUxlL8xR9sxyRdEv1rNUzvV+o9b/iKRkkHndp5hjsjnlIAKCnSbD5aMC8MX3a/vVV nkIvw9skzxgYH/4z6ptNy27lfj84sWhejbgPljRw/JXpkah23C8E/iH9Y2XUnNuYQX1cqp3AuOos YEiA5yH44bKDEJ9Qpd65vbKVsoyEziPc72k95m7/P+y4Ghs+eUY8V1CKGsQNRGqpTe1bseATH2+v 1KZK5FfNt0pG1Pv1HzxE4FZVOzJSZrTNb5IXJye3bf8DIgcwBGFU+YUSIEqQFyptzZfjT3aZ7b59 RWlbFcFltT/BtNBqQOgaVcf3nDszO4I+RbCzBj5DK46CtNM1DqPaHOJ7OVAdy9bt7uZTIQy3SPXH NZLWYvaj2KTh7JIQccblICUuYOIvi6PH4UI+SB36kGagi0+QqaAMLo7OodmGfBGTWTd06acBdSXl 3QomHfjlgZCBRS26xtjQy0w5g1ow+vaEVt+U2EcMjPLKK+4QWB/3tMqpd8kNm94rwDrfO/FqYaSu dTF3+kCzqYO/iVXlc5NFxyzG9ZTx1ZqIo/E+J1kXEwhUWd9tBRewtjtF+OoLR3pklXGBHDZ5LxWQ truHBLWK2/MaOeHhrgBtDKj/1mRrUEhcUWAVimy8XSb6hGkmjBDUeaP8U9OiS+IEVFCqgrPlOFae UiVN3tgFfJRTDzvcRJ93eOnBfg/mt1xSrEbOToivfCpyFF17B/UkpJhcQXNVtJuSXbHn3y3In8qV eZ0EEsl2Z0lijlNZ4LWzHLDU4tFUM6CgINaMCgtyB7AcN9FBeORT2Tnj2Ed57UEjdHZ4acnVR6ya DghHwyJBf6KPoeZhiNaZqZUXHDwI/W0TxdXgjRiOpjk5lIOOLu+zNwN4e3WvtsMK/qaCF5jKA19e iAosC3IOqIsKZCmv9x69+UamxkKsi4cUW6jhEqafWAu+jCkatqHke8yqI+n37qkr3c6yqDjMmuO7 QM09IhpXM1+cr+OItVAAratOT3oV2uEto6sMoIdYee3XPJKj5YgsH9OQbuXI1/vA1BhqzEwABmI2 mWMrvk0WJCrb3dvtfb6DwP8dFq387dNLU0plopitOJy11n0xEo0F/vhRAO5ZgfnajoIk2K1hlh7h 3Qx8TAex6XTwz6VUeJ2rFEgy+w72AQgXONpCANpMOHte39RkqaW1VQzjp9YpM7wOnKcWoA+PwSJw Bn4pVigTKAP1okAsjg+e/7DaLGndG2LwzvgsQMSsz/5J1EoTvpEdXSU6bQLP+B3I7S4R5F821tNE tswEdgC8lFGcU5p1ztM+vmEZYqgjtcXEiTdbe4gC1U1D5IBSjblhMdN5XMUnrTQaGBpZ4+J/AYWg RIIfDT92d1XUB772kp9MfyN8IRG32mZwcin+N0f9+J1DHRS0T4piw0dTMovpUvMm8Yb672sqB0mk OOBXlI8V5i023Hfiw0YKPJJY1kmn28bZ2RHlMxDriXgxJgD1cnSyxn6leV0YpAz7joSTF2zyq4Y6 +c+F+FPkzMpBH8BE1a81XRdPiIQGecMdWSAp+9iKIKaSJdXlQbMlS4b+lh/S4AyPu5f8BxCKJino AkEug7HSnNYlM/ckc/EttcvKqsIQthpSRP/IHmXkKiixjwW13hDqzY05YyyHKQ+r0qo2KFx3GvIY LfyGkSBv9SCdMNQmqgPqdCUM7WJlyh4cqQKppVXSBvFbOvPR82nBY2hXXKrIUJYTpfnyAqarELM9 8dSHgihE0xF1URQmCPil+9InXfZOVj4YFRW/EGgIUSQcPOZqVqnX0C/8fB2z2g/CHWJHkFJp+V1D 11ImYhq3cYHDs/wWzIHTpQ8mQCZXSH7+QVn8YXPKEs1Mqeb2kWL3HjgVMbuwvOc+wRaRgYoZfL4y /AMCyMLwr4QowVvCIghJzh0zq+bUry00yEVNjUA7McuhRVBr745tobGdlLw27cN6Yy2qWK+vZtQt tkcd1tcJGVYh691yaMiW/sAGEfzC1yzHil2xPKTfodTpj371gz3N12xdo6wXTQwUohFmtxgu+7ki dPJTdJQ6uMtIbfCRWc+ZEMozHI2VWsbob8uI2hKK/Du+pgcni4Geg5QsV5KnYgbNFen9/bBw8EJu o37XMnTrFTiHYwnV8Y3DJ92H4jZIucVXKoUPaUoIVblPuEoPlZfQnm5yllNjU4UF/CZXWhQt8Wv9 woCFRQHdFMcO/khUxVl9nR8IxrvNaH9wYHep2nCPjuKt22V3VDHbQDsiV3P1s6qlM5WBuSKv3lMu LpukIpvGS3BhjPE8l1C12fLr7uTbxvIyeuFDRAuvTYAaBOrO1Io3AYNydWc7SAGq5nzfJzn2djNL 7QEgfaYfhVU552yduppXrH8BS1tYlLZBv1ovf5aesK30UD+WMPAFCjdXsOX/QWbvW03He2/0GQPF PNzX9jW9TPkXnR3dHnt+CXbJmXuTocE7rJky39xZXNjbtBWuDoFOkxuSiAZW5OLzOjPZLrkdue6D K90oEKnCQP6AAVYVqAFsEX6/h1tsXeSyX8Ya90YAvCJWdqqXiL/MNiW10aC71n08kESACtGUMjBP 2LRdvdX8M14vaJDPR8+3gRcMla9M1c/sfFHt1o+RDV2z81KwH558U4c3JGz3qQCqLVAXcTPoTRUr Efair8zbcRanRrry+fUbxpRSGjS5pqmZd4F5OIrSpiRdX5akzmdmgSK20Yzi2vtNHNHDOqQy/1wm gLnhXjsIwlRch5wNwAxHXzqdACKk/Ec0AWpuParr2t7za2w7sYUqttSx/SxbnYHIWHjzGEVHGW2J nLwDf2yfqmqeIeGCb25Spm9XuLkmlilshTyene1/GDMe3BRHV2RGPCINxJs4SUUkBkOwDTypB29D ixUS9kmUysptJPyqU9TTIIPhhz2d7091m+9Mk0iIrOIPIc4WPIc89CH3VQtSzgi75SdRARzxGPl/ hoKI20LS/gc+MWQHOqGeI4cF8oMQUbFWb3Ra04kG4hp6Ammh7Y0yeJ8WqY4ha13piMbrHmYvWVhJ z1DZZhoLjK+FRWQ5I3L2DH4iVi6qSfwfRzf6lY/ln1QhtzXFy+7Qs+ieLf3SZybm37F1uKW/8tmd Vu8VEZh6qwYBJ8l3AkYTngWXZRz9uhBxNBoqI4J4QZjpaAIeeJ5WbR18purBCipKUHCEFAeRXyHN /paYV7PJ119MLSMjNp1NEoZXb6EfBQ54nS6OfXrjslefqUDTiybRui5EooLCumFd3K4Qk1pe5Vxd NiXTknEujxfTMGME5ZfPDddQYXgvSOxc9yLsuio2/m73UWAOHoYGGnAPxdqcdUcoUoW9yf9Ws3Uy 0HZJ/Ql49rfDImH1Amt0V9w7DtQF9jYfyMZn0cOybORgqwpBtVj0hTazVZp2oLXaToD7J+oGG9K7 nT053C8FkZB0BS4OJcT6aVkYeypQKA+mrc1kbuz96r/pG/LFIHsSYL2pCLGTr0ItzFTxifSJo48r V+BxXZRPSXMM+hEZbxbcMZxnwsTPAvnZc7hbmsrpLzjPDlAvc+dHroGPn5ntX2TqZln5UYmO3VAi 8+8GFJtzqYwctRSJb5u5QZZBRA0cpq+tNswnzW6PQ/g9t2GyIlYmZdVNrp8mXtXkZBvvi77Hf0Kw +hWG4cwEWkMfcJ9Wt6QgWPAmO3RckY8H00JABijAGWt4+B40FjpUgVtPCe2VX9/IV+SW7qegs3m4 U6w6z56moJNB68lV0+CHS+XQZZPi4UmFD5mO1MH2GVs1M7L9jqEkddBkRyG5Rdi3MTk+/+FIFDpK 1yIGe2g/baH5PvdPb8pPnWxHXpOKCEZzZ2oObOuMDfE8IKv56xX37W9DviW79sMFMzCd8EYtSfxr omRggwEF+xoKmdkThOF+TfzpYGM6xUjzH/DcdL2mJIJEdtWdEgXV245t/dkqZCDSjAFBQ2aNxNCe kv7e/cq+AxyfKmv/wjSyPkjZq4oNH98oek1QXN1ux862XOjpbpr7i3P7Ypd3UXxcpP0d4b7c3dsX Rt2guOXG2UZGcokOpmR8fzwGdUiL4OGAVMx7n0BMkapPSZsjALxEEUMYt4fqt/xYA8/kx9WcUNfi xnyzfePGBBhhZ0cOo8BcIgY6MGWN0ZkZtGljEfaz+Zj7/hQqaUKdec+db9v3/+119/ik0NHRhioT Z1xWwIDkiPpqrVASRzi57GbUKZnuzevdDMyLBMgR4PualoszGX70F+tc7GWM0ymg5NG1fG5C2/SI 4P15LwKGMftfzjwBVfobYIAxAZvO5UokYFz5ZRkswVlwAVnktsgWKMpPnkJEg8XioGHNBL9r1wya mR1SQRQlR2FOzdHoaipDAZmazcMmDKC0kjnb9uYBCtU9d0bC+RhW0XSNXBbFdYLPNfBpcDNqr0ED C2MTpQDBi82FGPinsNFP3G7CAQ2Uz/kDDlsmP1apXq3DOJf5HFmchowHlNojWDhlgfXsboZbhwJW WUlSgkxlvYtaLYIQV3SvhlDQxindQtTz2ZZIG8jUmLUw2Yh75cwoo47VI+lLB6UriWSCXKuxo6PL 0LI9zWhkXx/jEgI+rZ5FpGxMB8XJpkvU/3VIlcBQPDvtDuyPgy+HhXFYh6TORAtwGzi5niGB5z0l vDXOV9oXyiyNUUNqYzko+7g2bl+4niTIW3Pc8ebFjKCw8OLciY/C6O1HcZs4pambsLlkFeAzn6YS i35GyxOSs6mSvN5zHCAD4VKyhC83EhoDFMcsIdLL/X+WDSlAOhQdWpMc5TNCpJ3DjwEQ4g1++3h6 wboWx1E7Yt6Pss1YkStpl+AJnxZsgI2gkw9I34OZugm6ci8DvkBcktZ38ewKxET59SfpMek0UKI/ V0rHjATYuGVVvosRO2Oscwi8DC6FxPVYkWrHkweafn1iOKPPTrdr1mGJasqwj77fFeYbYukmRDng Is7zDu6TUL7q3YX/mDQXrCw9jzNjwWOi9zZgFGlST/lpytl+s+k9knfzIWzATEIaIcIO1XKsQPTc fkI1z0Ou2g7iAp0ZpARrtSH1FXl4eMYNy+ZpEaEy7RuMIa6ro9qwpSBUxQbytxVXQdXNsWOHtSxi rWl+28pQId3BSrEwdudLWb8CCA4TOTLhUzewAYehtCi8OCx9lLCtIfuKYsJTDXfm7ih1flwZUilU 2QUzmDPF8VXzux/Mpd5TIv5lz9IU162e5/G/KH5xLieY+Q1wQW3YXIT95URzJxlHA5Jl42K740yw OYC7dlYqYkV9+5WKGrXmNSmJZlBthwr8Yszk6Xr0G8rodUlOT8JFAD9Y/En03KkYBwIGo/Xc/XVK OuulCFCS9BQVte1IhktNlsmTgth1GsVptbWr225b4RNYa6z6oRA4xiV7rUD0MmwsmHYgoRKM6c69 4OMuMP7rGlZKC8VaRs1Af+NKtOYy6nWVc0Y++CEu3azaSJm1z1lVJQq0yiAvr0LCu+6uXB0s1rAF qFLjLrOe9mazxxzvu6pVHuzV0r/L9uqt5l4YZelCzPVZVAM+9qPuUCFeO1TSReAxxJMpPMxmmrDk A5QufIydz+NfNJqPLgWKagXrLYR0AJo4A8Yt09ki5fW0KOZ4HcRk2/pxHMp0Cgt5ZzjaB0kouHdH iPNct92Y+MMiArMq7kIwh7PUtfB8Hees0CQSnEB3qWZbmJlX5zDt7Jo/tySrzllhcQjqxO0qgVSp Tq82BYAlctDA0rgODAwHeYW+OWP7nbIr/jZIkJSZrMT1AuT/7R14XcYvoMB521Fekje7h5NbPAMq lCLaPSBCWPgmeY4Hll6nPMud8ZyPYgQp4C2nAVdtJkAX6XePdMNPKltdJ/HFJRj1ykjMZ+V+Gf1J 4asFcYCziozFK4CV4k5eMJaarJgNcV4u0oCPzIT5Bciv6fwXigVCEqAZmGpmxJ4WsKlTZEm373Au ZjHQh7T+m6IGxsjNmPLaKK7MBCR/S2F1IL5A9pwaBtP2wlmD5fpQ+s8lwoNRUD91SV+uzt/XlYbw XM3uAHGxXYP2JqSPmOCfxAMxpiDfomgsqNOvMUH5u/CB8yq3l5N9g2fI1wPYPHJcmzDtTXcq8Z+a 1QgkIDDseCwbEU2LbRswo+X+WNbFNKf/XVx2eSuG1QNFDbBboct0e5HtqU8s9YSlez3SQnXPpO72 0mwr7j5tNelmwlYZsN1PXRpnPRbNUVTRXVGpEem05kYQLGApcT2w6Py+XPYlo0P4ukBZg5vbJOXw nE3ZdSGXfuw0AOfZKDn/jj5E2pxav5VaKb/NRgHl3lNY27QsLogyNciaqyfV3Hbyn5xzEBK9IM2A Q6OM9JyDafbpgpEEG49MnbWQfvbco9D0pEqEIQoKgiDWYrHr7hfjpqGEGecqqMT4NvSFbM5+fp61 5Y+9HHYJMc2zG5s4nEiR+utfB4+U2sDey3v5Z6vKAWAI0VRtCZWqW2OVwYJ2V7QEttS4OkUwXV+G AWb2R8vZXNRjWsl6Huq6vjsCsON1ZullTIz9xbU/8DcY10+jRReysZP9IM7QDRl0r+Gh/xTpWuNE TR9o/l0ark7t1y+Cy3csehjEA+7K+9EdReZOtDnONapH6VNB+A3l8MWeU3u+wziMrRKbBGuls+pE jULfqjC9tO1DtNejrBxbpR7gDDXc/n7ImfhlYCULhGmZyAhkq0IGYJr9WMIZf/4l0BwZCGYrjnet CZqM3Ys2Q+grN+bN4JLWXrmTtMI7UhlrLm8SaPO8KrUW4LqBREP3mCdRvMbhmGn+SmxC8xTZma6F rs04g8Z5/ywdODtwqql0OBml9JzVs5vwVAT9Mmdre4R7zE5zK9cTiVsBFFk0szQumyfAEwyNfyUq FynMp3Wq5dA/GMMwjh9ifcWvteuz1/4Z3LVgsWQa08aYG1kYJNSq8/AG7ti8QyzYSKvRKbXW6xij yZVSqvpqy941AtVkh5MOnrSmhwAgeZ22RZGLL3snX3+vk+FZJiiV04mrHyvVKw8jtm40Sb4Ibsig qNh0h1kpCMGkIip5il3rNn8R5CVEuxXbH6+tIYdxTA3ndaFK1Ye4QFfROQgeUIq0wffSLkhznNKg A+v8k2jT6HUxJ6r++Dqi/B6cdbNiXrDuosEB/+GDMSMg/QZ0owa4iVwSHfVvF7L8fLQFN9yvfhjE rPu16aO3BKEdkaavQ5CohOjmuiCi/Db/qVGA9shif9Idejk3tVMqCM1j3IoPHhQjGanpMCq1Iw33 Lp1BU0y6hvHBlnpHF7I8S0RsvmVO6jNWMyjunfCpK2wcQbw6Hs71Tc0ErLOBXR1OWZob9JvSllFh mqdqkCUffvQFrFo7S4KAvG4d+SSjfSiBqu7uIKvl41fLz7Ujx+DkJP8iv4EYBfe/2/Ivjb+TV2xy bnqUj9+ZFLO/mofq9uCtTv/y80dMVQeZyToz7Bi/sR1ge9EGq3to2Fkl8tvoMEJ0InlOUg15GvfE cHpjGcoKjSWXTvOu6sKaRGu26QpEDXQ6bKZOSQAnwDpdHqfWCeUVmOF0Ppo2LBCVuqqxHJRkj2Fn +TL257dMfeDoJjJwrcOUZACO101upByptDHy/naVaAoiY3p02L++Tt67SfiW8+jUaSgL2FKogXrl z51BWdYRXB2Qk+6Q22eISFtVciZgEoYTSLUHsMFVRkL3CFkdSM/Siq5cUzSBQ4JbfyGVKz6JFf/e KwwYxjBXHxBue/K5SPIGjr0F1Jv+asNPLYAVPOUDVKzgOTC5SUFvY2PfYugWx9s6cmkMWu6AaHyl NVM08c9ILPB4rWQP7vrYFqjL8hXmmpAngD8F9Qlf7rAKKdiRoZJZjEsvFMOzVYuZPSmbY070u42d tcpZcPp+ctGgIxYJkFLOyl78Ui1A+a3Fj+bXkh9J3tZZzLnHTD7ysQidEX0LVAFvIsjezngfkLr9 tPBiDYFNbtl3p4dfDO74/xUt0gtZpYWbHDPnBtPyq/CHbZQ2+Nm1RBAWuogr+90nEcAwuWL9AJmr MaIVd8kmAl5J4Paaj25p2dBhFN5sIIHvXuKsMFBKlpJbnya2wic+JypKcq/om5hi9TpHUOMpH0mM +sPXA1q1QlkFPbRuoelbDUkVihm7iUu+tpyWI/h8tCanksZVcZZAw9Jyb1R6vO/wdIwE3cXs1t9L QbOeSv3O597bO1EovS+FwGL6aaFfXF8NeCURiEqbWRsCz1LIiOLD42Nglu6i4DQoHeo8GJux0OAq q9g3g4hdWfRmCvAiAK0WK0rGmPrwOrxKfEoWU2uj0t8Cw7zOkbQdoJ5F1G2gKXvpWcntYRmD5KO4 FSGOvkCncIpFDmsesy9kDuHMHKwzziiAjFMSMGUTOd9hiJuuI2xd4xsU96PBkVNSS0DHU1HxP1iP S2PXz+KHOaHLmngD+IgFNR7n81yZGd/PwFis+xJmx/Ya26YGOKxJcBkYOhUePbO+tyGdIXi7i7oB 5pFH/FF4e81ILV3JpKpROat21M24AVaZGY1LHw3XXTPkhOb+f8lM8DRoef7Y3+PofQrogtz7mfqE FDuBa73apnYDJP1uD34og4lmK1oXUXiC2PrXmq53bWroyVWhpJ3iswS8GGUxkn8+25kx3gHPpXdt +f2vwAnDtmiC0Fx4hMeWqR0uEnzUS17/yRl/z0+S49HHgPZBMI3mppNufRGN7D9IgO7vQgk3ASgi LTSPvy1nZsOVFdxN+HWVsTN1ieJExRgBGKkZn3s6WvocLVlNZP3/5rzwCLvgB/DBgHuR2eQPCszr JLQHD0rywOByuRef7cYhLmDybpNJD0wZGIYvAvE7DccvoBCRJPnv6M9uJW0lzuSXmQbpeKJS/qlq aCusUDID3X8TKagE6wZiknXz7G5VH8WbxNcRNDxJ+zz0aBCNUgVeLdUcL+pSh1rDJGDySYA4Y4fS ly1VKBIVvsGhTVnG5Dcl3VM5rrHALNrlxYWIoSx1ZQ5O8405eTW3PN08hBDcuHynMG0XJjnXuaAJ UJItiNvL+SLw3zfrTwcwC2iZXjFDlNviUw5/fKwbjXqeGlpjKqKviOAWGimQkVByU+RaoA4YlLP+ 1IVZIO+sV8yljVRWhJk80h5Af7hR1CcmB11mZYKFUxYyPkfRHxvnv9sErdEmIMn5rysYLzDWKYLC QDnN2jUWb/WwnT9uudxpSolC8x7xJQ4KpBQY7+8h4JbMoQKDE/HJIWfEKgyXWF47QofU2VHiF+Za 166QnVxvumefTppYFq1meHip8vVBCR1Zaq0kgIpsTTawL3Yii/183J/2NzBPX1XrETwFiFllQdQ9 vusJGNZbjZTbCLogv+jPVskPktokW33rKLinEKOKFdWqiE3Y4wxCBMj6Da4bnzdNHPh+hV4UJjor w1hKxLXe50Gt4wc3j4CBGoTnttI5ocfkB5lqGrOBU7xLQQCQ6bTbwMtK4rj+btPdLGDCGVNlONFQ yUfGO/3/SWiTBCvZ/xRgUy02H1C/5Gl6WaA9opNUKMH6tLgSjDbNPy+rY5KZoZR8pyHCQ/Vxk8I2 pguYB82mFYgmsLpblu9Njf++YcT44wHwuPi/ZmexpLXGiqxEDueA3l0mzaODLnY0T6wf94u3rHYA x2SKcJl+/Kl03Xzms0BxTJvydVqSP0w8JS7us0Giyhc5MIRWhEq5E93GqkUTR+BrVSe+1WxCDZFW TRNSAdqKtBjQ6+Os62lrxp8qj6WmSfaHjNe3xrYEMtsYYZdUHxHbISQXs9+bCrRSUjxMCxkduBlr 2KJX6SVJmUjQK9Hv9BfhRlrziz+aUlYDHSNB8WaSt/oqR80+DyJ247lWEz/PlCVVjw5KpGhLRdk3 +PLpyIGDxcX1KxZSkhRXwSDlEceGBEHCbv3+8SGhJyCPrRlWW871GwFok1laFxwJJ+4WCb78x2Fw 6T14G2RUh0BS8e/CoXTU5JdUjehtzMkQP7UPF7bw+cteWdpDKyVJlgQ/9ZMBGTGXUHt9mYJpyWZ7 HB+kNE4g1Fgzdiv55Np+VmlriPbbVcx/ePwOpprMsHj0bZxPf/moqQsq5AjoFsMiKe+Nw2dV6cNg OgHJ5gqt3bkiXaAa/XBwDt6sNiSvbm7UEHuID7S6D1NtVen29KVa9V97d1aL1Six+5SohKasQv4Q UHjtrGzmujCl0845Y/JU4mkzwoHqYFg/mKjUSsZqKZxad8NBzrA9G+dvJSOdKqpy4fQu396th/+Z A5i6IoX5V8S4ZZpPFuix3AWoldpae9pdW9PIU5MWki1zgjvnmP2DxSSIGd2BiMMqR1b4lECKVcWp 0ZjTf5L99QkqXRmXRQneHKtagNtWAu4YXpiVlHp2WdElQF8z7rxpLuBKm2QWVpfsK4i6S2gADcxM +2QjjwbDwCznlQ2nizRtyuW/xQfbqW8S/ptUiE/Vx3M91rpuSq48fiiDHhKNLPma8cdge/XgqSMI yJ8p2kXu0iU5xhp8lyZa8SoeIpXBfkFrE1JU1ZkYSO9eUbMCqVCJZCCZ+3whro1pB9j1tgbYX814 yfO7db5xR7cfknlrlIlsET0oZxKLO3MAwqHAznadDXOuwVxomlPZewVrX2JclK/ww5sC7/lULXIA qk7vmKaSNvpBMR9ayx2yp75hQuum6kLAx5OH+ITBOZrXeIINPnm6/Y9ZuVIc9e0qgsL4Kdre8B1y eti4avsI0WBdyRILXNJDDRxcj+PfmBWvxN3+SY1c+er4eIMADK+s4ePqr6hyB/j515xgMYbAr1Ez xsQ6sMWQQx8Z4rh79iq9oY5OF3eeQJnjLYH/Hz6M4Bga4HgKHsfvmLcfmPKOndDNYfktXr6yMp3t cInYQKoiBO1MmjkAqU48nH8Vdzi3bKt6cx6j0716xYXzpiiAzEDbi3JbinFzZcYneXaKECj+caX+ Gm953EDrNrx/f4wHHfjYE3YEZl6bbPpYqN7MyAPCWu6NJB6isqiYX0IZxW4L3B+N+46kSoSQapil 7TjPp10rwVbQDhFJGe1Ok0egGVSeZzr+yWec5kOHqOxny2aTi/nkkLQBiearmg6LQYDC1IJDfZ9Q P7vgpEbj8I8dACVFLYpqI7LmZeqYEq4NWYxqkJy/XYbwiivEDXxS3xWg4Hccafcv/vZsO54a5t4S B0M5THouzVb5B3CyrkLUPD4aPJ/xUIsITX4dUV+/+ZrToyv/jApJH3YcKmxYcATwPSovpxKuYdCf 6mU9UweyOVDU9qm7MRFpSeMLnrwAwS/elW/S47BH6LLKvrs8GjyGj5t/Z8HpBTAwa4qAkFwjwfpp 1dW//ABy9M61Egv/WHqlnHMCb6R0utypbFEKGL9vu9qgrQz7mSDJ1phBDMGldVMn2DyK3Rd6O2K0 Mk+GMOkqSiujP6wUhFQMhsyyUNag0oYIGMOeEVAl3fVyqtFcJWPXSpHH88P+anziphfh3iFt4g3W NZZDZhUV8nBSKttksHDLvS9ovb7m8iLynIV5EqhNQJz6Evbnwv0bZY+XjVpyiP5wVSZtAtVwDtt7 IwlY389jSn4Q/hXZx+onid7BJ/1M6NZboop2U2T5t/5E19TqSU/v+IvIwatfTnCc1TXc9p6rJi9P CiYYSnobnGo0CGTBYsa3kyobJN6hYcFehr3DH0hMsfrTBsTpdee0M+P3DJO+Lhp3fJZFzfhWv6GJ cZbAfAfRIBeXDx691/MdTX5tnyNr1sCOI9pSk4RG1y/EIFvM3fNhxJsb93vX6ce7PAcMPYWbWriI KnCa9DTy0U9zvwImuVO8XBQdDgR4rExFL2/AzCB/W4lZXnrMfCoPkvyfdovKdH5prRMHi387PaH/ FXaU40yXieclB6YHIuCDvdazxMOjGibaJkaHUEN5W1zMeDuyuX0caDwhqsExTNOqaViTkoeGO80j WnKW7tmPdDf01zy0oJgsemc6riuK50hwqVnORhXg3RWUlYc+17F8Jigam+E0k5gB4xTJjtD5L5VD OnwEFVKo+SjcUcIXI++KI7QGFS0pnUOqMJL9mqzDVuf5O4zJRCKyR3tMeveYrkGglzlZlnC1eCbU gbYI20RRtdil0EOd+7lSphQLf8f4vb/lyVsHYkzkjSNRT6dCpmMfAG4RPd2o21Uf43ocBOBXMfMG UCdZMKzPDdqyrGTT++3VzdwWIxJ4ycprv7wyVHMVZjQ1MlLF0AHXIe4SCtQxiwmOKa61KaInhcmA H+THjwfPdsl96xEohUMGzhbAIBBF4iBFbrRuO/opajtssfVyaUAA3331f+2DVAjwRGFGIJ6hgy9X P8XXWIYTuUwWsxicKNXJ34JJ+qrZNQD6m4mx+FuN7rqmDB6qyOW08SZDvMqnnjPhCH0K59UIhnqA p+dfb0CjhK9fDimm+rgi8E9R2w0g7vu+7kdC5JMv0484Yq+vxmgu0doXHMxIIOhQmskJi1d7goGb GxeHiPSHixglhIRjWwWaRRHkl+xm8C8tYGbGPYrBxsN4I8ZospM/2i2X26nk0cq3nxALotq2xRpB pI8cNDHlOYKI9tSSIv9XSBmrS814NgEAz4X+R23omekqB86DvaeIb5h7veFgga//q+ASDBUw7klZ JhnumvUcXueshH1X8vuTKCKYYHogx9kXIGd2BA2lXO/yps4E6AYAbFoaD/XPoxhegfrA7KUM4+l1 hwyoSN1NjwbOI5lmflAjM4t4lFj2GsFp1SfmU9NYLKRTwPR2MSkv5cEmcjI+Xo50dghKlcqGuM1s BUkbZAoldDIpUasuDTj7T0L8+0nETxQXUuFcc4z9ki89rmyh/b15JJRbnNTtU/9xtNlBzAzCAUnc QWnuuFDliou+1BN5tQO3hqb0NZySHmgVy5B1N5yMUL5MyPzEqMrTXojs8+kaqCJrXOR2ZageEnnF fRH0vynog5pyEwOuAbcVarEJr5ApDJeXKRkmPd0UWpJ0qoS8/rAyr+FEEnZeVnBlMvEJhLXzYkt5 pxqIzRB491UFZQktNuzbOyBMAeqhUl1P7Hn5SIA6zgAO0gkBxqJ8D7iB0cZa2Fhbp0t6qSxKX1d9 U6yGqUK8f+98pFMnx8scrQimTjQXAq7rmGKTThFrnB6fR89tyL3v8bi/aC+1M1KNVouNSvJUJDYL moePHRAr4XtxjC3NZV4nxOydDawYwzJLKa9exYdb5qu/8DInntylxHnJCkkr0WR6xHlnRZf9NVM1 834yY3Mg274P4gNDytvSfXckdtkQS1LbzALfUuI34xYYzhhivVfYpx4TSDg9RxVc2LXVm6U1hkUP 5KrnP3kEMQlRLeBXXKe8RkJem9HTL6XAV66Z9ZeiYHoSZ8US1RBpnPkqAY5KR2BzZlHewDjZ+pBk AZUymjF3POZ+a9DoUiPqycFKXJWqRE9kbjJd8oP32z+w2cu7hDRRgE5yenEwJCNVieSbTeBdckz1 r5aDRugKl91Kv0ijwsUMI5NB0fDw+So1tqNu6gBG4WEQr+VwxQjet8OL38NR4p3ma1PDC7iL1Xav cPEouxc3RrFqMBP9EFLacoPIJCZf22zDti0w2ipEzv1Bve02aQbmjPoUUNQabYVIhvuypOtxY9zE lJj/4F2dYM4Rgo+EBQxPYtYWLqcQUVbpIpYG6Wm1hrGWGnbzGce0C/anfOBOUBlqfAKHk2MhC+Np DUtMMmR5QI5mRhRmux+CuhHNYAutNa+5XvRS8gI5En7Ff/NWCMf9tbFZhMQUciHcNzFjopbe7UJj 2mZrWvhQqQyYkRAVyV0Mp7CHLHZFbjmlWnNSnEGPPvMJQz8cLtTQmtHcZdArW64QnziEXwKvK4UE +S+SrYHDGugeiE+puf3/22oHv/ngPln1B/+jQSwjwmxe75HVijTzrrs0MUWXDx6jAt+L+2DkplLD xZmhAEjZ4/fuh2JPVhMQUktjcrBXHJHrH8qgypaihv7BDOin48/fYI495hQ5mL/22q0gT01uQq6T Z09oZar/MPK7EPvZuFbidq0EwvNSS7KyhGqo8buOj30gFdd/aAGoaRt/1a7v+O3LCvOhx5FLuXLU W4d1/ljnQ3DCE8ato0IrZ6MFYRs6v1dr8eojIzkHuv2VsqSFQtqpWwJI1qm/bYPAn4LmI57sTXvx hV1BXZJsAYeUK+BVwMNjU9wH2rtyLNkaPie14j+ZjwvLJA/t2puaEPoyKoKscppkZw/v9yOdgvos r4Jho1sulKsNAPXeysMVpoUYso531x8SI5+uqOsQvTZGXPljkFyK8FhaBxI5AlHUsFDgHiBdCA7k 2Z7gC5QIuRFa4z9/EnUHe2GVaQGSocEtBu16RlCtkttXOl7xKbnONWJiw6OLpL2H0cHDEPWlw3k9 C8EtKtQ1v+go6V/HClGTzWrVxgeXN+53zVrWV+1bYw3QKLkwj/LB86RCK+/NaSJb3SnqADRMbLMg 6JSsDt2Jk4c+IMcbLbvaoQZgeuoulHCTNZ/pdB/j9GI4ClbIkBe1eupKXYt3PWBE3r0HFzWRlNIO o0YDvmv/HsxkZZeGNa52OE+beMtirGQmDqaOgh/kQuAL/J5vq1k6lxSouEFoX1qq5cHw9vi5eVae 0Me9X8MOu/Reyo04idXM+uVoztxk5ZEVSBV0nrij0mCmd5apFTYAUoIBMKr8a+j+10i1JRc2/ypA CuO8h46+s8pT955GhwDlnUIBBM5DOVDEuDuzjmdWrEGwiHJbJAzHfp3r+ANPnkPPxQdkFfY6Hhxu a4LhzyAJCeaYbU3NuRi7X/x43NJwgbSJsPgI/aC7xSPAvL3wIAY7fOF5267tTWwBViRwAs4t8gko UPA+cWiXvTH4dANA+7ZUi9VCJ3m8vK5UCyyyZHlq83FwxbOOdlxjx6wh/xWjIBzWjWLc91FWCvfU bwhS0Rkvp4lLife+Vsj9e/0O+oB+NMNSX8zDgkPjdqxEN4T8GRSgCa+hi/66iO+qf4UVavyylZQL vCfTrF0z5u5GntjpNWs8LWCK3EHj+o7+BrjlgDVd0X/uREUsj7fxpuDsGipRqi+J7u54P/c8CLpz FRrjFGwkvW9dCfIrs6to83AnV1HGp/7UhpDl2Y/UnNqCNR3B8KA41dYDqPmGv/j+8Eq9JE+LzCWh qQwNYgCxM4DZ0FBLd7+qEPPaqqsBgbICa+3IpOqhWWHOz0924FyMNJ6ylMwOfD4pmuwHQDotGjRX Fe0WcvPAMFrFZ7dzPqkyGQQeu+xemyrM4wmGv4kzWZ8HumxJgQF2rgqOAnuj/RvgbMyjpsZgLN5H XyE+bR91qY4m2BfHiB2HyJJjb8ro1U3XTlo5/yawz2R118JGBA3EMVvToZ0N0g7DngMpYhA64bD4 I0Kvje0R6rl9pPtIatFkFJ6W2VEwgbZudErGDUizZETXIa+25wFjAAfTH4FsTD0AE27hPOV6AbOE 9DEXWmkYILOyDoLdJSdLBBSBRmI+KTzdhWuaDb4yl8f6+Qv27kfXxbx+aRTRCKinvEG2zBmPouJE aoPSxH8sVTyTmCAuBvJ7+0jQTTmdouMgFnszYZtPvbBdnDgMlFOttRyWYptNRm3B1MBE4tqIL/PT uM5aPYvNsN1xsReN9keY5Mlfo31e8fC6MjN7to/3hAFy2ad+0DyODbXGuLXfKIQaKUX3PD86SkWa rwCsjTqFVrh+CRYQnY2A2w8ucVgJxLSDienRplhpyoxO685wOfeuPd8VkUQgm+ajbNOKZOuHSSKp Iasp/wxDnKa/NQ67U5fmzeTtbcXijzD21lNcn6iXOOnZP0rtdTn+SLMaEG8kRHMdJGiGFcLRO6KE XTJetOLnIN2xGCs1rN3yI5Q1sdFj8HwmJfprCrr9pLaL64iM7EQAkgt/rPl0sfEYEnT6+AJoc0Ep +Bxv0Z2WndbSNmUVP33cTi5N5mE0jZbqicKljJh1rxqSBzTzMO46sMaMjnzwN3b4UqG6lBe2jLEn f52w7xRiUuFZ9TFucMmNrAvjiogTnrc/nor7J4jEf6Gg6UJnsdgg4I+zlIB1B39Tgc67c3notWs8 81Z6ZemkJaisTPB0vO6YYQ+MwCYf/JM2CHv40M1sT3xT4BhQT9zt7TA+VkBCRL+UbIJqPo2NQ0zC EeUI9WWoAsRY4G9lIs3JrvUNdAHhQu9Byf2ZbyEtAPZk3Ynn3GX5CgJMVcBZcU1gDNEZ/+NMAOnt ggV0XiIzCxE8/tJ2ROFIonsvJ5DYJ91XH6bNJSL5cMHR0bgieLkzwd2njOoCByzwShbyHjMbbi/x cYqPpFP+60gFJMeGyfI8JMSKxNKfEFg/2od5PZjetE5V5Cw1oWrvoNnJdWTSN0+V4d5bNZVlAPPP kiUq9KJiIhFx17bP7fWFYDJf4pP1fEjll/drjdGgUg3r58AgtNY8o4ZiRwuWgtGReIq9xpjUn5lQ VMtzK8sgAJb0gpAHrzSDop5datztxVNkyPnmC16NjCWhrn2VwfUCxBwTn+ZfucWQqZ6+whvhcmG3 cYIKgtgwIkRwAhEPnb19EaJh/i7q/fHKthbgaRUp72jRm93+Dsk35s6CbCoEVEM4j7MrWg3eF119 iC/jkNLO5aHm1qCU5E9cVpIgufgdRaQN6UAbaVDIZCZBLaJkeebQccIPSSR++NxyjqO4smWI3DWZ KZLb87y/xkzF9eDzY9MqJpniGyLq9Nm+NYl/Y2md1hb2W4Fg7SJa//7Azozw8Z+1vtIbJAu8r6Vm RNNwnqz7ofjuMJGE2/wNFqHwSZTJjaHr3qkoBeEWX/FBFf4rs7cgc8MXfov7tUHXlA4w0bH3cAha VmKNlxPBP9Uv/PVmAwIM9bLw8HOKti6HrwWo0ufILhRr0qmtJFlk9jPE6UtsckDJ7Vt4SqxQHvCr QbO4x/yKsjgiTobUIAXuthSvihh62h8Fy/FHreGujuX4mKEt/uoRIQF4xrZMWavCk2isNqsk1Gzt 65aEtN3d7K1DTaOLturNE4YPC8Rs4+iDRiNhqStyEtuumPYXmKXKo9g8y9Sz+POoEP4cXrSe29cT QmeUbD5rz6ReAPZyOBJ0RHE8FzWNqxiTEqdu4V68E+dRIqf1a3MpmwGpnQwEc59L5e+RqOcIkiWG gWQQm8bPMMImzqvnWTYcLtnp0NFpzcDory6MoeY5dMiXQb/ys7ULeQEa4Pz1YW1DoK24lidkYy0B 9CmFdC09ElCECXf2KKmwLeWT765/5EnoGX/SRB0hho2EMoFAhdTbLGxDwZ3jg5o2fA2jIrYWemoh v2qFAnKk3Plr7MAHgw3gXKXI8uaXZ4ovaEIrs26Mh6Qp0gKUXHHxdykxfmatgKoRMhl26nA4lb7t gq4WqO84BiT5JADZkIk3sVveigpzcrx1yeKlprQOJb/Ld9oEUhrZ25yYEFmIdknJPg5K/AtwDQzV M3CgvnQm5iRxHcsu3ICLdsfO47orKrsjFVzlTRsr0ubBinZAt3iDj3Q8zdiK+ev0vLxmLz3qmAm9 oxQUaQXjbJcFTawsamA52d6rmuvvXNTJOeYhBU1fkX10p9NoJA6anj2WzdYmaKHn0tZEr6Lsopz8 FYQyaYY21XMMg99ENzicc95nwvaND8nN29xFtBHnWC7P2ShoBSP0+lnDWMNxNPycvdAQW+dwC2Rc tc7ExstF4HFqXEM4sFY9CHKkVnzqubea2VQiVNL/0TWtHPo7b7NzMD8cHtZsiKKh5yyz/IRP0GUM CNWlDCX2OblyvKkpY7I3uvD4Fb5bfMz9v/WEejKYr459y/QKZdKe3/K+5DfTIzu0yL+GSKlvPqxM wAaf4dVlxlPzCCVfvafT1XjSoeTdk5jz5Le7OMi0g/sr2UaZE/8RxUqOgOx9rbEngNdRdL9TSQDr LsjpUbQw+naoL8u/PmTJpwE586+AOzmgsVmG1DG7IgzE/k8B7AaPZgJCkfgMtjGgNRcsIhw8nyi+ Lbq9y6a6ReQwGHQNn+T+b0j+PG78HyOf/6+yBesO3pqX+tnHqOlHKaB9v+bhQHC1FmPNNn2FkbGQ dTzwr6phwJoAnYR+XQkSO+UA1hRO4SADyuUhAHlhTcGd8rWwBiQKiA+RMbrF0iOZ1owLpkYBCUao kMjX+C2efmSjFVsQvE6EtjjkoBZRIM6nyo+7eqJwS/Cy1zgh0wwr06wnm0UUfecwk8D3VZslnXak +dmgMxZ2vZZXdo1t7y9/FbdukDbLo5qzZJTH8070GCywo3xkFc1oYRNF0CsgCGSRywd12kv7QEFM JnBdmDaW+1D5g0N+tNc92cOgK3Ulax1CbCvFU8gUDOTgVmNjbvOknXT7rSpdZWCFETiNSZI9kUFM jgfnuc8Tvc5HdO9VAPAWabI/osfyqusm36wl+Q5HW0/q3Nsdm2X/E5SB9OE7trMzGBahsgPPM7hL qZC3bsmn6+2RZ5WEqFD8d9oxGACaJd32b9figFGur5z6XPqb9DcQVNpzyCNj9evkmIpm++Co6P0i +znnKqdl6ezHuBeJ+tHoK85htmycyJXAFb+giwsXKfgb9/pxwv0YpOJFJgIAHIKUJpqUOWF1X1El 98u2lBgBU+pMqbdSPYVe6JSkr7pedXerduFUS8RUcz9XWrtj/KgGBlOHp4TypMGTGrhsAxkbcerQ aU4oaJsZagJNZ1DTmVfGGteG2WWjXVxEkQ0HuZE2AW6s/7zCMzGLvqUV0IOvtAbXopwtj7UE9cDD CI8EmcvRb1JCypCKNe/1snHO3OIqYLR49H/7VHQtOYtIUxN9vNUW4+tXQMN4P9eu37r6SfFrLAOb JwBwkDwBAwqK4TTDMOMjwz5t7egGZzHFEFXI46sslw6ggVTif7V7OMxCcztl+ncU1SuEt6Z/whEy KEhjKYXiY3jus0D6LVtTZqTF2ehL1405MpgYrLl5UO3DZ2KMop+gQyz5Ar/p7JTVwW4PRKbwYo1/ /SaDrrLuiSO1Cg4eSNLiDVgV77cUVQI1WlutEclez7ELjlyDoIp2qTJ1vw03QNDPv+BjmH+92YYI Q28p3kTYrmOCuzTMwDyZeGCOl+VunkYj5395u6rGcRN3tX41fKDEpUIMnpAmZILl5Tl/vdb9DwIv 4Y60CumK1cVQF4llaj2U9MkyOUG5yEcKgGKz0Xkmmy4jeToBlgwOSpssyoZD98VW9VSfVAk0aw0+ pz1ra2d0uKu+g1MlbYpx/SmLRJquo0Tgo6zFZlQLiw0m5PFCoya5E33FY61dTB+GodfJ1LiUZ0tp wrFJRylP2ldoK91uNqESnDO4jFr5inppK2lBujbAO4twhDRigc6IOkNkwDMtbC14Ia+bihmVSQWq m4A2+OFYPEB1Scbe8H4cyIKtT5xuBldgfdAdwUMfzK2JK18teUo0xDY2zueLxeLmV1JEGi7+n+Sn HmuMkl8UHMGGFjxyLX8SRq6PrtCpSbbpedp5MkF2KqNb7DqYZ5smiOb4oECr6OB1nQpXWJdET0dH 3DHuth9C61QEZB0Zuuh+OCdsbrCLvrWMMBSAq/lJG5MHd+cYy0H+qy2/XofdznnNw7C4yMnfO4g8 EYNYP7UsDs3M7nbd+ZTCQUHayqF1HHR9xm68fBwGk9R4IiJ97dT7zcDFja7sVCekwNsOtbeVP27y kf2vYoFF4IPIdXsYUIW0V5a/OAqn0T9rUCcscCvj6Bxun3BSUGutJMsXjzhUFpgtc24lt4g/vsaK COjL+db5LW5kDtkOhKA2kmpgnSA1YAGyY++xxxoxloquW/MIk1iJKtjVMdJfaNMRbgvfk2KqGlFX EY4wVtAcFAFU7R3RztDpveChWptYo9uhbOJ3MLE/S5Kl+QnW+NqrkamKJJna50ZdvOoWdSH8jwcl jZaom6wTqJVJzJG8+ROpFw8ZmUllwhzJOjgk5sWqjeJ7ztWVM/4StC0ds1UufyGQRQCi3B1wntKL StRD0Ede5xyID7A1zYJlY+nYaVVABNy5TiqNHbZLkV1YS8viG1a8sLpUYfgae/NGiSV+ZPWT+9nX hcegrs/X8ajO34vtWoGUCEg0KeumWe7wrsA3MHLkzBFwDLaKgToOwt7IrXXhV5Yz2URx8+mnqo6N MsPBak7CuII05rEjbJ/ZnHKHpyjuQ55+yCMXeXce3EojUMzRkx2nbtQTxK4h0CdV8YbEPJlFIBLi gVM31sMVoh3xDEbp+oohbkeSWrcy4ZtMxYgKhe6Npi/12ratS0+Q+7n9FM+frGERapaeHO+Mm7Hs tNqqxZFju5gQFPch+DW248nBSxqrgnGgRWnBZnLTNeTzyqaG8wU2B/SdfZ6B3+BO62+8K/wU2Faa LaJ26lNoAZlAo33qQ/KY1x1hEHHHXVT7sbO9k29zrjcZPE3y2jiRaVzdOzDueRZEJF5uCNPQpyW1 wmV/B4OLZe4ZiQLK74NCzNHDNkfnX3EnBXD08xAQAe6WqbHO/c41pL9FKxUGB6uUHd7qR4yCRRCV milQtvf8wAxsVQ2kKkhaPdf8zuQgM/8mP3Ni0SHjU0ygJDn/PAjc4b+m44NoLvWzTTxZBK8h2VTK m321CYgGJ9jckK8uAMnyVKJRPrNiJe/vn7BuvbRsJG3cfdGirX8HhYjUQb9Q5fMWcfwhq/kNxA3G gWROfBdW4aBLcfJf+4YZsPXmlIDqFeuEIAI9TwaeEZ6o+e88d1Lo2fsV8QXq0TgD32TSxP5c39YV KG9RutbxafMNpRpebRrCqIIe8neKG+8eJf8k0qPbLui4t16WLxam4Xiq8rm9ZmyEjMIF2x43YbTX skOsvrEr0u1IVyjz6HsUY+fpO+z7+w9TazlsX2JZXzOWMxLjhDH/PV4XUZgdAzwPhbWyUb5TsG4M dzrkuj0CmNWs7ZaDMelNT1zyMCSroSYHUhla5nAmodPYvwRuXjOdVxnyRQF8Gn4JhxyIz/KIGLdh /vj6SFAgJyaqoVIB/KxtWrjEYqYXOhl3upsF8dE1yMbFvlCiWqBD0FqAtxUehWY0w0pLRoqcV2nm NWCgltASWRry7pXAhiDkiQ4w5i4wGjgV/IifqIw0jKeJQ7hZ4pyPsteyK1fRWP/mRJpcXyetNsx0 HI4XFJPvq94S/omTLAd2U6EuphzEnIM7RoPVZsHLv9vuRRR9D4qxVwT8h28Osiw4HTBEN3wMrXfS d6u7QdtrG23W9nH4kKJNpoEpC2WGSNHPgzggta6OaquVvyfFKpM+qiOnN8cSZYCLhanA0lF03nSD 3r7RSTSsePFkZNgG0YRJZtRbh8phBA6VI4yUQBOVRXzB6xK6At6Av+Qa8OD79YfpAfV8NV8GV49U PdlkDnVYMLbVw6SDKnOdkUndSBViCQqodeQdOXlMP/yIKUyMF5Cv2VVac4EikorD9+qL1oI3nLjL KQZerg81NeEIZ4Q4vdsRYP3q//qQjuQVTdxjsjsRitRsX+sBEr8Mxq8eKuHC9DXNzATDx3EinW3s oKXgDsCM8OkF3mafuQNlTCZOoQBb2LZMWpQWIAxIgLlGsWYvzGJkb6Zd7crpDSP2ECYn5l9kHWJJ nI8tv3Rh76r2gClOuAfANKONjFIDGYBRYl/p+Dad4rM8kTOp61ewAgYOoTDFpQTEdc8sFuvE54LK FXRhloiSwUUfrR6UvGaVCCoq29nH1U9P+unlC/SzUIAZ9qtpFN79UkdZrkircRmKzmQd9QfXkSTG 4K/HX2iEeUAeKPotwaHljFz/GfY04Hyy9O2nnjbQ6u1jy1zQACp2hMOq6fj7kx33cPkT2NwVYyeA +BQrhdg5ZH0fUcUBWIJfg1Wobod2mWQ9bjE/uyRGJBuY8g6u5bHGb3DcO5lPiL2N/L8kil2b4B3e aTckYdEHfn+drKmSx2P0GwAtfvIF7DZxpyldrbrsPi8JyFNVWS8SwNvvF0qLM2cjcxrmq959pzZA AqTM4SDb9Lr82wo4wPTgUHa96wuWFS9vpExFmsoyaF5WwsHyeHsvC41xDJIxAKIiYNmLRRylSDJj vKV1E/3dhzs424GE2ENNaR/2XNB0U5bcx8nI0wBW/WMGuCitIxkuxvgEpIZUhHktd30l9TsXF2Y= `protect end_protected
--======================================================================================================================== -- Copyright (c) 2015 by Bitvis AS. All rights reserved. -- A free license is hereby granted, free of charge, to any person obtaining -- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'), -- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions: -- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation -- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole -- - The License file may not be modified -- - The calls in the code to the license file ('show_license') may not be removed or modified. -- - No other conditions whatsoever may be added to those of this License -- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- VHDL unit : Bitvis Utility Library : bfm_common_pkg -- -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; use std.textio.all; use work.types_pkg.all; use work.string_methods_pkg.all; use work.methods_pkg.all; library ieee_proposed; use ieee_proposed.standard_additions.all; use ieee_proposed.std_logic_1164_additions.all; use ieee_proposed.standard_textio_additions.all; package bfm_common_pkg is -- General declarations related to BFMs type t_normalization_mode is (ALLOW_WIDER, ALLOW_NARROWER, ALLOW_WIDER_NARROWER, ALLOW_EXACT_ONLY); -- Functions/procedures impure function normalise( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector; impure function normalise( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned; impure function normalise( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed; -- Functions/procedures impure function normalize_and_check( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector; impure function normalize_and_check( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned; impure function normalize_and_check( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed; procedure wait_until_given_time_after_rising_edge ( signal clk : in std_logic; constant wait_time : in time ); end package bfm_common_pkg; --================================================================================================= package body bfm_common_pkg is constant C_SCOPE : string := "bfm_common"; -- Normalize 'value' to the width given by 'target' and perform sanity check. impure function normalize_and_check( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector is constant name : string := "normalize_and_check(" & val_type & ": " & value_name & "=" & to_string(value, HEX, AS_IS) & ", " & target_name & "=" & to_string(target, HEX, AS_IS) & ")"; alias a_value : std_logic_vector(value'length - 1 downto 0) is value; alias a_target : std_logic_vector(target'length - 1 downto 0) is target; variable v_normalized_value : std_logic_vector(target'length - 1 downto 0); begin -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & msg, C_SCOPE); return v_normalized_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & msg, C_SCOPE); return v_normalized_value; end if; -- If value'length > target'length, remove leading zeros from value if (a_value'length > a_target'length) then v_normalized_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE); end if; if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE); end if; -- If value'length = target'length elsif (a_value'length = a_target'length) then v_normalized_value := a_value; -- If value'length < target'length, add padding (leading zeros) to value elsif (a_value'length < a_target'length) then v_normalized_value := (others => '0'); v_normalized_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE); end if; end if; return v_normalized_value; end; impure function normalize_and_check( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned is begin return unsigned( normalize_and_check(std_logic_vector(value), std_logic_vector(target), mode, value_name, target_name, msg, val_type) ); end; impure function normalize_and_check( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed is constant name : string := "normalize_and_check(" & val_type & ": " & value_name & "=" & to_string(std_logic_vector(value)) & ", " & target_name & "=" & to_string(std_logic_vector(target)) & ")"; alias a_value : signed(value'length - 1 downto 0) is value; alias a_target : signed(target'length - 1 downto 0) is target; variable v_normalized_value : signed(target'length - 1 downto 0); begin -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & msg, C_SCOPE); return v_normalized_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & msg, C_SCOPE); return v_normalized_value; end if; -- If value'length > target'length, remove leading zeros/ones from value if a_value'length > a_target'length then v_normalized_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE); end if; if a_value(a_value'high) = '0' then -- positive value if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE); end if; elsif a_value(a_value'high) = '1' then -- negative value for i in a_value'high downto a_target'length loop if a_value(i) = '0' then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-sign bits in the extended MSB. " & msg, C_SCOPE); end if; end loop; end if; -- If value'length = target'length elsif a_value'length = a_target'length then v_normalized_value := a_value; -- If value'length < target'length, add padding (leading zeros/ones) to value elsif a_value'length < a_target'length then if a_value(a_value'high) = '0' then -- positive value v_normalized_value := (others => '0'); elsif a_value(a_value'high) = '1' then -- negative value v_normalized_value := (others => '1'); end if; v_normalized_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE); end if; end if; return v_normalized_value; end; -- Normalise 'value' to the width given by 'target'. impure function normalise( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector is constant name : string := "normalise(" & val_type & ": " & value_name & "=" & to_string(value, HEX, AS_IS) & ", " & target_name & "=" & to_string(target, HEX, AS_IS) & ")"; alias a_value : std_logic_vector(value'length - 1 downto 0) is value; alias a_target : std_logic_vector(target'length - 1 downto 0) is target; variable v_normalised_value : std_logic_vector(target'length - 1 downto 0); begin deprecate(get_procedure_name_from_instance_name(value'instance_name), "Use normalize_and_check()."); -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & msg, C_SCOPE); return v_normalised_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & msg, C_SCOPE); return v_normalised_value; end if; -- If value'length > target'length, remove leading zeros from value if (a_value'length > a_target'length) then v_normalised_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE); end if; if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE); end if; -- If value'length = target'length elsif (a_value'length = a_target'length) then v_normalised_value := a_value; -- If value'length < target'length, add padding (leading zeros) to value elsif (a_value'length < a_target'length) then v_normalised_value := (others => '0'); v_normalised_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE); end if; end if; return v_normalised_value; end; impure function normalise( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned is begin return unsigned( normalise(std_logic_vector(value), std_logic_vector(target), mode, value_name, target_name, msg, val_type) ); end; impure function normalise( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed is constant name : string := "normalise(" & val_type & ": " & value_name & "=" & to_string(std_logic_vector(value)) & ", " & target_name & "=" & to_string(std_logic_vector(target)) & ")"; alias a_value : signed(value'length - 1 downto 0) is value; alias a_target : signed(target'length - 1 downto 0) is target; variable v_normalised_value : signed(target'length - 1 downto 0); begin deprecate(get_procedure_name_from_instance_name(value'instance_name), "Use normalize_and_check()."); -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & msg, C_SCOPE); return v_normalised_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & msg, C_SCOPE); return v_normalised_value; end if; -- If value'length > target'length, remove leading zeros/ones from value if a_value'length > a_target'length then v_normalised_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE); end if; if a_value(a_value'high) = '0' then -- positive value if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE); end if; elsif a_value(a_value'high) = '1' then -- negative value for i in a_value'high downto a_target'length loop if a_value(i) = '0' then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-sign bits in the extended MSB. " & msg, C_SCOPE); end if; end loop; end if; -- If value'length = target'length elsif a_value'length = a_target'length then v_normalised_value := a_value; -- If value'length < target'length, add padding (leading zeros/ones) to value elsif a_value'length < a_target'length then if a_value(a_value'high) = '0' then -- positive value v_normalised_value := (others => '0'); elsif a_value(a_value'high) = '1' then -- negative value v_normalised_value := (others => '1'); end if; v_normalised_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE); end if; end if; return v_normalised_value; end; -- Wait until wait_time after rising_edge(clk) procedure wait_until_given_time_after_rising_edge ( signal clk : in std_logic; constant wait_time : in time ) is variable v_remaining_wait_time : time; begin -- If the time since the previous rising_edge is less than wait_time, -- we don't have to wait until the next rising_edge, -- only wait_time minus the time already passed since rising_edge if (clk'last_event <= wait_time and -- less than wait_time has passed since last event clk'last_value = '0' and clk = '1' -- last event was a rising_edge ) then v_remaining_wait_time := wait_time - clk'last_event; -- Wait until wait_time after rising_edge else wait until rising_edge(clk); v_remaining_wait_time := wait_time; -- Wait until wait_time after rising_edge end if; wait for v_remaining_wait_time; end; end package body bfm_common_pkg;
--======================================================================================================================== -- Copyright (c) 2015 by Bitvis AS. All rights reserved. -- A free license is hereby granted, free of charge, to any person obtaining -- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'), -- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions: -- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation -- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole -- - The License file may not be modified -- - The calls in the code to the license file ('show_license') may not be removed or modified. -- - No other conditions whatsoever may be added to those of this License -- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- VHDL unit : Bitvis Utility Library : bfm_common_pkg -- -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; use std.textio.all; use work.types_pkg.all; use work.string_methods_pkg.all; use work.methods_pkg.all; library ieee_proposed; use ieee_proposed.standard_additions.all; use ieee_proposed.std_logic_1164_additions.all; use ieee_proposed.standard_textio_additions.all; package bfm_common_pkg is -- General declarations related to BFMs type t_normalization_mode is (ALLOW_WIDER, ALLOW_NARROWER, ALLOW_WIDER_NARROWER, ALLOW_EXACT_ONLY); -- Functions/procedures impure function normalise( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector; impure function normalise( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned; impure function normalise( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed; -- Functions/procedures impure function normalize_and_check( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector; impure function normalize_and_check( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned; impure function normalize_and_check( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed; procedure wait_until_given_time_after_rising_edge ( signal clk : in std_logic; constant wait_time : in time ); end package bfm_common_pkg; --================================================================================================= package body bfm_common_pkg is constant C_SCOPE : string := "bfm_common"; -- Normalize 'value' to the width given by 'target' and perform sanity check. impure function normalize_and_check( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector is constant name : string := "normalize_and_check(" & val_type & ": " & value_name & "=" & to_string(value, HEX, AS_IS) & ", " & target_name & "=" & to_string(target, HEX, AS_IS) & ")"; alias a_value : std_logic_vector(value'length - 1 downto 0) is value; alias a_target : std_logic_vector(target'length - 1 downto 0) is target; variable v_normalized_value : std_logic_vector(target'length - 1 downto 0); begin -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & msg, C_SCOPE); return v_normalized_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & msg, C_SCOPE); return v_normalized_value; end if; -- If value'length > target'length, remove leading zeros from value if (a_value'length > a_target'length) then v_normalized_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE); end if; if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE); end if; -- If value'length = target'length elsif (a_value'length = a_target'length) then v_normalized_value := a_value; -- If value'length < target'length, add padding (leading zeros) to value elsif (a_value'length < a_target'length) then v_normalized_value := (others => '0'); v_normalized_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE); end if; end if; return v_normalized_value; end; impure function normalize_and_check( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned is begin return unsigned( normalize_and_check(std_logic_vector(value), std_logic_vector(target), mode, value_name, target_name, msg, val_type) ); end; impure function normalize_and_check( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed is constant name : string := "normalize_and_check(" & val_type & ": " & value_name & "=" & to_string(std_logic_vector(value)) & ", " & target_name & "=" & to_string(std_logic_vector(target)) & ")"; alias a_value : signed(value'length - 1 downto 0) is value; alias a_target : signed(target'length - 1 downto 0) is target; variable v_normalized_value : signed(target'length - 1 downto 0); begin -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & msg, C_SCOPE); return v_normalized_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & msg, C_SCOPE); return v_normalized_value; end if; -- If value'length > target'length, remove leading zeros/ones from value if a_value'length > a_target'length then v_normalized_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE); end if; if a_value(a_value'high) = '0' then -- positive value if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE); end if; elsif a_value(a_value'high) = '1' then -- negative value for i in a_value'high downto a_target'length loop if a_value(i) = '0' then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-sign bits in the extended MSB. " & msg, C_SCOPE); end if; end loop; end if; -- If value'length = target'length elsif a_value'length = a_target'length then v_normalized_value := a_value; -- If value'length < target'length, add padding (leading zeros/ones) to value elsif a_value'length < a_target'length then if a_value(a_value'high) = '0' then -- positive value v_normalized_value := (others => '0'); elsif a_value(a_value'high) = '1' then -- negative value v_normalized_value := (others => '1'); end if; v_normalized_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE); end if; end if; return v_normalized_value; end; -- Normalise 'value' to the width given by 'target'. impure function normalise( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector is constant name : string := "normalise(" & val_type & ": " & value_name & "=" & to_string(value, HEX, AS_IS) & ", " & target_name & "=" & to_string(target, HEX, AS_IS) & ")"; alias a_value : std_logic_vector(value'length - 1 downto 0) is value; alias a_target : std_logic_vector(target'length - 1 downto 0) is target; variable v_normalised_value : std_logic_vector(target'length - 1 downto 0); begin deprecate(get_procedure_name_from_instance_name(value'instance_name), "Use normalize_and_check()."); -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & msg, C_SCOPE); return v_normalised_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & msg, C_SCOPE); return v_normalised_value; end if; -- If value'length > target'length, remove leading zeros from value if (a_value'length > a_target'length) then v_normalised_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE); end if; if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE); end if; -- If value'length = target'length elsif (a_value'length = a_target'length) then v_normalised_value := a_value; -- If value'length < target'length, add padding (leading zeros) to value elsif (a_value'length < a_target'length) then v_normalised_value := (others => '0'); v_normalised_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE); end if; end if; return v_normalised_value; end; impure function normalise( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned is begin return unsigned( normalise(std_logic_vector(value), std_logic_vector(target), mode, value_name, target_name, msg, val_type) ); end; impure function normalise( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed is constant name : string := "normalise(" & val_type & ": " & value_name & "=" & to_string(std_logic_vector(value)) & ", " & target_name & "=" & to_string(std_logic_vector(target)) & ")"; alias a_value : signed(value'length - 1 downto 0) is value; alias a_target : signed(target'length - 1 downto 0) is target; variable v_normalised_value : signed(target'length - 1 downto 0); begin deprecate(get_procedure_name_from_instance_name(value'instance_name), "Use normalize_and_check()."); -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & msg, C_SCOPE); return v_normalised_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & msg, C_SCOPE); return v_normalised_value; end if; -- If value'length > target'length, remove leading zeros/ones from value if a_value'length > a_target'length then v_normalised_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE); end if; if a_value(a_value'high) = '0' then -- positive value if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE); end if; elsif a_value(a_value'high) = '1' then -- negative value for i in a_value'high downto a_target'length loop if a_value(i) = '0' then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-sign bits in the extended MSB. " & msg, C_SCOPE); end if; end loop; end if; -- If value'length = target'length elsif a_value'length = a_target'length then v_normalised_value := a_value; -- If value'length < target'length, add padding (leading zeros/ones) to value elsif a_value'length < a_target'length then if a_value(a_value'high) = '0' then -- positive value v_normalised_value := (others => '0'); elsif a_value(a_value'high) = '1' then -- negative value v_normalised_value := (others => '1'); end if; v_normalised_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE); end if; end if; return v_normalised_value; end; -- Wait until wait_time after rising_edge(clk) procedure wait_until_given_time_after_rising_edge ( signal clk : in std_logic; constant wait_time : in time ) is variable v_remaining_wait_time : time; begin -- If the time since the previous rising_edge is less than wait_time, -- we don't have to wait until the next rising_edge, -- only wait_time minus the time already passed since rising_edge if (clk'last_event <= wait_time and -- less than wait_time has passed since last event clk'last_value = '0' and clk = '1' -- last event was a rising_edge ) then v_remaining_wait_time := wait_time - clk'last_event; -- Wait until wait_time after rising_edge else wait until rising_edge(clk); v_remaining_wait_time := wait_time; -- Wait until wait_time after rising_edge end if; wait for v_remaining_wait_time; end; end package body bfm_common_pkg;
--======================================================================================================================== -- Copyright (c) 2015 by Bitvis AS. All rights reserved. -- A free license is hereby granted, free of charge, to any person obtaining -- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'), -- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions: -- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation -- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole -- - The License file may not be modified -- - The calls in the code to the license file ('show_license') may not be removed or modified. -- - No other conditions whatsoever may be added to those of this License -- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY. --======================================================================================================================== ------------------------------------------------------------------------------------------ -- VHDL unit : Bitvis Utility Library : bfm_common_pkg -- -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; use std.textio.all; use work.types_pkg.all; use work.string_methods_pkg.all; use work.methods_pkg.all; library ieee_proposed; use ieee_proposed.standard_additions.all; use ieee_proposed.std_logic_1164_additions.all; use ieee_proposed.standard_textio_additions.all; package bfm_common_pkg is -- General declarations related to BFMs type t_normalization_mode is (ALLOW_WIDER, ALLOW_NARROWER, ALLOW_WIDER_NARROWER, ALLOW_EXACT_ONLY); -- Functions/procedures impure function normalise( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector; impure function normalise( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned; impure function normalise( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed; -- Functions/procedures impure function normalize_and_check( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector; impure function normalize_and_check( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned; impure function normalize_and_check( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed; procedure wait_until_given_time_after_rising_edge ( signal clk : in std_logic; constant wait_time : in time ); end package bfm_common_pkg; --================================================================================================= package body bfm_common_pkg is constant C_SCOPE : string := "bfm_common"; -- Normalize 'value' to the width given by 'target' and perform sanity check. impure function normalize_and_check( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector is constant name : string := "normalize_and_check(" & val_type & ": " & value_name & "=" & to_string(value, HEX, AS_IS) & ", " & target_name & "=" & to_string(target, HEX, AS_IS) & ")"; alias a_value : std_logic_vector(value'length - 1 downto 0) is value; alias a_target : std_logic_vector(target'length - 1 downto 0) is target; variable v_normalized_value : std_logic_vector(target'length - 1 downto 0); begin -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & msg, C_SCOPE); return v_normalized_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & msg, C_SCOPE); return v_normalized_value; end if; -- If value'length > target'length, remove leading zeros from value if (a_value'length > a_target'length) then v_normalized_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE); end if; if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE); end if; -- If value'length = target'length elsif (a_value'length = a_target'length) then v_normalized_value := a_value; -- If value'length < target'length, add padding (leading zeros) to value elsif (a_value'length < a_target'length) then v_normalized_value := (others => '0'); v_normalized_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE); end if; end if; return v_normalized_value; end; impure function normalize_and_check( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned is begin return unsigned( normalize_and_check(std_logic_vector(value), std_logic_vector(target), mode, value_name, target_name, msg, val_type) ); end; impure function normalize_and_check( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed is constant name : string := "normalize_and_check(" & val_type & ": " & value_name & "=" & to_string(std_logic_vector(value)) & ", " & target_name & "=" & to_string(std_logic_vector(target)) & ")"; alias a_value : signed(value'length - 1 downto 0) is value; alias a_target : signed(target'length - 1 downto 0) is target; variable v_normalized_value : signed(target'length - 1 downto 0); begin -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & msg, C_SCOPE); return v_normalized_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & msg, C_SCOPE); return v_normalized_value; end if; -- If value'length > target'length, remove leading zeros/ones from value if a_value'length > a_target'length then v_normalized_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE); end if; if a_value(a_value'high) = '0' then -- positive value if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE); end if; elsif a_value(a_value'high) = '1' then -- negative value for i in a_value'high downto a_target'length loop if a_value(i) = '0' then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-sign bits in the extended MSB. " & msg, C_SCOPE); end if; end loop; end if; -- If value'length = target'length elsif a_value'length = a_target'length then v_normalized_value := a_value; -- If value'length < target'length, add padding (leading zeros/ones) to value elsif a_value'length < a_target'length then if a_value(a_value'high) = '0' then -- positive value v_normalized_value := (others => '0'); elsif a_value(a_value'high) = '1' then -- negative value v_normalized_value := (others => '1'); end if; v_normalized_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE); end if; end if; return v_normalized_value; end; -- Normalise 'value' to the width given by 'target'. impure function normalise( constant value : in std_logic_vector; constant target : in std_logic_vector; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "slv" ) return std_logic_vector is constant name : string := "normalise(" & val_type & ": " & value_name & "=" & to_string(value, HEX, AS_IS) & ", " & target_name & "=" & to_string(target, HEX, AS_IS) & ")"; alias a_value : std_logic_vector(value'length - 1 downto 0) is value; alias a_target : std_logic_vector(target'length - 1 downto 0) is target; variable v_normalised_value : std_logic_vector(target'length - 1 downto 0); begin deprecate(get_procedure_name_from_instance_name(value'instance_name), "Use normalize_and_check()."); -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & msg, C_SCOPE); return v_normalised_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & msg, C_SCOPE); return v_normalised_value; end if; -- If value'length > target'length, remove leading zeros from value if (a_value'length > a_target'length) then v_normalised_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE); end if; if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE); end if; -- If value'length = target'length elsif (a_value'length = a_target'length) then v_normalised_value := a_value; -- If value'length < target'length, add padding (leading zeros) to value elsif (a_value'length < a_target'length) then v_normalised_value := (others => '0'); v_normalised_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE); end if; end if; return v_normalised_value; end; impure function normalise( constant value : in unsigned; constant target : in unsigned; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "unsigned" ) return unsigned is begin return unsigned( normalise(std_logic_vector(value), std_logic_vector(target), mode, value_name, target_name, msg, val_type) ); end; impure function normalise( constant value : in signed; constant target : in signed; constant mode : in t_normalization_mode; constant value_name : string; constant target_name : string; constant msg : string; constant val_type : string := "signed" ) return signed is constant name : string := "normalise(" & val_type & ": " & value_name & "=" & to_string(std_logic_vector(value)) & ", " & target_name & "=" & to_string(std_logic_vector(target)) & ")"; alias a_value : signed(value'length - 1 downto 0) is value; alias a_target : signed(target'length - 1 downto 0) is target; variable v_normalised_value : signed(target'length - 1 downto 0); begin deprecate(get_procedure_name_from_instance_name(value'instance_name), "Use normalize_and_check()."); -- Verify that value and target are not zero-length vectors if value'length = 0 then tb_error(name & " => Value length is zero! " & msg, C_SCOPE); return v_normalised_value; elsif target'length = 0 then tb_error(name & " => Target length is zero! " & msg, C_SCOPE); return v_normalised_value; end if; -- If value'length > target'length, remove leading zeros/ones from value if a_value'length > a_target'length then v_normalised_value := a_value(a_target'length - 1 downto 0); -- Sanity checks if not (mode = ALLOW_WIDER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is wider than " & target_name & " without using ALLOW_WIDER mode. " & msg, C_SCOPE); end if; if a_value(a_value'high) = '0' then -- positive value if not matching_widths(a_value, a_target) then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-zeros in the extended MSB. " & msg, C_SCOPE); end if; elsif a_value(a_value'high) = '1' then -- negative value for i in a_value'high downto a_target'length loop if a_value(i) = '0' then tb_error(name & " => " & value_name & " is wider than " & target_name & " and has non-sign bits in the extended MSB. " & msg, C_SCOPE); end if; end loop; end if; -- If value'length = target'length elsif a_value'length = a_target'length then v_normalised_value := a_value; -- If value'length < target'length, add padding (leading zeros/ones) to value elsif a_value'length < a_target'length then if a_value(a_value'high) = '0' then -- positive value v_normalised_value := (others => '0'); elsif a_value(a_value'high) = '1' then -- negative value v_normalised_value := (others => '1'); end if; v_normalised_value(a_value'length - 1 downto 0) := a_value; -- Sanity check if not (mode = ALLOW_NARROWER or mode = ALLOW_WIDER_NARROWER) then tb_error(name & " => " & value_name & " is narrower than " & target_name & " without using ALLOW_NARROWER mode. " & msg, C_SCOPE); end if; end if; return v_normalised_value; end; -- Wait until wait_time after rising_edge(clk) procedure wait_until_given_time_after_rising_edge ( signal clk : in std_logic; constant wait_time : in time ) is variable v_remaining_wait_time : time; begin -- If the time since the previous rising_edge is less than wait_time, -- we don't have to wait until the next rising_edge, -- only wait_time minus the time already passed since rising_edge if (clk'last_event <= wait_time and -- less than wait_time has passed since last event clk'last_value = '0' and clk = '1' -- last event was a rising_edge ) then v_remaining_wait_time := wait_time - clk'last_event; -- Wait until wait_time after rising_edge else wait until rising_edge(clk); v_remaining_wait_time := wait_time; -- Wait until wait_time after rising_edge end if; wait for v_remaining_wait_time; end; end package body bfm_common_pkg;
-- CDR with SERDES library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; entity cdr_serdes is port ( -- clocks clk160 : in std_logic; clk640 : in std_logic; -- reset reset : in std_logic; -- data input din : in std_logic; slip : in std_logic; -- data output data_value : out std_logic_vector(1 downto 0); data_valid : out std_logic_vector(1 downto 0); data_lock : out std_logic ); end cdr_serdes; architecture rtl of cdr_serdes is signal AZ : std_logic_vector(4 downto 0) := (others => '0'); signal BZ : std_logic_vector(4 downto 0) := (others => '0'); signal CZ : std_logic_vector(4 downto 0) := (others => '0'); signal DZ : std_logic_vector(4 downto 0) := (others => '0'); signal AAP, AAN : std_logic := '0'; signal BBP, BBN : std_logic := '0'; signal CCP, CCN : std_logic := '0'; signal DDP, DDN : std_logic := '0'; signal use_A : std_logic := '0'; signal use_B : std_logic := '0'; signal use_C : std_logic := '0'; signal use_D : std_logic := '0'; signal use_A1, use_A2 : std_logic := '0'; signal use_B1, use_B2 : std_logic := '0'; signal use_C1, use_C2 : std_logic := '0'; signal use_D1, use_D2 : std_logic := '0'; signal use_A_reg : std_logic := '0'; signal use_B_reg : std_logic := '0'; signal use_C_reg : std_logic := '0'; signal use_D_reg : std_logic := '0'; signal use_A_reg2 : std_logic := '0'; signal use_B_reg2 : std_logic := '0'; signal use_C_reg2 : std_logic := '0'; signal use_D_reg2 : std_logic := '0'; signal sdata_A : std_logic_vector(1 downto 0) := "00"; signal sdata_B : std_logic_vector(1 downto 0) := "00"; signal sdata_C : std_logic_vector(1 downto 0) := "00"; signal sdata_D : std_logic_vector(1 downto 0) := "00"; signal pipe_ce0 : std_logic := '0'; signal pipe_ce1 : std_logic := '0'; signal valid_int : std_logic_vector(1 downto 0) := "00"; signal lockcnt : integer range 0 to 128 := 0; begin serdes : ISERDESE2 generic map ( DATA_RATE => "SDR", -- DDR, SDR DATA_WIDTH => 4, -- Parallel data width (2-8,10,14) DYN_CLKDIV_INV_EN => "FALSE", -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE) DYN_CLK_INV_EN => "FALSE", -- Enable DYNCLKINVSEL inversion (FALSE, TRUE) -- INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1) INIT_Q1 => '0', INIT_Q2 => '0', INIT_Q3 => '0', INIT_Q4 => '0', INTERFACE_TYPE => "NETWORKING", -- MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE IOBDELAY => "NONE", -- NONE, BOTH, IBUF, IFD NUM_CE => 2, -- Number of clock enables (1,2) OFB_USED => "FALSE", -- Select OFB path (FALSE, TRUE) SERDES_MODE => "MASTER", -- MASTER, SLAVE -- SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1) SRVAL_Q1 => '0', SRVAL_Q2 => '0', SRVAL_Q3 => '0', SRVAL_Q4 => '0' ) port map ( O => open, -- 1-bit output: Combinatorial output -- Q1 - Q8: 1-bit (each) output: Registered data outputs Q1 => AZ(0), Q2 => BZ(0), Q3 => CZ(0), Q4 => DZ(0), Q5 => open, Q6 => open, Q7 => open, Q8 => open, -- SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports SHIFTOUT1 => open, SHIFTOUT2 => open, BITSLIP => slip, -- 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to -- CLKDIV when asserted (active High). Subsequently, the data seen on the -- Q1 to Q8 output ports will shift, as in a barrel-shifter operation, one -- position every time Bitslip is invoked (DDR operation is different from -- SDR). -- CE1, CE2: 1-bit (each) input: Data register clock enable inputs CE1 => '1', CE2 => '0', CLKDIVP => '0', -- 1-bit input: TBD -- Clocks: 1-bit (each) input: ISERDESE2 clock input ports CLK => clk640, -- 1-bit input: High-speed clock CLKB => '0', -- 1-bit input: High-speed secondary clock CLKDIV => clk160, -- 1-bit input: Divided clock OCLK => '0', -- 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY" -- Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity DYNCLKDIVSEL => '0', -- 1-bit input: Dynamic CLKDIV inversion DYNCLKSEL => '0', -- 1-bit input: Dynamic CLK/CLKB inversion -- Input Data: 1-bit (each) input: ISERDESE2 data input ports D => din, -- 1-bit input: Data input DDLY => '0', -- 1-bit input: Serial data from IDELAYE2 OFB => '0', -- 1-bit input: Data feedback from OSERDESE2 OCLKB => '0', -- 1-bit input: High speed negative edge output clock RST => reset, -- 1-bit input: Active high asynchronous reset -- SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports SHIFTIN1 => '0', SHIFTIN2 => '0' ); process begin wait until rising_edge(clk160); if reset = '1' then AZ(4 downto 1) <= (others => '0'); BZ(4 downto 1) <= (others => '0'); CZ(4 downto 1) <= (others => '0'); DZ(4 downto 1) <= (others => '0'); AAP <= '0'; AAN <= '0'; BBP <= '0'; BBN <= '0'; CCP <= '0'; CCN <= '0'; DDP <= '0'; DDN <= '0'; use_A1 <= '0'; use_A2 <= '0'; use_A <= '0'; use_B1 <= '0'; use_B2 <= '0'; use_B <= '0'; use_C1 <= '0'; use_C2 <= '0'; use_C <= '0'; use_D1 <= '0'; use_D2 <= '0'; use_D <= '0'; use_A_reg <= '0'; use_A_reg2 <= '0'; use_B_reg <= '0'; use_B_reg2 <= '0'; use_C_reg <= '0'; use_C_reg2 <= '0'; use_D_reg <= '0'; use_D_reg2 <= '0'; sdata_A <= "00"; sdata_B <= "00"; sdata_C <= "00"; sdata_D <= "00"; valid_int <= "00"; data_value <= "00"; data_valid <= "00"; data_lock <= '0'; lockcnt <= 0; pipe_ce0 <= '0'; pipe_ce1 <= '0'; else -- clock in the data AZ(4 downto 1) <= AZ(3 downto 0); BZ(4 downto 1) <= BZ(3 downto 0); CZ(4 downto 1) <= CZ(3 downto 0); DZ(4 downto 1) <= DZ(3 downto 0); -- find positive edges AAP <= (AZ(2) xor AZ(3)) and not AZ(2); BBP <= (BZ(2) xor BZ(3)) and not BZ(2); CCP <= (CZ(2) xor CZ(3)) and not CZ(2); DDP <= (DZ(2) xor DZ(3)) and not DZ(2); -- find negative edges AAN <= (AZ(2) xor AZ(3)) and AZ(2); BBN <= (BZ(2) xor BZ(3)) and BZ(2); CCN <= (CZ(2) xor CZ(3)) and CZ(2); DDN <= (DZ(2) xor DZ(3)) and DZ(2); -- decision of sampling point use_A1 <= (BBP and not CCP and not DDP and AAP); use_A2 <= (BBN and not CCN and not DDN and AAN); use_B1 <= (CCP and not DDP and AAP and BBP); use_B2 <= (CCN and not DDN and AAN and BBN); use_C1 <= (DDP and AAP and BBP and CCP); use_C2 <= (DDN and AAN and BBN and CCN); use_D1 <= (AAP and not BBP and not CCP and not DDP); use_D2 <= (AAN and not BBN and not CCN and not DDN); use_A <= use_A1 or use_A2; use_B <= use_B1 or use_B2; use_C <= use_C1 or use_C2; use_D <= use_D1 or use_D2; -- if we found an edge if (use_A or use_B or use_C or use_D) = '1' then lockcnt <= 127; pipe_ce0 <= '1'; -- sync marker pipe_ce1 <= '1'; else if lockcnt = 0 then pipe_ce0 <= '0'; else lockcnt <= lockcnt - 1; end if; pipe_ce1 <= '0'; end if; -- register use_A_reg <= use_A; use_B_reg <= use_B; use_C_reg <= use_C; use_D_reg <= use_D; if pipe_ce1 = '1' then use_A_reg2 <= use_A_reg; use_B_reg2 <= use_B_reg; use_C_reg2 <= use_C_reg; use_D_reg2 <= use_D_reg; end if; -- collect output data sdata_A(0) <= AZ(4) and use_A_reg2; sdata_A(1) <= AZ(4) and use_D_reg2; sdata_B(0) <= BZ(4) and use_B_reg2; sdata_B(1) <= '0'; sdata_C(0) <= CZ(4) and use_C_reg2; sdata_C(1) <= '0'; sdata_D(0) <= DZ(4) and use_D_reg2; sdata_D(1) <= DZ(4) and use_A_reg2; -- ouput data if we have seen an edge if pipe_ce0 = '1' then data_value <= sdata_A or sdata_B or sdata_C or sdata_D; end if; -- data valid output if use_D_reg2 = '1' and use_A_reg = '1' then valid_int <= "00"; -- move from A to D: no valid data elsif use_A_reg2 = '1' and use_D_reg = '1' then valid_int <= "11"; -- move from D to A: 2 bits valid else valid_int <= "01"; -- only one bit is valid end if; if pipe_ce0 = '1' then data_valid <= valid_int; else data_valid <= "00"; end if; data_lock <= pipe_ce0; end if; end process; end architecture;
-- $Id: simlib.vhd 1210 2021-08-26 13:27:26Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2006-2019 by Walter F.J. Mueller <[email protected]> -- ------------------------------------------------------------------------------ -- Module Name: simlib - sim -- Description: Support routines for test benches -- -- Dependencies: - -- Test bench: - -- Target Devices: generic -- Tool versions: xst 8.2-14.7; viv 2015.4-2016.2; ghdl 0.18-0.36 -- -- Revision History: -- Date Rev Version Comment -- 2019-08-13 1202 2.1.5 write{oct,hex}: fix for ghdl V0.36 -Whide warnings -- 2016-09-03 805 2.1.4 simclk(v): CLK_STOP,CLK_HOLD now optional ports -- 2016-07-16 787 2.1.3 add simbididly component -- 2016-06-12 774 2.1.2 add writetimens() -- 2014-10-25 599 2.1.1 add wait_* procedures; writeoptint: no dat clear -- 2014-10-18 597 2.1 add simfifo_*, writetrace procedures -- 2014-09-06 591 2.0.1 add readint_ea() with range check -- 2011-12-23 444 2.0 drop CLK_CYCLE from simclk,simclkv; use integer for -- simclkcnt(CLK_CYCLE),writetimestamp(clkcyc); -- 2011-11-18 427 1.3.8 now numeric_std clean -- 2010-12-22 346 1.3.7 rename readcommand -> readdotcomm -- 2010-11-13 338 1.3.6 add simclkcnt; xx.x ns time in writetimestamp() -- 2008-03-24 129 1.3.5 CLK_CYCLE now 31 bits -- 2008-03-02 121 1.3.4 added readempty (to discard rest of line) -- 2007-12-27 106 1.3.3 added simclk2v -- 2007-12-15 101 1.3.2 add read_ea(time), readtagval[_ea](std_logic) -- 2007-10-12 88 1.3.1 avoid ieee.std_logic_unsigned, use cast to unsigned -- 2007-08-28 76 1.3 added writehex and writegen -- 2007-08-10 72 1.2.2 remove entity simclk, put into separate source -- 2007-08-03 71 1.2.1 readgen, readtagval, readtagval2: add base arg -- 2007-07-29 70 1.2 readtagval2: add tag=- support; add readword_ea, -- readoptchar, writetimestamp -- 2007-07-28 69 1.1.1 rename readrest -> testempty; add readgen -- use readgen in readtagval() and readtagval2() -- 2007-07-22 68 1.1 add readrest, readtagval, readtagval2 -- 2007-06-30 62 1.0.1 remove clock_period ect constant defs -- 2007-06-14 56 1.0 Initial version (renamed from pdp11_sim.vhd) ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; use work.slvtypes.all; package simlib is constant null_char : character := character'val(0); -- '\0' constant null_string : string(1 to 1) := (others=>null_char); -- "\0" procedure readwhite( -- read over white space L: inout line); -- line procedure readoct( -- read slv in octal base (arb. length) L: inout line; -- line value: out std_logic_vector; -- value to be read good: out boolean); -- success flag procedure readhex( -- read slv in hex base (arb. length) L: inout line; -- line value: out std_logic_vector; -- value to be read good: out boolean); -- success flag procedure readgen( -- read slv generic base L: inout line; -- line value: out std_logic_vector; -- value to be read good: out boolean; -- success flag base: in integer:= 2); -- default base procedure readcomment( L: inout line; good: out boolean); procedure readdotcomm( L: inout line; name: out string; good: out boolean); procedure readword( L: inout line; name: out string; good: out boolean); procedure readoptchar( L: inout line; char: in character; good: out boolean); procedure readempty( L: inout line); procedure testempty( L: inout line; good: out boolean); procedure testempty_ea( L: inout line); procedure read_ea( L: inout line; value: out integer); procedure read_ea( L: inout line; value: out time); procedure readint_ea( L: inout line; value: out integer; imin : in integer := integer'low; imax : in integer := integer'high); procedure read_ea( L: inout line; value: out std_logic); procedure read_ea( L: inout line; value: out std_logic_vector); procedure readoct_ea( L: inout line; value: out std_logic_vector); procedure readhex_ea( L: inout line; value: out std_logic_vector); procedure readgen_ea( L: inout line; value: out std_logic_vector; base: in integer:= 2); procedure readword_ea( L: inout line; name: out string); procedure readtagval( L: inout line; tag: in string; match: out boolean; val: out std_logic_vector; good: out boolean; base: in integer:= 2); procedure readtagval_ea( L: inout line; tag: in string; match: out boolean; val: out std_logic_vector; base: in integer:= 2); procedure readtagval( L: inout line; tag: in string; match: out boolean; val: out std_logic; good: out boolean); procedure readtagval_ea( L: inout line; tag: in string; match: out boolean; val: out std_logic); procedure readtagval2( L: inout line; tag: in string; match: out boolean; val1: out std_logic_vector; val2: out std_logic_vector; good: out boolean; base: in integer:= 2); procedure readtagval2_ea( L: inout line; tag: in string; match: out boolean; val1: out std_logic_vector; val2: out std_logic_vector; base: in integer:= 2); procedure writeoct( -- write slv in octal base (arb. length) L: inout line; -- line value: in std_logic_vector; -- value to be written justified: in side:=right; -- justification (left/right) field: in width:=0); -- field width procedure writehex( -- write slv in hex base (arb. length) L: inout line; -- line value: in std_logic_vector; -- value to be written justified: in side:=right; -- justification (left/right) field: in width:=0); -- field width procedure writegen( -- write slv in generic base (arb. lth) L: inout line; -- line value: in std_logic_vector; -- value to be written justified: in side:=right; -- justification (left/right) field: in width:=0; -- field width base: in integer:= 2); -- default base procedure writetimens( -- write time as fractional ns L: inout line; -- line t : in time; -- time field : in width:=0); -- number of ns digits procedure writetimestamp( -- write time stamp L: inout line; -- line str : in string := null_string); -- 1st string field procedure writetimestamp( -- write time stamp w/ clk cycle L: inout line; -- line clkcyc: in integer; -- cycle number str : in string := null_string); -- 1st string field procedure writeoptint( -- write int if > 0 L: inout line; -- line str : in string; -- string dat : in integer; -- int value field: in width:=0); -- field width procedure writetrace( -- debug trace - plain str : in string); -- string procedure writetrace( -- debug trace - int str : in string; -- string dat : in integer); -- value procedure writetrace( -- debug trace - slbit str : in string; -- string dat : in slbit); -- value procedure writetrace( -- debug trace - slv str : in string; -- string dat : in slv); -- value type clock_dsc is record -- clock descriptor period : Delay_length; -- clock period hold : Delay_length; -- hold time = clock yo stim time setup : Delay_length; -- setup time = moni to clock time end record; procedure wait_nextstim( -- wait for next stim time signal clk : in slbit; -- clock constant clk_dsc : in clock_dsc; -- clock descriptor constant cnt : in positive := 1); -- number of cycles to wait procedure wait_nextmoni( -- wait for next moni time signal clk : in slbit; -- clock constant clk_dsc : in clock_dsc; -- clock descriptor constant cnt : in positive := 1); -- number of cycles to wait procedure wait_stim2moni( -- wait from stim to moni time signal clk : in slbit; -- clock constant clk_dsc : in clock_dsc); -- clock descriptor procedure wait_untilsignal( -- wait until signal signal clk : in slbit; -- clock constant clk_dsc : in clock_dsc; -- clock descriptor signal sig : in slbit; -- signal constant val : in slbit; -- value variable cnt : out natural); -- cycle count type simfifo_type is array (natural range <>, natural range<>) of std_logic; procedure simfifo_put( -- add item to simfifo cnt : inout natural; -- fifo element count arr : inout simfifo_type; -- fifo data array din : in std_logic_vector; -- element to add val : in slbit := '1'); -- valid flag procedure simfifo_get( -- get item from simfifo cnt : inout natural; -- fifo element count arr : inout simfifo_type; -- fifo data array dout: out std_logic_vector); -- element retrieved procedure simfifo_writetest( -- test value against simfifo and write L: inout line; -- line cnt : inout natural; -- fifo element count arr : inout simfifo_type; -- fifo data array dat : in std_logic_vector); -- data to test procedure simfifo_dump( -- dump simfifo cnt : inout natural; -- fifo element count arr : inout simfifo_type; -- fifo data array str : in string := null_string); -- header text -- ---------------------------------------------------------------------------- component simclk is -- test bench clock generator generic ( PERIOD : Delay_length := 20 ns; -- clock period OFFSET : Delay_length := 200 ns); -- clock offset (first up transition) port ( CLK : out slbit; -- clock CLK_STOP : in slbit := '0' -- clock stop trigger ); end component; component simclkv is -- test bench clock generator -- with variable periods port ( CLK : out slbit; -- clock CLK_PERIOD : in Delay_length; -- clock period CLK_HOLD : in slbit := '0'; -- if 1, hold clocks in 0 state CLK_STOP : in slbit := '0' -- clock stop trigger ); end component; component simclkcnt is -- test bench system clock cycle counter port ( CLK : in slbit; -- clock CLK_CYCLE : out integer -- clock cycle number ); end component; component simbididly is -- test bench bi-directional bus delay generic ( DELAY : Delay_length; -- transport delay between A and B DWIDTH : positive := 16); -- data port width port ( A : inout slv(DWIDTH-1 downto 0); -- port A B : inout slv(DWIDTH-1 downto 0) -- port B ); end component; end package simlib; -- ---------------------------------------------------------------------------- package body simlib is procedure readwhite( -- read over white space L: inout line) is -- line variable ch : character; begin while L'length>0 loop ch := L(L'left); exit when (ch/=' ' and ch/=HT); read(L,ch); end loop; end procedure readwhite; -- ------------------------------------- procedure readoct( -- read slv in octal base (arb. length) L: inout line; -- line value: out std_logic_vector; -- value to be read good: out boolean) is -- success flag variable nibble : std_logic_vector(2 downto 0); variable sum : std_logic_vector(31 downto 0); variable ndig : integer; -- number of digits variable ok : boolean; variable ichar : character; begin assert not value'ascending(1) report "readoct called with ascending range" severity failure; assert value'length<=32 report "readoct called with value'length > 32" severity failure; readwhite(L); ndig := 0; sum := (others=>'U'); while L'length>0 loop ok := true; case L(L'left) is when '0' => nibble := "000"; when '1' => nibble := "001"; when '2' => nibble := "010"; when '3' => nibble := "011"; when '4' => nibble := "100"; when '5' => nibble := "101"; when '6' => nibble := "110"; when '7' => nibble := "111"; when 'u'|'U' => nibble := "UUU"; when 'x'|'X' => nibble := "XXX"; when 'z'|'Z' => nibble := "ZZZ"; when '-' => nibble := "---"; when others => ok := false; end case; exit when not ok; read(L,ichar); ndig := ndig + 1; sum(sum'left downto 3) := sum(sum'left-3 downto 0); sum(2 downto 0) := nibble; end loop; ok := ndig>0; value := sum(value'range); good := ok; end procedure readoct; -- ------------------------------------- procedure readhex( -- read slv in hex base (arb. length) L: inout line; -- line value: out std_logic_vector; -- value to be read good: out boolean) is -- success flag variable nibble : std_logic_vector(3 downto 0); variable sum : std_logic_vector(31 downto 0); variable ndig : integer; -- number of digits variable ok : boolean; variable ichar : character; begin assert not value'ascending(1) report "readhex called with ascending range" severity failure; assert value'length<=32 report "readhex called with value'length > 32" severity failure; readwhite(L); ndig := 0; sum := (others=>'U'); while L'length>0 loop ok := true; case L(L'left) is when '0' => nibble := "0000"; when '1' => nibble := "0001"; when '2' => nibble := "0010"; when '3' => nibble := "0011"; when '4' => nibble := "0100"; when '5' => nibble := "0101"; when '6' => nibble := "0110"; when '7' => nibble := "0111"; when '8' => nibble := "1000"; when '9' => nibble := "1001"; when 'a'|'A' => nibble := "1010"; when 'b'|'B' => nibble := "1011"; when 'c'|'C' => nibble := "1100"; when 'd'|'D' => nibble := "1101"; when 'e'|'E' => nibble := "1110"; when 'f'|'F' => nibble := "1111"; when 'u'|'U' => nibble := "UUUU"; when 'x'|'X' => nibble := "XXXX"; when 'z'|'Z' => nibble := "ZZZZ"; when '-' => nibble := "----"; when others => ok := false; end case; exit when not ok; read(L,ichar); ndig := ndig + 1; sum(sum'left downto 4) := sum(sum'left-4 downto 0); sum(3 downto 0) := nibble; end loop; ok := ndig>0; value := sum(value'range); good := ok; end procedure readhex; -- ------------------------------------- procedure readgen( -- read slv generic base L: inout line; -- line value: out std_logic_vector; -- value to be read good: out boolean; -- success flag base: in integer := 2) is -- default base variable nibble : std_logic_vector(3 downto 0); variable sum : std_logic_vector(31 downto 0); variable lbase : integer; -- local base variable cbase : integer; -- current base variable ok : boolean; variable ivalue : integer; variable ichar : character; begin assert not value'ascending(1) report "readgen called with ascending range" severity failure; assert value'length<=32 report "readgen called with value'length > 32" severity failure; assert base=2 or base=8 or base=10 or base=16 report "readgen base not 2,8,10, or 16" severity failure; readwhite(L); cbase := base; lbase := 0; ok := true; if L'length >= 2 then if L(L'left+1) = '"' then case L(L'left) is when 'b'|'B' => lbase := 2; when 'o'|'O' => lbase := 8; when 'd'|'D' => lbase := 10; when 'x'|'X' => lbase := 16; when others => ok := false; end case; end if; if lbase /= 0 then read(L, ichar); read(L, ichar); cbase := lbase; end if; end if; if ok then case cbase is when 2 => read(L, value, ok); when 8 => readoct(L, value, ok); when 16 => readhex(L, value, ok); when 10 => read(L, ivalue, ok); -- the following if allows to enter negative integers, e.g. -1 for all-1 if ivalue >= 0 then value := slv(to_unsigned(ivalue, value'length)); else value := slv(to_signed(ivalue, value'length)); end if; when others => null; end case; end if; if ok and lbase/=0 then if L'length>0 and L(L'left)='"' then read(L, ichar); else ok := false; end if; end if; good := ok; end procedure readgen; -- ------------------------------------- procedure readcomment( L: inout line; good: out boolean) is variable ichar : character; begin readwhite(L); good := true; if L'length > 0 then good := false; if L(L'left) = '#' then good := true; elsif L(L'left) = 'C' then good := true; writeline(output, L); end if; end if; end procedure readcomment; -- ------------------------------------- procedure readdotcomm( L: inout line; name: out string; good: out boolean) is begin for i in name'range loop name(i) := ' '; end loop; good := false; if L'length>0 and L(L'left)='.' then readword(L, name, good); end if; end procedure readdotcomm; -- ------------------------------------- procedure readword( L: inout line; name: out string; good: out boolean) is variable ichar : character; variable ind : integer; begin assert name'ascending(1) report "readword called with descending range for name" severity failure; readwhite(L); for i in name'range loop name(i) := ' '; end loop; ind := name'left; while L'length>0 and ind<=name'right loop ichar := L(L'left); exit when ichar=' ' or ichar=',' or ichar='|'; read(L,ichar); name(ind) := ichar; ind := ind + 1; end loop; good := ind /= name'left; -- ok if one non-blank found end procedure readword; -- ------------------------------------- procedure readoptchar( L: inout line; char: in character; good: out boolean) is variable ichar : character; begin good := false; if L'length > 0 then if L(L'left) = char then read(L, ichar); good := true; end if; end if; end procedure readoptchar; -- ------------------------------------- procedure readempty( L: inout line) is variable ch : character; begin while L'length>0 loop -- anything left ? read(L,ch); -- read and discard it end loop; end procedure readempty; -- ------------------------------------- procedure testempty( L: inout line; good: out boolean) is begin readwhite(L); -- discard white space good := true; -- good if now empty if L'length > 0 then -- anything left ? good := false; -- assume bad if L'length >= 2 and -- check for "--" L(L'left)='-' and L(L'left+1)='-' then good := true; -- in that case comment -> good end if; end if; end procedure testempty; -- ------------------------------------- procedure testempty_ea( L: inout line) is variable ok : boolean := false; begin testempty(L, ok); assert ok report "extra chars in """ & L.all & """" severity failure; end procedure testempty_ea; -- ------------------------------------- procedure read_ea( L: inout line; value: out integer) is variable ok : boolean := false; begin read(L, value, ok); assert ok report "read(integer) conversion error in """ & L.all & """" severity failure; end procedure read_ea; -- ------------------------------------- procedure read_ea( L: inout line; value: out time) is variable ok : boolean := false; begin read(L, value, ok); assert ok report "read(time) conversion error in """ & L.all & """" severity failure; end procedure read_ea; -- ------------------------------------- procedure readint_ea( L: inout line; value: out integer; imin : in integer := integer'low; imax : in integer := integer'high) is variable dat : integer := 0; begin read_ea(L, dat); assert dat>=imin and dat<=imax report "readint_ea range check: " & integer'image(dat) & " not in " & integer'image(imin) & ":" & integer'image(imax) severity failure; value := dat; end procedure readint_ea; -- ------------------------------------- procedure read_ea( L: inout line; value: out std_logic) is variable ok : boolean := false; begin read(L, value, ok); assert ok report "read(std_logic) conversion error in """ & L.all & """" severity failure; end procedure read_ea; -- ------------------------------------- procedure read_ea( L: inout line; value: out std_logic_vector) is variable ok : boolean := false; begin read(L, value, ok); assert ok report "read(std_logic_vector) conversion error in """ & L.all & """" severity failure; end procedure read_ea; -- ------------------------------------- procedure readoct_ea( L: inout line; value: out std_logic_vector) is variable ok : boolean := false; begin readoct(L, value, ok); assert ok report "readoct() conversion error in """ & L.all & """" severity failure; end procedure readoct_ea; -- ------------------------------------- procedure readhex_ea( L: inout line; value: out std_logic_vector) is variable ok : boolean := false; begin readhex(L, value, ok); assert ok report "readhex() conversion error in """ & L.all & """" severity failure; end procedure readhex_ea; -- ------------------------------------- procedure readgen_ea( L: inout line; value: out std_logic_vector; base: in integer := 2) is variable ok : boolean := false; begin readgen(L, value, ok, base); assert ok report "readgen() conversion error in """ & L.all & """" severity failure; end procedure readgen_ea; -- ------------------------------------- procedure readword_ea( L: inout line; name: out string) is variable ok : boolean := false; begin readword(L, name, ok); assert ok report "readword() read error in """ & L.all & """" severity failure; end procedure readword_ea; -- ------------------------------------- procedure readtagval( L: inout line; tag: in string; match: out boolean; val: out std_logic_vector; good: out boolean; base: in integer:= 2) is variable itag : string(tag'range); variable ichar : character; variable imatch : boolean; begin readwhite(L); for i in val'range loop val(i) := '0'; end loop; good := true; imatch := false; if L'length > tag'length then imatch := L(L'left to L'left+tag'length-1) = tag and L(L'left+tag'length) = '='; if imatch then read(L, itag); read(L, ichar); readgen(L, val, good, base); end if; end if; match := imatch; end procedure readtagval; -- ------------------------------------- procedure readtagval_ea( L: inout line; tag: in string; match: out boolean; val: out std_logic_vector; base: in integer:= 2) is variable ok : boolean := false; begin readtagval(L, tag, match, val, ok, base); assert ok report "readtagval(std_logic_vector) conversion error in """ & L.all & """" severity failure; end procedure readtagval_ea; -- ------------------------------------- procedure readtagval( L: inout line; tag: in string; match: out boolean; val: out std_logic; good: out boolean) is variable itag : string(tag'range); variable ichar : character; variable imatch : boolean; begin readwhite(L); val := '0'; good := true; imatch := false; if L'length > tag'length then imatch := L(L'left to L'left+tag'length-1) = tag and L(L'left+tag'length) = '='; if imatch then read(L, itag); read(L, ichar); read(L, val, good); end if; end if; match := imatch; end procedure readtagval; -- ------------------------------------- procedure readtagval_ea( L: inout line; tag: in string; match: out boolean; val: out std_logic) is variable ok : boolean := false; begin readtagval(L, tag, match, val, ok); assert ok report "readtagval(std_logic) conversion error in """ & L.all & """" severity failure; end procedure readtagval_ea; -- ------------------------------------- procedure readtagval2( L: inout line; tag: in string; match: out boolean; val1: out std_logic_vector; val2: out std_logic_vector; good: out boolean; base: in integer:= 2) is variable itag : string(tag'range); variable imatch : boolean; variable igood : boolean; variable ichar : character; variable ok : boolean; begin readwhite(L); for i in val1'range loop -- zero val1 val1(i) := '0'; end loop; for i in val2'range loop -- zero val2 val2(i) := '0'; end loop; igood := true; imatch := false; if L'length > tag'length then -- check for tag imatch := L(L'left to L'left+tag'length-1) = tag and L(L'left+tag'length) = '='; if imatch then -- if found read(L, itag); -- remove tag read(L, ichar); -- remove = igood := false; readoptchar(L, '-', ok); -- check for tag=- if ok then for i in val2'range loop -- set mask to all 1 (ignore) val2(i) := '1'; end loop; igood := true; else -- here if tag=bit[,bit] readgen(L, val1, igood, base); -- read val1 if igood then readoptchar(L, ',', ok); -- check(and remove) , if ok then readgen(L, val2, igood, base); -- and read val2 end if; end if; end if; end if; end if; match := imatch; good := igood; end procedure readtagval2; -- ------------------------------------- procedure readtagval2_ea( L: inout line; tag: in string; match: out boolean; val1: out std_logic_vector; val2: out std_logic_vector; base: in integer:= 2) is variable ok : boolean := false; begin readtagval2(L, tag, match, val1, val2, ok, base); assert ok report "readtagval2() conversion error in """ & L.all & """" severity failure; end procedure readtagval2_ea; -- ------------------------------------- procedure writeoct( -- write slv in octal base (arb. length) L: inout line; -- line value: in std_logic_vector; -- value to be written justified: in side:=right; -- justification (left/right) field: in width:=0) is -- field width variable nbit : integer; -- number of bits variable ndig : integer; -- number of digits variable iwidth : integer; variable ioffset : integer; variable nibble : std_logic_vector(2 downto 0); variable ochar : character; begin assert not value'ascending(1) report "writeoct called with ascending range" severity failure; nbit := value'length(1); ndig := (nbit+2)/3; iwidth := nbit mod 3; if iwidth = 0 then iwidth := 3; end if; ioffset := value'left(1) - iwidth+1; if justified=right and field>ndig then for i in ndig+1 to field loop write(L,' '); end loop; -- i end if; for i in 0 to ndig-1 loop nibble := "000"; nibble(iwidth-1 downto 0) := value(ioffset+iwidth-1 downto ioffset); ochar := ' '; for j in nibble'range loop case nibble(j) is when 'U' => ochar := 'U'; when 'X' => ochar := 'X'; when 'Z' => ochar := 'Z'; when '-' => ochar := '-'; when others => null; end case; end loop; -- j if ochar = ' ' then write(L,to_integer(unsigned(nibble))); else write(L,ochar); end if; iwidth := 3; ioffset := ioffset - 3; end loop; -- i if justified=left and field>ndig then for i in ndig+1 to field loop write(L,' '); end loop; -- i end if; end procedure writeoct; -- ------------------------------------- procedure writehex( -- write slv in hex base (arb. length) L: inout line; -- line value: in std_logic_vector; -- value to be written justified: in side:=right; -- justification (left/right) field: in width:=0) is -- field width variable nbit : integer; -- number of bits variable ndig : integer; -- number of digits variable iwidth : integer; variable ioffset : integer; variable nibble : std_logic_vector(3 downto 0); variable ochar : character; variable hextab : string(1 to 16) := "0123456789abcdef"; begin assert not value'ascending(1) report "writehex called with ascending range" severity failure; nbit := value'length(1); ndig := (nbit+3)/4; iwidth := nbit mod 4; if iwidth = 0 then iwidth := 4; end if; ioffset := value'left(1) - iwidth+1; if justified=right and field>ndig then for i in ndig+1 to field loop write(L,' '); end loop; -- i end if; for i in 0 to ndig-1 loop nibble := "0000"; nibble(iwidth-1 downto 0) := value(ioffset+iwidth-1 downto ioffset); ochar := ' '; for j in nibble'range loop case nibble(j) is when 'U' => ochar := 'U'; when 'X' => ochar := 'X'; when 'Z' => ochar := 'Z'; when '-' => ochar := '-'; when others => null; end case; end loop; -- j if ochar = ' ' then write(L,hextab(to_integer(unsigned(nibble))+1)); else write(L,ochar); end if; iwidth := 4; ioffset := ioffset - 4; end loop; -- i if justified=left and field>ndig then for i in ndig+1 to field loop write(L,' '); end loop; -- i end if; end procedure writehex; -- ------------------------------------- procedure writegen( -- write slv in generic base (arb. lth) L: inout line; -- line value: in std_logic_vector; -- value to be written justified: in side:=right; -- justification (left/right) field: in width:=0; -- field width base: in integer:=2) is -- default base begin case base is when 2 => write(L, value, justified, field); when 8 => writeoct(L, value, justified, field); when 16 => writehex(L, value, justified, field); when others => report "writegen base not 2,8, or 16" severity failure; end case; end procedure writegen; -- ------------------------------------- procedure writetimens( -- write time as fractional ns L: inout line; -- line t : in time; -- time field : in width:=0) is -- number of ns digits variable t_nsec : integer := 0; variable t_psec : integer := 0; variable t_dnsec : integer := 0; begin t_nsec := t / 1 ns; t_psec := (t - t_nsec * 1 ns) / 1 ps; t_dnsec := t_psec/100; write(L, t_nsec, right, field); write(L,'.'); write(L, t_dnsec, right, 1); write(L, string'(" ns")); end procedure writetimens; -- ------------------------------------- procedure writetimestamp( L: inout line; str : in string := null_string) is begin writetimens(L, now, 8); if str /= null_string then write(L, str); end if; end procedure writetimestamp; -- ------------------------------------- procedure writetimestamp( L: inout line; clkcyc: in integer; str: in string := null_string) is begin writetimestamp(L); write(L, clkcyc, right, 7); if str /= null_string then write(L, str); end if; end procedure writetimestamp; -- ------------------------------------- procedure writeoptint( -- write int if > 0 L: inout line; -- line str : in string; -- string dat : in integer; -- int value field: in width:=0) is -- field width begin if dat > 0 then write(L, str); write(L, dat, right, field); end if; end procedure writeoptint; -- ------------------------------------- procedure writetrace( -- debug trace - plain str: in string) is -- string variable oline : line; begin writetimestamp(oline, " ++ "); write(oline, str); writeline(output, oline); end procedure writetrace; -- ------------------------------------- procedure writetrace( -- debug trace - int str: in string; -- string dat : in integer) is -- value variable oline : line; begin writetimestamp(oline, " ++ "); write(oline, str); write(oline, dat); writeline(output, oline); end procedure writetrace; -- ------------------------------------- procedure writetrace( -- debug trace - slbit str: in string; -- string dat : in slbit) is -- value variable oline : line; begin writetimestamp(oline, " ++ "); write(oline, str); write(oline, dat); writeline(output, oline); end procedure writetrace; -- ------------------------------------- procedure writetrace( -- debug trace - slv str: in string; -- string dat : in slv) is -- value variable oline : line; begin writetimestamp(oline, " ++ "); write(oline, str); write(oline, dat); writeline(output, oline); end procedure writetrace; -- ------------------------------------- procedure wait_nextstim( -- wait for next stim time signal clk : in slbit; -- clock constant clk_dsc : in clock_dsc; -- clock descriptor constant cnt : in positive := 1) is -- number of cycles to wait begin for i in 1 to cnt loop wait until rising_edge(clk); wait for clk_dsc.hold; end loop; -- i end procedure wait_nextstim; -- ------------------------------------- procedure wait_nextmoni( -- wait for next moni time signal clk : in slbit; -- clock constant clk_dsc : in clock_dsc; -- clock descriptor constant cnt : in positive := 1) is -- number of cycles to wait begin for i in 1 to cnt loop wait until rising_edge(clk); wait for clk_dsc.period - clk_dsc.setup; end loop; -- i end procedure wait_nextmoni; -- ------------------------------------- procedure wait_stim2moni( -- wait from stim to moni time signal clk : in slbit; -- clock constant clk_dsc : in clock_dsc) is -- clock descriptor begin wait for clk_dsc.period - clk_dsc.hold - clk_dsc.setup; end procedure wait_stim2moni; -- ------------------------------------- procedure wait_untilsignal( -- wait until signal signal clk : in slbit; -- clock constant clk_dsc : in clock_dsc; -- clock descriptor signal sig : in slbit; -- signal constant val : in slbit; -- value variable cnt : out natural) is -- cycle count variable cnt_l : natural := 0; begin cnt_l := 0; while val /= sig loop wait_nextmoni(clk, clk_dsc); cnt_l := cnt_l + 1; end loop; cnt := cnt_l; end procedure wait_untilsignal; -- ------------------------------------- procedure simfifo_put( -- add item to simfifo cnt : inout natural; -- fifo element count arr : inout simfifo_type; -- fifo data array din : in std_logic_vector; -- element to add val : in slbit := '1') is -- valid flag variable din_imax : integer := din'length-1; begin if val = '0' then return; end if; assert cnt < arr'high(1) report "simfifo_put: fifo full" severity failure; assert arr'length(2) = din'length and arr'ascending(2) = din'ascending report "simfifo_put: arr,din range mismatch" severity failure; for i in 0 to din_imax loop arr(cnt, arr'low(2)+i) := din(din'low+i); end loop; -- i cnt := cnt + 1; end procedure simfifo_put; -- ------------------------------------- procedure simfifo_get( -- get item from simfifo cnt : inout natural; -- fifo element count arr : inout simfifo_type; -- fifo data array dout : out std_logic_vector) is -- element retrieved variable dout_imax : integer := dout'length-1; begin assert cnt > 0 report "simfifo_put: fifo empty" severity failure; assert arr'length(2) = dout'length and arr'ascending(2) = dout'ascending report "simfifo_put: arr,din range mismatch" severity failure; for i in 0 to dout_imax loop dout(dout'low+i) := arr(0, arr'low(2)+i); end loop; -- i cnt := cnt - 1; if cnt > 0 then for i in 1 to cnt loop for j in 0 to dout_imax loop arr(i-1, arr'low(2)+j) := arr(i, arr'low(2)+j); end loop; -- j end loop; -- i end if; end procedure simfifo_get; -- ------------------------------------- procedure simfifo_writetest( -- test value against simfifo and write L: inout line; -- line cnt : inout natural; -- fifo element count arr : inout simfifo_type; -- fifo data array dat : in std_logic_vector) is -- data to test variable refdata : slv(dat'range); begin if cnt = 0 then write(L, string'(" FAIL: UNEXPECTED")); else simfifo_get(cnt, arr, refdata); write(L, string'(" CHECK: ")); if dat = refdata then write(L, string'("OK")); else write(L, string'("FAIL, EXP= ")); write(L, refdata); end if; end if; end procedure simfifo_writetest; -- ------------------------------------- procedure simfifo_dump( -- dump simfifo cnt : inout natural; -- fifo element count arr : inout simfifo_type; -- fifo data array str: in string := null_string) is -- header text variable oline : line; variable data : slv(arr'range(2)); begin writetimestamp(oline, " ++ "); if str /= null_string then write(oline, str); end if; write(oline, string'(" cnt= ")); write(oline, cnt); write(oline, string'(" of ")); write(oline, arr'high(1)); write(oline, string'("; drange=")); write(oline, arr'left(2)); if arr'ascending(2) then write(oline, string'(" to ")); else write(oline, string'(" downto ")); end if; write(oline, arr'right(2)); writeline(output, oline); if cnt > 0 then for i in 0 to cnt-1 loop for j in data'range loop data(j) := arr(i,j); end loop; -- j write(oline, string'(" - ")); write(oline, i, right, 2); write(oline, string'(" ")); write(oline, data); writeline(output, oline); end loop; -- i end if; end procedure simfifo_dump; end package body simlib;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity tests is Port (clock : in STD_LOGIC; switches : in STD_LOGIC_VECTOR(7 downto 0); read_enable : in STD_LOGIC; reset : in STD_LOGIC; write_enable : in STD_LOGIC; anodes : out STD_LOGIC_VECTOR(3 downto 0); decoder_out : out STD_LOGIC_VECTOR(6 downto 0); test_led1 : out STD_LOGIC; test_led2 : out STD_LOGIC; empty : out STD_LOGIC; full : out STD_LOGIC); end tests; architecture Behavioral of tests is --Queue component delcaration component FIFO port ( din: IN std_logic_VECTOR(7 downto 0); rd_clk: IN std_logic; rd_en: IN std_logic; rst: IN std_logic; wr_clk: IN std_logic; wr_en: IN std_logic; dout: OUT std_logic_VECTOR(7 downto 0); empty: OUT std_logic; full: OUT std_logic); end component; -- Synplicity black box declaration attribute syn_black_box : boolean; attribute syn_black_box of FIFO: component is true; component Debouncer is Port ( clock : in STD_LOGIC; reset : in STD_LOGIC; input : in STD_LOGIC; output : out STD_LOGIC); end component; component four_dig_7seg is Port ( clock : in STD_LOGIC; display_data : in STD_LOGIC_VECTOR (15 downto 0); anodes : out STD_LOGIC_VECTOR (3 downto 0); to_display : out STD_LOGIC_VECTOR (6 downto 0)); end component; signal read_clock : STD_LOGIC; signal write_clock : STD_LOGIC; signal deb_read_enable : STD_LOGIC; signal deb_write_enable : STD_LOGIC; signal FIFO_data_out : STD_LOGIC_VECTOR(7 downto 0); signal display_data : STD_LOGIC_VECTOR(15 downto 0); signal address_reg : STD_LOGIC_VECTOR(22 downto 0); signal address_reg_enable : STD_LOGIC; begin process (clock, reset) variable count : STD_LOGIC_VECTOR(25 downto 0); begin if reset = '1' then count := (others => '0'); elsif rising_edge(clock) then if address_reg_enable = '1' then count := count + 1; end if; end if; read_clock <= count(25); write_clock <= count(25); end process; process(clock, reset) begin if reset = '1' then address_reg <= (others => '0'); elsif rising_edge(clock) then address_reg <= address_reg + 1; end if; end process; --The camera queue CQ : FIFO port map ( din => switches, rd_clk => read_clock, rd_en => deb_read_enable, rst => reset, wr_clk => write_clock, wr_en => deb_write_enable, dout => FIFO_data_out, empty => empty, full => full); rclk : Debouncer port map (clock => clock, reset => reset, input => read_enable, output => deb_read_enable); wclk : Debouncer port map (clock => clock, reset => reset, input => write_enable, output => deb_write_enable); display : four_dig_7seg port map (clock => clock, display_data => display_data, anodes => anodes, to_display => decoder_out); display_data <= x"00" & FIFO_data_out; test_led1 <= read_clock; test_led2 <= write_clock; address_reg_enable <= '1'; end Behavioral;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p7Rd+JJS6BPhm3C8uEMSjtB2IOpOZImN8ABL10O7dB2/wknTrPPVnggIUugEe0Un6rsHScVa0yw8 WbsjeU4skQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bancDuzOXzE/C1Vj5QpW3wyih2C6ymZ1vv70urQ985WeT2kXc7KQyN00fbod+1ycgrcEzdZs+OxF /cQLUqqV1PAWyHyEqXlxABFUHjs/nxBl/f/B9V0jlBhAzKCCHBVtW+DFv8KpHE75Z2lg+r4JTjg7 zQiXYHxUisemJqUJdhA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block rZMEEzwWFXOuo5snJgtfZx9Urf7eZRBCxLhuSc3DgaT16zNB/FC6Qo2PLk9pQbhTwkt+6VFrAqaq rIuJ+6NqrQaj6tzRnuILLQxRIcZaZnlaNGPM0QELT1/pgSpbDRVs/w+jfcFf6hDgLWdb7+lF2lZt EzdkUS2z3RzGxMw0dEl0kPzX4BrObwXWpUb1u4DD6JMZb6O50zBS5jLIs04xzSPqxA3PuLRWpuc8 zAMmWK1PCPqsF6JmUA+ToDlUTA4DP+Qb/r/OItKXADHbpGUiJXq85NgUc8TOMYazRmcSDk09joNa rvnt13K7ONnKnXu7DU1cLEZpB6zC/Q33/JmxrA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSUvPGwGSOzh5U1OjbBgxWaXchd+ErSm3+d+gvsNPzEzvrhBDlsbz7cjXesFumQgP32hemPRlsUr lFspe8TkimNAMoMtRIt9Rpr9MJxdvSAJ2AckK92TaQKYGICYWnAAwRZdM4hFhKQynq8onwVPOItS 8G6qhIBnq17qx8rO48o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MVMseSXR8Gidb6hUpBeQo+a3Ho0qfbo2cQ4XmaaPwOf5p+bpngyRNVgFStTGlS9V1Gq9sxZR8m59 KVYbqvyTG1F7VywlVWjcCzm53JiHqc7770pyh1TFlHFmlBkxaKOZI17/BbAJVPtrgC1AFUgqJIKl KWFzGNfBnaqYhwSBpkZVKTp2N/RCKh6/dORV7jPLmH1kXSt5iI647oKA/xzmV2IPvCjRau9wfIMP 3BcMw9SliL4YOeA2gPuyEVJdJ+sinBGqyYpGCshGE4syCgACrJDHcCC8bST8+Ee2RwROkSw85PvD RmNqdRJR8yBkuN8MggDeHwsPe2oFAGN33DaQEA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304) `protect data_block Iv82dFjUBOJtp0CC5ikeAzmK1F0OGzQayjkX38cIYatIOxf7Sc+0UDNdH8uM4zjW4KY3N5nnWdoS kL9NC+RMI79KYV+cyoIoh9a4WnqJVaraMiIzFgt2KK+kKDnmrIcgPPjBWCBt8VdwcHRi5Ut9B2Mj LWMF2Egu0qyiebByDT9hU83VKBC8FuCbHS4cMzWBkS1/dX4FKbCwuLwv4rYrRb3RwIu0u/ZGZML3 sfgcdg/t9ARFZ6jjG8LQo56KBOlP3Z6yDZlipM/l8PXrTiLYeS8RkrLXQuXiG58+Yg6tddKx0VDC Wm3GbF+cmnJXuMmZTbFQna4SzA+fl4zGdiyCiB3/spzz864E0//Xa3s+bSPHDUDkABkp34vQYUlI 8zqNJooOtt8RFwbLXWAr+gdzpGfbW+vxUwDzbkRHa1TYBZpc549hy2amKl6D0XyfmVWJi/XUfkDS QnBqOibdObp/1MvseR1F/YI+4zRWfjeB53h3Kmk/92gKe12QwFGV+jniLguICEL+rU9T/V9hosex Nu70r8pJrIdjLoojfvPmE6Qtf8rTGKe05E+AOibSesFEDHcMfoz5cZnhy5nZ1hIYvftB9+idhW1c et4Sg3KZ2Vmkjf2GwJEqu6PUEbq9pGdlOkyqwZjYymXqruLGjZMXnisf0ObB/jWsILVSn9CdOLsT hsDnpoXnxqFj0HE0mNDSfTMSQ4NJbQV0odITaKG1THpbLuObDBTVXgoFtTKMI9+YKA2EqUSt47hv 6bDgs17pJruxUhqABEBA/CAqfL1DFMzRHJuUG/ATdqLAHNrb6jKFxCYWR1HZ69k1jbDIgbviHuoa BUi2/7IzCtmqg5Ftl171TyHb5Fcv6J/GVfy5irGeqrwqXTv73EaepP6ADzSGize0AhlkMkr0itSZ hnoa66202gxrtD/GryFfYM9HnU+4GtCviapT/g/1HcxxsjVoakp6IGspv3iQwXY9Y5JaiEeX+SCE 1b73rpiUX/cDVl9bilWYODGaMonApfTzBubpyEqS8NVofK17+BzAvR50PFsBD0dsip+tuIGXy4Z4 /0DAJJcxTeWQIfWFPvC9MPDPgcUbe3Dp5EJ6WI81XLz4XO52aaducvt4igg157BZqeMVpLXfkCEB zS4NutgAkZjNpQ+ZTbGVVtfLPWr9AM1UDkjEfz3Yvi146TYcV43OqGQy6Te6QyWWlfsq519kal5/ EgEFRa8Z5BOneytGZ8xd3jc+PRpFS5qMvtflKCpq5t4sOBzXZ/bSsYH8LXnth8TIY/YCXN+PLqoh pJWqCMa7JaCwdTyL9XiLHXyBq7HbbS7jr0kwuDt+pdzFYoSI9k4tVxU4ad1yIliONrV3HVCQnXou IdQ+GmhnpVMNUUzrhkN4mbjH+i1IHJN/3AvZUdmHBnXNVQq8bW0RSORvzjapDD0GpcCz2M354iLh A+cpaRTjgyAN4T5x9zE8jVuyW+3YNs1dt1ThGHlbg/aGY1xl4v6w8PMRxdgo6kVMKiMqeXZVQnQn /4GuhAt01ehL2IOuSr2Ndc5wsWCZy7Vv9LS6+UUayywO8Mzwx5HCHTaJ4+hb5EqIxY+yp171eAY8 sLaOMLeCHmHod/hjnkUoKj0cS3s4wkyFihHKUmpWDth4NdMRqlhj58gejNnsE0162AL1fkj1/5ge o+SgN8oS+BoKpAAC8iFyGsYr5RjUKUtI9w65oESNn8apEDxMaV31UIBxQPauUpAQCADTdkiDYHE6 TWj/0DKvdWkvyPodF6Q5KgMmtzDLGPwpLJqpD9PoKjecv+1hS3RhTpgfXUnXTDwXSNKAnB4q9fR2 G6h+k4LfFhDzW+14abIcGFDMiYFT4lc9CPTNj680oHvhBnpc9nbiJcJM68CEmPXij1fHM9FfXKzr M3lyCLuv7PBs9A/QdQxk71NRF0qLm+8y+Ndkj5Ba8KccCp6DYClkjmLgvKCshKOUJqaE82TVOXla 9OO6u5dfnwZ3z83r3rVymOOuxqMOUc7wUIe33sMUyJcThq8+d0rqY2oSPT5hlIY9n64lnL7Lk8lT J+iAICzSQ+rvb1xCr/BN9e2cb3ySOXF77PucO6ncPuEaF6yRU+v0TdrNsNFyEH6ESqiETu7/m95l Mw7MzPP9IRWyWazGgQojcdg5T2ORcBdW4G6BIF5uGgp5ThiH2qlYCgdZurdZD1ZoMA9GKM0o99pq 9zJlMVixQKpvv3o6a6xF/sNCkur1rEr4fAVvB8ec5syIhkwLsGDMLqpNsgp9UliBACzrPp6BcG19 06jH1XF7HO0KMFMzKBvmM3rlO/rWaW03TNGKsdeRCoBRtBeokdirkixwfPBkhv8S0ObaUK4h6XpW LjeOSxHQVaBv9GVQdCE3TPCKInayheBkC9tXiqcGeL/MgAxh0ZJRL9+Bv+BnV6vkajk8VFxsk7If bdAN05kdDLcBjzqfUHC8P0wm/QWS+BiVvgrLgUDSRto6oaZHrY30GtU8MKSglgUrwzREQjXEf4Ce 0bmOYpuLlbtY5kby/GvXAMXrTt2yiHso6yuZU2sRWtXT49AGPUf9A9kUDFJIoy38Yl932cQqLXWT LoKX/3t5RP59o4GURIgjN949c+Muva5gTigk+Pu1Comh9HIvSTIJh1Hn4Fmjl+ZRGhZiQ4H8V4mr H8kodbDBhL2Sx71Zahla1S2w9BNrwcaj6giesQSSkVoVhWv8AdMQYvYsv66E2pc+NrZeHIpuj+fw 1IBqRvte8WuVAMTB9XOErQiL3OWcq/HN7bE0RTLGmDbcJAnivAoSlDJf6QT4bj8N13zHYXysjE+O xm0g4q3B4t/vuTGqIib4EMaxMm7h1t3sTlYUhUL94uObNo2gLeFHmjxFBPULlwJPGtScEPFsskSk 3R4HSDGh7C4JKYdqOqSuGrb7MU9F9SjufTnr+ROSVWqKqfEiPMqC4SMLmCh0T0U0/i66uN04AKeZ Owk2TTJXM4oVZPqdB0yuI91l4HQMb+HORuvHQa8BJ0NqIdtTO37ysbnWRBbpRCrRCoh6OW3bz5Hx VQogeuGzfcVQ7/09VA/eQ9nOiw3EN8DFjdF2kaHBEpx7XFkcNM+b06mhbF+fFsIcCYjyuZXjU2a0 2ktVaZlxjh+W5TWCLcv2X5+oTv30fp7GMhKqokQ1UKSIyb1/bp5ZVejOWyBjqFb0S2dZPJfBZCQq 5u/4WfUDNM3r2Yybb9E7uLY15oHUUMtbT39/c9zIQJVyhkFBR5Ou4LXjHPjsEgrw45FT8iFPSCMP OhM8aQDFHb2hRsj/NXnTdm0aQBms9Im/P4IplXkkYNLJEP13dgwbKACj3ALBWcidpGy0iWCXQohz W023Wcoi3sqPi4IfxH948R//BmtvNNi2/FP11ozNlccdsxVVm3ItKULmNciePX33Ksgcofdr/R03 f4gG4vYWsUOROxpjhbQnO8x+EvVatrDZN6bpVr4E3jpkJbZZIxOSPEg/T5pKZuVUyqB1ZJUXT7kQ AShWhmgLl+00meu9ZFKi9HKCflPTiYw5H6mTah0dONt2ufQjcfM07P8PI19Wibe9ilEs2X9YoRHC N37BjRLUNbL/C2vbSZWpnbJAEaFAtA15etdOirQv2JNN7l0cOtuf+r30IOX+LLuobXdd2Dxhk+9H +H1gwSMJryRoJF/BpCv4cBNOfPruLy1yACjP69ShTHhbp+0e61dujxSumNMqEf3lqHXeOHqVwAO8 4+1bG3GKb3H6kWvcI8RdWYYQz4Ggyoa/AiEgHNYrAbWd4JnGJEoN80rtVWJSHvMhAT3qrrAqay3b ZlLiwTkXc0UWAv99NSub3qafJqKtwF4pNAAZKkq9O98C4+RuDpS0W0EMGkfqUxbre9+BhuQBamgE 3juH0HznDLf0SDjmjTR28Z7VstbcGlMunViwxSWR43Nc1KuvnWkilco5b6DmemlxmxGkHwlfi3pd ykXudE0xoyLcqil7pRcJKQqfCnvsk0YvG3RvsgDAqYe115yPLT8N9YWdEBw9S8zH0s77ai2ii9Oi kK+7MP3/RQAuWw+J9fWCJo46IlpTMF6mPNhCVXVr3DOl9yEhEfxMWguAWG23ZI3hRuoDcrTuAN8M mK/JIoVsoX6cOgW9B7qOGcaZIthBthRJMY56NC3bdWjx84qi5b5QirNB7jDX86XsxTvSblMJ4XR0 EYKo75yg0jBNtYfiJOG7QHe3etREMzbZagAbm77HqJQij70zY8yZT113rK2KOKM8HeYzFOzAq+CU MnTGchlX703QyWGTC1GkjT7Qro74trPI94MZwhUHw+b+kC4o2sJPP26dmZ+DKEIa8pZJiDiAPviM kjkYXzX0B/r4Vxx4s+rxRtwimLp82HXCrfZLKAm22lUAbZ0hQV1WRgAc17K4xuGahOnO+kfZJr2n /WUyZXhYaNgI/TrtGva/herOJjPvfKtRk3ul6SCnTMPk85BL3uR20/QoJa//sGSpSRsgDnYUqsXy 6/+k6RO8lhk1Dq/94S5yjO9u7o+gQvGqQc68PiuS/cPyT7zNC9IXPojl3zl1NA4Inrjc9QlTTqJh dKveVDXkS2uS+53eFDnEWDjAh9dhVMUkcuffB8EqgyI275U3D48iV+fDNok7eLx1scWy58jGY1Kf irGfpnf+ZjwwUIm6Uhe/rXfjSFq+DexvMwmd3JSyVVoIaHnV3HKpTAZBSh3FpQc3335KxkDbyIfd 5KvQWE+XWimyTnLYOMlgv9+V0yE35XBebFUezUPRAKtPvrXQgxrHsbBfo4rs8SAYmfXX/mwsb3y4 Wzvd0AJ4tAoHaDWy79koQGpu42E1aZV2hM8W3v9hcg0N1E63j0Gg3yUhrqAQXMg17XK1n7oMo69N KiLVPhh/yPufFDIxNq37aAA698hU78nMv+w/aYNoXE4FQQ58wPk75fy0kV0BdaWUm8K+GeZ2fH6c Tt91U597C3iaf4NQJvzDnWo+1c08u+AfAxalmCFomRirMzRI/vtgFHBxeIn4e9Dfd+rFro0LYJob EGJxIGk0YFJGlfL+aZirbFtDEj7Sf/EgS/XRcWp4vackoOC3BASqCfEEfLBqYspnMmv0395ibrG9 XCqTuUawE7qq6d9QO4RfJWXO7kbZc2DCZ5odRdgZy9Y676zoucEPdcDP0Ql9Z5fArCxn8IpGbhAC 9SCo4MXHJmKOBW0xz6qiQsJiEKcPfOggDjHWGZPyNQ9zgRGvulbHmdF3JE8cP47UsX0wotWIzkgN 2L1vYZWTqSTEL5s3hWBK9vTHFpwf5I4lEFWZY08fd6jIX/irrX/ayYjhSUWDKTr3PMZwQXBp8lW4 2RIWjJoGTMTP5srj5NfAKiHxpX19ySy/7YbQdSUKYyz89fpUGD18ORtDIYXlDFYx9aa0/feSX7s4 pO+Iz5wowDspHGuoqBK+D7BV6Npfd6mJ1/8RRMWqKS9mUPB4cz7UHB+JHupIqiQsFI1cW2Ajxloi utNQOgsbfSPeo3i9WesYxwxyEQBYKdtN00diHZEhmAwGeSyVCXQ2R/lho7SIz9d40+M9ye2xmTRr E/NEhmnZfIGtu1nJ+yqzxHIgWCTaRWVbf0rcqLPJTbRbYgKm1R4lZhxV7CZsKF29GE1t5szbHT8t JiXbJysLkucFEOAhA8NlGkUQzV+1Ao9njuaTsQ87ftAgtYWiLuM8DzsNMPeoOzyW+/063NWHOPcO BgB2lkQtN8MSlwEx4eO8q9KU5TdK7sLGz/JSuSIEP+yc6Jyf5aXyRuDK3RCfFLBOcw1M7WPWxGBr O0TjqGii9CrEmtfJHPJGBAcJwn2RYmBLY34AkNThr0iQZLYNv7eNaXtoDyB6ncofsels33V29O6G M7XQ5cwDDlAMokVpmlrPSRxRStXfv4Jc4GQm5r/FaYqPGFx1iYBWkFmUKmzp4k9DZgqGq2H/KrVb FSXj5Huk+FGHV/u2Tk4uGHMzbl/xYYiuLhGowpsePBs2GftRoXCRaN434a/HcCe+MFmg/WTcgGej EqZtyRHBgHCok6aetsWNayGJiZJN1dtkvi+rw+RmqvdV+3o2W/D6CMpvnQxNqpTF7MeysawOg/JC WjPVBUtBMh1p2gZgEC4sRDg3/2kFg7on6ZD8ae+HiK5tORpPCFgi/HAtg9SPmu2UNci1+PQ0K7ha x5UAcWGxQutMIGhzHxZ0/KqcLAxSmxVv9ZkLSqJnKSqFMr1Ah+jNkIE8HrW98kwgpCWSPkvsw9oA YRSyVw3dw+j18OpIZZ9S5dht2z4dAKqJ/z3w/P/kCEwNcwfmHar+zD962MHkUTiifzPUJl8ROPCo i0seE1SBxo0IT5wDFY3m5B5+IC272dFrhIZonG7xUMO3IMLljNFP5vFsicy+4BjfBJ4RVbYSfkGQ NajJlkpJ2p/EqjtK8TXmlgaZ+fsilScIza/yxhr8No0LZep/Na5lrNOT4gbIPIlL4NuOm1j9zNoc LruHepY5h+C4p2iXdyo/OTyd2rYuHuoFMmHlhkkpeZ5FLJhpj8xqvSX82Tecl4qSUbx5URxl7wcQ OECKt0wdqbccpse329cuLwEW7i4GWpfUZLFePtCQkOa4AEpaF22XNaN15i/zePmU5riOVVtt4pMv E7aKDrfZ8+oDnyJL19joQyqqzYa8obRPtxqh8TsY7gF1CUqEP4GZCkgrLzfKhtg5EYtzH8CxMdnQ 1kKmurfYbmS7jzALEWyOCWeiXfTtpsquLicRqUpP4tj/0Tozr4qnJ3rbbeaGF54Tvj7sa9Y6lf4W EhZBjqmBrS6tUU1ACpkXaZxEanyHh6obevxEBq7CnzZuFn9EGl76jPfVmCOnMFpMxHN4llJoTo5Y abtj3YeF/E1B0RHkxkLh+GEkQ1FpJPZm7gcI/rH7hWfGDbfv0gn6HVoAffRqyQmLT70Jts/0CDM7 gsn2zZlZJUoT+KtRflJywq2jSudECPREVylMqPHmO8a3+Vy/ie/oJ/yHKmNFB/DqgGyUgpBKK1Om ChJ1XatejUFxlzpmB1/8GIbGPHN2aEKg6gAQJ5hl+LXGN12qc6L7vSoZIBNXYRF2aQGh7elOFU7A bv4RWtg3yW8u45qGWf5lzB5cmHtkzTpLQdwy2QwmUuA1qLqjIyZbthP7Rg9Hhkv44DKI86HhiHa8 gEoX+q9lbdaUGk7DLgRRF/kNN4MfIbJbHV0DVDxYUnRSyrLvCB5WOdzwIYCHmdYfI17Iw8CH401R Y6SHB92qFN0fjyNVEVkeCI2V67LpaB7R2uL7VD4pZf4ciyyX651Xyhh5WPV9Z+hLcLh9QPt15tGm a7GrB6Jj2AXqoByESiu9s8l5Z/SBfiLbJkc9pzJH6L3LvCNx7BLoL4aK8O8dodEXCJSAhfjeSiIj qiWbAR01vsCOgIHnv5Vlmgwe4FmFr6taXvIGMDzyTzyB1ueMJz6loaLwdhPgZ/m6AGx6/rgoUJbz Yhs4hT/LiLGeSg8r+tdyqTbNQNB+p7sbQHMD3DmNVysvrx+PBqk0yn6Xozdk3LWk6240dbnsTfkM v+htPb+TeSltnO68pGfmW0XsjXPx2Rwj6MVV4V9hKiAsvFSyMi2fQyfH5+Wa/jhgmTIX3m/nnfIw OppnOXKG6S1YpkvdwDOSOPQOadsmkG2N+uLatxsi9k5qFMVj8CQcsq/5z8kXHR3LwWazK5KdhUlb 5u2usZVhPwEeBzcG0fBCF8i9VBXLiPiU/V2HXHMd0R0W8AB9UoqsTkqqgZyqLQ8Llt+mP2NtpfsS PfnJvPtjSxa+Xwf+Lz/NMl0yJPRCFMY/1XehqK9iqdhVQrbQF898c7UVZI+x1ZCJFb3c7PlKYoqF awGKc1Lk1XHqGTpPg30eZSHuR71tEKTVCtxufi/KENKqXoONLM9/0av6AAsD6E4gzslwYsIPJ2mq V5Ht4FX9eB423c436rMlB3L1X/YOlNVYr2jbFJl6GcCYO5YXqX4Ds6xD91jfCVDDR7Nonvc0Mmuo VDtGYpBe8pqAdEyHTNjhhZ9VgJp7aEiYYZaFlYTeakCvtZ8lIkPC8mPNZ70QaJhYXKXQ2DXoSmVt Oojdykx5PyrohuHSdS1+3qXxMUWJrVVWlrUe7uU8Ykm8SngsPS8fEvUBsPCDxWTkWjtgCvMRX7WA NjHOPJUra7WJjhY7ClAJxKf/yJ2F89u50coCG4efr1ajnuvC2JKomJ979/DrnU806Bbyon7I20Pi +ZrSyDzMKQ3IM4hVSUV1bgXE6nxT43NdyYsy5D5VaPC/+jbV6XRuBWMtkBBm8PT5cwIUDSqHlDRP 4lRukwra4pbdNfbLPE0FB2IcXX7YE1XB/juIxBgA41rPvk0iyjDD9PQkNLR+MZRO+UdRTzf7ovYc kA+O16FMRnvQE2Qj1IAwuevUBIzgm7wCLQYY6hvQ8oLk/G8B1yuqK/CG7aKchQP9FASKmTvVd8QI 2IhBGzFRK/+kuXMHueDgTGjalfqTuY9QuTkDGHqwL+1thiFN37BLZ88MVc+xjCcGxXF4jFY4Hmkc 7ISBK19wnth43RbNKu4MIwJhHAPcFwchumXMlMa4w+UUiQX09B1u04J9e2J2GTgSizU4ASSc4uuf P2jIieXChYzPWEDJ3+OPOqxCQrul1g4QXhEydHaxcBw4hAgd9WQ1M/yrNbPnYyqNAahl0pebFF58 skjQjxr7UDlgq/tpY4KSq0h5BLqBo+El2iZvA7s9XDm4CR9C/KyS8WdvWynStPai08912vREc9IN b7/opW9EOeycpz9kado2gj+MwPuSN3jpcNOm0MhhIvn2qEE6Ewye1PuleJ0dDiEyTckYLoptnPvT VGUDdN71CbtTjHOyxwTtscpubI0RepIdjC4c0zWTta9AHpHbdvvaBOe0DVmZLmsW50LIpiJX8yh4 r83c38zf5khQH7AkChIr/z632K9tHdmJuBH9swai6/DOf7bXv9R/6PZV2FzqwsUxXyneIHZi2mng p/pTRjMT9RrCKzUn+4doJutx+S7V8HHjyoJ+IoHC3OFW1h1jSSg2fNou++8sitO3qPiqWedl+pmL sTapSD3GE7oRoiQibkUArFhgR9ZM8OlG5Mp8YxXLJRuLT60wASizR9xJ7OaQlDzc/zsYg/Apmn7m MU66ttbYHW6Bly9TFunkONmQRpdNDEtVC5UX/+XiOvdjq2ZGNRFMKIvtkIaJnXwrarkTENhYzGQV rH7PnKtaBEJxgkuAgTYGQ+T6TAEB2SUxKiDnXUmZSUrUTFaKbz1zZHDIpdcdz2Z0Gf5oziITKHGn jkWA3Y+J1kt2VA/cw19m0E9VXlSKnUuKUrcu7bjq0mmrJLW8VyTYfndeG8phVtiSCaA0HpNaXdPv e5AbbK5LxVJusRTTEbPJ7a3/5q2jExg3FHLwZkLg0coW4dm9SvUBT1t4E4cpxXCStf5ZLrmjkzov y5T5bXCD4ejY5jqpFfQIOTqDlTlqungSu/JPq+nDEGLQ+FENA/qWvPLGFA/GgeLgeZBAXXReYvAm 2fqhhBish/M86qQKaVzQcmpW+EkKrpbICXTrAQA9m8Lg+PvZr98E5CsUJ16iTRHyijwwtzoLcbkt FrH0v5t9btcOj9QRxXmCKo6w8IOA/awgO/zwwPrENZpnKAqhfy4k43V+4v1kh9U4Xl8Bl7wOOJNT s6Kzu9ESh5TTeW237yMH6l+gvBZorkvUZDH93x364t5bYWw+CgR1Q2hrcMWgj5POpHs6qkGi63oV 255lNeEEh7ZZacXLhGOIygLbe2DLOZZRyNb0oVcP8bBUhvgHS0NIz3nxNn/vxIdk0CQionTDMjcN V9Hq1uajfDc1PRe6QWnh+EJ4H5kH/DIdqcqfQq7bxd44lCYbNMsae10tBvZFJ7xBnvnALp7HN6kE 1THyckX7a76gmdDhZ57BZzEAGoAEzs6wdUn0lLsSFSpLuDr29l7tzc0jVSjVJmH5oX8LgTVKUBDG adAC97pHqCSGVaMTe1xsfJ4/vhijrsNUoSQZ8aYKZKRDfqtJA7BQMe87ka87T+bY3BDYPVt6GJ3M yEprWhNs/RfpghDP4KcmQ/FLuSk+G/CRFgOJ581me9UJ4u1oRBlqYamExmtnelcw01YhRh8IW283 FOB/00XDOGtekae4LCop6gQKYMyi1D7y8OJiDFh/5sJa57e/D6eSqkURmfcoIPuPBtpuGxdNTQVn X4cfVHyn84r1HkIPn8ItmgyOe1Rxzv6/ZlEwDS8goPyEPpRdxbltJVJ30D+yWR2T2bEcs7kx4+tY QHTCYCX2hdwj8BL3Bi5/5mL0xABlB4s0NKQ6wE6iJpmscUtVYHLDSwOL/O+dyoNiYP+3be8P5EW8 RGaVd4LXTZs1I2MyHyXhL8kxwZPIA3uM1XiOZ31QeUjJkVRvJViMJbBYlEjyK/VPO7aMzKt/8FTr IYOJFAekEGbtJm5yo4qEyVqXJDQ8NHjWbyXBBlbEDQT3rij5mkqmfEoDz0Ef/ZHEMhWTRO25Yc9P xk3qLWHMuZjRcI/pwXz87d6WqXDwedlpkD9E8nu2KjkRQz/MNdCN+R3zvz4XYoN3vTXWUSbvZ8RI QItZYComwHzHLeN3bW7EB2me2TkrKaQF9Ap3n0OR83ks/LcbV6IQfQNsgYnWRul1Iyz5pXOK4kUO /S4axaP+iho4Lx4mYRQOTJRi+74EeNeAls2z3CAH5HpmNJKUySQzNlcO6nh316rAMX5JF2spmTSX XEo3Vflj3uTme0ZaJ1YExy2UQUh2hInnQbFZpGiruXUmr09ZWv7qwbp2FSJ2aYPdMLztOHu8df4y Rd/Oazuh71QRjRiCuW0vhfb//zod5jNy0+aeuLAogpSCKfn0dC6xtXhyNClYpEzZhsPscGll1jGo M80qkWEiEX8mqWPswxy4GuWuzseB67mNRpDVemfsmoOOVD8inNc+uZCD/eKz8H3kSAJcTpCNgQ0v 7xD8X8OCwmYQ0M0xQtUVAydqIte50W47rdQtzwnMJh9OkTH7qgphWFwLPsmJTJLwuJfLJBaTLkWx MydbeKDpbeWaNIomqHwneGL/++9hc1505AfyaXrQhtXFVJh2IB0+RN/ph7HKatcOJ+MsFMAku2xV h3NMgyHg4dOg+Srjbc4yT3dUiJ9o91PSsoGf4h9QxalnrAex14RA5ZQ75auBbv70J8uA84XE4Jee nsH/5ZqPGXYy0I56MxaplNLlBcPypQHaYUQPSszZNITYN8SV6GrEq0sFmeFZirEMD2Z3ikUHlVIA 2SD3ogFIz+zhCvUcJqnLjgS6blDf0G5VsoJ0RC3j27CjqIgRM8yaPIdtRt2sbfYlzldIQklppzEr /YeKRSQOtpSMmX3K2dcB+4oOGpvhJjHGCM09eD1gwAisREOMolCsHXPeUE/yO6NKbfZoLyle1sq2 pUaCXRLHF3wUik4/f7plTVvYzmGPwFOP4zyWYAHA+mFSyc4o6pbsqu1RN2hfVUy1ClETHMqOa/ts ibjIM5ABzZKDF32l0OBaV9sll+Nj+NaS1dgBnpQbf3mYTHvrJKhQD+M0K0My+T3bTEOHx/i5t7D1 yE3+xR8xy2OmaJcPbLMGsI1oQEHbE5fcYtvM5WVXm0+tfJALs1NhoI4G0gg4xV8QuA7Ugf3eL608 loW24dKBLWTPtk0so+Cc25G1+7orzplMlIc17wmUzIm0HlDbHSkvQWqewsiF90MdR+BYcf+IhrX8 YVNer7oYbaAi+Xy4q/1SctzDMkKuBdVFmOtgjEUWR8B/k40IY/zfMEemvWVr44ua8TqGo5EvlDMZ CrggUPsfbgsMd+vbMjGYUnY7qiZ33s57EgbJeZ3kfml5/0gq5bR3EnBWyV2ytfy2I4GS47F8OdrN UeqnygcNisGFIhtWGUAL/6CRhr7yHC/+xpI56GbXgUuWKiWiPILlgH+Fksl5RMb5HFhwKx2/nWpe A6GgzXa2Wxw2kNDZt7VRnzb7vh+HmXas2KpQcwBWTyUUyYjL3LDWfn6AN0/932xnvEnbECLNpIFK yKEwKPcTWwEy16sRBtyDvZ5yLdInfaZSfn4jAuBgYBlPhqPkZb//iJjuyq1lLpfJ2gmpOsTRIRmC xPWXUjLI0+2tPJhIfx8eCv8B5C2CpZhLtTOVKIfQMyza5TZqdifrFnf2Mqk1rRJclhHKZVF0CxIQ cUWOjNKObazGS/6/Ncs7T5K9DT3IYeaNxilW8UnllJlyo1T1I7oYlz7WbxqvZktSrzBZzpMu9sU7 O6Jh58MWTP5DXj6hhpX3cMNkmRaTZcnJZ2ZNu0MXDulqg/lMba6ydDMI6QetHdDlUhK7qdmCnxP0 SiZ1RQx04kpuf44aYkrs3BTgkt1njfBPwWyDS5ns7fTlOqgAjiBC5VCSbyljd5N0dugl+wLlPdPi LI31UfjJCfinDwFGpo+p2lVT/Fd5jbwmbaobmvuQ0cBTGP0B2Gst3ykXD9OODasYafsgWYlsQ2mh ZgijQbb7FDDWw7KSMzq0ba8pcL8i+3d4jZnvZOsmqhMmpluo4lVwC4rIf34GYhsssDqwvrsLa+Ux IKssVVIBvNs68n09xUDH52q1k6BDuK3940YidPKElFOLEKCGLVCdIzJhMd++bwDsySoMFSi2Z8m9 wlI/6D5s6WHp5kkm68j2Q3Oeev9cV43GTVRWTEphmJJcokYeZ+R92Z5Zcg1JqUavk4EhakTEcmz3 1TS/33Rch0++fxuU7ZxCe6xcVB0r1x1MataNO0E5exxGiq+KXQh/QrEDXUwDzJ5YdHuKtbi2sCED niaLxeYOQkpYneBrD7mchCFMydD92a5HzBvxTro3zD3Er8tw8XqMYLO2F1K9oX+mxYGqLjJGT0+h uKBhXMs27YzXury9s+hBHDKpIhWS50ZAx2eMpYMkiEsl62lLNryzl6uMBAJ/lC+hBBeR9vkE7M5b Z91Qmmm35dnv3q41VPodJ8W+1sZEny1cOhPMdmDWTYhPYKWSIdRRT5WqinRUtp0qL8QwhV5zz01r N1UgRchDcJbsMOfWfa+rZhl1weIrXwMpuAxP/Vp4Hee+afmkNFYO0vBouAyUQxI1/7xkkTuvwc6J 3a4dgi66j226fVP3aRiB2EmpMKf6M9GsiDhWrxp5WR1luVA4Em/hb9tngAgkTP4hwzyJdVIepHoN HLcJXB1e13iQl/oNm8NmW8lF9EB3H31OQkqKpMBaIpVFHmIcBeOdARocpCgzbCOg18HXWrBgj52W AxK4IvhrCd6Hw4031QAsu2dOG11L94soruhXN4PSmXiVRhsZAoCwlUPGYVQmsVy5Qom3eUBZbOnP PaZDwlzZnCGOmzpdrz6S5vGM7ugulwPu1Ggf4LVrN9mEPaJPRLexRskcHZQRnf3uK4l7fp/JmIiF z5hyWH/t5F9RAoIJs4QiWG/oVNo2vD/4S8tHIGePkV3V74j/ZR3f2eFwmPqYo+RG7FPs3oeva/LU POeJbQMkYCcDwQ3wAAEQbIQUGVBQ0cJjr8Jwdgz9vfFdBUWMYB+myBqWp5fsnMDslnkUUFNDEWDT YtaRLlPyj6HTldJR8ToOpwPeNkWjOkUwlNOCTO0E+L0rASTOwnFUNekQFVJAFt8tUzIEAmckyfoI W75d/SzzvT5a+tHfye1mxJAimof25G6/Go2ZCHcX4vvE8cZDi8XX3f42jg/iyHeWbXXhIApyoGPo S9oObuu0HrTypgy1xZ+iQtZKkOWoKvSEnkfYwO+BY8Xc9XHkbD2ebDDNHLlvikVTMs2hy4DZ/gH4 NqwsMEuOCkgJq0B/6N0bkH3APO6yjGxEeAkMq22A8cTEJJvkg8Y+h2PvXa82K18gxlMhgR9TXl11 u0w6I/Zqf7LeL4PX1oajjHbxEEot2O/V9+BxMmCUKCM7NgEWsMoex/OUjN+bnEC7qzsRb8UVNPwZ ZZzay+8eqqNXGZDJ9euZTeazyKac0Om0AXiHZcwINHGTfnQWYLTBGbzj4+FEEc6HY6e+vb8vxV2J Tqio+KibSS18baPj3qfRcKxJp1ahrRkMd7BTCcYQaPKW9qY3hI3VtXWsrpVb2m9ZbFYCqZQl+0VP N/q3GqO/70aZPGvh0WmgMWcWumccfAQgGOtZ/V6GShH4/Qp0EqHnNfPqfsQlbVPfMdeXsFRyJqGZ bps/93/mAFX+j12lbYY7mdXqX3zZFkCwouGzV5XgrqKAHuI2Jl9N/0xd7rqScHIIlN41amf85e5C /HCGQb9+a2pexOGLyx7qtwxbIF/l6uFaiBJXPspD89d/6kSbMZ0S55rmC8SL4aGzGOzwxeIW1xNk XrFf1zWP2nvoYiePkao2frXLyUdxBbG1qhjZi1qoAwOX5upcr65eutg7b4gsJHv3OrUQblTivvRi GxbsO3WbJL4/iRSNEHFGeFv1SmFAPcizcp+x886mqAoSUcsnmM6nd2Aa74X/nKt6rw91dlAAxfpQ 3JOhjko1NP2EwX75nk9Qhzxk1R55pTxVn5/i2hRO9qhFisBpHUplZTzrz1ZkgcYn7fv5nTuA8tbw oMyoxcmur1ozs3EtGcBRN/q7moEtu/brzScR4r1kZlpXdFbCS+Ikyau6GOCf1dKQktT1zcmmxfUN 9E4XhHUVTM8uahUZoNCDz0ERMC4SG8D9Vl1R6l5Davh2ur6XZor8mVHcGzyXDaHXZjpa1mvHtSSR yifPNc4ad1sDsnL7N31A/3r2T+PWeR+fdqbyhhyK8sIOPB3N7pUnQKGbDQyyBDrEmDjSRuh9RENh yntYLWqrs0ZqrYh80w/J7g/Z1TpJ1BBqUO73t+RV4jFs1UgQ51rQey24slJiO5UwSA13n05wFpjZ 99UTxqzMJbwrnL+pYZSAMol/aDOsNYQl/mCVzvV8bUYynw0TSD7WhQ1QhAl0tRp8DnPDoG83Cwek Ckk8dTQrQk4wmKEZfVlqRT6hAoAtfAkWvnfQ2ZDXsMEG/fkOen9vXr3Gqj3xefv0P7FGZsfIfnny vF/t9HzuGKrhbaRJjWfmu3Bhh85rEfig+Eo37eDE2szz2bdtGznpXMQ9hckufbmjhcaZPBCvikOi FenCSJmwzNwG56diSfjGIoBWNv/sC+8lKRgbo+6Jt/UzVRuPOhBvlzo2iVsRfGK7XYGcF+UApOyw sOgxmd1aPMCT4q7jClW1mpXhhVIAYoNsIJUSefSgdhzD6EZwoX3Fiib6RPv3px5tiA+BLgvyvu22 5RMVphi1PR2QR1OOjbLe8rYbGmTlekDBiyCa5+8iTOZFnbH6vopssnGJlARkamPnjQuzWs3LMAj5 fKl9B9Fa+NKhNS+4BTY3XcWecZwgnUSUJQlMsH4L/YRCCpiPZvoAd08naR056EhZyHhaw2pqtk/F Yd5A+C+HgHxaTp/BiVImgc6PvpVevIhWI+aUxM3vS34hOU3PsIqayWgeVVM1262SfFRAwQ1TjgUT EMRb8Tkbbf3PIYrmm6kXqlJ9Fm1cFmkk8sTH7HxVp8nW0aja5OhZ3f9eSBGOSjwvXH5b8Zfi0e9U 4qsudpJjAru2AeNC+4oBTDXg7fmZzbAnmP3VmPTTkyQ3TdAwKmT+9ZDhq9TBp+CdRwNvkaHRoR+H ni6A0ntvG+0dVG3E/xbR8b5gayZ3FJ76ZsUTdDgbwYUY906beZLgXkKONi6ZmuonsSIdiPEQSb5/ D72ZgLU/tnscHtzNcN3+aS7GCdcnOB7oloL2tAbcmZsV0uKcOENL+Dxql0bRDzBOC2WB8HqHhjcd 8qCCR/aeg84AgD++LVgBHKmTpCmHUdP9/0A8ldu8n1gx3pUdkSl71N+DwfQiEGb+k+/q3D6F9dh/ 0GSQrGywWPPBgrH7ar4qRR2go3+RRgJZ3ceJRX6Dh2/I4KPs8YzUhVlRzDJ3bEpO2aIbJeFUWXko Nt9KJBpx+ok+2NIZP8j9TB+DOdGs1h9aDP71V+JfewWQ60Dc/lbOaF3B7n+cppjmHOFx3268aT7E +NxjwMHMN62eArTo3LLYe/pwhimA2kziw41HJMxTg2TfIIHh0DvJoBN0ZuQniIgQdPWr24uh69dF YJV9AKv+j5ihUEBXJMpdmul+EwenTcZDfTbJwL+yuibYbIqGoO2zw/gt+kbW6pubGO2nmYtICOLp DtDOHA2aBPvMDMZB4/cxImqyhxIQfZdPrQHVrzzIftW4UybFfyLSjxB3ckJCa+yy91lX2KgM4HmT 5Hb3Oq6WpbZW2UviwkzWgFwvSCpuEsiq9J7gAKCg6dm6LwzORC3sGXu9D8M8thBwPlnks8JzJk8P gpPVXNB8ICK+A48RgU2qTlYUwuKH/CgekRLTZknTxRM9Wo8Z2FiuI6UgfW4twPto/lAuxNgFfsjk Uh8sXH6Od+jlDsZNlCxSG11DqfYM6O9P4q9xBBJv0C8cGYk/sKKe0k5Fyf7KhkYUbFt6OiFd+SNa tKQKUcqDIiXTl8TD9AtZtk6VqhN4ip+pR0z4xOCoi7+K3nRhkp0GQjIH8InBEwM+BOqZlkqVZb5/ SQQdOScTC4+S2PDODmC4Bf5KlXT5Cdvqr7P86C+799GoIBi4oRN1us7tHjF3VKtltMrjya5c0KG8 1UnL2mJKxzMQoQahcuVMi4gwrg7hyknqjKNgVRbp2DQ4W40cFcxHiyhnOM12SAJf2qtidKqOATxc uMgCPiWWClHkck+GkeZbSt26znHtYIj+H4y9SiNvNBIDHrEXXi/afNwUQ6E+dRqRVa7TgqfOCCYG Nk+S94ZTyoBOT/SECDOSnP25Boset51LN54jgk/maYfVZIlDaEx+nPB9oZ4vjYkmXPg4NmI24o62 V0jHAEFJ4Z+hPbaTnvUbSF/2zg40r0Dkg9fmc4vkSOx/+tWf+hQBsyaVYJsyh5EGMR3w3zdy+ROV n4YiXqCuPXij2FUmTuO5SHdZddKYZ2AbNOGRnwI5znja3Dpaddxp+isT/y+ummb8oNVnW1fpG2AT 0Dr0Bpn8EZ1BdoROabtIoqin2r1o+3vEb1voiy21szL4yFX3EDJNE5unydCLPPfUIZ9GeC6pcHZF /pweaUk99g2qm9QYUfef9TquQuH4BnldULhAZu+8BRTwfOCJz3zwfEcy6QWgnRy2nT0ReyUsEbI6 EnBzPuvUfLD/+NyPoYQf89JY7iK3XNe4fZUUJ1K93Dn80iUIELzApviwRlzK7rXR32Le1RM4h8n9 zKK6es3KTyJSn3gsPdXwWJqkQyDdgGFXlYpUlhSjiA+UEI/XIzcNuJvKFXZAyOcwx54jsB3z+FDE TgO8W19LgoBTyNTYGFei5tnJMRj6mYXMv+g2qYUCB9ASQbCJXujyvsfryjkvp6p1QcYl3ycDhcmM dpJHuTJEaUimP1H4X8InqmuVKRw09DZEGK0jk4EaWd1LCVN0K4MsaUczEZPOcCrBLrr6Bonq8HIW bXwPGEvKCLmiE4qEyV//rhFmHW+wA/I8Iy0ICkYMlnO9GRPZngeAIqMkbWTlgUZEWyE9KBrpPapB dGYWQ+2/p3nXW9ML6ZGwG1GCPsblVPXPCa8QtktlvlqXkCL/9cF0oXUHJI2NKRC8QCTtf44gNDDM yvB2zrMpJgN1ZdG4G74kPsE//v5BlMS8JOB0PXnbek2cnrKeOkeOuDCvIvQE0W2qVUTGBEUrGWok zVBAG75oDi46INSibyYsuSDx6b2A9+iHpAF28A2cO9kFnq6hIlKi4rYNJGbHerl+iMRhl4ZJoZyS BtVnkqvagFZSn7SMOgE8K7bIwobs1JHonCgROG3cQ93DXOtSRdP4kbDwd7EBptvUK+A/Qc7vMYC4 d7f/rnWJDW1l4mOHO1tEF0fQIQU3ppzVobIyF+Xev/75PdZXFZEBBEplkZGo+/B3BNQaDx6+BYTQ LJresxOZiTvD1YZHT4yuGxkX8q8kopPBl8CSmpOsCZh7KmX7oTzkJSWLlNJDeLyM63jp91jP6HpC fRek2X7lZI53tl7bRtwLZwOydBX4/D4YesLXiFDib+PORxMh9UUDCHrvzToxOPyS4XD9n0lXsyvh RCEBazWE/fxGSAsqmbq7pOKqqwPP7PjgCt8Rc1JA9sIMKjg16ZjIwPkFsD3t/veeyCWqxHHXefuM HwejJBQffUOKFaPiI4VKHEH2mjpULNM/zW22HRor4FcTMHXtXSLrJbChywDKqhNoN+5nvYzni32E 1bnTPSYuiIN2ZnSYre085ooHB5fFmt6ErfonVaSbeAxp3OUOKeNSjsUU5d5RYzfYFIkDBWKjB6Nl W2dHXrIlvQBAcndPg+U74J2+E3umQWiPpO9eskF/uWf3JqEn0Gc8w5trCbdzyDUW27kL7EDq1CV/ PDuEgEHEv8PXsrT+B16DfbnciieBnrcSpGqkBQMea4+gb7iCjdPv90l+vnPfu8WSavYi3VqEbC0t pvoOcFjd29JE1HxnBiLFKgHMnOVvJPvBmvr+jJbVtqDMuQHukFaeESh49kdgItX1ddcFroQ10e7v AtAcmWuzvVbgh5l5+J1enHlSMpbp3zLNHshFT1GpBY8khOXP8vYzs3OsMQ27ZkxDFwRqzy30PfCZ lA0ll1KoZxjuRI1zATYTqfYCOuI84s14OlIZLffwW91hHR4hp9Lm91H7/UijvwYj091KLY7JWw5R hxAG6YbUafLVG0ap43mdBXTwYPMAkyOJ3lHmpd5gOsmcGI6wHSScNgSaKKTHoefuhPXEm4AcQox8 F31VrK6WXCsi+LnOAtNodc+9GjWI0/k3LYazBBPfDSvhRIWsheprkvO7r/kRYVi4EL0LFNIVC+d7 7EwyIG1P/dV7K19jLeM4kAU47QAZuNzrsvBQvAyZ1ex89y3oufJO4geETch8bqh2s2cu0FL+gTu+ AoSylNO6apLbqU24MDtS27KGAAZPhbGwqfE8H/fPCMHk/f5/KsEilYAhro8xVB7mc68PJAzkq2p+ 0mfg5g0OPGzSOkmL+aX8eT238v0DRoHaPYWhBAuaOewnnlKOUjs0WFV7Rk9YzWRJ4hExnChBZ69O 1GW4ZV82NLWj9IKt5Pwn6lRLbSAH8GZ1wQaQRRC32998cweGJZBqheYmuruyB8x93aWbPaSG84IU 3ejtQKXzcC+7tAc5+/j0sHh3IhbqHrS8DGHG5lg4o7WDK4MYAig8m2bY8qFAJjwFRONVzl+gyB7N +E7y2+kGdFEBmtzOz5VRoUd/YPh6L57g5fSAdd9YOfthX7dwfVXi7kb9WzK5kveAvbegPOKctF2M IG9BY0EK5LKaH5yvn/bsyUR6Ded70uQ6ENs8pRx9GfN53EAorJsAfRMjoHMFr99QgXLanWza57ei 3iJY5lZsdf7Q53JHVbIQzwQf2HSwJABSHZdnXY4brK6aXEg3chZGqeMrFaK5zeEOKHZbb4apxH2X 0eT2Khx/SQ3iX0XoTYBEa4+xhFiRs9qmd7IBTecyW4Gjv/uTog7sPEhM+2idAd8OXfIbI7o9004P Jb6L4BTdyqGd2DP9I91TLkMXCTgIixNILJrLAUYMz6OAixSngksa9IM+pZUCfn+YhGiuHF4pIX+i ikVmwPe+uOvCNc4Kdfb5QoSoxbxQs9janOdhDCmu+GCucVi09O0mS2qk6fS8Yc6ZEYE5soTv5crY Izy+c30dWuFvdIEnJqGhp6af90X+JujcH9wn7FWznIzrm6WMvDiuSBIxhg8PPMhalE2hkb/VL9tk POV9yGONelAoBaCbdx4LPZYTeToGZ6hwEvVg55nSFoMmFzSajDBJPWW29C2V7N6ou9mnno++abmu IqaIGQZgNZyGqZju0PpLOxa0WGNbN65MUQGq8BX4tXJVo5b2kgkiZ2sQrW2BegsWzRvOe7EGDnfa 1gN89l5D2vUpEzSUlx+TRSRqmfjPT34gmxHJ/sa1uGNEHusnW+paVQ9RGfzbhnGkRu3DS3ba+qu3 rchIIMuKKXn5nME5tJJSFgmX1OZNpfENxcRImvKDC0Z7cL6tVJhnyFf3J6Z/qj441HvtKPtX8id9 ev48BhPxDVRcCbQI+74AddJxurkXXpO3kYZHO+XE0Wpmggdghx1rVAly2+AZFOAXX6PDAn/mpbbT zYlFyJAQ6LAUWH1pI9pVdBOzVglqdVYrUa9ZAOjdKn0vvbPlPPSpydmDNPU4hSgO8/UxsMybNp4a hnQR3WgYrv34Ycn1ZbSH+18vUw5R8sSWeTiwf6Egx61v06KpFq957F7eBCSWqUynOdUoBzGKzHtV v2Bm0/6vM8esSRvlY9AVgHwJvyt56LLPZaNH/EJ9jOaMKuRYjmlnN6SjuCPGB5QTMHXPrp82HR3P zo/9F6lDEIuYgJLsC740h1XarHrtJ/NLumtDHW/YszvOs9xsZqpjNaqLc71yxz7TgnPHE4AsxzXf OZQXlRgFi5K1sBRAqN6uN053jYurvA2aoUBCUONAiCtFcO7umeh//Qjx4zbquu1Yc0y/1lboybzT aGv6PyJZCFxmZuKFLcH2HO+fubH1DADAJ1zNQfXT4QiLH4L5YiEzRQYIYBteCT36sbb30YBJMI24 NgVJH/1WL9A9zRj8hKgD/pgZUxfTc4DYLYYbjOZI1LFrVEsa7KRm/2bGiD6vKLn1fsTAumUu4X/2 VPATiC/TBDdb8oAAWkjE5jbk7NV1w+YRuZKW8rYx2KPgu+V+wi8oC18b2PBWLpUtC5c5wlK0ALL5 b336/STBnYLsiR7pRFBd9tJsyJ/hvjpFXOkqS8qlphIXVaRV5itvJG+D+VtB7f2VzPn75B+e8Pi2 5bTxkNWttTdUSV/qSjGHUh+j68HtMlG75BS9t5jwRpbQTuE+/ymTOSnXdRzz1IKG78NsX7x5EL6m I6YCYpjQdlpH7yFNDYuqTGs0uhn/vJlig4v2o7oRHqSLaP8+mc32AoqFPb/u2c1TOsSk8yjhxCq3 f4Q3UaBAGSyss7Lw+JZ7PYi99u0zbtoeQFaoW3BY3Kr++W4gMimhGVkXyOnm2bPPGYqo6ciz3TjD fFQvYS5J8kkOaSlLEsIa68AIZ3nEoLAG41o2MNhvGbM8x96vaBVQ9wt9EOtk/2vZD2XzgAgbM0dx Y+tjGELszYQX1wCgKzIfBnrE1CGAG6YxrpGNcW3/AYozCj+hfu8Q9AlWaCLIPWveXZinlmk4d3Yg UtJ2PJe4+1g8/arYZBlTZOaZn44j1rQDRK8NZXohIXlEfPBHYoc/lDnf/hqDbVMAw702aoAJ02ds aKLcI2NnEf19Ea9N0qgcj0zx+ID7auMUOP8pzsl7gtOx+kj47rCYQymqBTxtmlH5WSe5WitwgzSU 7iim1U0Fy/mFisnWx7UISGRgTiNJDnDOHZQhN5NDb9yFY54EgkivUhWCb8npZMXqECkgJtxPREsZ 3KIBKFSXo63m+MKQ9Ldp363mJznZ2FfljU0GeHJL6gbWz5FrAjXjQL3kwIE/qhWLoY4a337DX3/5 LilimR9ERC0TI33+9tCl25/ZhaVxzZ7RT66aqYJoPqKPfAHunDq8PpW904TnNIIFNQhGUlFofTNU Ue7tuPTeQXwwJ6o4aeRxkcqZbFQePfMM9JZ/aDNm0HRWLzOVluY6OgN4IIyyw73ZnGgpTr38fRmi 9B8QDlnfsRJ0SNraEVBU2OgwOtsumHE2ifdLbwmmtZr85pP9rc6nEqGU2nU6X1OIa/o/IebNEM3V vzC1gXUSN4vnUc2+VrI+uPjP+3L2Hye9sp04NPTdcULrGAPt6ZZbc21GpNETlb/m7Lasmz7x7hFV DE8MD738V8NVCU1HPytytVSPvvTmI7jR4gxe+ID1x9d56NMmhx+4pfy1U4hV1lzVbd0K4AqfsQxP mDzQ6WlJkIUXsU2TGHEZBsp8Ct5q6X1kqC0soZkflgpaBS3x4v4woIqlOF+74U4UO+PfOBf8WLw2 da3dTYidP1K9iRrmzrG7mHLrrkqUvPcW0aXLuc3dJiHnTJEOtpp//P5q+oeDqiqBU6caHXw7BJpu SBY6PH7jMZOGue6KR4A6XoXoC4M0oVOYF3Y9cY2AWJt+SFiuYGysTebdSWk1kzAG59e2BENTY/wl 8lclLa7BMhTsR0d5M7jYz/DdkX0bKN627oRPI7LL5RiXzYBS6WUKVt4eOfSpH/fAThAaeYCHdJDL 4iRHUqmcdQcxVSPoDTQp3HTVsDjEf0Gw4o/vSjWcvMlg32sGXue2D+VH1sZtT6bY9xncrhpEjyXt zLk25Jti5i7x4a56iCIZWMWTG5s3DMjmskNfEOlMRSmyjFWOQ+JRBwaAGqZEkrvJp4qk4QcUPNKB xRMD0NndFbl1xQsugiJrBkMZ8dqOcKDUgH6YuaU40yP/CtXP69IP+12yeYZYdClmeH8xM51aEUyj sYgEaDmBC7IZeN1lDmD2C0jck9oMERYClbu3ZbPsJt9WlsWrawvwHWX8uMhK4YaER/u1SrOKzjZe pevJ7UXzpQONATx0bZNp9+qe7rTdKx4zEF1NsF6oK9gCeCHZSTz9ogOTJR+LdehnJblOxL+4GTB4 ylsXIiCj+8C2RTXB3Nh5t54763gyfMeHYeYUU2ESN7C/Nt8TyYthbnSqIFnaT9IJVuVPciWApH+l ly+ycP0EUx2jsIjfO39RogAZciEuKEDGHnJtuX/DF7bieDw6KP5GX9bPFfPbC9Y1L733xP0PoAK0 qCn5+mRRsiV/B1b3VGorfvTRc/xxuSd1jPQfvajTewZNPt52s1A1IOUDgWijxzjBdh47Yjoq4slZ B4NvXITWOB5i9AUsDd+IS8tw6+tZq17esUGHeIqm978Tc/pvYIhpb5MhJqrv4Lvu3+kKEarEiXL7 0zh/Qn5E2xFeRrCr6/3leLsJgtwGEwDzhtM4cDuSJSpdL3v2FK9pyQBhnmXj4wxCwXb4v92Jd246 wmVfkBinBOGGjgG2i6u6FLTrivqW92hFlZsKFtEMoR9+YGYoHrUlCYfCsghZ5EUuj/KPXv9Wg5Mi jD6YdPvmzJahmUSTJxsBZn5DpDTdH+/Us3QqihlyM/hmPTh2WGRdCA02WUCkZtS+7HrmSZKiQEOC fB2CNqJy/2kJwLLT+tT70odAoxAeYLe+NhsdG44M2Wo8zXbOhrLsTchbQOc9Anc5evxLJUcvK9ej /olA7KG1ZRR76zYv8kfcEZVCCOK3aJvpSv/j9iu4IesUNQ3IVi7ffGtACwpAM3TBVQsltAbyrz42 1s9+atWuQqwqWqYcaKoVjNl7eCSumBr8MAiuqN1SyDivvj2ulW1GmX8NO8NJifpo3W4/2jIC5dKM lPm2PNAkIngJbrxpRDRAPO7+oS0h8IKgF4lb6kSe4+SOJYCBTWuyTP2HIWGDr9LRP65dL8w6MKFf Jw1BwQ0cbU5szf+B5VyL27CxXq9wFtvUGQ/JRAGcTvN65NPPJ656GOgHUwfFQsJnL/vQi4LXrma4 qKwO5QY83g+vHf0XTDBbLtmBuzcORDibF3gxGTMdTePey6+zZXycrIUsCUvHsiSzJFx+yPCy8laS lM0vXOvyf5VNl0pVgxl0Ni2NSgP0o9vKt268HHoUDWn6gQIwZJN8V1MbGkkjyqLm5HuxFjALBod8 akAr4ycVWsX7Y0BA8Y9b7F2wdxkcqsPm6FvPyhl17+gPCq/RsTLHB9XZjq7bd202nkzYxOTeL8FN zYKXPFM9q4PeG4t7qm3UWua8TQc0hVNiJ6ryJ8Rwh/ASVzAuxM//Qvl/rTc0+ueDUqf/VqN+NqPL bT4LTdtah7A2AMc81z2dVC8HHdvjtMn6ztrOuXDdOcXRvDoNoDoFKMh+TyYbNqJmt9lVkuiiy7C7 0Fw2kXoklWpw9vGuM+di9nviJb3hvXxzL3AJUJGTeyJ73t7YB9LFnngbJnZ38ABRfGti98K6t/oB yA3/2mXxRdLhMigW+1BSrYeQIw4grgYefY1zfdCcdJKIc2CjoxFTA0/2HgmCFD6tJCR+pCO+uHif oO7t0mhKcAwTO64hvCPVDYD0E+B88aLj+/oNBAwVguhpxEbJhclPqVbgkvXK7MV/8I2/wnUsvkxY bflsIwWHVwL8Hxj2RHx2Oj2Nj7Y5XH3qQDVklM49Tub+iUBvhYQt8iejHsO7rY9p1KXN/9NZLZbD /j6fhc/GZSMK4Nw+bdFUG4UVGIoF+plo/KqmQSYGDHbDHI+mxoR1BhffGEoZvALnu2ENmAfT922x wu4uvOHinpxiEQ3XHMAYoJCAGZShW3FN+nWkTd1HZ4HmhqiqqIkstRDNAH0ls9QoXPS1q1GDa0Qj piAGQsQtSC1QI17epTFLxC4emzk5toRknSCjAGkMmKQCZ0UeR5OLA6QkmoikaPi528cw2z1AweOI t1O3yBcKP+tgipVGnOAuRcfaQK7h+yKpG7bYehiFBbANUqS3q9ILltMKEtLyggZd9d/jYpWHP5uQ xegerE9Sffax8in+mtQ1OiwVXCizhr6UVjsitT+TscStP5nNHph/esbRDsYzE+bpFI6T4JYCLJon UAzn/vvG9iqMbRZfh8kNqak2T1lVCdSx1dJPwfJL/ZsQJcc5YbkDz2x0DqDDkhdreVn2j4UqtLCq i5u0mXQTkHBSDON0+mZAXDMdIWv/liqfd3xWl65c/ig0S3MX18jAl5kTPupa6IppC9WrJac8f5my Hhse54uMm7KR8WXv2xjuqxwk55/mNnsCHHqbnyM6dY2lKNYZ38kzMMbjm2v024IVpQ3tkm/mwDNq tUSBnARq1Y9oHc7LQO3R7XBMm3Wxa2ucW6lw75bO4s/g+cDz6StK8tzWPEVewjt6PuVF6O9kzJ/i 2ZRMN6RELgDikcOwnLxueqtZknrK5h0ZYhLsIDAipsYABa4zws+XXk03/ITrH4EpmUHz6eqHZul4 ayNncimIbqbPNKHBg5zU3m0mxTqZyS2fD6wGsz/UUDGxxNEa+03YNPYH7iWMaAT2eD7JEO04+0cF Rpo36thrMjy6CJce1+D1gZ/dBOPYOlKiABvvzvLYAPXA8CXncQtbs7d/tm4z6QPYW/h4R9dluDrr o0dVFpvPuEUVMDe+RF9d86rTqKgwE4j58+x0v7NWNK6Ck0NeAsvMEr7YZbIzl25Hg/Db5bpFlYGs V4JetBZiNonYHuNmI9fVMcdMHHLSLugalLtjn1TGNuEBa4M3Vd4k/IQf7O32pSz2y+EijVxMJvIJ yr1JpCGqHP+8ZP4xAiomfaCVw+3bmzc8rW4GCRzsdZhT4Fp9aPSVdqezRzGSWYtfK1200Ktcvdil BpdiC33GGTW0Xt9CrlC5DitD8zBgWxRwG6LVSmugTdl08iPDQZxUwZjsBCI92I7t7NjDzb0UJDb4 S4a0j3Z8mTuF/9xYJspzRB5yvvCDpsxfXt88+n0HL0RCj9x/o2xGfzeUOS9VaOlAGoP/c+N6fdGA +Xf0jgUnEEGQsIZ/wb2FPrsSDjM53NKxBo9NhW6ECUi/tKNCR9i3FJbbL7rWysrOdT6ZY8Jkj3Dg bGDSk0sXPUnwqcEs0vcaOxTH4BxbcsevXTQt48XqZGWB039UrT+0oBB6/FNGn+lp7JhUg5/EPT5o SCuVnXLLh5NTRMZOIY/Jun6tRztEp1D8/7HmPxct37i6QLMaNgYLO1sMpehFnlf8i4ISXJTejnmg 8KVeB/bb2K2ym94oNb92z7fcyoRwZMldC7oTNcy4e4eBhtayntgJUOPeLUAfkEGVRTIutyd+fyBb FX1QFANdt+6wmY/UZq6AW2UuxSvW7zBLS/5kGX/uMiJnDS0J5kU1Qr0EH7TAipoLrD/qyUf3ZzYA 4mtuJj0IkS4fKtyCPKP4LSB/88S216JvpgtkoGycopEaVd0HeRD7IAm84PodOBkPpHLnJuUhaCdz iB0+GRMdAFBQg4OaTAYC/Z6Nl9ul9wJVqq+cpmRe3fS6excURLYHLvoe9ucosU+tPTnca3jD+S9q n/4AX1Bxj37A4KV92MW55+754prfpIr9pFB3NxqKxE1doRDXZh/hf9hpsQrYo6zJfPAu/VYJoz8K rKUWRoFg3laylitK0CelOq+6ET8Cia/zQnZlVSDq/wh+gl+MDjSnV/7GTrF8fLZNCDWLWwEPwRR7 3tLOXUal1AAW75aYKfp5x4/jTrBvpDrJs4udLnhx3vGNz3uNzPijBNhEznkXi/KvPGgQRW/c+9kP VRdgq3voAQvOpwtuSA/4yWfP9NXB4RMhcQNxtpDVgDrBA5AYEQmG4r47V1snHnzCjSUPvoYxoaTE QZnlYHt2ySegECut/ZBdmpar4osYnyeISH/a1UMOSOlih1g2MS+Y2/qmiSQ6DOfkH6HhJalySWeJ Theh6RshORlbMtXDGBItnC3oahU9+MaVGTHsKBEoEOCHo3HOZEb8N9yon1ft7wUPrbX8g0q7wcUq E1kbOqZSrdnFfhTeDyg/GdD3SG2jC0/yxzdIteWGG36XhcxZrVW0zXtuGT0zRhDAjFO91gY4is/W VxdtIiBjDJ+822KeQJQeNa5/krEIC5oY4zhGyQLA7fcyqW9pp5TMQ28P8bd+pIHHSTGV75cqsv28 hCejWNtLDZC0MFHQ8rA+yQo6cJm8X+spTWCfQwM27fx/Slz76dls/PAQxUw2pO00OJdWy4vlaAwD e5ow4ZHGqYne/pUB4c+D/jFPUytx6aVK+rqyMaAmc09PFWOc7NtUYxp/4Gbq0V/PUN93i0Fr/bM5 PtG3LCuMUKl7uT8I91joPFRdVWQsFnnvWnyEQO78zzO/HWBM9GyerGWSjz7fZoDtqSLgmO/lhuDQ V9nwBIuN4VgHrXX1d/Q4zVS66hl8PnQulTxaRkJSU3njSl4eIUwUZPpT7D9exSJ19QFhwpNIj4Rc eioqoNx4BGt/iVYOW8zJvwBn35ppeCsl3XG1YFizECxdNSCefnyg8TM5g8olJlCKmCxoPfF/EsBK VVWSwWqcZhVMu60NEYo3weUsCZ59DRdMJ+aErOf3Otz7fsSdNRif+UZnEtlRFnVi8W3gYuXat435 lMnjwe5AgpfCW4RYmetUBayBlNP0hFTSCEMWKNsw7fplFUFlPY/BghC/IyaGqGwEdy7wM/QYNmNp oYNbsmxr5c0TYu32wZFd3p0Ko82OLwMSYzaYvZUoQR/0QzGAziiJs8h0H3ffMJZybczKqkOHdYuf VUv29urfzSIklHKWFLMYmC5FIE9OEAUEBjRB/ktPgciJ/6/qIsE1nBozDUFMW17Tu26B733cBcGP ZLLhDkdxUYT5+86zohWcCwDaLaj54mObAoYdw3TOgGYd85c3WR7L6dicRLbcBJ/CvoQWqs938XfA HjuzzTG+Lqd8MF2jtdyLrXCwWlYIcio5v7hLIQ/TAYfVl9aHKuKUZcZro9rn8BhBfa+xTzzEk+GG UPqc4e49ALIU2m1/JpA+2X8oL6ZsCyrVJbAbYPBiG5zq6qQ9RTfKPR4oTWSLO5CUfskJ20Ema4rM E8ex7pvqJqt0vvuVoBAKKAJcGErvXaYUS8+a4k9iqqB4l0+IiktvC30uOk2WtEa1XXy71ftr/bMG vHkQ7G2INiMQfr7VZTg/RIUomssMgH9/E+VIXTJA0nLA4jbs88Hd7RjW8a+oEjk3/M2s0GpQx6dD 4e5TEEUmEtoB4RxBAW8PHnsD3qcT5BtqUBrng8pg3CVYdKh9KHATH3ljqIAyUzWMUbkygpqIDMZX WEyOts8ksNjrziDPTiApA7RXP2W5lwACBr/hc2gsC2Ope3FG0LsmOZeWz6fvAKXvI3AUZE3QkBjX ErUoX/fNUOHn38vPU/eO7FpxCIw//ZUeyh8dnE7XCV+j4ul/OdZl35XzsVNRBVI+TSdO9Yt2sMQA 9gk+sesZTi9+zXOig/73oZO4mt5uymlBoOiqdc94LR/sKXXlD7IF0xN4K0OPpQMaJ8AERdAMcTSr 8XiiPwgT2kIwTi7XcmHqbpIP+Q34DrdU1L0k124uJ1/6/rqb15kTnHkuXhJVnDpkCdougw7hOowI O8fHNcvjXYivlxyy0fACBQ25ZWH4/FkGFZ35Sw9hzknYQpTvFFTg8t05rM947vOuoU/OdnWatJjW QCI03GPvCYl/5eJXDU5vcXJKcGCxoLNH4YlgR7lLnTL7Q0sISxGf4Tn2x3qOpbKI4j7W/cuDnURL o4OnwlGI1gQnUWSVoek8gQoQUG4GUDWYEc2/Mmjd3gGKxr7+R2g9atmXCEc793tFIg3gqWjGXFUZ a7uoYs7sh+EQg4tXJ/AyTdv+KE2KRMzPt8aBr9WK92hVq7RR/DY5nro4iiCucRxam+kDF0q2RE7f 57Yf18qnC7AiajbbHS0Guyjl+tUWBM2w1YS5i961OUN5qqlCQxuLCXo5PR0CYpg5jKg807/C9gPr hRBGmfb6261ZBW4I6Rsiiem+U+QnderWSSuNps0PSD9Re5kiZz0RDnqnNxbaFkiTMDKMVxAmjvau 6oKAe+GBaZVQvwC4QFm2o+7Uk+1pRVIhbc7Nhpp/MMTmH7oJH5jwKeoOr3p0H30nmsxMOLZXrcxY KEFKqcmNiTg3V8NsmxOW+cTOLRspTZbP0C4BDbvG/aOIUOA+yRdtNnuI0aRFu/xUeWaOSbs3a1DE tvor8K/jKohYJpyBKdsP1Xucfjdh21xo7PZ8IBa4D9/0bt+xG6rHaALDKnGNA2Ky/myuMpYtjSF5 +pAOkSK9YctKqEZxTkAXWKP7pd5BkqBDTHVU/DdOH3V1/X/HLH8PpyU151YP8wnf6qJPCL4WqgBH hXDaggrb3mZRhI+wtHQ66RYOZhqtywgSeo3eV0HjlQTdW0fCBv7pDLpMDfuFOQoNT7fRuYAsBUOI GL0cZaVVoEhwcI9G6aScxPBPpq4DTYV++/jGGDcczkh/HoJpvZGovXXdjAfkr1IAJMu4/NNo7IWc /PtZnUTAqRRCX8KdPg4RhBm5ezpqhCRijiYNDm4jcpXvjRXO9zo5VDVMQjJ20kDBz1REIsms6X+V GZqBTEZHfkZojNB6AFFMXjoukIcVcpM8SVpE655sIZrdlPMxq1uyzFFnL0Z75jJDkTj48NLgmJKr CzrLSmTc8fWvxUYR/OYZGeFLQSTHcitJPUfDncU9swPMXdD+fe+UD9r9nNjlnY6xDBiHpxA2y4ds E1U8vtaDyg/eVKdpDBU0RTVrIBj7Vwaak9SdO+6R3wG2/B+F5Q6IdE4J6b/bnafJdSrn5xhCwxAt 2NGWnIg55pW6EabrMypHgo/x6Jk3x5YWp5mHZe6utURYHsP4ZMuXgC3m+B7FekwWdB3LrqRO+5bT W0iPStCNQBYPoY/WRQUHiclIqDbKgDYgyLBfK9uMVpgwBtr2U9YtfumweJdeLpEwo6GhC8qYCxlO 8eiC3AZGsVDKhb20XVk8qf0HkduOxhyf8p2UkcTo3ywIM19V4FYe+VJwLOVzWVWEduH/2QUU7qq8 c3MrCitzhTVL6uD8kV3i+vGq13F04Dl/65aRKnVRbvR1+lRAJrxjrj62LA6zvrF/xfRRUDfugWtT I/XfBtWC1I/4QPseBLg2oRPnvR9I8eed+i6dst/piQjm4JsMCHMJIjn3AiGEpzdtsWYcb6dasFhB /ZBnqnwM+PI8hgNXYah6L8iUHpwj2pKYNdcUBEEg3KUs3dp8S9Mwxp/Myi7gaMx++PopuiSQuZix g3JwUzblrmwv5w2BRPSCbHc+iF7vxYL14l1Uq9dR0YU8f2pxgFf/tbdPN10tzWelGZdQHZlMN830 Ezgb6vpkmfoB4JlVwchQDSRZpTmby5/V3BnXjIHp6Kb956OK7BWL60KgHmhkRHPtUpGpIwHadv7a Xa6di4t7KpnL87AzkVQRl5zvy5ExJwUVJ/aw5JxKQvysdccx/1Q5VPvyVLwKJUVBaXyrnwn8pcdg oXHOeUOp0VGh6kpITq0T2P3f3HeJ2B5W6HqWPG+MZeq4NW8zd9/tujipCnJ7FLH0300PP8am2YA4 /55tDFzY1Jq/kyW47MyT4elKnK1B0OxgSkrW4wVFbXxpsIxbgsmA5JrxLnY7l8BNO4yK+y9WfEEK MbAD5x8tC+0UkowdRPqwkYlr+OK11MFPhNj56n3PQhbJr8td8ZVc08bofcZcXte5D60e6qQOmXT9 DlOq1Y4zS3tnhWB0pwUqeoBkKbieLn64h0eO4e6Ct04gFy2Cg9Ql5QyOMTZG3iuQVN1YOcMLiFQS o4qzq+VfpcgvZPlbsVyre+/K4zbtFubNtIexBF1ZC+EdSLanTYjEmwyYWjAnp2FJ5tmbwdBa4HFh ImEZpEs2wjJS9d49PubFhtcF66zxrZoDTv1XmuM+sp1jvBRMGZERnzH5UlzqxlqrIr95sNIJBqX2 Lw7qYUZtQmh8QdXN0Py6Ealt9tjpxxvcsFyRbhUMYAXWPMCmHvv76OVO/+Y5Dfuoxd4lbPnOhnkl DYY/KBHoDJ0HPYcQWDhX+kVMlv9luTh55x/bSCXQmc7ZQ7RKHfTzE2CGv9/jtVd4lUH4d6fFH+L8 I2I/kBjJRo1PESQhtcnEN0SHRP8pYHy+fKeMpusTPIgZpguH3hjDHOzZilvnFD3EVta0f5jGGXgM bbO5Woqz4vnI76HrWRT4m+Qp8u8tbzKFFgFkn7JQIsopAmCd2UQLa6h5p+1RDYNLA06LYvbv5iMe nfPJrR6h9jLZ8U/FcyYsgBrO7oGJBc1/OYtrheWc1Me881dEHQCRcicZRVsXASOom2XJzJnoHYVc TFgDwHOOd02907M6jjjIE3L53kwLW+z0x63zrSdHeF6fNyLiisSU+zqDF7Bq+1gy7XP3N2D/TwjR RaipVUtrzfwKQAzmCP7f3aYn9hEICKYy99TySEQPq7SKQwpT5WUAe3zOd/mPGz28RklDvj6ieb3D vuN9/0GCQ+bbFaAEMsPiLcz/bITbbc+FhVcDOQjxb8vRzigA/dC0rj1nE4qkEAsnsiiWmR261Q9t Diwpn5x2Fn06c95gnRF0uDAvCUJqX8g5fbxY+YHTH3410sL8lLlFVj6N8yD669L/BPSMEaGkS+iL D2cZF14my6zmXxKzqbyJnZLdaMurbro7wmmnhgaxBwgA7Thhydw/bg2tSbrthXt+On7oo2N04xCe CjIdAs3Je3J3xC03HKo/K0KyiR1iNUf3auULgKYjODzde5JiiN19I9gZMEEKU1vzvR/BxS7BoPGU b94c7SZPe/I3MHcaRrB3mP5a0OXl51z3aEb/FZM4ZgISBuTRFlOBJsFaKpZG2umINHhKpWq9teiU gElQLi1OV0dnW7YvO1ztBrEGlTuSipZNXf3MSkOSmMR/XLCMkxAq1+G7PZvn9L5vfIj1ZyY+Xbq1 fo9ADfs8erVe+rPoC4DwOEUgowLTfaAcjLxGafrQnC3UD29IZV0S7iWg68AGrAvWdkosrh0qf4zV Y2Lg9fT0JEP8qHzqIuAckytWTXgyJN6bDDUniDQPkAvJhdNWyAEd9UIuYkLk1vibgBC3HLQjTRgl I+YH9Qc827qnuBf1rZth/i3yKV4jGhI5bJUoMLXV25yOqC0t59jm+rw4aFidiBcR/68/Wqo1D5CH pV8OxEIs0YPNKsJrFV0fLJc4vR3JfCvgE+LfRusiZYoOneFe7qNdYRxuBxzzF4D87Q/a7obY5eG+ jkcPGhHCBYJENcK4k0awGuoOlVo61GxD7zxT1N+rYewCxqHvHgZV3Pok/bCYcV/qmsNqK61aHLYy bZqtSW2PEodjj3jnbw71kARCDnzFuKGfBjtj8j/e7/gqxlveW1E14/7N1Lq1hH6N15+CQ+rdFtui NiePysyraZAwtXtnV5KwQb7mZdy40ofsqDemKz4iYUMCsKA/RiwztUdBtEsPpW1OxiehpK+FEJyp J/T923TCxhRv9z1v51RiL8hvI6X41nhB+FSznI6sxBq1pfe+r8Kg2tSX83llH7T+KcPm+mJl6qw4 U8C6rifzFbEQMUJW1SNfZSn1s7m8KYyf4HCquVOEDaIS/yxuklfAEwgW7Yo1Y9gDnCXseBtzvHhL FmmbutfHMYYYEhG+bzNgXcjgzxNABbszRuS3gf2TuPBq419bvAeV4IupBJ7lj94jWnblNJLvVPm7 Q29x0KYKu/YN2MG0W2BJFRueaCFCKhzhS7XUVVQNfh5U9S5c2ZPXRc0LHBhmqhhOW/bjknFbo6tT KMLMhA3cg0XKVsAAt4LHflFZyccthUFqnfrFgIvoi/s/MjJnS15cJ8Vos7I+Wii/jUvTTaxbtZZy LZeKWI3ZBZCieTIK5NoXbYdra/LBnK0OJNHJx7aR947y6IVQJM9W455+4v8K4gmE1Theze9J8Fa3 zKCW1ciQlYyjctvBOLp+D9t4JF0aRVlLnf4X+RL2fDuhTvuKIpMjN72DcarHQGd66SHY10jUqr0N ypdmXEYId4wxBTucxFLf8Fp6+4fuRbsnVMJBPgumA9bBJOESQPBkZPVQnl/NwVlzS6u59axWUJME SUVxXSl7TxQHYBNohBSBbZZFtJrTm6OIPtvxqF0lZ8bRSMmTi0QnCN8GhGTBFcSxz7eGu8/oCXtE hOCCjRhTkUU+fd77Kc+9QVcilf34JB9Tj5LYLRg6KtSVT71zfHzsozIut46LdkzyIBDsfcxaH3ug 5jpzWIq86WtpvgA/JfOUFosuWwNB1YxfycMTGxkRWRf0uOZO0nlhTtHVNxxfKj5+yLlXsLytj43n TkiVRTkm525ldIMoDW4AwMYViDZ879OM/wDldgpZiECui5cf9ly8VEEGJvlRiPqEZo3dLS5nDA8b T21xixz72yqUpPgASoXYnT95eg8q7N4aZN6g9SqgVBPxqI/RuWlbeWc5olccNyb2ARA/JMMCJzfW hbB167cjK6r10UAgQi8lrpRFHgK3GhORBxNPkc3fDnJG+3TSgCFhD98CS1QxL6dgFCLAlycKK/5E zOrLZo7If+XF1NZq/IApWG8Kwk6DpjznuPEQ3Wiax8aXrEhnr4FgBZqdAIlpGhW3O2jOQRcBiadP tfZaAcfDlNeWgzK0oy3+cDTtfpDZaUOVhgqQAbCUPQQZhWz89DQfo8h+BwS5Ji/6edSarftRPXoG Sin2oB7ORp0/M08mIK2uvOt+rF90t47lHtrswN859Be+slzKID9ye0nVYoljedJ/bOYbBtnVraW3 t9+EHO+t+agGu646ql3QhmzOrGcmrpqFh1viDBRBpxEDJnwjKc34uzFWQ+jqJO7deZnL3Yo1doDC rrLrGa1Rk8/HLYPmAEKW5RKs+2gFnR9L9RygJAV7sS92T8Nt5mrZjHX4qsK0VVtSiiey4cbKjEwR KC9qui+kEqZrMGNj+svA9o0O+CfPUutZvvOdohscmy7xdMMLB+aPAU89NMEdnrov8LLeWiPUiwHD 87DEOcVvOl92kihiQRnTWW2qbVs7ryTbY9/3fcbm92TAfLv82Do2JJawtxDBSWor2AHWxY5Bkxj1 hOeUVLf3xD7glqNQ6KUTMPTe5FsJdEozBtMnQ3u4lbXYQqbLkInZPwB1abj0qJFkyQJ+q+dfxiRM LUuvL7UMSpiIjKQ4HDV+U95dpllR2l+O72fUoDc4wRJTaS6VJj0ArcUXDDYv0IE77ac9Dj7LhpZN 1+ztJhwbOpAt9zPlxb8kl7C5N0mAdkIssz6xDRMbPM5IxO+99DM+nPKjcU2t+5nS26IligWAdLj+ UoKREghQS/uN2Ms0LL5ysY2mzVZndKSQU+FMuYXZ4qlUiAJRTTsAQDajgTTw9emaIQc1yxJJ/iPH /O0YbeUEjqNifkqb9Nb8jRC2lmn5jushrpV9JwYxViBZ5m6THC8bsTxExIAN0QpFCWzUnC5oZozk g1hwbbjgY8GzpqiNgsTEELt/xHCbk/EpK65L5+/LJTH5CZmLw9dPc3ct7ozTaHFd4BRXh6fJ1ud2 DoFy2PVtfxWUs8o7VVsznhLuZjGCNWUdiJrq5eZuttar31os0fqa6cIp1jjJa7aCAb4CvRygVH3Y 3WcY4N3nyMVmfLGVt0KEZaayPEWXTHzZ8dr5edmVbe97I6ToNkZMvjJlbnMWofjBPHoplJfqT5FB 3lKXXJgpLcD3WobCqeR4UsYGGxafGIZ8Eln4n64KkjDwaxeiM3cd3Qjd0js/k8e92gGFx+wBA41x 36GRcB8frcxwnGPEBKBGg2ZSl1PyC27x322zv86ZZGW4ygN2Ywq3lf9vELxuzjyGBAM0bOy9/v0f GTox89Wr/td42lOM3Y+ewueYb2IZQ4AwAb8VOi6nLFZwqPnJMRGrP3hOmf1BeYsl6PjnBoT4uQ8T 8yikcWLAjoetLhFe1thTzH+ZEMDm5X1s/zAJunWQvrLFXA4Ua7Sg0I0SKPf8Y1GiCb8k84ABwI1d PebwumGvb55NZVmiHOTj/uTnBc64bEtYdiGBL/ZDf7tkw9PD/kc5+xHUtfxUckAIRE9YG906xwHI Ub7I6pAzqiwMze48e5yePzlPzwh4qX1RZkG9nIoqlqRFZgXAPfjwGjM1Ag4XkT+QVWfjn1ofVNEf EY5I3hFjaI/VdbM4vwL0Qvd2vcou+Bd0SPTKVii2K5HdtqbF4Yd6QE3LxTJU4QqSArIEEiuEt8ms 29ie6RoCXweqVBNYScEvgHtr7iD7+v+dY6JdZX/y2t4pwstpt4g0RjMTZfjq01jMLA8g7vcDloZi GStj3c11X/JKOOT3dPHvuK/m7mH0imRnPJUjsttXbXkNyqWAN2/7tqqujnj0qbfItLun3IviMb8g GDFIaB4ezR/efonJCVej0tML/ffC+6UfLcB8QoFoACtLh8/xmnE3g7H/3Z7CDF8gScpdCr8hCA9I Wzj47eWgNrFu/43Rk7tssPkMspYjLv7b1PEXeYHFzDwPFLTKtN8LoxGIR+n8P+CyRk9w8V2U1i5k imPr4WbAMvKzJU4AoDPhn1m5CKdhDNMO7ZFw4HE2tBnF27GzdRVsF1wwO46n5zX7gfH/9dWk1dZ2 hQBzg2dxNAwJ3TiFJxRSPp74TooK75mzU0zwT66+rYVcYnU/lBHzLdtPYAPwk4bWf8YsKplEHvvD WwNVRO8d/+d5h90A3+3ItXxSpOgfaE0+i/g1lZTxd56Zw5HGA3YGX4JlG+S+pjmVznr912asqDwZ x7QaJrdsa9Pin0kwupakXQkAEm2OPcP4TKbjWX9rTmvcgNv9RWcX0B4/koLAYyS56oxHo77EDpFc IsrL7FHH1r/i0R+Q6Iwo0TexL4EEMqoMhtWQLSjK9aorSUvf+Xx8eZDu1APOiEg/bedr1eFFluOW RFa+iw8sxPOtl2Ajnc2S3HwhGFrOKiVBAqKn3H3zNfC3UlV0e5SwXTA5RPu9cEu01poJw1WFFCbR +mCKseNr8OyR8LkgbnAVLHXQ087l4ekKF5qL2CEeIh+cN/7BOJknW3DjS2vYUDrMONynmSi4N6d1 6f0dNHdVjTOxbponJFE+YbHkv9Uh8gO7SsfC6ZhUF1tITYmM+kTco+lsXKL5Uv66K9cIrYMg+XKM ZmKWzH5gRsd/zAQzQ1+F89/xrA/BfHHpbkYNsxDRWzc9xzUjJeHkBJZRTCVQAMz+Uz5dOa9xUMpm bzXvYmWOVsdeRPG9tFPZyq6O5amCNw4Rw3aEtbUHBLHRTuYwTyD5GmwYd6WATJQ2vRrk/r0P1zT8 dLu02k/u8ik74Zw1CWIbJ3ux1OHlfbHN4iQ7Gn4TAy5MtszZdHnELVTOF9xaoo2rRCb5KVYoKreV pASsQN1Tfme69loOkx53jEbS/r4Tdah7mw4+jU3E9oLiJ2y9rwZLqbhg/6t9yUN5EYoRlfRkL+5Z NHUmXvFHAEED0HeA7D3sBpO2ikIwZRiI7aEyjrxSPW91j8fhD7Ovd52wOl7+YrWI4gK1UeebEZEp Z+KqV5s2DdJdL9W3lYCIdYWH/LlEHaBPAk46cnA9wtAf6imHzL7PLISWfI9Vatnx3xFfYdnWxbw0 tHtKvWRf8mSlVA4oKCzDd0YDWhft9WXllpb0LV/rQIKHH5ZfViSQ/62fUY0joj2DFtamwRT2PMQz m+0fAr6TowRYWIshXaMnb86uNtOO0LZJBmgSc4vmmHp5ydSl7RHEuar29bijEu3d/BcxReS4MCFB +B7Kb/i0PKv4Pc7CNOLHVErVpxEQtXqsM480LDOdsdpq2l0CU5R5r5n9YxWJU99to77BRMVKwf4T DnP4IFl3Go/Dj8qJ8l/m46D5tMx2NPsuIOFx4fxFtllNgX8+58zGu+glbXEzpcBZm6HYLVh5MX7F 2TXixH2b7BDbBxKaP40XFyLRh1UdgqwRmYpSudeog/nqp8wh+JAF2oZVK2tLv+GQsrBSMKpsH3ts P/2Y1on+zqdb3dk+GiGnJr5vfhsdma7AzOMDxkyQiKeMpEz+S7uKsRA0Yuf2H3lqalDyoJ7lgW7j ssW/4UgIYqgJLv9nVSTrZgabKR6A5jmMtXERr1nQKD3rcHRNOymqfiFHj8dUQFmvVOCgWy2OgNsh g/H/XRp6ChX+m4voWySbJCp8K5uye0MdiXyKk/KVZQohEhtLI4gWTmnSZTUE6zlMyFbJ4V2Loy9u 8/dDenXJi1LVWMnmG0+d1NPEr5pQ8+SMu7sH3zhLWoCXyXpzNCRzQdw+y6pVdKetPIIPyuq+RBsL A8ulOZ6Uz14fJP01iZKg88ZdyJy8Yo/oKQoYG2fbpiyKZBWOAMRK7xDyekpESvlJLBhCxcNu2yLW c/jaoCCHW5JHImZ757zTneRmsMcWxyiD7ejdUzBotguh/KquXBrFJhyXmi70NJefECQ0aXbT0Hia JMc3IBdV+f4B8avHdAiXUpeOLUMe+YGQbsEAScQO/wAxB97W6CJIdFH5+FM9KYqJQJDOV7NnmvDH XZTbQZH155S8ECLVpREwSF3NDnVf6x8/hLYfxugrQ7o7jhl2YK9ONqIldaI/v1fOM9GCBejG5rI7 8SQ4NsRBj/3YRzcy/rIamUXwfSROyY31KYlLNBROJbZnEGqCX2VuFsrOsCXrUaOy4+fNI3W2Cswa 0X8fXK6CgH1PAseyGkqg4v7EYv/X80hhRfFX1qRKC/mHUYBE53B56MUES8xdVsFHg7mFN3dWKudC 1XwEh172L5hBkhXGrGLBuNkpBJMZz3O2JLLZ9q/tLjvrGypE1yaHJL9IlKHnuC2GA+0muDgfLt3U xXHaGZUOcQSGXovltbjWKQDRuAE9LbkX6Rufit0npJSS5Lu1XzZ0m6FweiwKwm/DLPQ5YI2LmjmM PCm2Cm8mb4MGAqdH5kx8DwuP2SZcKX9CeCYQsKjVV3j/a7/6GaOy66ravmU3U9nLkuKLRaT38iPZ PBYTFO6iaaD5QUQYgC3bJBa3EB5GLQY6sk4M2UieEDAQJJbtUw+CPwJTMM6GF7GFxJKNX/B2xKkW rbjqE5j/46ItGzhfOQVyLawoSdiDXcOZEm7A4udgqs4i+pyJPJmKrDiO2r6QpwhvZ2tq3ZNtyZcP pM3ma2Cl97V5lkUQMhVU6aEKGBfqz3sUKokm16YiHVREbDokwVscHH6lnwkR+H4E81ycsAq0NkwM OOcwRJGAniVLG0hiqLeWVaAjzhwz+DhLX4hANcdXduFRwVt5nQuaSRMGplqzb52EW2H3Bm4YWI2C Fn+W1RvUeGDCFOcZLcQaBPnO3pC2mW1Ra7Mo4uQJuA897Bvnl1vR6ROqC3wl3OEKYJyCgJExZ5K+ YTW4M88wskaou6ZK29yQST97Zb4LYqeNtbak47xDl19rxwBHdrDs4R7THEqP8KMpUZE5nJhku7oW dSagJ85TR6bzUH6Wrrrbpt69l1bb6mIymrJnR7Lhgs87CIjm5c9DZGpGN9SDbL/SMyUT+zg9tlBJ CpthVCZs6RtWhDw4Mc0/B/X7NpaRWUtR10PCSryrb514DDh2lsRbntKQ1pLN0TX3DuzKmWzrisqz cghLoon/FOOV043Ns7Y3v3Gz2Wxx8T07A65LYkc0dCf57jlSGj57XztgAzcRygplyC50B4cydWyH M3MzrrXFKfLJC3kt2d5DLbQ56SwFlOw8+FmNNfW8sBMRe5Xin6IbmzD2PyyvCww0/ZEQEiq/G5gm oMUa3mDO2gHYsaInFe6dWcYCM2ahQSJwZWHI9E1WP/db68ZqY1QkHbrGvgzdYF3rBizQ8kKO4g5n 8gLKvtiB0WlDNvEIInNIzLi8zil0uSzTFlxAUWYqr4NtiNyIhdrkJoTH+sDz1mg1LjG2qpPeeTMu r3h3Cp5T30iwLzvkhXBcGQ+CcZyXjiqtYtdTXTPe6WXREK3ZFis7Hwt1+7sRgP/GocFSys6an/FK SxDmlxBJaXSuiM9ZkzdO2JdccISx+4ZqAC31eluStc/EGgIFSPdOEG5RtAgWFQjtgChuV8zDbL6K exYCuCNHCBg1NkokDdg62rmlxTlD4n8o64J3F9Ik4xFxgk5h7JKMh/sICEmDQoeE2YP25Oc2HfRW XvnqPqeAzUpZUSQGlYCc89kPfIX+P7BOuy41j3uPj67F352gkU1nk7Wy97saHlUM46tBgGg59pN+ o4vJzSPfzwzoU7PgUtdxik9T2JRgJy0OgPnkQZNM2sx0jTQkPpzE3rxu1CW3qN7/vxgFIfMApKj6 sxc7ZZmD3OF+FX4Iz3XiFh+X9aOY9muAi6Cg2uX1uFjzgjSgKHu1KJxUdu+5p8iZU02EibqOaWcF IGB7qDU3wIwEBiJasGLD+aA34LEHn/5LbBf9rOIOdG/Bu1HlvGc6SyEs2FVbwsH7oH+4KXbe6PAy A6BVQpqivrb259Mxe/ev3rXlv9CzU/odZBCQar4LTLctwJz9NwxrtoYhugJ8XXS9mnoiAfY38ukH VC6OBYzEzJNHuG024d1V8u5rVUKxkwRTT6qsZXF6VFdmMGRpeeEGlVHyTv86dPaRoku9sPWJj929 ZpPqRAQh+Vms4vVKykbCnWS60RO0PPw6ftZIIqKu21y8oz+CjaevJdTwTYLJNp8bEVt+LOqm2rMa OuuneOFu6wJstLlweSKr9F2fe60QZx5jMowPizH3l4ho8vSgpiRr1fuUdzWNWdOXh++937IOoexG UmalDisfm2/CwKPG2wdRhxp+HotcP7NeT57/pAlT9Zfm3h4OgvC1Dsn5ibb68zfO95qyFk8bum05 zT5p9Gx7DW3u+0UGr65kyNjEQJG9egjGUlu/k9+pwNdtDcpQvUr5R9NOipC1rvShgRIKcGzZQl9I NAhejfTNScQrIMcRjBRedx4dvHTvZFnWeNMd1rRBx3iv5VhtOd8S1PhSNzgeMlUM7I9urdQn6tYE YmFwwdjXEvlkI0s1v+TyiWfOtMLBGdqUSDTVxFgNL0X1nZRYbH+n/Us34axb2VpJrn5IA7iVosIR f20Vy4baItA2DyW/tF6RpK0arMx9YKz1rZa9vnd8iwFATG1OOUKWO0m6kheIflNjqdc/hzsoNxlU ycwjiY7k8c0jB20eI/ekSwN1a94q58s0XzJ9QhK5HkbCOLO94TxDjlN+HGdfVpDlxR1PRzmvW/q3 7yPJbcKR/3z1DnIJcC9KLVL0E2HsN0aZ1sE2o/aOqebU3ydlW32rSiqYNwgt4J4U7T/HfU8XnWUa 99lnsJyoN7JVD1TZkXoauOoEAsRoJUxhimDhmjtw5TdRE59EzkXE+dZ/h72/lj4gQi7SXo7bMgwG XGlV4++vFcYzUvorJfqvK+AimCjo+y+fzny48Ix0WJUpjgIUt7KVAiLZilGksg9aHIKU4k5D4LzC O5JBp1WZ+SneOpPyxS/89PIu8cqLWkUWE1jZdX9c8Vd9pmixE/vBQ3IfKVGKRSbANpk5r26JplA0 otCsEMuVP5paxz5lPFbch01C35M0KO3FZXi7kX0fLlI6D2iDhE6akZkTbNF9sAahsomqdJAI5KZR S7+XIEHWFnhzIs8r1tFglFjAPu924Vv02Nd0mNFfa9McSnO443pumJ4zV+VcKOKF2A54nlp6ZDIw Y8z7ee5tQ4b4l/OotJfbAhhVIEjFX7t/i+CSlR3XTTaAB1BIwq3PMn5e+hdGDTDX7z60/XTtys2r 8ImMVigqbXxs/ZwCmxpseZRYvyD/WdWQFy6XUM3ox1KqS8u1IgOn6fPUMPBlWAGaAF5vmQgdvEMj /rAZ5xEgsKJo/WsFnt68yYf2unzGmVuZ/7JGFhRbJ3ZlhJg49G9Fpo4k9v/vUE2c49MHuuiLanTk yF6WJMsl7rvxWPocFm8c5B5gFiWmjUX7mYf81ohboHlbbFFO/GkpEI1YJoUzQgpQdn1iKGRXtfei oGazO7q6/uCpyqH5C1EaXAXwNyWF1ILT4nLWSDLd+jG5lr1NUzqp67bwdp74Z9nkQJK2qgPKMTTQ HYVKPqRWL0LgthaBYYSzVHecxIQ5VlsKITWEauPnnp8Xu2DAHSIqDEH2Q9cGQNfKnpYL8EsqfInH yCbZJQg5n871dUDBz1ONJqdyEP2WVFDQ8/n3kEnbba++EmROFiIitxksz9ktvv35mcmSPPTNzCHF zHZ/NtjCndB+x740AfZVaK6ukh2UQMvN66Js4Ji5aHL6hpRtZok3jKI5c/++wu4hqHHQE46dZLKl cbk+dVmmBlFbY5O0YpNw3dBcHpn0OtCxlPdyQrfqGXZyzW1iVjHX52RSzBJ815JTK/KCKFD1iilC SDYvfQv3BOkXYg0shGRiouESc0MZ+l+PvSD69QflP6f4wIXhztgomr6ui63eu4nOrTArRK/U23p1 vPBEn0W8aNOS1um8TZmWaLWYLR3B4NwfvCkZtqXPITkMm3PQ8R8oWe/As9IsZtcAlf+VqtluAeXq d8EpQSMcyvoFYNbCRxNbUwngY9FXzYHW/bVbM7OGLF2hygxXcl4IhQgC2s9wFjg+EizuUTSrdbuM vQbkyjSXvU4A7ACBljq4xren3ywmS6c+iH9dSkGh6Bn2iaDsq0TQsDeoTAh47tQqFxLkLDL9Jk94 zlkLwajoGVyNotnSv5uOaUIRt3c4m8j4mMLSTa+axUV2wZB49ZDaatVbX1drQD6mm+TH7lnkY4m5 PwrrvxusBlXc7qs/u0oU4PlTesG2E+4QH6V3tnf3S1A47QyXkMFUK9lr0WuJPBJkJgfQIsv+GUQA WN3aA6Egbhqnb8lti+V1aTUE27jQS8/WoKjPlhIFJ0G6I53YAjRzOi+7D8yll1GauThzpTh0CyKP E6d+vtkP3pyEy7LBJmIh2aSjg3zHcywSTGUxzdHrUiD6V6QOizAmLkdv8tZaGZbAFps127tGJdVX bPuFpMZhujtS4hnIVbQLLjPvn6hqQqMEJU8AHEJ3PuCK9ylQZ6z/YESbzRDIhyAfU9EgMZVLp9QG goJ9zOm5EuRjy+D69CToMMm7xTIdvN0ocLmaFBglb7IPHqJ8x8bhjidighwk6KRU6sK2f4zAtuNa DLfXMW53eE/8W0F1qR2f72pS6Tv86zTQLjn0RT3eKKCXtYzEC4sUKTIHmUzJb5BCt2wT22f7OS1f FNfuPEQSg4AAfrzDRBjDYt6Oi9H3SV2Yx+spFCWGbhehItfWrqYwDC2MqQ2g+yK3UZ1bJLnObQ6o ZetqvgW1xc38F359Ewtruqp0L9WpM4vcDk9KumJ3DYWcqkm5xOoXa+eOSuApFQq4Jx4wYodQOsWQ Mpq0r9i3tgsHZ3uKcG6VZg37rUGAQhNWL7vC7tsKo+cClPPCuvCAzHEgxLzRtr2Og89HAlj1VMxC oJGt2/Xp/HFvYJr2i8DpwOsaOVElnqY5z9yrmfVuvOr/JHArSMYWuVyNlCM+HLy5t8+zd17sIcpz H70LKIp0Q4eKE1Ubc72TDk3+tFCzWfPqctKoDrKXXcMV6eLCMRpSkSMgpVZhyiWMFRw7Wmj/JWGz gPSD9BXuGVoBivaOamYhBwGjzMkKAwohv1buQHIe1ZUwcM8usJ8kdqIIqg8ghxBPYITZVL1PxiPw NTNlLYVoukklfKRcLC0pogHNrIS8TVH7okzt87XflQ548st1oPpG/W5FpxMTOkfofIRUDPGU9c2N ZouAJuxgKTnLEHZ0uU/Ctd3x6+EUZ3jf55w0tjv4Tw2S08fbKvwJ0clMX+XIhV6jjO2LG4tO7Ww1 CguZlgPiVtw9S26k2T5R1Ixxpc9e55jKUVU/0xGkhoqOw5CIgAI2V09f2R7xX7Ceud4bBF60CKi/ rBMbKRBwz786wdnD1iUIPRrOo7UiAhK050azsVmE2l/i6NiWx0s3+S19EUF9S5jCsQFa1Ufiguqj eD+KydRf3nuqX+eqDB1Yzy7/jhFkFgmc/Tpxelf2QzKPtHctJ43KlvnQeTqBkl1UrRSfb0t1Hh7i tWb1ZNSV4GP9PlWycOg/FLcbSYbXQswvwyZhI4800IEzF+q6SEGKr92HGfc35CskJq6C4PljAxxq k7sGk65gSFtL2OLQE8utsH6SHpK4GKg1/8PkttWVlNE4ltB06bzVB5pw3egHtnwjCok2CwOEB9VJ DerGjwsuXxB41/V0+VApdZytVPb6FAiur87ATwg8U/e4hiNuKQjWVkGZ/bV5XoLxX/tjPCiPWxtR 49t2bLrMWVAfEx7roq9+4tUHjTy4lAl4EFRflTY7nhZZzd1ZeF7OHI9j6DgD5RSIKbgm/a0td6VV +jrCb0kAsfIEz+iyqWBtnyQBgsoO5KewUhoVqlNNvghXC+E6x3pfNmfKpSd3PtxAmRNs11SbUhUY iRZVoOnI885j2DrjE0DbQPGOC1RvPGaqh31H0Luu6/eLPOSW7cbSmxuZD9Icb6Lsy42wCFB4CvjN O7xtnY+zeI2SA1bH3S7s8XNDvmI4BsXNB+ybWsaKQgn4dTRvwjY69UAYIJoOrPyvN8oP3Iu1OlNW ecvSCGEp9U5Y1iZM/ktIHuFY1np5EflXqmjXuZeBPDSHWG/RFIcczFfItGlDJNBdNpVcEF4+rY5H 6hNcgvovw6zF8k/L+Ha9++zT41ODJaRCqwTmpYk9eSoh7AGTPj0pbh2wkq8fS+WaJzSda3SclufY mmdMeu62Xb8HUEpBZ/JHPcZo+CJYPXKF8YorB1jDGU33S92GnEb7FDixvWUYY7knMy+Y+KWXZ1xF 36iZVsXhnY4ctgj5ePvu371/zrFtwv2aslbQcBIty6yiqlQAWN63VC1E+Wl06RcluE5yqmA0N15F L376xjDViV+sHinuW1KP0FtnY0DrBbqGcBTMTOIkNhLNeT3UfGWlV+Gem+BN2j4b22FTDGioccuN 3mRQX56oMP0izR9I2GCL98C7WPkOXOvDb2BMb14LxD4u1znvxRFFd1mvadDBWfruHNQN+euq4WFv B+s1Z5i22wrE9QJ2+iqw+yfUwU3D/SJpjW28w1RaIZI78+yPhcZa8St5fAYuby7+xcUnnvLxo2pD ZJe+wceXKUa1bBmA0W0ZtYmxWbZcc//Bo0vWPakcZNI5xCD2GdJjlbp+3aerCsgqI0pA4J0B125i 5CEli5dBY6ZMSyaZf3k0I7gllBQ/6CqXII4BPnJXkNNNMFFmvqoJ1biUSOsHZKC5OMLby4wAwlU6 J5L19NGULPKk6UeNemovD8tZvnX2nbDBUXIh7kiQryolF6E5czYkrA9qhyix/ylKjnvy3ghrnAP1 k74vxDbylHRmnCCZ9hmbKWUNSX5W4cdsvmr4MNJmMKjS870v1Om10Y3YlETK9eD4z+EQMrhTStfp IDtwpuYD62UNLPtuYkjwEMv7FlOweLrbcmHsCjQFYsW538+UTy+fvTwcxZvYvN3m26SKdVgI4XLW y/29NeF2ztu8hkEAnl4VGANWT+41RD/i7azV5MeM9ZgAhKpmInsMWmL/Rb0o0XOjCV3I9tkqQLnk 8dueo4L76TLY3PfOegpltDIR8PxzrqtH1BsVHtOBTf9DjUslroNPzHWLjsl2X/saIEz6lACKCclb VZAi2QqL5Qm7rSxxCUxsH90DPZfTk+XR8iZLaTgfCVt1njz6B9ce0CaZ6zZQIn0qzmco1lxAd9o3 1XzCrx3SQeGLFjcCmQx1sTE5zVJErORjWCM7BMSZJ8pTNQvlqQ01YOQvzFJ4kLgsrr0MT/BbEWbW wLEXtwc/JBP0l6ep9+A2YAzZM98J3WaIAKOVR7qH7qZcKaEk2om8fg53E80XkbpFiRomC+dC7IB/ hF+Z3WTY8Qm1t07e70WAjf5r+x6e+WAomp1H824seeW8UHv3iEbjsj37ogrbqMvDWVnnvOtwlgL3 ONyEKGeE3Z+ELTh5nQVjlEy48eJUOzPNzgs3yqvpxb1RqucteGm8G7Os1o1hHJLnNijgvJJxFT1y 2FKqLT+Lf9uuqqodMalbu2b9OMLh7vQBsbzKY7JHZBX3WI/T2GkCoOpYkFnDrFNRTejeeVal/M6Q OzTioviVXZ3lIxHBactsQOS0mbiAuY9QyLsv3CVDLpGX9PjBmMok0WDn5GHUXMw0U047V+roqYrr YvtIwm6gA/ffEWGdQ3v7qgB7rR0ph8IUBpMCOTrWV8Ljz4f3iIsxpVJDN9kEhZe3M2vm0bapGNfT GARlpjo7szx7x+ZNGZOReSxe4XRVyuv8SAPWGP3/jokRnWAi5zzZt2KyWcgMpIWl9WKSQwXXv9Zy p8nHHwW77sua79gG9EmVZN7aLusmByaQ51hGsaMz4E2g/YP4hIhCLIHbRSOgFRljPv/Vs+cFjm49 o5NId7RyqJgsxL2jI3y+VFLwx2AuQlU91LkV3tR2Xkw732sW02kriIgZ4yYI1BFeqynbcSEjQFZc jF+Y/DmkoEAI0ym19VZ3SW1c+W9ZjqQtDogM9wWczPH1e/t0EZ/LZgFLuB4z4qE+otPBb80OWmRa /AB0pk9zZYc9hHMdRnQvy3BiOMLDFQ1yO+MUZFlwoMJMP/nCQj9gB5/LdCpm2OORXy92fVTrqFO8 IRHSTjgByNYIjbKPRqgaW2o5fz/ycsi0nfMRtyiI5N70Q1+sibD3nTrrpz3SRVpV/wZm8qk+MHfK /rhUYz6spShjIXO1HyUVWoT4wLXckUur+VD9PQrXUUqubEX3iUdMypSJj726Qij87FVHdzxUWfRy JhWHC8PVy4cUjhLOcg/GMi9E32Qirl+50luSRUgdDGXMDvs1OpOrNJt3rEprTvF/DY45MFYvP+xz YJQyCWgLrtsyreCdqMh5C97jixLuK3rhHkgoqMTWVgoF5j7+V36ObAPOdujfhIeSKZeTyGnegRNN zA4V6/5VgJbo6pY/DxP/Iyu5L3EI2Z+RBv8y+/qxMop9dSeYBjkT5ITopCqsa77ujpOd+0Qjimhu g7h/4Yeej5QQwvZ7yTy8phy93380bhiRMq8aLUjoau0Ex0BBIKDZkMVlGjnFQ776JnfMVl5jueUA 90T9N5x0gtI9T53E5YB1NwRN9MdFICKiVraq1rc1j7GhYPny7vYZC6eSZdseJvA4gj3PHPWZ0u2P tq2d30p9csTyzzb5Bjbs0lHkn5/m7rE6jvjeod+yGTZty3VyYAxXMt5NAdL8MlUq3LiPuiuUzjDf o0cIb5JvpYxjYwrA+sdMZUVtFdJr2knZ7cv/CpppybkQsvxfG003dkzuQjM1k/zM9/d3DiVIRfMv +PNXM+tpN8zXzHSoGY3cGfBLmTCV9fuhX9lX30vu021DPDctqTWLD0Incs47DCe1OOX3ksXMSj89 sn9YcZiF4Lgda7JbH1qCeu+QG279vT+TsxyD3S3JlukBP84BFAdGg6IaKuJ4gID5QhuH7GJsU4n5 IPsJCbh4Jgbo6EBU/d8b7i5Gz1S4E8kaqHGLzBwlvghq21BaPwKBH9b3IvJHanFL0MPtxDNGBgIB qIxcHnT6EH6/A9++RGAkC28W86JSXG3Gyero1xSsItL54EdQV8mrd2dYvCKJVfq+VLjBOF+CK0jG Qwty5yNgiJWQPUSHUhL//GwJ4dmTay8Fy8iYyJsm9nKVH3wLSkCIN57nWZ/AgvYccRIntnMHCtSJ ttHwL5IMDg5QtVh6FvGzjyZNBQbWc4RbjLpTYm8tmnFl5o06Q8doV6XoS0u9/beDac8KwcatPkTo rL/bQgrpY/zeObEnf0aLdxNuFsvmOfCKbrBehBO3aHzH8o4lxCLZGBUcFzJ2+LPWbpbQtKb/WkgZ GAh2sOq+jwWKNhz1eCpVIWK2YRX03EcOHRg+EpIueSSCFgtO2cWxDK1ASSY4/WNHMAJ3rg7iMN2X BGzyd9/ZMYPrJvSQAEjzi1iZ+85qqp9zXGJbvU28usqqY6AaN7DJHR4NKx4c+ECUtM4BUAAjq9jp 1IZvi/w5gI5ehET1dxmTweBT//MUJyVnA64BOmzWakcFq6PhP/GzM3mPMPfe0ySIgGNZJDfRdPYo lmdZUKY5sjsNuQlt40P5gIfQ3imgVBZ2XQwnMQyMDs7o84EXvduCnN2QpMBBMRj5kCBf1upmb/t4 pcfdue7gK+Dbh4FmwkfUWOtt9ih3MLltFBYbEVxWohicfEC8Chpv7fmqu/38hVN8e5eheghWZnCl ovsD2oondf2YiyM5wtmQ5AGEBpg06LHgDL3RRRO449dzutFKb9Otd2ky0TGDiSHedM+yuuAyVfPp vYFyWHWqICsXteV3ucBqRHIS1eNovstrZErVA5ydw9k1zdP3QIcvEkzVJLMLO6plCHd9gox0t4sH SgKyVls0A3nLlskS5rHWb64KE/WV2B81w1cm5w+HF2SV3l4ECV9tHALNo0n1zfpQHJk6AMSj0tKS FDC+w3yFQ9tlgbZrZjXDLUw6RK1MR4omeL5f95TQ7WxIOMBKSTqrYiBPkyjEVzfCCoAX58lPM14h WqSXye2lHannS4fzMUz9TS346s+J4Hryg7MG5j+WdS4LEDzOMNz+oeDuQ/ii5DV6HpNaroQpvgsa MNjtvOZgWRDJUnSMIcxt2tIih2M69geXFb+I9hHqq/aOrxEWIDUPt592P4KbpR+RxQaVWmmnlpgs /qbCZQJgSeFmVbajSdFRv6Fuxg9JIFiCG4Md9cKv+Ga3ImsGCOVORUbSb7gZQJ6f1CXYP6jLQ33/ TXTnWscyW2tE1POh7USVoDYU5orerBfuTHyLiYAOR0KUZeByj1BdnTQG9lKT9Rr5teIPvuG2kiFi U6lrXZTCpwSphbjsl/7nzBZ+WGIapbbw+y7Q+EtpGnfY022lHNH/ClIE+PSVVtuIeiwYfE7uNt44 bcLmFbY+MedqzG1NwPyjcYat0AzWq5vtbCT4p7qS29zLtMOBPc05r1E/9DyLfk1F7FKPuksy8JMx 34oC7HtiYyWaiWSdJljUrxZZu8eUtK1ahTWaAOfOZbTFq8vUVwwP3iS++sOkXShT9GLh4Jh2Mnxr ubFwPNSjTw5Z4lVmWJfIxdmYiH0lnBhyGZiHX+Ep3u7JVcHYwBJKRT26AgzzjqoigIpyiZfgHhQx brWA+veb+ubXRwf0rpdlipJy0TFVOSUeu92mBwaw9Ep0E0TO1JxcMs+w4wF2pmr+mEIKhMWZ1Kh4 vAVjM0NyzHvU+I0+L5a07DwdS8fxHmm7OX2PhM2FZfK1fjK6yfDxEmn7R2Rm3eWDIyqpJlBTnaUG tqH1hmB25sjmRy5r+KvDHARv1olA0JudqpRdz1NpKWek1b//2FquhH2rWoU/0T+/o8kyq4/euPZ/ 4vJhHPIAOMdegl7JRAqXyayqDmcejuGiyJS0aPOtsfs6Ia8WQjq8quCz7t18x/2kKCfZghRRakqC 2KPrcQBzQNoQVBCgcFu/1V75+HASF7ZC4B6qnYsjPSIjDMeE+ql17V8fFkPF9rvM0yKiOQiTfrc7 HytTDfor2NrTeocA08XxDkWGxWK3u9Qk3pjlN44a3lBaghhznvMVfcAYrZXIoy7GUPdITdDQKLfb 3uS45Q8b+n4ueQUjMV3yIPhbalUyRuV+sSvi2NzToR7a/QeX0Ix4a3Bh6KJTdvJLGxvHA9zTyO4Y s+Me0NOwSqUM0M/OiVCVLpZv+IpIXE2SiMc7jZ7MePhoiRvGTuzcPE39Zz58beQMENWELezpMwUp jOhqJ+aDAWDWaiyQqiKAHtKKNfNAa0oz39SfPoMK4J6FCDP36TcX5BXsiX7nTHZjmE0FwZ/g9xBY k4MQFD9Ks7SYfEeWP1Z4kyu9FiElLi5kpi5na6iQJwOV2sQg6D9SwRFftsWgtaF0x60slODO/fAn u9qEAlD+TdzEWBoRrTnb7u82eBim/n0bJgTwa+jLBH/xpwS19CHIYWWha/WmRZ2/YdJOO3Im+XqU 5bxrT/AMBiRm9Azt69aDSxIlqaahUmTeWa9KPSJr+0ytWiRTV5rQaek15EJ/MqBY7t6oIZ/0f6fZ fXlghYL0VZ23Q0uPviYSdHHwZa/MoVUVdTh2+I94tkhC7z42c9gv0PGjb6A5W7JEAO9pXqzG5Zh8 NgiPLWJ6Gw14mnQQ2sR8kRYGyFMbqAhVJ+m2MFnkwVWxMlmUl7wBYcyPqEQbRzk6okUJQLgotaR9 6G7AJLf3bMtpCsvonSTMSp/7wITPTD5FTyNKb3bry6J5YRZfLytCb/n0K1+LTq3edRRR0EoIUd9h N3iw6zEVD8F7rkUfXWlUdCSoOg5Q3FKRKI+UT08wqmhXbex2Rd7del28ExRVmDBCwGYPd1ELnWrD Q3iPxN0T2S3l1HBdHOiu/qgXOUjJjPvMpfLbemTDNNZsC6cHS17x8G0kCBu/qS0AsbSbQe/9F1SD iMyTI07cV7wKJ6j+wLwX6h1gqPp0so2ZSANZ15LSZnfrdEl7CcM05NKOK3zFimAT6NjJ/2bff/AU YoyOy3qPZQ+y38MEWx7IVdY3aaKEnAV/FREqaiSUtP/fpvh4uVeZLz/muxuKvx8FWZaJO7hdr2Jg GR4mBiuX3JW/dq7Xewtw+6r/yG1YmK4G17BzaEWSk/AmIcjkNWLtxFfyz+kfW5BzF8/wQMlSskZ8 lcyZosWjy7qhtKo/M1VS2rG0JH2MhF04tRIJ0Wpq5dzJWGa4bAie0PP2YfdIuhmHFKUYoJgbjF9p iBFWk3teLeCoZppYYDuol3A69qPoADESqgVLIKij7+9Z4/9jbjhQ4mcqHkw3KT7eKG99OVxI8HSj jXK4PimH8QOEK0HE0x+kdOECiffb8f7MqUN+WFJgjio1b+f74SO7iIJrrWJJ3iR5q0gRn2wD9wfW 5nNGWpCLe8Qo7q9ulw3rMRiNhic3j9bsBy4cCbHOkPlFg2yOysX7j/HGs+XOI5YKSAZI3dEzZpqL UCsdCJFrR/MiykVJ1gSJVmv/JrLnoHcVHQBllLE3u9AvMcezlXQ6c5k6sYn9YnggH5UX2Op9tnDA 6CtMAypG8hRNycXdkFss9cE9858pd4M/k2zagYHZPbFblmhpJdkZr/bfMg3aQqQ8FG2AhnxOYvEM bLNtAo0TG29P9z1wV7OdHaMxJqyB4BMfQraiZ6hg+Z6jg4CNyp/TMeH7PzbnAG4DrRV4NVANrpjY RjkTm2gy17C4TVh6ABywYBTFZPokzKoud3an6f2yf1+zzr/IBMq5MVQesYCV7Gl73AHPcgp3hnV5 lLwi+g4x6adI9u/h7nBSXWQ+zv3YrfGBBly8RoFwkOB2HqeHmjOuI8x7YKqKiPHMoIMZXNfn/yTK 3EVZFWabu1pXa9tw+SvMtHYLDJxby4U+CLTH3dUYaU4mVK1hPIsKj7s1nWQ2XMj2s231UVw/Qwf1 rpN/lS65FR/mLqAAbRIOvo/jqNWJYb8zMradaHM7FRKFE03XfIt2ycAinrr41wvr5W6JJz69whav +/kRWuXGocnFbEXXrsOXN+WuJUC6i0FQNYmYpGgFtjucZyG1ET4pYI3+eMHUIuQGAv+i7m/FE6zA AzfA+UoPJjAnQEI/Bbxw9jzC9XofTPjMgJ8AgtqDWs+t9PaUMae9MDoww4WqG4Hl9A0Oi7VWfr05 fVvP/sk/J1zK3xCAQXCKdOFTfEade3BkJY2gYsOUE/r+CRuwZX765A6jnAKsOmUiWBpzIYZ++KKt BPRNeeDR400WDwAijigeT3Vqt56N002/K/Xh8PJXPrup/bUFU595HyIzb/APq06ykJYQhf+iJa5D 7Z/r1kxjO5uNrrhrUPegSw0aLQE7aYu1hH6reqjevztA8EtELXlr6lDBGPryHItSvhwnvnWpBe4f /ZpzjoSH9Ls3+zgNIqqV4gaLHBERpPM4H39oRTeYPIDaVT03GgqZgZ5e3HAtidTKj3+m7vghaU3P Gy+WYzxL5wAyp5OGfKUk1TTXgyMN7wnEbSq9doZkygKpFkWz2cAyZcA2kYuswPdrV1jVcqfAosff 25erUDeoXiq0kDmOJ1JjZgTDmRWQxFSRb2M8Enspft+a1eqeqK+Tyzt5NRgaRvGgUf/sDEOY98O/ yHAzmtKLbCZIczfBbsnaxIhtv/bDmXEVcWw5ifv+hj/VFRuch6rPUdWkn+/iXeHOM+k7C+ZWqKzS r11ArWOFmwUfy6i8NsWcDLI8dwbZb3DPDI3iAlVxs7TiVzz3iBULvqPzRZG5JwQJpPefLjcCxhln A7R3CSWn+nMHW4xhA6/Tjfo+E8R4O+sKDy2JbS8/iXZUS2ObU45hZMto7s5G0+Msbz2rvK3k+Hls oUadWU98xo6yWDjiPatHx3np7QX6LKZMU5ztzNNHVsJyQbp7nbIdZTSXSpFPnx4CBYY+pUbkpY7g LU/PNpPHxI3imgDbLit1NBkVY5uRQF8dULvTYT7DbNHdvZZw0Bw5b1CsVllaS9zxOpU550xC18n9 7ib1WYfdiFceZmtDBsKVIqmIlA7840cnaJxRhgw+ypKHSNkfOkoVpU/vqbwcUVddFHVmW0FU3OsU 5Y54Weg+Ysf+J4Fb+uQC3SUrLuogrXCXcantpcICoCZHBTKARBiQKUkv97zHt4qSiXG8Qxs+C6jm tIeIvpzrEHe9pA8KZjuvy8ifDBMyRkSHAHeYOVFZ94LLnQWdQjBLtP1OWJVklvFI78DC1NVaXUzi gjwwcRjElGhHjNAVu8PwQQJGXKI0cb/NeAo3H57jb35kY1rpaDC9k10k3bOrIbbxxB+oXeqxKvd3 7aEgp/Hvv1aAZ7DwXJIiF/uUflJ7alg5OfyiiNooxpw5D1ccBjAUwqvvtDv3zDayriou9IqW4fF/ T32FkkRMrh0Rw0jyDwYH7NLyiR5KwEmwzTY8FuFF/dIp/aWVJ7MQbT/8RpfP2nBIM7PpdRtVFnMq q+pSVPEMeommLfn1TKHsY2YyUctwOWqsyFm3yOKJI0ChJpt4MRjLSPgez07XrxLN1n4XihEfFbUr Rp24L1zHMkCQqisYPntSkMmpFRECIE5uwIyWn6ZrrAvGEXPo9iExy0jBZ9bccyK54lBs9K4NLZ1i WRpDIG00/gt2T91Ji86fbzYuuxxPVywEWDgWJjN91EOswYpUxxw8WvXgDykXbOaQDdIPYBr1VQ0R r4L3C+F4kMEkq90Nstzyp3bUzdNbpysrCYZlRbmuPy8onmI9soYV/3x8uY8JxcuNIRgPNWbxbmOs 6HYhs3e+XhSam25fqH9NoojYw05GuxRdANZzGzaxCjoi1Qf3qJtO8v0l3Ex4MkKu2XlmblDfNDMB p9NEFh+OhAl21PMvTjJCMGaxcmzxhTxBXXsy6lrSQn3v8UJrlFkmYDAay2YQqNa517tyk0kowOeJ m1Ma+3YYMDfmkQhnaQcXsE6gBf/rNvZ5w7HZgJkdl+pOosJBnwgQbJNbp2IFqRaLW6FLd2fWwp3G /DF9AiNfKDYzHWirUwGpx97RkXga6Oe9N6NnhQXKNQA7O0lVbtzgpiDfBrrQum+7lPeqfs68MzmS 2bfdycFcynVHgYEj57dtvCRHHUNZV+t6l8VgQk4Fj47TaAsNa3LBCfj/hAWvzSCzxn71zfP0B9DI 3VwiKD0F9W/4yGyfb7n/5iuKaC2OxvfQI9TGCf+/HdqZ827aRBVXi0Oswppuo5wYY712Oe963JcT z/tSXGO9a0L2XVFepSWVfK+3h8VfOwLf0zer1IC1TRzx43w9A4CIIxtAQPEkyqu47B4rFbJyiyPp SArG4Uf2c2pSEkMTMakM73OozIGJCAmNvpV54wahL8jNlYkc08M0O+mLAQeHs2JgpOovcn2R/ujL TmqKYZz97fSXuEf9P9npeud+MB04gmkRV2JO8sXayOOqaVNJfCy09cQmPOE1PWXi4DnKHzj31RYc 3ghFpoRBHQujePT4NtMGqxznjoKkm/xcMWx/KxeQHugHLbX6aItgH6ctiJfAajkW9hsBbwS558GH uQ2ZjI3Sb8+0E6rVYbD5sQ0gUZtIXObgZSzcq1gYMCO0cg2aWH6kSgC7zDIPBrWS6QNFHcm5kACI 7iuZdVzCE7Ri4zJNdSuoioc/aJjog4deObFNJMshQ47nm4g6ZmRvgby6K9689iJ1SxGXYyiCNDk+ AWQzbWHc5u2EvSuaiq5gc4N03jjPqttUOYNLpfnfL4oZPCCllqn6j003Ofy8uXKpXgeZBP4Kcqzb eUPXzxgYerw/9+2TqSylW0wV39m8TQ//jZ3LoXt13TEPWJr3p+O9tnaxw2AZ3e5PbMzsP5OEfYLm X1TpQ/TtSa08YjZX3FFf4ff/edG20v/TchsDAO+tdGpcizAQk/Q3jo7b15S5wiMpNnv2Zd6RWSj2 2pzfRGXy7ZgAaoS1J66ZofAPihXdMZdihOqDCdhb/ORh2uunVu4Nl+T2S6GBJtiKYnOIib6YUuiL Sx79p7SoW63KbeDLQdxOm7f4n8Z8WTs1t8TfNNVE5TnhTCgQfy/whgto7Z3NwoJMEiGNWbatpaRs /p1yY+t/MaaiRFM+b6k+EipdrCL/4Bzlv8oGrnmfUi6LYcLJYvB5A7pn9fYU/N0PaWOocVe0Ub6/ b/97gqyoll6ZD35ha7riNIdSTlbFfZmviQSft98RsuRWmCp4gqKQrMT3Ie9fhIm2yJFGYBzBOR+j +Ff24arpS7/sPdwV+b5Ioi1Kd2pUShsgDs9mDgunvzAHHSsqw+MTSvNKtTKLVTe5ZEwTl4co8XBZ xFtdgi6YQI6i333rQeYitJ9glHS7Uzayhjmm7pjEXoJ48mudl6vOdv70FVauo7yA9C7VlquOJ9f8 7yGdkU+1JKu0EqtQIj73XGea+vH+79LQi5Wd/fVCpv/bUNDHb/ctKW2Ozjdv7nfDTokdkYd2rBDK u3AYwAHYzHsDgficPQmSsau+3Uce2a84pD52Xk9wHD/kaIbm70mTpIYcrmPJ1WbcljhbPKZl9Vu7 a1///Buc7p6cFEgyLml6EBCjg2F3yni/Mc0E7ryt8v04Wd7oN+YDwBNCRMCgrrTK5DBDDptsbJtX tynNCj443LArEelA0jfK3aMlJvpvjoDmW02QuPmbXHdlDghAJI7VxLFMIhHgSziwk+dYRt91ylHU ITcztwSEcVRGcuLrDBCErVBfTM/f+b4NrRUsCHgzJERnFkF+DF/DoFmHNmINn1h7hMMmO0jvwSU/ Q5v7NPmo06pcV8/W26mDSRsYBpmFG4ybaNRJcoAYi8tZKonCWao6vPP4N4DuEKq0+KO+iD08vYjH Hci02eF/S7cp18WvSYkyVnO9lsiVpiiicpdTdEO+g5efuUOij/421tovE04bBRniIKWjH2jfXlEW PEIy282QOrA2YRrl1RGHh8ysT/QDSujM0D/DfEu+I2J8kEUfLWYSNthhu57VbFy4Zg50b+RT8hpi f7xNbx/+CXaIyCf3DEzTiY0uN7i8aICl7njxCXaX6hKoEl2OxJIX66xf9ZUmWrvQjnb2j2cVwbe5 5xNbWhDL/4OTW+QSKvKS5O92/tNTZXQKGq+siUePq6VwiHiOUyd4h3ZmJD+e5umyGNgFT9Xo5a3H 1ggxRlh7Eaqjol6ux2NFfAWD5Eh3RSNpT5XmbrhPyAWItPhNTlTZGBVrCbxP8oufITqRLaDaUKqn FGNFp/pqaqf2gOVN72KSpaErrusPWQeHC364Ip3mtn/1mexXjmkJFKhpy7YfkRlCl4lRkcMjw9fv DLlSRehKcJ4zLmf2ObeMnZoSxRtUJa+len/SRx8Dj8U4pqKc5p0lyCpDmayr+fNzseBF/tq0FRCo Im3modzJocrepvwwmLNp4rT/BouR17Ipwg3lpsfLDK+WIu50SVPKYS1Dqc5Yq74uCCS+nntYesOj S++SSn/vkaMmWimy06XL4fcM6jG6kFEN9eF4E+zrPBia7INK8Dz1jEhchXANrlcBYz1EUn01+vE2 TYTBaXnWJUCwFD6jIpfA9l5iKs9Kc7TeLKxvnqFZORVlhHwLey1mo+K/ON3Xgz3YwhaLanpZq2f8 vRbcvEzVsNQk0psbst0XiqkdEJIKo7QZK1Ujx40OKsnyxj0H71eWnYMLmW7sjppY7ZYBSowvzr19 /iGs6zXGicpEex/a4wd7ZYyvUg7h1zeqI5GO3zfK++Ktnkm+6yO+xZTYPmqdjZGkw+4WOCQORmHw t91CQYLMTBWlSjuQ22tkb12J+25/yY649E10VlnV1ApFDYdeKwlAkwBJEfgDnn1V9Uh/F2gp1w4Q kQ05WAasaa6Tdq6O1wQcHocJzfDZxK/cp2qkIs5tKouUuoNZxOS71Y/RNTZRiR8Xidv95gkzzRHx BYLN6UoJXavGriHzfA7hLsZZK8Bu12of5fNMHcpAuSj8fTFlWDvIi/Sd5K8lTm9xGfW64O3S1mKR c9pAZCDwWQWzOKr0fYm0DCNbcmuH2ltVib4J/WhA9q/+fwzZLtyJq3GZKJcnnPXypZ411CXpL50r a0jmLZgDmmwhc51aazPaHyt/fKb+c7oZipGIlzsT6RjhVLeG2uZqr4x/QffFdk80IgA5E0K5mu96 dRgAq+goxDfSFIF8qjJ/G/Yt0KXpe6gGUwXwMGpM4RG+eXXQSdcMjs+UyEOPPlmFEitL7/aXd8cr AeqKN3jf9ySYWpqlA0K/7nqJmgigU/3Bj21k1AyYynt8WiAhdpPl6wp8nJguB/tlP4HU7E2mWGhx P1wTwmwkpYgDTFc8ognJmCnw+w1HVOVBQdJJIZhfTbJJJFp+1LVJariCulRGNEmgHPZROxCnME5c BqtTf2vYujbTB/VMnBrl4kE/PWHSlBWij3kPM4BOl50kU1TPMXNsj/Pfpa74QKkP7MenwEH9Xt+w wwaf9PArVD0ixfe2+6h/Qc9/WHhIHlLLEMaiWtyj1uaCP1lRc51kPvGh0ow9WYXFL39mPo9EZU/q 9SZLUJBR2xJQwJ15bti3LU1qSKoDdteB8w2X7D+//6YuKqm+WtQJhhcGzzljI+V4NVpPaIsO9EpS Jfz5Y3W4oY8DJyy0NDZogRKzlncHHWTzVEXleHJ59EG05OhgxTClrJ+MxVUlppmIJooTnvyBRprX cJXEgm+VKnYHxr8qP435kSDu8+J2WPXOhiBLbeaH04+np+9hvorcS9gPAMu2He2Hvd/efC/FAuCF krAgnDMDFIFYbZTrnx4PeFIuMMMVsFE/Jt6umGMABXfxtQvCXvSG5ggp4XSlfYtIHgo6+SFk7JBQ 6eDXLKpciJo3tZ7E10a77q0hNWHCKtV2MaPGhexINvUIZRcEgONFvj7GN0/w51Mn+1nueQKGQPYX tVcnZEL3muxln2qJ5mPqUPJUllyDIZaaJJ4vsG7Zwh/Zo2SeB03gX7GYv+TCSZWm9NGqbduyKNRL iYW3VMEKNiDtyZGlUvGbg3Rp4b2oUYJpjWEeZ2mtaqR5f+w8dX4Sq5aHBQABqOLuGfN/4ec/Y5FZ zXxr5ZubDcJbjBorz8lVKYdI6GeVGdrb1Y0tk7E5oPZa5drZTB64jEY2kQcBuyY0eOk/jdWHaRNh 7W7mQIPa6AvJ/NLvDzs0KBlt47CKzwFo3WA1IOub3Ug4o32DA/Gx++GjTK+mZ10m94E1nIjcfLLg m2n21lBnqLDZVuQ8g3XYqS/st4V+mgG1Jq7fkKjFPjnthmptMBeljbC1UCjlwzC1kxM+unumrC7M DoXdSgct6Way12/7LmRCZFOhJopmpeZ2auvvvmWc8bVZSy+JRCNwdcUzBEg+PMauyJV1XfXgTm3X S6M0KCaeYZnDgiaT0cPwKFH4mQ8r6rbPLj6WTsa0l0QR96HcA83FL49bCAet4Pn3N5KVxywJWoLm noEpMQOToxfwWirtKdjuThOmjuE+ScA0l8iiq89YEiMjo3MYDWmzhDLzngWReMF5wKknThNzplV/ xTO/vBpHK2B2NpT5Rm0fg4x3y3I4b7ak5BeY/X/PawjbCqSM4IzQwnJ0fVn/B7qceakS5DhREwh7 a3/VZz4tVOSJbLVW6xGR2lVUADJDw7NaGIDHXMJHLS3OPNBm4s6KKCDrlzmDPYTpYrEr/V+bOcca R+fjc1OItJUBlm9qGn8C8it2EbSBVuqW+AfLEGnTanU+nR2u7D5MkHZbWC4HNTpjmn4pALpxZxVY NrwxadzCeY8o0orTwIeo/rmZSuIi5z1gQyU8LkNRrFLu54hrH3DUthfuI7nWKTi4BnEhAI0zjFch EW6jWZyimGqw5InHLa9/hqVGAJnvCV96ujGkY8HAjvbCrSRL9RKoeUyXm6vbt5Z3Cb/qO1UjvF39 FeJ3AJeSRlpXhGCLLElZtWyEorXhdQclSzzEOMYU3FbpK3Oxs0MLs8wczDjAwkkD7i5ioPsTO/RW gdmjW2E35UbIR4sw246GmtqW28eTX7nPzDb6LyJp7GOFCjXU8aMZ8r88jYY+1y2xDmzv5+RpcxsS SHFYbE0nkCQVkQpEdaImUlZC/l/FRxPHag5UaD8Yf5ZBbzvAesZAFH7FHHOM/uHddKAdm87GOjYm popiwisNsNGKcaP4PJHs+fchoXFEvNwQL+mZMEERkwQpKFvln1QvEWzuxDOFXAIx9UEEg73GTtRi s4DjYwrW0Cua1oii6NJgn4hx3Mf8BkZlewDK7Oq5Rj/Wrp7LmM3GWMPW8iadRH1JtjSAbhUeZMuW GnaeMfXzlw4ga2tzMO9ZhB51PIY8uQ+ztTnkU8rYHCgEm/zQi4Wv2kEV9laHkGnWkJadZWE6okXO zHNu1Lvf3ndOEBnOz5llQN0WCgynIyhXTIurljRjADHBwn6seCsH0uMUP5fB8rDhwgJhHWd8y3G4 WTIpD/CQpf+KP1NPqNKfpgsOZ91qgrNBHSDZzugyOfMCDtsxtc1+RdR30WMrBDGS6bzj5itEiTM6 oUYvlEheMXmvOxBnWcc+jom5cCiDLTm8kI1e4AE73KNaNtLZqlxOdxTQ6vjWj+Zy4QK/vVAYUCFo tVKsIEeh9sQ5T90e3j3AvE1E/yRTMgrmM0VexDzGWp3D3z2iroghsFbdmo5tWRQwXkrvFaPbrxJA gNguNqu4J6wvywI/PKMa91qnEAMrC0bWSm9nTS7QlYjc/0JcWLLFxfBBqigUD4oh5nASymQiw662 znpd3LtnGFBJTvGdkx1Oz/K8VymlywXBBJBX+w34tzbanx5QI+NRQfby+Z1ygfnu9meSVdhCrOBX m2DCjSK4rSsRMUp16w7MSpyAC0WJw6iRALZw4DKC6MDC4ElFVOCagBmU/pTOM1oLBQxguOuc++GB o/ejLtyEyvqaPSYGc5Gj/yBKU1H1jGr03Ga/3Nwx2dUC5oV1fd6h5udyXfG5d3CIPR/pUO7RBKPh c4XVAGtIDbYrAEM6z0sniEevbrqc9elplrPz/V+vDW30dXqdANJ0z27WzC8yHo5eftAmVSwCVs69 hlcn6GHbWBZSjhHmexjEv9VIhalMUZMV9NAbUFXHoB1Nc5hj8YvryDKGc4KZduQXWdIQsaHlMZ1H xwoDlz5nM4affajnd7/EcTTTvaVxKDTzEPzqIqrPoXeA9ZJWLnzcYEAhu7AeZZk2LjyzVusyWMaU mKQrSru8isPUrOQXjJUHslt7ztoMX0ItFJ8INELsvCWTPCVlNTzPNEua0Jlg8yiaYFq8M7GTOZuI sGUrrdGFyz/277geOUW5pRoeYkOxF/tNF7227bEWUV+Ai5z3DKrYMT3n7jomidC37tpPEpyVukiF JWdlfkv94SuTWiwVwC/VHq/J4aNbwmsr6W9hfECrYOMqf0xz/XmGUzpJx/P1s+tRdCCmmwP0JWMy ypOXSrVSKVcNOysWIH+f88DFaM11azN0jJFgQKabPIumDstUoCcWfjMriK7+gptDj2Fx9hF9ibvj 63EHjCZwaSUs5CtW0LKWFUXxMLLUywufc8LfNdguFY03NdhiM1UiDUtzSl7dCfcOPHwFnjGqUCsH K7Q8Fah4aeKOQbhGADWcsrG8GAi/fcqasNzgxkvz9fWbEy1r74N7d+fLQT6TBcXDnqEpgy+3OyfZ 3eSlIriYsYdooV55/aFLkpzr7A4KiPMUPOdKjhY0BCI0ru42l70od2ErCEiJVZTUErAl6ntDIsRR v1A3+AVo3UKZlAqiNETq66dLARaBWRJ275ArTPRLisRAcAhs8sMXG1CyquhoapV4xv7sBiOXwyYC a6ZLi5jx5g07dZiLsuoa+JZaikvE1X63T3dXby5nKoxIUkDJFX70s5E2PKQBmRIFY4ss/oDf2+ZW zw8On1tPDoceuVgHC6ghQKYaKPrjyt12IvXOiRBOH/a2Dj1Nhkj5UO6O/GrlDnXGUhaQ1Vs58qvI 5NibkrfrUvKipOjUCDSOYiKuYw3hYFqTEgaWGKluQZrEvqQr24YVjX3+/Gx6EvPwZ8C9d8BAh6Gd C2ONnfJDwX/h3gIURw3EqIgKteHjYQz2GQl+HM6XdKHC+1r0tobxvuMCX8B9m4eFp/+d7Ju87pwd h3g5juf0cjhvEI/axt3CX9ylEJkVNCjObdeUT8bEsGkU2ukf93PW/5ILN4Il2ROd+qlD0IJxb1Xa Iywc7TzLtFMq6+odBaaCq8CrLCnmbJZ2YKKovujGvR5LAJCTIAXpgeUezw2E/QReCWzlI/8wk2Qj QPPw83SVv/pB8fugLT/mawjNbYQyVBAm3R06+qPwbwCpfG5klgG6CFj/1xiODo3Ha5cywDRC60NV tZasLKpuvH1l6QnvAh4pMYQqYU/xwlSFsfuPtYhGsfhvN+OnXqPTJ+igaYwn96uGKL9fXX4+KhwL izkGtLUNaT6ejGfB+DJucaMVEhYd21A/WfjI5HpziI75pe4F1fBrltel2ya3mX09D3Y3zVznUf2L 0awiUZGIKkMk6/7e671J0q7n+SAxv9bX6jZbKfKYoYZSVzge6DL7vNKC05QwkZtrtYrv1GQvKJ7B +edX6sFPizuwicRZ3owIaChWUkOyedmQh0GlXjJ9qnTIkLotzU65eqCq12Al5DtMulm/XYZEmmXl 5IJW+5C9EzWME0vP4g95l3C8VLXzsNqfbWlU/IIbLDyg4a4JoS2EQbnNhT6OhgdLwCYcav8M7qCD Jht4iYFtNO1eb4OUkFuLNFgATdufV7VEc/QPo6Zb9NegoTdUDXJTpQr8CR0npsFbzHkPvORYYS7Z 1YjcGrjRW1RdtBUDFaYXz4kPLrbBXUxCtfGrQn1sxra+4a8gKcsiGF8OAL98jVv5tIePfNp8RVf0 WZ8gBDRD9rmwcN9qT0y0M03s/ibhNkyB0hiXswdyFQZU3GVYRimuvjKC+3+h1nxEOdoWmFuf/lgg cSgpSAQVQePXwyij723jS4KF0YpVvo2ZjsCd2hEwWY6XpDtopBt1HTja/QKcC3hRx3YxgSnklNdM ufMSRwvCjUTNpnsYSvbq0feHKTt2KayfivMgbcQWK6ONmpDRUyKsXYSXUqELq2x64pyy+7D1zdLc efAk8uStH6pScVdyxS4irOcl05APk7QEbgDdyPHGsNXVIfQ8i4FYV9PWt6C51sS/E9N0E0sWDwbm lmd0V8wzGUqRyFnDc9kQNPrGl6kzNvnxZtZVJ4gPaSQhfKguC0/S/Tj19xJmsAVNet/ULI+x42Je 1doL/8zYDNaWgXR6/jmMx5enPTUjxeDurd9h9DA6mTFWASSIxcg2GT32cdzTyAI5LZ5gyBNb73re k71yVYWWNsfo/whaIsgDFrtWp7puTgS/+Ln8SWGZvb4KFzlaTFiLObqe1BtU1K1HuysQhm5qB5df 0LYqFCfUXbVJyTh60XDpzzjza9am+/buZ5KpBD9NBnGnj9MsI2a7XM0t6ZtTEMK3dH+e8nha/uoh d8VmMUkk8aShcbRpth7j60fTQtibWlsS/rXL5i6sIYiMfdFjamwEfkCx7GZEZWdMn8a1/N+0PFvu L+AgNGb4pRoGhMdwoUNDYjloSCFzRGL52WVbXv7xkFK/NhCI0lFmYb2/0gphdCz0o3KegZd6CICC 5w7D/EuEaBPp8AAIeVsCahUQlrdvILsiqjTTWG4aSmfRoyY+mxMFqbeZKpeMkuzCXUeSFX5GrTnu t4t4kv7ov/tBVKMspijnOa5QcpJESZXFkdKIKswX/wGoC5PVu9yiOJD2X/ffo9Plf/AKoQ1AvzO/ /tuKY2NjfiZyzg+hbDXiTALHzhoGOzZvc6ltkcJJsdf0/SYYPIus1PrtCqjLT9Pp92H9xuqUyaXU 0AMuN1YlE2eWxwWT6Wo+/RZdmBWGvXEci/+omTOVhZ6CxY6jKf0KK7WWuw2PLNh3qzUCPoP3wsx2 iqUBdRRjuHOZ/SNZzg9+aL/v1LZYQvlndQvXJWVHeYbtKn1g2OFlCoFp65DGrFE5vtK1FHf0UNhf KiAz41cSIzk95S2phaWGUVStX2J9+j+Wl8nP09bKwq6QkM2CXp/JylHe/TgRUOFkIx+2HwxTn/Vy 7mttq4/nL7g9I+tpAnZP6XxlPgPe8/ZaqX5G0mTOwvYRMnT+Kz0OvN70wzmePgNP5xd+TQ6le67A Imr521kLYr9M3q/YhO7ksGzLgTe/SfNaoiGqwPooNiu0XqDRNx+ntc2/XMht1dG/7iFrSMVM8LYv /fSyAdBTQoYVyG2icgZXVEqFB18hkJK/RMfxEbr7XK4EWd711MnFwQp76k9TiSCAcz/1TeVdlOAh dzZpooUBhCk+LXLILkPkZHFt0Kwr0pBSWKv9G+/o8jnMhHSWo/FVGYWRkZuhKVyc8vm2iIQAcx9e +1xKiZWRhTp3aWLksCn1X4EyTnoHMQolHO+0hA/or9/efwjgla5zCidbiHKOKoAJ8m3+KnPYFpKC j776+xXg/zgq0qY7nsIjBLEPxC9r6rcPpybPMM9eZv/enia6Nz/cwif6L5xVBcLPnGBb6Xm4fLIw yIiiFk0Z9DvjUWQjgzILrCAZbwNHJAp2YqFs9gnWn9rFL3PUmKs9zHv4XnKbIGt80GjZ6jtFdkET akdgBg4j+OOdlPiSikxW9C4IPk1B/8RjvwbE2Cg4DYih+8D4Z3OR6hrx7IOauw7SJSkSFdM0d9gH YWd33L4Tdkw705/Xva++Ft9XlJfQCrsGx9QB+cw8zDO+Sg7K+zubIIIl7kny+PQ1LPH5l7Y3Vs2t m5NXnJcKhQd9f43JCthnS68TGJLLCF98lBiBvUTqfkz+zx3G860x7H74QkN/qL2ymKTlBeyhA3ap y3cQ9QVzDn/Ih6jgH96vhn7UVaxhl5ToeVmb9oJkILpVMbb5Dmh20q8nNBiMTHqZZDJFCIJr+UsJ jZRZPYPf5obJTpl01mvtMwrhHInKMKqHeR3wK3BJT4SAJWrLKQvp/gymIrdPkymNc1Ydzj/LeLwK T9EecrY6uxrJCNO4nmOIT3Rt6HZQsjvayEJ2UhVrup3dOSnHnftNQy4kjEvR+yl3HMwtAd/wpN+U 24F5Lw68atIf/6m0Lxzu2I6VEbpX+vsDoXSpqB5Z85yfhfSRG62l9ShGbgOIcLD9CyZEahn/nm4N 4JBtDkuSNcXfx5UnWpFSxcQn3/z8yXz4cLHfQmg678OmoRc6yIGNU+rhpgbzbUOOFelOfScjWcwb 3HxeMCW/xo42ni51qc7SX0ZSZbx1mlIobtZoMsniXanb/EmoXNimgpcHU+XB/B3Q38qkR+7vN20b qU7iu38rnTUaw2thWpvlJyzyY/bFQHY9qGrYHM3zUuyV5MSaT72HOra51u8u60do3XtZQs6f+4yF ccAt6h/EMFv2YRB5uPy1w3BmUD5CPx/PINDL4MbZ1HkcsH1I/D5q054zxnJ8cUqhho0joovuxzLy 70jwtIadLfLuIrx5zzzH15Lr7CpiFiP0apljFJ49D84nQ16SCRVnQqaW+w1MpSNkeW0ngGuY1lui 1RtJvBzzj2h9TBTWOLE/YrAgl0D8WO6w1Gx3K96Z8GdZnOd61xibDRHSCWxumupp7+9JIxlcKAxF +A/3BFl4gOt8S8GzoaifbUk5YUvjIR6hnkIRHruIerI/549GbufkqHRiRtmBOdICY6+uJPqGbhdN o5ZEpp91U+/Q5ueJzzQ3EtHTad3SxQ2BYyxk/0gbKNG260qz2j6aqBS0iCmnGlScc7e4a4Vhq/yu 8e9459MzP9oYptxRd2VuJlW0D21FycS7aexXxo75BM/IV9pwc8gWgvjHqXC46meR/TBVpKLGHjzq crsbEisAlw8ZWUoxK6u8Lx+ObGyrstIsCvmbwFfe2g1EaPJ2pC+2vW+/G9ZFlZOuf2E1sF1nxX1Y KgdyvwkTBIvUnTr3hGbSqeg/Lqp4qgvL+iauy8FCcOH31o92C+nj6ryPv23lfet4negjdHMqdst7 FVMP5vh4+w+CEwC6EGGTzA7EdxBC4MMEWKcUzQgqDG7nJWAcjRDnV/qixS8SGxTsbSzfCv8tv6kr prViiYHAMzoz3n+z1INqXES66J+NnhIYdvuW5DeHoVLBl9tUewEyLNVoRu62MQrFw6EumvBot4xC nP+PuExW9V3NTIZtllhthxl9tNT6o/B4/LliciMSI9KQHvruWb6FmweOfwrpRwJRyql3Wq6aZWQe JgeonSXtJNjLKlG5R0uOyYrjAkgcSpZ1O1tk0MgWpb20LE3VyWIC8VP8nf3FuTr0/iBZrdtg6FGs OCkMhHNGOpTPqbnRLiTMQtwND0pEdcOTs6FCGX7ALYqnCetfIuQnDa45TKFCOd02n9N00XH2EDvp A3xgwQyuWIBcofK1mxKfepHHR/3DsAHOuYJx3Ja7kIfhirPjZ4NJasSWtPS0RPkFXXSiLSGVrFIf HjF/Ej/0Mpf723bV80x7F+xeApRvbhyPjdyYuWtcwaE8Z8pX0MQEQOM3oxwI40FPgrg1duOFVCPu My5gGrxFbPKzt+PldJFleoyyeGY6aJ/C1CBWEtf99lAuuBKKOAXOvQj2di/YWvFPodrjfqiIMPHV 2Zd2KBJjkLGYph6hBwKDXvmfgm44Jynx+KFZTaQFu+Qp/SQ8YbMpUFN/JHcP2RsgPFT9ap+mQyou 4RqMmx5iqdESLIXYO2rqHQM87TiuPy+G1mWR/0cyx5pjKXF7CF6hwYoXH4+vgZAIZEKKyoF8xdt4 ScdOhWDQFGnP90gpIdXfGfgA35yvLFmK2PqsBjZn1Fm/8pWSLtPIAeNhLnuu3A5Z7fzZJTnweGVA /cZgxeys6MgWKUh67UJSHhpzZjWkcM/9i/ct4TlDWi8WrHAnWTo0vBilyl+q6kGk2I481GqSxEM8 xY0vx6EHrNP/yF9XhdDdHI8UO1pNYSwJyy5gA3/CUwW2imz1qnKR4xo+iqnMy6E7Eso8TFydpO7T 53LQYTopED6LjCh5iaJCOvy2kmkXU437vMTvMF2y3ilN1xtZEBLyklK6bwqB1ynp9boFE7Upsn3m /CJ6XRfMFK+zFYzOYTIv5y0JX2H3JUveR74N/sh8qSymxZwJ2Rr+EHJnK2B8DNCuN+f/N+CmoaCj Dgh4WIuhgT4ldrt1zZoqXIxDrK7u8t5m6HpDRFL3QUaDXNuBqFh1MuH3n++sYVLbP5t7RZ5sBBH2 tv5/QM7aATcRkFjVQF67P42I6RTzIa85Rohh7rQw0GKYa7FwOQLf2Ej4osEJGsnoqLTNMmK5Wg4q rAhaw0bTdHTmaX+y8jH3pInVNyqud8IDqPT8fZmiz516MTLB5rx5U6gmoOSEik+zRg9gUHZ7RtaW jA/LWQhniG6VnxoaMfzr/AQSeB1uTBCgwybWlmqlGMkyUsui92SKbbN1kG0dzJDoKeMlXrzpkGy0 hmI397viltALYBlWLmaJLTAP6Rm6LJ6d3ZHJXGvN765vaSFrhuGvd5GbMrJ8aQCSPgr15T2PClah Jwjx/MPJtmEyez1kZgB3bWNSvX9fTGYjiMhmSgqclBgTECfIt+ZyZ038k56ZDSKyTgmeHeESiZOT 4co/hqxuYB/HoXcsl6az3pJAuK/NJVhCwxIM/hpe1guWofHfUWZoBN+hUc1q1podb4mW0Wq0YOiu uvnVzMumblnDxl759mh8T2/gF8VVLz6WPKdDoognXL3f9r1V4efX8rTnlD6HnsTpolncsOV0F4b6 7q4JTyq+jhoiReefF+yknpa/QHRP1qUDBcSWRtCWOoHez9dkDEZyafMWy9ygnSEgMFb3mQtjslir Un0Zaawv8CNGsxwrlnLV1PhmXQ0BezJW4cuWcORlgmfbvGECpRoWgD/OPs3Ep742L7VnRFem3qYX d7ktYED91Zh6hqDRVKEEMU1BtSvBtfvirD/1tLhXooGlGxLahILD2NtGmpClEN8Ud6wJtovLoD86 arcvxRvcQWfSAjylp9DgaJ2/Di4HFCP/XmM/9P5jisilOpeVxNDWawGvLZ/Fxpx3s1s5P9phecp7 Ri/iIkeViJOu08aqZTVPZLJON9fzszU9JeeEJ3AiRISEZxNrr4oYn/bT1IwRKavfz5zxnbEAeE94 6dzIjKL72zhXtGmV7m1Pgn2vk4TyxOHdms8gpB2lznR7w1msSEY1IFJvCZ2sGZofCRv0zli0peVY 9B+HKCeeNY7Bb512o+K7Kr+6ZkYQ8sx5+EoZejfDTHyOdUwhaH00b+S8g+EyQ3iXnG+ScttdJpY4 BNJ/HBirzjMK+p7NlAzGxf9FIl+0E+u4ui62pAqtxwUd8uA8F1Coq79L1Vb1HVMT+UeTq40frVV5 jErMBl3LAzPamlNixJHubeNcRYL3Ek4NdTkzyo46Qv2nCF4erMMEA3cwolktOqmw/+FfUoc11T/T 6LMGUqLvxTfy+r4XsPh6NOZJRaKEuwNIL4wsc+x7/MzAYbT4ifqGuGhqCIZZ5QDkGs2kats1tPyc ayavd8UmWblz4hxzZwackYKYUZIhLGgPY9YQx0hLDulm9AusI0VwkJovTEzvz3ut9rqEvRSfWdFu wuL41hWqghoRIAkp6bdEHBHE6KGr2MfG4mORLDSnBGnJ6KqvQWugD4zP0MxsVbJR2EEwW4RWVn6z R0uRWOlMHRjWSEt7T5zwNRx9L5uQHopScIc3LxWlKYZHf/qe1RFTtd4Te1c81wLgKWExC8TALIW7 OnnYydi2saaiTU3PWnzwtCRBWvhochdcDWSqYCnXJ2tPkzVRasl6l4PUS4JPHlBHUPEiguCkICJz tv4Cye0skEcFQ2O10lVWqRyAWzHwCwgN8eSBtvMtTnR3SSwUbA12hg+TnykfUyUwwGAVi9uMjDlH /25zF8P3RsVRDeRO+6yI3igPHyBL4EtPgOElpsKHXcUB8SdouF/g/SqGt6EpqKOO0AcJuWuW3pPw Y+1IjEbteqN6HHetd+eJ6vT5V7wd4yiLHnwWGKctcblWwjczlLt+1AlgSSqeaa5zCxuDBVeyImHi mSyZJG3iaKWzNaNLdux6HhCw86TKO39lV6ye3A/cgZpcSl+auTnK7pEuUt0GXEtx+S9iSCWyq0d9 hHx7tXEg3kSIpcOXElgox4mCnJHa2X+Azhcivxd9jblFv2nR1CAf/cyg8t3akSTWALDNAZc0PUSK W6SYUa5gIBy2iZ4HRhRjS6b+V2thIg0kBnnzBOeO98Rvd3h5DDVf+6+vVbuUKjnEVOFLCyqn+j3U TWTvJQtE5Rqu2INYC/yWWDAutjL+x8KP9VBxAoW4YvvuAQHYm0G0+HCt4M8LU+fDCu3UOSW6asMk 4hQk8Hh8jnWjauowh9zv5ciH3yOVTql17ggj5yIm2e0sNkqp7io0eK7UNjzOAPFFxL2dOjtz2Fg0 tS68hO4MXgvkPDVyH/hiWguS0pCvstMlNv1ZY+ZvxJR/UMIJKFaVQCRgdTs3M2spA1U7dyd3fE2O mqdiDnUO2zSFJ9SW15EAaeomZ9EeX7uJQtK1L9g59ICLxWxitb3hgzRFK0jI8slxWUVX0Xn0BLAd NqbViGxMkT/SeJ/u+T4EPSQJ2dbXdXZ7a5lFGxQQlV1LTOY4YT6jFY9nX1lO5QwyZU4tC+N2+F1D MQAvZzgWsNex9jKDniSlNbuDh5rPmAfGWXeKJ0BzlxT5szRiG8tYNww7f7RQe0O1H8mIE18cA4py EquTtGF2YXDc2HorDE7MIExaczT6f2g//m66Sznmz4aNHwpD4lpGZDnPIprn/Y1V4Dl5FsBitdKZ /MRz0s+iK6tR27+EPNHKsz2gxQygopH6ivlJjk6zO7P/WDnRwI3oY3RjvslQW3vPiN4MAafrOBe6 dbFzb+QDUQZLMN1iqHcRtD3EUkax0ju0LJFkbDVF9Ya6Evnv5tWBT9tlVcGx+ZhKzUnoU31eWwKq sM5c7pLH+WC2VoUwSQDPAOsQ+lFCyBLGNuHWtT96bYhQLqa5pMh758NAFuPeSG5EmNhqWqK6Hek3 DW85m4PInGdOtLYdmvk9hsmxV1D9DPwvu2bVZKogQqrSzei/nXutJesfGaSQmyoho11cXvA+aJaN L2AdDl5aWfHCFBWxk82X9HZMWmJgjUHewMkgyidKnVEf4WrZQYJfW+OAOkoh/HR8Z3lvi8trVGnD +1kLKihU78BYXNXPG3D4nVgtRg/0ex6nEZnf8e2BIHWdeTi+RGmd0PQvep6zDwlaSQxxgFprwWPc BkP+91S5oE6z7hJIx3aEaQZEWQFuMTMzh+pBTKx12p+CnQETFcnFER1EWl5+7sLEhbmNONHyCCTO hSqFaYHCM3d7UGsCSAZZ79oFpIUs47aH6yF6zsz94W/BYrKksQuCl+yIBtzoh8ZfJzXEszBV6k4w ZdRYyWnX3BGgJH/xc/M33KYSmZqlevmVNEuMDwoiicKcBhwFm2PK1PRtDYAHnqjgJ3zEA0Xs0LlR JDqNVTl+tjJnkBQNPOeSCO151kImPXcjXrdoSySIE61BeYmC/L/44VxhRz7kk2Bs5z5hA39EZQjR Yw/JSZzZE79gJuZT/Hz37vgsnJYetG+rUY2erxv08DPmF9AypxniAFqt0V+tRp1aHjuiZM0weVdu E7rHqvx9msCR7DkR3zu0ac3di55++UNH19h4pu4+QO/LT9Q4EA1vkuVSSMF4i3Uuik/AKohHK5LC EO5xz+Afh9jj9CAaNTjIocyxPQ6beu435ZpSBq7u9VHtpmJDw1Q4ffEXWP/d98zn70lKszn4DYmf QGFV53H+JAt9Gr4SjSHsC2x2fc0gW2KE4qCYYdVPTISDL7idWDNBcbNTIzLK6zFSlKb4MXPqJ4Mn fWV/bnMZMJLIIksn2bpzAsZftNOxtPxF5p0xqyF/v0mYkEkVEz/V2aqf6IevNrLBjIepXmVtRFLA piaTygQ9YrAy+FRoAOLR+IoICnQklBARdEvPJRLP4Umulvadlq3BLnkidthJYgK0U55fNjZmwPiJ cdGV27jRIuWguoBF+FfxxdWzAKsw9TkYlUQM6daVSdPgjf8C3dOAOBPQ4q6eGC3FazW3B1R18Qx2 69iBvT0D73DkJnALfQehUNCpS2UWyQrrDB6DChawSiK989ln1pBopRzK28knbBqUthPqMUEP0wJ3 ehTIHMttiYnTQ95bJoa1Gv9GXHR2NNtcK3AoAsbPTkEGcx3XWAqFutmbOBcCsWl2lUroQjPCmCEF w1E4qMlM6e/P1tb57U9zxPjssNagHL1p2uQEM22JffNqgaHcAxm2VZKkY1E+gLOwIAWq/kVAM+fZ 32/azfebZEyFnnSF9lSnF3IL3+WLjKD3IhgiBFvLNdBcdbb7WJ+Tr4rRBcxcdZ1ft6+d0ivfuYFk P8Bk9uQPr15cjLz4WrqUMoojlt00EouyEDfVepikT4V/SEKkO5u35I+uPhnG6dIQl/YSUnykpMYE VccwAIdT5BBv0fDTFRZpRSapan2hFvItpLpAMir22CfKpgtDk3H9erBvk2gfJZzLJxZ9rmqkq19l EENxD8Sceio9yOqOL+n+dTho7NIIlhGX8tViIzF8RMvQtEQcuU+bvl5O6H134yLTmHqIzeTv8CEr PxwHshScrYKoceet2y5F0yLcqT9chLTrVgcFQfouBzw3KpuRwmSFq/7KFkUz3tOCwH7r0J3oSGZu P6J9RGn+XVjzLthGaG0fvrNcejplkq7WeFPgidsk7yr4cz3+SSJUqM1SROqpSd/8Hnm26uAw7M57 atQD4/pMcPNulN29sVIFQFm257YFqVGkvjSrbGo8OFvpVPhlfO49/zK1WRtS9AUZc6AooOcfVDJC e1bwe+ri3pE7A6K9UklS67kkG95OsQFg+Tqs4Wjtk4jBGzmblEQrB3wEEVQmmdY0h5grB/2MFcp/ WZCRIOpn3ctsYkz/yRC2QlmE86y04moe5bR80jNNARCBUIcji7qPEUVKRNS6d04SUTb3mZYszKU7 +fLOZCGDXG7o7vPqArEN5Tj4Gd4T8/3AbKYUZccG0Q33RAUbwCN2X9GMqLm6WtFiEFwsoswjbS5a 0fVOKIA4IlvsbtLqNBUXzI09UG7UQLZlgGZyG4CE+ZARAnnvQvb1dR1Vl91V6UyfWFHmx4FxIltg JUQALnrxa5P/dYk+hISuUu68uixMpoBHwXekggCnvzaT5Z8CZANwNMP0OOF9/B6nHej+8RS9S5BO xzGj3BtJsHyoyto1OEyNvmIm2g8AHBosqS5eGfhrunlbsyaoR3r2T7JnyaVYKxmoKwIobZhx9U35 WcOOOW5hvSeMb8UOifY0UlmQ6LOHHIc6MqD/DkvdtikxcTLP9lwmi8Bv/Db/cuDhuKa/cJ43QTLw qsn6bdF3yx1Xhrb3VXFqKuT5QqDVHWobK966Js9pIAIR7XX/PbEizavCgdSSe/vOBIQM9j2eNIyQ gXMvET0HD4+ydvmFnXgpFNoJ7dG/tkumeBaWzmK+okYSxUzT153s6eHvStnP0GnrcZu5UOPOphtT iE4FUo8/zWAuo2U1kwXvXZ4cHsJ47Rd2vzXdzFLT+ep0/ZR9oRtDu32F29rkjLHYQd0HkLeeHBFp mp2xdQM2w0qey/ytm0NzM+4N9cnTeSuyjA8XgaBJ4y4fLUqHySR2XM4LaeqcE9UcigHEgopSR9nI wi3WVTjf/mbpbNUz2F/WzbxDIAodPTy2AWT8mOBwwnluH2W7TisWLHMIA+en24nU/nSIYFjFfWhd FGISEPGQFfUpctM9mbaDjd6v51Y6SByhCxuMUKuKkf0TMdH0H+xBCl8RJXLj8hoxf1cOAAg/ikEb YBznT+VrgNNEyElbivJGquHWCSrH4SIB829KdfpITy/yDmABmsLx4dTzFu0h+3INdBM3gY8ZAiSG ukK8ondTWsh+j888Ji8GBpIGM28iDHEjDir1jSswXlZy/72VaDs8P6S3yqnAymhyjtiAk1TT+SpD omSTy6dFpKEFkQo/iBEGP6y5pQIe/BufqqxwKgNHoga69jurtq6Hm9tPH67IqDBC/JylCsdD8ITr UoJzyqfXQN3mtROc0giEHsPctiHvfU6IqD6uql7ZrlHlLsRXSu3lsRe/V5z7adaRDYpEMm2LWx3c 4n75zOlDHHtY5RDHXeVwP7Xe0R4/hCeyD03MviLHyMXOzlaXMRd+SaK33We0E2qotZMHkPC//GHp cCNFa75+5VZO7wgVS/e8/h9WVVhV6ISgE8nxcyJ3IzOYFcqbQVlf+y0b6y/ODQizwpnKV32GffvU KEuGMl8inyhh0Aw1dGcM6+iVLNHGS5E8BDFuOpJ8AEYcVa++OTvabyYSiYdGytpzGrhHO5Ov52zN XKL7mwQYd3Kv3uRxAQCuDo14CTGXdKp0n3ajm5IqqdkJbEFUxZXPTSuRsQvqN1rbMtBEM2uRPjbW r9PVqHNXeOHdUZEwLn2Wj0DhQ7uVMrz0xWkkqg4TAMoWx6oKCMqVN0qyhumjhl0+9scDo5dq/KB9 eNKXcaof6szC11tbe5YW4eYhYwMsf2474We46qzswFJomi1Cw9V6nClkCkX1g7Y89BS00beSBiic SQhxNZHHydMr4qGKY4Qgr89kPHJTh6JOHQOKKYPJFPNQCklrR7uigp1SwxiSUvvKs0PlMw8yzUt8 g6Xx4eBW9nlK3Boi2jfBMuClDamm1n9bols+etYQ9smWmFMF96fk2ePfUS9yVwK71qqXG19gDJt7 S6qaVRTpvGyfwWAgr3j7kVw5Dr6rh/oNPijy32nBJGd3TYs5kN+wVWnLNfMoV3cYmAaiePyVeBUE O0oI8aKEINENFESBRI6v17wh8LznN9Ak4mY3jziCIJdvX1dqnXyCO8av+YgrEeFv2VWXtQXaSKYt GwzdMggc6KlibeVstOijTvlBm7H+y/lSLFEh2Qsx+btlCOw1HapSBn7sBzPqAspWYK+HjTzSaTmS EvoPBqBMXwjP4m2tIreAKTEIVlF8b2DebTsr9WYjhL7pE0TEWmFybOZ6ml2HdgrXs3WSfBqRzfJ+ EwrFfLwqG33Pa/f/ft020uLIAftEk9ksfZ+2+QpzwCDnYRGBXmfPwmji5pESPR2VgVYUots8IVHG 7ox8EFtQR/7ofRNldWmLd62j1eLu5JNXJksf5XERmH8vqUrJFOuS8gY8vRpNbTUZJ4E74CsZtrWI ZGh972CrardGm4RD1OPY6TRoeoyFk5YP9hjDYAWDbTaMUSDeErOlyFsr9vMi7AEwZfMQdEor+Sfu q1bq882lU+IJjnIRnOn2+iDSXQnNPItqIu6kypTOSz1pbNWsgEbWB11fosfz92OXZE67iSEtG7y9 BqLAzZc/x1xwoOir/dWCRiuhfp5g+XfNBJN7rSnXKuVSuDSvPvnyVNS5uK1jVum5/qLtor5/lFoC SSLyZsf8xtEfnSzhlJiMwmHgVFNgzgbzcktGiuF5s0wiA9+EPw+o1Tc3DudflACHE3ZT0gR+ESkN JPezc9gt8/6GAdnu6bX3qH+yDn3c8PfXbuSsQ4QrXfLxxlQf5oWA4Vsoup2hEAhJyglYx4abQQS4 bSzRxleA63rmKVEWNVhrcQq7jvY12CeVSljWdLQ5SuMwHzxQL405A7dwOAuFMDkfV4eV8vDkyeP1 AWNNBfEmOoBBEUUAydAXiWiGSRl/sZVdw4f7uYlnJhjHp5YtSi3jkgSmbcJoDBQTKY8T7Cdpm1dZ WxvHNrg2+7XVUcbx1s4ALOQm/BBD/EJOELaqfZ+OLpl+vOuqrcSt+/rLJgqnrj9z8T2YAiJ8yu7T hMEfzpEm6SqAKEbG4xrQihu0m4nIQi6P0P5A3vQ4PP3A+JJ50tMLRZBH2cdj+IRljAMVBTyb/CAD 8geqiMAiVX6+/YA3peaEp5qTKAgoYAoSZ2krztU6Gx/Ty1iVhedrbefUWL0vdjwEAggYLUT8jq1w tAvzkVNPKNIhyIdUhI4DSFYyWmNJ0QuPEARBiyBfr70B9q/6abDbL4mcDaXo8cRvqy5VEyKyp1NK UaziOp/BSU5maAoLVpp1FZECT1U1iQoQ39b4RFkMoGqEBniGbbfauh1BaqM+Kdl0R+ctDPxCl8sN LvPnWpqu7CnYaDpz/KZVhxRuyLn674nCPzWiZcXeXGyR9lQS7dB/nRBAo8ccgouoO6bYwZPoOvtA siR5S/fGfCkEq9FZBVpNDteg9lJktNaTrKh6Iqc8DIB0OFI8XOtFkJ1sbkGqR9Z6lQqljP+Opfzl /zz7zOQx9wbCGMYefxlBckjQDYptICBitxQObP+TnV2QMKqi+FiUYcKbs8bv2ntAqlsHRHVfkOgP V8UYe1ezAc21rYda0KgWEAQ45iB3kpozL8JmrQHqw0WJ8w5hjgO+ZG/GCKRoMj2P46OOaq+NLcd/ J8xCFjnPWzjfuCyR5bWgvFVaOqqAsuf5/aF+YeOEZo+fNY+MZ7VhQ1MxD58NiMQTOVFU5dat8/89 AgsDVAGUjsiIZaDbWbtM+ouQWLYlniVMhxbNzLAxHoHMIN8qJfg/ORX+xSGqNTGc6YYXR4VWeC7T yib0+yA6Oux904BRmaCTFrqdaI9bLjMsJe1sy6+Z4ZyPsidy0yCdaKvH5i6qn/vWV8yS0Fkd7TKi ztZJiRPvF83C9fRHLTARbRJZUnYGEUc0zeglietFSFMd+EwWJ4Yl6dV01H5mXr9wZkJAsUXuwJOZ IDGEYmNuyo413uLoAWBJfkCSd3G+a9qYHCt3paAcRusLSsT9D5W7HRnjsmLFXCACAh80Ive1xV4P b+I6ICyWC2nixOMduneEM7miT1IXDRZaxaEI+aH+bZks6ad0NOM67oYgt7EydFUo7g5AUGcosFWI eFMpp4qjPlvN+aq9jyPv8cVqMmB6lfHPZtDIhLBdBVn7z2rrOW4ekzaQg805rTm1iv/URUZTs4VC CKzT1nGsOpo2wyBVt1q6RALmrgsXOU1XPmh1F/yzRwYAT3ENUGyfq3VRER09DbCz98jb5CvKmZEv hDv0SzbHBvx/ZGjXftggwvVBWjFdrh/heXIMUf5cdmMvsbtMIEpBB6+GtT06HliAU4pZJlGYvi21 /CBfAxRI3AT2cZOodM3GVln2Je6BLnrPCVMa4xXilC/yV4g6f8kvPCLYpyXcXBFNDXLdLHFnP785 C+ijYiKgueH4z9a/igZy8H/wTKI6RwlN9vGdgvGKCwR6vOxGffOciYrRha/8QOPjiG/CDPpl2F9P ROe1rN7oyGNKczfRHWxp/rRLpKacdciEDhtbaVCTrUcTehZQ/px/tm9DH71kxls5Vue3jzwdG1Vp pwxMH6yJKCRa+SmTKfefkcGWxNy0y3q3f6DmyGhT/gbpYBgMnFnWzUrP/oE4l99ncrPxJ3+VKOYC 0cjSxOa+kYBDfanbd6AZqLYSohXFGrlAErBOb9QoHpb+mcqFLfn43QakQgSZqOCaxj6qHmQFqgyh rOExKMfF/gpo87wC1vULck+x6K4+Fzby4EHmUhwmxyQ7FDtKGr9e2VNPPeulzSaeJ3GnNsqICtIG C2LWGNJwiE70NyYF8idPir5CjJpFQBBZyPruVewtOshBtFvWtpVY6rVe2Ro82fjB1sSLa/WKezo8 QmSCTCHtK544VxvutzVXf0RmJZEk6dLSTQ+RNxCDtsDRovJIf8RfnLI/gkIIsQGgCvi4uVCYYJsn WRjTQ3YOFE5FIh7kFq9FAozRjK6WuTd96gg3FWEvH3EQBhrdz4am0jZNKAoHkKOMGf7N4I6WxuLT jjfALRFZvUycyqY0wpg3qX3EQmLJfZmCJna1n1BwcC2D1NdeC3eI8840eBgcmDepuuOXNpz21jQG 4yiX2Ee9j0YGsYRspjuXWLQDV5s44gQ+nbX3DBxCPLHGT6eQVqriuTFyAOxankSAqhWXROsx4HiV XILYquMvN87SAPkanCErdqCjLweqmow9ykmi11fRpOq6mIidRZsdOqguvec1hlT24D7O+bADBXc0 opE/cJd1WYeTGcsvP0zGqsyPABvCvHEb7S9Y/p7Tp6bZa+TI8GH+q+ykYVrI5vUdKlzXUjOg02Sz xfCCFdU6IAYGEdYek6lCM+i9R+pl4ZyDqoIL0iVvIVosxcPjD3xu9zN1LZKHUdlgIv8Y5nLzwS44 iqav4IaQoSTrHfLiXhlKaSRYut4mgYA9fZjUmnLgaxmjQZl9wCuvk7ay8ThHvsOUMCfzm2uuOGe8 M6402MkxU+OP6d0ctGuNTmCkR8plvy1xey8EV9adQckwX8bjxa9Y9hGB9l2u9fvkzs+bKXB6j1ke E40+A7pLCzu0CeRX4AIDWqpXYpq8CA+RwPjTdk4GRe5bA4VPCdwmxmSk4Gl59EUeFqQerzHFVaci ovxXUuEYiSeyvBjKG1S3irp+Jm/6pPEKDT6dtyJMG48a6G/Hhe5neGYVM6hivWi+uZwlaMHMNFqE /9+/+Go/ds1JOdC/UujknXCnMkax31mXXxIgI+Zije+0JrMdrP7q2fojx+nbGw1Vi8WJiNj6vAYm qLyoj9nm+EkJEOHAns9fEAuADMSb5QmNYqqvPUZc0aaDAw+BrSxFJ7rj2ztZpImcqydWk0KEoycc YH7+YufD09ytGhGNNDR7DLfil07hY6G1YCzmCHCCvKeUmlhFnmpaT+p3pMOqH2aLlvUDgTT+VvYO oFMEPjlTOiDNK0r1OLLlrqx+DWZ9h5SLAPgdUXZhQ5SHAbAQ7v5mJLJddVQ6SIEdJYeg/+N3K03s /mlcRYH6wiI5PIt04bGa47q8VCWY0xOXUhjFvfr6dRgpSebYZWudwTmR6swy1q+XM4rNg0XE9JAF iZ1i2TJc3pTR504KvATbXG1YbhgABJf4CNzO6iN8mMSZJi0sM0BDMU8MpB4a61uVBu7hixxYRg2b A7EcYujKiaBya+d9RZCOJqAa/J+LLsZHC9ZvXap2ZLS5HQK83H2BBDpySdxNAUoyKiyE4ru8uS82 mljzRF3sHH0uIY40sRIIm5EBD5dvXckurxodPvmCP4wth7Bjc9pLHez2hy5htNbMIKiZ514QTXit N17HkzrsUxMZS4YE8EsL0w5Apd3rvVaiT2+LEkdh394hkcNQPEKS7blN/DLAalMMsrc/ZkJErTW6 JbKlCHi0fRXnl+102aWc/T1gOVvsrbbqYowxwImAJaZN2XMIWdj22/3IiJ7OR864IyxZVBqzrawa UneEOBB7jtcQuht5xNOugk2R+ddRI+910LFa6lt7pazotsh2mC647KCOKxVUXJpMRvq5hHS5S19r ghKtr0VIRJHUzZJyYN0CQ6eOKLj9T5wCW4slG82hIdTsZ5Nf6X57MrJSaJof `protect end_protected
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3135.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c05s02b01x02p12n01i03135ent_a IS generic ( g1 : integer := 0 ); END c05s02b01x02p12n01i03135ent_a; ARCHITECTURE c05s02b01x02p12n01i03135arch_a OF c05s02b01x02p12n01i03135ent_a IS BEGIN TESTING: PROCESS BEGIN assert g1 /= 0 report "g1 = 0 " severity FAILURE; assert g1 /= 1 report "g1 = 1 " severity FAILURE; assert g1 = -1 report "g1 /= -1 " severity FAILURE; assert NOT( g1 /= 0 and g1 /= 1 and g1 = -1 ) report "***PASSED TEST: c05s02b01x02p12n01i03135" severity NOTE; assert ( g1 /= 0 and g1 /= 1 and g1 = -1 ) report "***FAILED TEST: c05s02b01x02p12n01i03135 - An actual associated with a formal generic in a generic map aspect be an expression test failed." severity ERROR; wait; END PROCESS TESTING; END c05s02b01x02p12n01i03135arch_a; ENTITY c05s02b01x02p12n01i03135ent IS generic ( test_g : integer := -1 ); END c05s02b01x02p12n01i03135ent; ARCHITECTURE c05s02b01x02p12n01i03135arch OF c05s02b01x02p12n01i03135ent IS component ic_socket generic ( local_g1 : integer := 1 ); end component; for instance : ic_socket use entity work.c05s02b01x02p12n01i03135ent_a (c05s02b01x02p12n01i03135arch_a) generic map (test_g); BEGIN instance : ic_socket; END c05s02b01x02p12n01i03135arch; configuration c05s02b01x02p12n01i03135cfg of c05s02b01x02p12n01i03135ent is for c05s02b01x02p12n01i03135arch end for; end c05s02b01x02p12n01i03135cfg;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3135.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c05s02b01x02p12n01i03135ent_a IS generic ( g1 : integer := 0 ); END c05s02b01x02p12n01i03135ent_a; ARCHITECTURE c05s02b01x02p12n01i03135arch_a OF c05s02b01x02p12n01i03135ent_a IS BEGIN TESTING: PROCESS BEGIN assert g1 /= 0 report "g1 = 0 " severity FAILURE; assert g1 /= 1 report "g1 = 1 " severity FAILURE; assert g1 = -1 report "g1 /= -1 " severity FAILURE; assert NOT( g1 /= 0 and g1 /= 1 and g1 = -1 ) report "***PASSED TEST: c05s02b01x02p12n01i03135" severity NOTE; assert ( g1 /= 0 and g1 /= 1 and g1 = -1 ) report "***FAILED TEST: c05s02b01x02p12n01i03135 - An actual associated with a formal generic in a generic map aspect be an expression test failed." severity ERROR; wait; END PROCESS TESTING; END c05s02b01x02p12n01i03135arch_a; ENTITY c05s02b01x02p12n01i03135ent IS generic ( test_g : integer := -1 ); END c05s02b01x02p12n01i03135ent; ARCHITECTURE c05s02b01x02p12n01i03135arch OF c05s02b01x02p12n01i03135ent IS component ic_socket generic ( local_g1 : integer := 1 ); end component; for instance : ic_socket use entity work.c05s02b01x02p12n01i03135ent_a (c05s02b01x02p12n01i03135arch_a) generic map (test_g); BEGIN instance : ic_socket; END c05s02b01x02p12n01i03135arch; configuration c05s02b01x02p12n01i03135cfg of c05s02b01x02p12n01i03135ent is for c05s02b01x02p12n01i03135arch end for; end c05s02b01x02p12n01i03135cfg;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3135.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c05s02b01x02p12n01i03135ent_a IS generic ( g1 : integer := 0 ); END c05s02b01x02p12n01i03135ent_a; ARCHITECTURE c05s02b01x02p12n01i03135arch_a OF c05s02b01x02p12n01i03135ent_a IS BEGIN TESTING: PROCESS BEGIN assert g1 /= 0 report "g1 = 0 " severity FAILURE; assert g1 /= 1 report "g1 = 1 " severity FAILURE; assert g1 = -1 report "g1 /= -1 " severity FAILURE; assert NOT( g1 /= 0 and g1 /= 1 and g1 = -1 ) report "***PASSED TEST: c05s02b01x02p12n01i03135" severity NOTE; assert ( g1 /= 0 and g1 /= 1 and g1 = -1 ) report "***FAILED TEST: c05s02b01x02p12n01i03135 - An actual associated with a formal generic in a generic map aspect be an expression test failed." severity ERROR; wait; END PROCESS TESTING; END c05s02b01x02p12n01i03135arch_a; ENTITY c05s02b01x02p12n01i03135ent IS generic ( test_g : integer := -1 ); END c05s02b01x02p12n01i03135ent; ARCHITECTURE c05s02b01x02p12n01i03135arch OF c05s02b01x02p12n01i03135ent IS component ic_socket generic ( local_g1 : integer := 1 ); end component; for instance : ic_socket use entity work.c05s02b01x02p12n01i03135ent_a (c05s02b01x02p12n01i03135arch_a) generic map (test_g); BEGIN instance : ic_socket; END c05s02b01x02p12n01i03135arch; configuration c05s02b01x02p12n01i03135cfg of c05s02b01x02p12n01i03135ent is for c05s02b01x02p12n01i03135arch end for; end c05s02b01x02p12n01i03135cfg;
architecture RTL of FIFO is type state_machine is (idle, write, read, done); -- Violations below type state_machine is (IDLE, WRITE, READ, DONE); begin end architecture RTL;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3198.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- library std; use std.TEXTIO.all; ENTITY c14s03b00x00p42n01i03198ent IS END c14s03b00x00p42n01i03198ent; ARCHITECTURE c14s03b00x00p42n01i03198arch OF c14s03b00x00p42n01i03198ent IS BEGIN TESTING: PROCESS file F : TEXT open write_mode is "iofile.12"; variable L : LINE; BEGIN --write out to the file for I in 1 to 100 loop WRITE (L,character'('n')); WRITELINE (F, L); end loop; assert FALSE report "***PASSED TEST: c14s03b00x00p42n01i03198 - This test will write TEXT into file iofile.12." severity NOTE; wait; END PROCESS TESTING; END c14s03b00x00p42n01i03198arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3198.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- library std; use std.TEXTIO.all; ENTITY c14s03b00x00p42n01i03198ent IS END c14s03b00x00p42n01i03198ent; ARCHITECTURE c14s03b00x00p42n01i03198arch OF c14s03b00x00p42n01i03198ent IS BEGIN TESTING: PROCESS file F : TEXT open write_mode is "iofile.12"; variable L : LINE; BEGIN --write out to the file for I in 1 to 100 loop WRITE (L,character'('n')); WRITELINE (F, L); end loop; assert FALSE report "***PASSED TEST: c14s03b00x00p42n01i03198 - This test will write TEXT into file iofile.12." severity NOTE; wait; END PROCESS TESTING; END c14s03b00x00p42n01i03198arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc3198.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- library std; use std.TEXTIO.all; ENTITY c14s03b00x00p42n01i03198ent IS END c14s03b00x00p42n01i03198ent; ARCHITECTURE c14s03b00x00p42n01i03198arch OF c14s03b00x00p42n01i03198ent IS BEGIN TESTING: PROCESS file F : TEXT open write_mode is "iofile.12"; variable L : LINE; BEGIN --write out to the file for I in 1 to 100 loop WRITE (L,character'('n')); WRITELINE (F, L); end loop; assert FALSE report "***PASSED TEST: c14s03b00x00p42n01i03198 - This test will write TEXT into file iofile.12." severity NOTE; wait; END PROCESS TESTING; END c14s03b00x00p42n01i03198arch;
library ieee; use ieee.std_logic_1164.all; entity mux2to1 is port (i0, i1, s: in std_logic; y: out std_logic); end mux2to1; architecture mux2to1_rtl of mux2to1 is begin process (i0, i1, s) begin case (s) is when '0' => y <= i0; when others => y <= i1; end case; end process; end mux2to1_rtl;
library ieee; use ieee.std_logic_1164.all; entity mux2to1 is port (i0, i1, s: in std_logic; y: out std_logic); end mux2to1; architecture mux2to1_rtl of mux2to1 is begin process (i0, i1, s) begin case (s) is when '0' => y <= i0; when others => y <= i1; end case; end process; end mux2to1_rtl;
library ieee; use ieee.std_logic_1164.all; entity mux2to1 is port (i0, i1, s: in std_logic; y: out std_logic); end mux2to1; architecture mux2to1_rtl of mux2to1 is begin process (i0, i1, s) begin case (s) is when '0' => y <= i0; when others => y <= i1; end case; end process; end mux2to1_rtl;
library ieee; use ieee.std_logic_1164.all; entity mux2to1 is port (i0, i1, s: in std_logic; y: out std_logic); end mux2to1; architecture mux2to1_rtl of mux2to1 is begin process (i0, i1, s) begin case (s) is when '0' => y <= i0; when others => y <= i1; end case; end process; end mux2to1_rtl;
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_iic:2.0 -- IP Revision: 7 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_iic_v2_0; USE axi_iic_v2_0.axi_iic; ENTITY cpu_axi_iic_0_0 IS PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; iic2intc_irpt : OUT STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; sda_i : IN STD_LOGIC; sda_o : OUT STD_LOGIC; sda_t : OUT STD_LOGIC; scl_i : IN STD_LOGIC; scl_o : OUT STD_LOGIC; scl_t : OUT STD_LOGIC; gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END cpu_axi_iic_0_0; ARCHITECTURE cpu_axi_iic_0_0_arch OF cpu_axi_iic_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_axi_iic_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_iic IS GENERIC ( C_FAMILY : STRING; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER; C_IIC_FREQ : INTEGER; C_TEN_BIT_ADR : INTEGER; C_GPO_WIDTH : INTEGER; C_S_AXI_ACLK_FREQ_HZ : INTEGER; C_SCL_INERTIAL_DELAY : INTEGER; C_SDA_INERTIAL_DELAY : INTEGER; C_SDA_LEVEL : INTEGER; C_SMBUS_PMBUS_HOST : INTEGER; C_DEFAULT_VALUE : STD_LOGIC_VECTOR(7 DOWNTO 0) ); PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; iic2intc_irpt : OUT STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; sda_i : IN STD_LOGIC; sda_o : OUT STD_LOGIC; sda_t : OUT STD_LOGIC; scl_i : IN STD_LOGIC; scl_o : OUT STD_LOGIC; scl_t : OUT STD_LOGIC; gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT axi_iic; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF iic2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_I"; ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_O"; ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_T"; ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_I"; ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_O"; ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_T"; BEGIN U0 : axi_iic GENERIC MAP ( C_FAMILY => "zynq", C_S_AXI_ADDR_WIDTH => 9, C_S_AXI_DATA_WIDTH => 32, C_IIC_FREQ => 100000, C_TEN_BIT_ADR => 0, C_GPO_WIDTH => 1, C_S_AXI_ACLK_FREQ_HZ => 100000000, C_SCL_INERTIAL_DELAY => 0, C_SDA_INERTIAL_DELAY => 0, C_SDA_LEVEL => 1, C_SMBUS_PMBUS_HOST => 0, C_DEFAULT_VALUE => X"00" ) PORT MAP ( s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, iic2intc_irpt => iic2intc_irpt, s_axi_awaddr => s_axi_awaddr, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wstrb => s_axi_wstrb, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_araddr => s_axi_araddr, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, sda_i => sda_i, sda_o => sda_o, sda_t => sda_t, scl_i => scl_i, scl_o => scl_o, scl_t => scl_t, gpo => gpo ); END cpu_axi_iic_0_0_arch;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:module_ref:ControlUnit:1.0 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY RAT_ControlUnit_0_0 IS PORT ( CLK : IN STD_LOGIC; C : IN STD_LOGIC; Z : IN STD_LOGIC; INT : IN STD_LOGIC; RST : IN STD_LOGIC; OPCODE_HI_5 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); OPCODE_LO_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); PC_LD : OUT STD_LOGIC; PC_INC : OUT STD_LOGIC; PC_RESET : OUT STD_LOGIC; PC_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); SP_LD : OUT STD_LOGIC; SP_RESET : OUT STD_LOGIC; SP_INCR : OUT STD_LOGIC; SP_DECR : OUT STD_LOGIC; RF_WR : OUT STD_LOGIC; RF_WR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); ALU_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); ALU_OPY_SEL : OUT STD_LOGIC; SCR_WR : OUT STD_LOGIC; SCR_ADDR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); SCR_DATA_SEL : OUT STD_LOGIC; C_FLAG_SEL : OUT STD_LOGIC; C_FLAG_LD : OUT STD_LOGIC; C_FLAG_SET : OUT STD_LOGIC; C_FLAG_CLR : OUT STD_LOGIC; SHAD_C_LD : OUT STD_LOGIC; Z_FLAG_SEL : OUT STD_LOGIC; Z_FLAG_LD : OUT STD_LOGIC; Z_FLAG_SET : OUT STD_LOGIC; Z_FLAG_CLR : OUT STD_LOGIC; SHAD_Z_LD : OUT STD_LOGIC; I_FLAG_SET : OUT STD_LOGIC; I_FLAG_CLR : OUT STD_LOGIC; IO_OE : OUT STD_LOGIC ); END RAT_ControlUnit_0_0; ARCHITECTURE RAT_ControlUnit_0_0_arch OF RAT_ControlUnit_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_ControlUnit_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT ControlUnit IS PORT ( CLK : IN STD_LOGIC; C : IN STD_LOGIC; Z : IN STD_LOGIC; INT : IN STD_LOGIC; RST : IN STD_LOGIC; OPCODE_HI_5 : IN STD_LOGIC_VECTOR(4 DOWNTO 0); OPCODE_LO_2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); PC_LD : OUT STD_LOGIC; PC_INC : OUT STD_LOGIC; PC_RESET : OUT STD_LOGIC; PC_MUX_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); SP_LD : OUT STD_LOGIC; SP_RESET : OUT STD_LOGIC; SP_INCR : OUT STD_LOGIC; SP_DECR : OUT STD_LOGIC; RF_WR : OUT STD_LOGIC; RF_WR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); ALU_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); ALU_OPY_SEL : OUT STD_LOGIC; SCR_WR : OUT STD_LOGIC; SCR_ADDR_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); SCR_DATA_SEL : OUT STD_LOGIC; C_FLAG_SEL : OUT STD_LOGIC; C_FLAG_LD : OUT STD_LOGIC; C_FLAG_SET : OUT STD_LOGIC; C_FLAG_CLR : OUT STD_LOGIC; SHAD_C_LD : OUT STD_LOGIC; Z_FLAG_SEL : OUT STD_LOGIC; Z_FLAG_LD : OUT STD_LOGIC; Z_FLAG_SET : OUT STD_LOGIC; Z_FLAG_CLR : OUT STD_LOGIC; SHAD_Z_LD : OUT STD_LOGIC; I_FLAG_SET : OUT STD_LOGIC; I_FLAG_CLR : OUT STD_LOGIC; IO_OE : OUT STD_LOGIC ); END COMPONENT ControlUnit; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF RST: SIGNAL IS "xilinx.com:signal:reset:1.0 RST RST"; ATTRIBUTE X_INTERFACE_INFO OF PC_RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 PC_RESET RST"; ATTRIBUTE X_INTERFACE_INFO OF SP_RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 SP_RESET RST"; BEGIN U0 : ControlUnit PORT MAP ( CLK => CLK, C => C, Z => Z, INT => INT, RST => RST, OPCODE_HI_5 => OPCODE_HI_5, OPCODE_LO_2 => OPCODE_LO_2, PC_LD => PC_LD, PC_INC => PC_INC, PC_RESET => PC_RESET, PC_MUX_SEL => PC_MUX_SEL, SP_LD => SP_LD, SP_RESET => SP_RESET, SP_INCR => SP_INCR, SP_DECR => SP_DECR, RF_WR => RF_WR, RF_WR_SEL => RF_WR_SEL, ALU_SEL => ALU_SEL, ALU_OPY_SEL => ALU_OPY_SEL, SCR_WR => SCR_WR, SCR_ADDR_SEL => SCR_ADDR_SEL, SCR_DATA_SEL => SCR_DATA_SEL, C_FLAG_SEL => C_FLAG_SEL, C_FLAG_LD => C_FLAG_LD, C_FLAG_SET => C_FLAG_SET, C_FLAG_CLR => C_FLAG_CLR, SHAD_C_LD => SHAD_C_LD, Z_FLAG_SEL => Z_FLAG_SEL, Z_FLAG_LD => Z_FLAG_LD, Z_FLAG_SET => Z_FLAG_SET, Z_FLAG_CLR => Z_FLAG_CLR, SHAD_Z_LD => SHAD_Z_LD, I_FLAG_SET => I_FLAG_SET, I_FLAG_CLR => I_FLAG_CLR, IO_OE => IO_OE ); END RAT_ControlUnit_0_0_arch;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity inline_07 is end entity inline_07; ---------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; architecture test of inline_07 is signal clk, d : std_ulogic; constant Tpw_clk : delay_length := 10 ns; constant Tsu : delay_length := 4 ns; begin process_3_c : process (clk, d) is begin -- code from book: if clk'event and (clk = '1' or clk = 'H') and (clk'last_value = '0' or clk'last_value = 'L') then assert d'last_event >= Tsu report "Timing error: d changed within setup time of clk"; end if; -- end of code from book end process process_3_c; ---------------- process_3_d : process (clk, d) is begin -- code from book: assert (not clk'event) or clk'delayed'last_event >= Tpw_clk report "Clock frequency too high"; -- end of code from book end process process_3_d; ---------------- process_3_e : process is begin -- code from book: wait until clk = '1'; -- end of code from book report "clk changed to '1'"; end process process_3_e; ---------------- stimulus_3_c_d : process is begin clk <= '1' after 15 ns, '0' after 30 ns, '1' after 40 ns, '0' after 50 ns, 'H' after 60 ns, '0' after 70 ns, '1' after 80 ns, 'L' after 90 ns, 'H' after 100 ns, 'L' after 120 ns, '1' after 125 ns, -- should cause error '0' after 130 ns; -- should cause error d <= '1' after 35 ns, '0' after 77 ns, -- should cause error '1' after 102 ns; wait; end process stimulus_3_c_d; end architecture test;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity inline_07 is end entity inline_07; ---------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; architecture test of inline_07 is signal clk, d : std_ulogic; constant Tpw_clk : delay_length := 10 ns; constant Tsu : delay_length := 4 ns; begin process_3_c : process (clk, d) is begin -- code from book: if clk'event and (clk = '1' or clk = 'H') and (clk'last_value = '0' or clk'last_value = 'L') then assert d'last_event >= Tsu report "Timing error: d changed within setup time of clk"; end if; -- end of code from book end process process_3_c; ---------------- process_3_d : process (clk, d) is begin -- code from book: assert (not clk'event) or clk'delayed'last_event >= Tpw_clk report "Clock frequency too high"; -- end of code from book end process process_3_d; ---------------- process_3_e : process is begin -- code from book: wait until clk = '1'; -- end of code from book report "clk changed to '1'"; end process process_3_e; ---------------- stimulus_3_c_d : process is begin clk <= '1' after 15 ns, '0' after 30 ns, '1' after 40 ns, '0' after 50 ns, 'H' after 60 ns, '0' after 70 ns, '1' after 80 ns, 'L' after 90 ns, 'H' after 100 ns, 'L' after 120 ns, '1' after 125 ns, -- should cause error '0' after 130 ns; -- should cause error d <= '1' after 35 ns, '0' after 77 ns, -- should cause error '1' after 102 ns; wait; end process stimulus_3_c_d; end architecture test;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA entity inline_07 is end entity inline_07; ---------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; architecture test of inline_07 is signal clk, d : std_ulogic; constant Tpw_clk : delay_length := 10 ns; constant Tsu : delay_length := 4 ns; begin process_3_c : process (clk, d) is begin -- code from book: if clk'event and (clk = '1' or clk = 'H') and (clk'last_value = '0' or clk'last_value = 'L') then assert d'last_event >= Tsu report "Timing error: d changed within setup time of clk"; end if; -- end of code from book end process process_3_c; ---------------- process_3_d : process (clk, d) is begin -- code from book: assert (not clk'event) or clk'delayed'last_event >= Tpw_clk report "Clock frequency too high"; -- end of code from book end process process_3_d; ---------------- process_3_e : process is begin -- code from book: wait until clk = '1'; -- end of code from book report "clk changed to '1'"; end process process_3_e; ---------------- stimulus_3_c_d : process is begin clk <= '1' after 15 ns, '0' after 30 ns, '1' after 40 ns, '0' after 50 ns, 'H' after 60 ns, '0' after 70 ns, '1' after 80 ns, 'L' after 90 ns, 'H' after 100 ns, 'L' after 120 ns, '1' after 125 ns, -- should cause error '0' after 130 ns; -- should cause error d <= '1' after 35 ns, '0' after 77 ns, -- should cause error '1' after 102 ns; wait; end process stimulus_3_c_d; end architecture test;
-- ------------------------------------------------------------- -- -- Generated Configuration for inst_e_e -- -- Generated -- by: wig -- on: Mon Mar 22 13:27:59 2004 -- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_e_e-rtl-conf-c.vhd,v 1.1 2004/04/06 10:50:41 wig Exp $ -- $Date: 2004/04/06 10:50:41 $ -- $Log: inst_e_e-rtl-conf-c.vhd,v $ -- Revision 1.1 2004/04/06 10:50:41 wig -- Adding result/mde_tests -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp -- -- Generator: mix_0.pl Version: Revision: 1.26 , [email protected] -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/conf -- -- Start of Generated Configuration inst_e_e_rtl_conf / inst_e_e -- configuration inst_e_e_rtl_conf of inst_e_e is for rtl -- Generated Configuration for inst_ea : inst_ea_e use configuration work.inst_ea_e_rtl_conf; end for; for inst_eb : inst_eb_e use configuration work.inst_eb_e_rtl_conf; end for; for inst_ec : inst_ec_e use configuration work.inst_ec_e_rtl_conf; end for; for inst_ed : inst_ed_e use configuration work.inst_ed_e_rtl_conf; end for; -- __I_NO_CONFIG_VERILOG --for inst_ee : inst_ee_e -- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ee_e_rtl_conf; -- __I_NO_CONFIG_VERILOG --end for; -- __I_NO_CONFIG_VERILOG --for inst_ef : inst_ef_e -- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ef_e_rtl_conf; -- __I_NO_CONFIG_VERILOG --end for; -- __I_NO_CONFIG_VERILOG --for inst_eg : inst_eg_e -- __I_NO_CONFIG_VERILOG -- use configuration work.inst_eg_e_rtl_conf; -- __I_NO_CONFIG_VERILOG --end for; end for; end inst_e_e_rtl_conf; -- -- End of Generated Configuration inst_e_e_rtl_conf -- -- --!End of Configuration/ies -- --------------------------------------------------------------
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity tb_moving_mass is end tb_moving_mass; architecture TB_moving_mass of tb_moving_mass is -- Component declarations -- Signal declarations terminal msd_discrete, msd_mdl : translational; begin -- Signal assignments -- Component instances mass1 : entity work.mass_t(ideal) generic map( m => 10.0 ) port map( trans1 => msd_discrete ); spring2 : entity work.spring_t(linear) generic map( k => 2.0 ) port map( trans1 => msd_discrete, trans2 => TRANSLATIONAL_REF ); damper1 : entity work.damper_t(ideal) generic map( d => 5.0 ) port map( trans1 => msd_discrete, trans2 => TRANSLATIONAL_REF ); Force1 : entity work.ForcePulse_t(ideal) generic map( initial => 0.0, pulse => 20.0e-3, ti2p => 1 ms, tp2i => 1 ms, delay => 1 ms, width => 1 sec, period => 3 sec ) port map( trans_pos => msd_discrete, trans_neg => TRANSLATIONAL_REF ); Force2 : entity work.ForcePulse_t(ideal) generic map( initial => 0.0, pulse => 20.0e-3, ti2p => 1 ms, tp2i => 1 ms, delay => 1 ms, width => 1 sec, period => 3 sec ) port map( trans_pos => msd_mdl, trans_neg => TRANSLATIONAL_REF ); moving_mass4 : entity work.moving_mass_wa(behavioral) port map( external_attachment => msd_mdl ); end TB_moving_mass;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity tb_moving_mass is end tb_moving_mass; architecture TB_moving_mass of tb_moving_mass is -- Component declarations -- Signal declarations terminal msd_discrete, msd_mdl : translational; begin -- Signal assignments -- Component instances mass1 : entity work.mass_t(ideal) generic map( m => 10.0 ) port map( trans1 => msd_discrete ); spring2 : entity work.spring_t(linear) generic map( k => 2.0 ) port map( trans1 => msd_discrete, trans2 => TRANSLATIONAL_REF ); damper1 : entity work.damper_t(ideal) generic map( d => 5.0 ) port map( trans1 => msd_discrete, trans2 => TRANSLATIONAL_REF ); Force1 : entity work.ForcePulse_t(ideal) generic map( initial => 0.0, pulse => 20.0e-3, ti2p => 1 ms, tp2i => 1 ms, delay => 1 ms, width => 1 sec, period => 3 sec ) port map( trans_pos => msd_discrete, trans_neg => TRANSLATIONAL_REF ); Force2 : entity work.ForcePulse_t(ideal) generic map( initial => 0.0, pulse => 20.0e-3, ti2p => 1 ms, tp2i => 1 ms, delay => 1 ms, width => 1 sec, period => 3 sec ) port map( trans_pos => msd_mdl, trans_neg => TRANSLATIONAL_REF ); moving_mass4 : entity work.moving_mass_wa(behavioral) port map( external_attachment => msd_mdl ); end TB_moving_mass;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library IEEE_proposed; use IEEE_proposed.mechanical_systems.all; entity tb_moving_mass is end tb_moving_mass; architecture TB_moving_mass of tb_moving_mass is -- Component declarations -- Signal declarations terminal msd_discrete, msd_mdl : translational; begin -- Signal assignments -- Component instances mass1 : entity work.mass_t(ideal) generic map( m => 10.0 ) port map( trans1 => msd_discrete ); spring2 : entity work.spring_t(linear) generic map( k => 2.0 ) port map( trans1 => msd_discrete, trans2 => TRANSLATIONAL_REF ); damper1 : entity work.damper_t(ideal) generic map( d => 5.0 ) port map( trans1 => msd_discrete, trans2 => TRANSLATIONAL_REF ); Force1 : entity work.ForcePulse_t(ideal) generic map( initial => 0.0, pulse => 20.0e-3, ti2p => 1 ms, tp2i => 1 ms, delay => 1 ms, width => 1 sec, period => 3 sec ) port map( trans_pos => msd_discrete, trans_neg => TRANSLATIONAL_REF ); Force2 : entity work.ForcePulse_t(ideal) generic map( initial => 0.0, pulse => 20.0e-3, ti2p => 1 ms, tp2i => 1 ms, delay => 1 ms, width => 1 sec, period => 3 sec ) port map( trans_pos => msd_mdl, trans_neg => TRANSLATIONAL_REF ); moving_mass4 : entity work.moving_mass_wa(behavioral) port map( external_attachment => msd_mdl ); end TB_moving_mass;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: various -- File: mem_altera_gen.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: Memory generators for Altera altsynram ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; -- pragma translate_off library altera_mf; use altera_mf.altsyncram; -- pragma translate_on entity altera_syncram_dp is generic ( abits : integer := 4; dbits : integer := 32 ); port ( clk1 : in std_ulogic; address1 : in std_logic_vector((abits -1) downto 0); datain1 : in std_logic_vector((dbits -1) downto 0); dataout1 : out std_logic_vector((dbits -1) downto 0); enable1 : in std_ulogic; write1 : in std_ulogic; clk2 : in std_ulogic; address2 : in std_logic_vector((abits -1) downto 0); datain2 : in std_logic_vector((dbits -1) downto 0); dataout2 : out std_logic_vector((dbits -1) downto 0); enable2 : in std_ulogic; write2 : in std_ulogic); end; architecture behav of altera_syncram_dp is component altsyncram generic ( width_a : natural; width_b : natural := 1; widthad_a : natural; widthad_b : natural := 1); port( address_a : in std_logic_vector(widthad_a-1 downto 0); address_b : in std_logic_vector(widthad_b-1 downto 0); clock0 : in std_logic; clock1 : in std_logic; data_a : in std_logic_vector(width_a-1 downto 0); data_b : in std_logic_vector(width_b-1 downto 0); q_a : out std_logic_vector(width_a-1 downto 0); q_b : out std_logic_vector(width_b-1 downto 0); rden_b : in std_logic; wren_a : in std_logic; wren_b : in std_logic ); end component; begin u0 : altsyncram generic map ( WIDTH_A => dbits, WIDTHAD_A => abits, WIDTH_B => dbits, WIDTHAD_B => abits) port map ( address_a => address1, address_b => address2, clock0 => clk1, clock1 => clk2, data_a => datain1, data_b => datain2, q_a => dataout1, q_b => dataout2, rden_b => enable2, wren_a => write1, wren_b => write2); end; library ieee; use ieee.std_logic_1164.all; library techmap; entity altera_syncram is generic ( abits : integer := 9; dbits : integer := 32); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (dbits -1 downto 0); dataout : out std_logic_vector (dbits -1 downto 0); enable : in std_ulogic; write : in std_ulogic ); end; architecture behav of altera_syncram is component altera_syncram_dp generic ( abits : integer := 10; dbits : integer := 8 ); port ( clk1 : in std_ulogic; address1 : in std_logic_vector((abits -1) downto 0); datain1 : in std_logic_vector((dbits -1) downto 0); dataout1 : out std_logic_vector((dbits -1) downto 0); enable1 : in std_ulogic; write1 : in std_ulogic; clk2 : in std_ulogic; address2 : in std_logic_vector((abits -1) downto 0); datain2 : in std_logic_vector((dbits -1) downto 0); dataout2 : out std_logic_vector((dbits -1) downto 0); enable2 : in std_ulogic; write2 : in std_ulogic ); end component; signal agnd : std_logic_vector(abits-1 downto 0); signal dgnd : std_logic_vector(dbits-1 downto 0); begin agnd <= (others => '0'); dgnd <= (others => '0'); u0: altera_syncram_dp generic map (abits, dbits) port map ( clk1 => clk, address1 => address, datain1 => datain, dataout1 => dataout, enable1 => enable, write1 => write, clk2 => clk, address2 => agnd, datain2 => dgnd, dataout2 => open, enable2 => agnd(0), write2 => agnd(0)); end; library ieee; use ieee.std_logic_1164.all; library techmap; library grlib; use grlib.stdlib.all; -- pragma translate_off library altera_mf; use altera_mf.altsyncram; -- pragma translate_on entity altera_syncram128bw is generic ( abits : integer := 9); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (127 downto 0); dataout : out std_logic_vector (127 downto 0); enable : in std_logic_vector (15 downto 0); write : in std_logic_vector (15 downto 0) ); end; architecture behav of altera_syncram128bw is component altsyncram generic ( width_a : natural; width_b : natural := 1; widthad_a : natural; widthad_b : natural := 1; byte_size : integer := 0; width_byteena_a : integer := 1 ); port( address_a : in std_logic_vector(widthad_a-1 downto 0); clock0 : in std_logic; clock1 : in std_logic; data_a : in std_logic_vector(width_a-1 downto 0); q_a : out std_logic_vector(width_a-1 downto 0); wren_a : in std_logic; byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1') ); end component; signal agnd : std_logic_vector(abits-1 downto 0); signal dgnd : std_logic_vector(127 downto 0); signal write1 : std_logic; signal enablex : std_logic_vector (15 downto 0); begin agnd <= (others => '0'); dgnd <= (others => '0'); write1 <= orv(write and enable); enablex <= write when write1 = '1' else enable; u0 : altsyncram generic map ( WIDTH_A => 128, WIDTHAD_A => abits, WIDTH_B => 128, WIDTHAD_B => abits, byte_size => 8, width_byteena_a => 16 ) port map ( address_a => address, clock0 => clk, clock1 => clk, data_a => datain, q_a => dataout, wren_a => write1, byteena_a => enablex ); end; library ieee; use ieee.std_logic_1164.all; library techmap; library grlib; use grlib.stdlib.all; -- pragma translate_off library altera_mf; use altera_mf.altsyncram; -- pragma translate_on entity altera_syncram256bw is generic ( abits : integer := 9); port ( clk : in std_ulogic; address : in std_logic_vector (abits -1 downto 0); datain : in std_logic_vector (255 downto 0); dataout : out std_logic_vector (255 downto 0); enable : in std_logic_vector (31 downto 0); write : in std_logic_vector (31 downto 0) ); end; architecture behav of altera_syncram256bw is component altsyncram generic ( width_a : natural; width_b : natural := 1; widthad_a : natural; widthad_b : natural := 1; byte_size : integer := 0; width_byteena_a : integer := 1 ); port( address_a : in std_logic_vector(widthad_a-1 downto 0); clock0 : in std_logic; clock1 : in std_logic; data_a : in std_logic_vector(width_a-1 downto 0); q_a : out std_logic_vector(width_a-1 downto 0); wren_a : in std_logic; byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1') ); end component; signal agnd : std_logic_vector(abits-1 downto 0); signal dgnd : std_logic_vector(255 downto 0); signal write1 : std_logic; signal enablex : std_logic_vector (31 downto 0); begin agnd <= (others => '0'); dgnd <= (others => '0'); write1 <= orv(write and enable); enablex <= write when write1 = '1' else enable; u0 : altsyncram generic map ( WIDTH_A => 256, WIDTHAD_A => abits, WIDTH_B => 256, WIDTHAD_B => abits, byte_size => 8, width_byteena_a => 32 ) port map ( address_a => address, clock0 => clk, clock1 => clk, data_a => datain, q_a => dataout, wren_a => write1, byteena_a => enablex ); end; library ieee; use ieee.std_logic_1164.all; -- pragma translate_off library altera_mf; use altera_mf.dcfifo; -- pragma translate_on entity altera_fifo_dp is generic ( tech : integer := 0; abits : integer := 4; dbits : integer := 32 ); port ( rdclk : in std_logic; rdreq : in std_logic; rdfull : out std_logic; rdempty : out std_logic; rdusedw : out std_logic_vector(abits-1 downto 0); q : out std_logic_vector(dbits-1 downto 0); wrclk : in std_logic; wrreq : in std_logic; wrfull : out std_logic; wrempty : out std_logic; wrusedw : out std_logic_vector(abits-1 downto 0); data : in std_logic_vector(dbits-1 downto 0); aclr : in std_logic := '0'); end; architecture behav of altera_fifo_dp is component dcfifo generic ( lpm_width : natural; lpm_widthu : natural; lpm_numwords : natural; lpm_showahead : string := "OFF"; lpm_hint : string := "USE_EAB=ON"; overflow_checking : string := "ON"; underflow_checking : string := "ON"; delay_rdusedw : natural := 1; delay_wrusedw : natural := 1; rdsync_delaypipe : natural := 0; wrsync_delaypipe : natural := 0; use_eab : string := "ON"; add_ram_output_register : string := "OFF"; add_width : natural := 1; clocks_are_synchronized : string := "FALSE"; ram_block_type : string := "AUTO"; add_usedw_msb_bit : string := "OFF"; write_aclr_synch : string := "OFF"; lpm_type : string := "dcfifo"; intended_device_family : string := "NON_STRATIX" ); port ( data : in std_logic_vector(lpm_width-1 downto 0); rdclk : in std_logic; wrclk : in std_logic; wrreq : in std_logic; rdreq : in std_logic; aclr : in std_logic := '0'; rdfull : out std_logic; wrfull : out std_logic; wrempty : out std_logic; rdempty : out std_logic; q : out std_logic_vector(lpm_width-1 downto 0); rdusedw : out std_logic_vector(lpm_widthu-1 downto 0); wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) ); end component; begin u0 : dcfifo generic map ( intended_device_family => "STRATIX IV", lpm_numwords => 2**abits, lpm_showahead => "OFF", lpm_type => "dcfifo", lpm_width => dbits, lpm_widthu => abits, overflow_checking => "ON", rdsync_delaypipe => 4, underflow_checking => "ON", use_eab => "ON", wrsync_delaypipe => 4 ) port map ( rdclk => rdclk, rdreq => rdreq, rdfull => rdfull, rdempty => rdempty, rdusedw => rdusedw, q => q, wrclk => wrclk, wrreq => wrreq, wrfull => wrfull, wrempty => wrempty, wrusedw => wrusedw, data => data, aclr => aclr ); end;
constant bitdataLength : integer := 1282; constant bitdataCfg : std_logic_vector(bitdataLength-1 downto 0) := "0000000000000000001000001001000010010001000000110000001000000000100000000000000000000011000011000000000000000000000000000000000000000001000000000000000000000000000000000010001000100000000000000000000000000000000000000010000000011000000000000000000000001001000000010000001000000000000000000000000000000000000000000001001000001000100011010000100100001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110101000000000000000001110000000000001000000000000000101100000000000000000101001101110110000010000101000000011010110101101011010110101101010000001100000000000000000000000000100100010000000111100100000000000000000000000000000000001101101011100100110000000000000000000000000000000000000000000000000000000000000000000000000110100000110000100011010100000000000000000000000000000000000010010000000000000000000000000000000000000000000000000000000000000000000010100000000000000000000000000111000100010101100000000000000000000000101100000011110000101110000001011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010110001000000000011100000000000000000001010010000001001000000000000000010000100000001010000000000000000000000000000000000000000000000000000000000000000000000000000";
architecture ARCH of ENTITY1 is begin -- Passing wo default assert boolean report "Something something something" & "Something else and this other thing" severity FAILURE; assert boolean report "Something something something" & "Something else and this other thing"; -- Passing w default assert boolean report "Something something something" & "Something else and this other thing" severity FAILURE; assert boolean report "Something something something" & "Something else and this other thing"; -- Failing assert boolean report "Something something something" & "Something else and this other thing" severity FAILURE; assert boolean report "Something something something" & "Something else and this other thing"; end architecture ARCH;
-- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_UNSIGNED."+"; USE IEEE.STD_LOGIC_UNSIGNED."-"; USE IEEE.STD_LOGIC_UNSIGNED."="; ENTITY PIC32_INTERFACE IS PORT ( CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; A : IN STD_LOGIC_VECTOR (1 DOWNTO 0); D : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- SRAM : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); -- OUT_FIFO_WR : OUT STD_LOGIC; -- OUT_FIFO_FULL : IN STD_LOGIC; nWR : IN STD_LOGIC; nRD : IN STD_LOGIC; -- FLAGS : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- DEBUG : IN STD_LOGIC_VECTOR (31 DOWNTO 0); SRAM_A : OUT STD_LOGIC_VECTOR (16 DOWNTO 0); -- SRAM address output SRAM_D : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0); -- SRAM data output SRAM_nOE : OUT STD_LOGIC; -- SRAM output enable SRAM_nWE : OUT STD_LOGIC; -- SRAM write enable SRAM_nCE : OUT STD_LOGIC; -- SRAM_nBLE : OUT STD_LOGIC; -- SRAM_nBHE : OUT STD_LOGIC -- -- suppress_no_load_pins_warning : IN STD_LOGIC ); END PIC32_INTERFACE; ARCHITECTURE Behavioral OF PIC32_INTERFACE IS -- command constants CONSTANT cmd_write_address : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; CONSTANT cmd_write_data : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000001"; CONSTANT cmd_read_data : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000010"; CONSTANT cmd_bank_0 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000011"; CONSTANT cmd_bank_1 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000100"; CONSTANT cmd_read_debug0 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "10000000"; CONSTANT cmd_read_debug1 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "10000001"; CONSTANT cmd_read_debug2 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "10000010"; CONSTANT cmd_read_debug3 : STD_LOGIC_VECTOR(7 DOWNTO 0) := "10000011"; SIGNAL A_sync : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL D_sync : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL D_buf, D_buf_next : STD_LOGIC_VECTOR(7 DOWNTO 0); -- internal value for D SIGNAL cmd, cmd_next : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL data, data_next : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL data_s2f : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL addr, addr_next : STD_LOGIC_VECTOR(16 DOWNTO 0); SIGNAL nRD_sync, nWR_sync : STD_LOGIC; SIGNAL mem, mem_next, rw, rw_next : STD_LOGIC; BEGIN -- only drive data output when PIC32 is trying to read D <= D_buf WHEN nRD_sync = '0' AND nWR_sync = '1' ELSE (OTHERS => 'Z'); -- set all registers and I/O synchronously PROCESS (RESET, CLK) BEGIN IF RESET = '1' THEN nRD_sync <= '0'; nWR_sync <= '0'; addr(16) <= '0'; ELSIF rising_edge(CLK) THEN -- sync all inputs from PIC32 on rising edge of CLK nRD_sync <= nRD; nWR_sync <= nWR; A_sync <= A; D_sync <= D; -- update all registers and I/O with their next values D_buf <= D_buf_next; data <= data_next; addr <= addr_next; cmd <= cmd_next; mem <= mem_next; rw <= rw_next; END IF; END PROCESS; -- next state logic: PIC32 read PROCESS (nRD_sync, A_sync, cmd, addr, data_s2f, D_buf) BEGIN -- default value for next state: keep previous value D_buf_next <= D_buf; IF nRD_sync = '0' THEN CASE A_sync IS WHEN "00" => -- read register 0: flags D_buf_next <= addr(16) & "0000000"; WHEN "01" => -- read register 1: debug register CASE cmd IS WHEN cmd_read_debug3 => D_buf_next <= "11011110"; -- DE WHEN cmd_read_debug2 => D_buf_next <= "10101101"; -- AD WHEN cmd_read_debug1 => D_buf_next <= "10111110"; -- BE WHEN cmd_read_debug0 => D_buf_next <= "11101111"; -- EF WHEN OTHERS => D_buf_next <= D_buf; -- no change END CASE; WHEN "10" => -- read register 2: L byte of SRAM data D_buf_next <= data_s2f(7 DOWNTO 0); WHEN "11" => -- read register 3: H byte of SRAM data D_buf_next <= data_s2f(15 DOWNTO 8); WHEN OTHERS => D_buf_next <= D_buf; -- no change END CASE; END IF; END PROCESS; -- next state logic: PIC32 write PROCESS (nWR_sync, A_sync, D_sync, data, rw, mem, addr, cmd) BEGIN -- default values for next state: keep previous values rw_next <= rw; addr_next <= addr; data_next <= data; cmd_next <= cmd; -- always reset mem signal to SRAM_Controller mem_next <= '0'; IF nWR_sync = '0' THEN CASE A_sync IS WHEN "00" => -- write register 0: currently unused -- do nothing WHEN "01" => -- write register 1: command register CASE D_sync IS WHEN cmd_write_address => -- save value last written to data into address addr_next(15 DOWNTO 0) <= data; WHEN cmd_write_data => -- address has been latched into addr previously rw_next <= '0'; -- rw = 0: write mem_next <= '1'; -- start SRAM controller cycle WHEN cmd_read_data => -- read address has been latched into addr previously rw_next <= '1'; -- rw = 1: read mem_next <= '1'; -- start SRAM controller cycle WHEN cmd_bank_0 => -- select memory bank 0 addr_next(16) <= '0'; WHEN cmd_bank_1 => -- select memory bank 1 addr_next(16) <= '1'; WHEN OTHERS => -- every other command gets stored in cmd cmd_next <= D_sync; END CASE; WHEN "10" => -- write register 2: L byte of data register data_next(7 DOWNTO 0) <= D_sync; WHEN "11" => -- write register 3: H byte of data register data_next(15 DOWNTO 8) <= D_sync; WHEN OTHERS => -- do nothing END CASE; END IF; END PROCESS; i_SRAM_Controller : ENTITY work.SRAM_Controller PORT MAP ( clk => clk, reset => RESET, mem => mem, rw => rw, addr => addr, data_f2s => data, --ready => ready, data_s2f_r => data_s2f, ad => SRAM_A, we_n => SRAM_nWE, oe_n => SRAM_nOE, ce_n => SRAM_nCE, ub_n => SRAM_nBHE, lb_n => SRAM_nBLE, dio => SRAM_D); END Behavioral;
------------------------------------------------------------------------------- -- -- T420 system toplevel. -- -- $Id: t420.vhd,v 1.8 2008-08-28 18:51:58 arniml Exp $ -- $Name: not supported by cvs2svn $ -- -- Copyright (c) 2006 Arnim Laeuger ([email protected]) -- -- All rights reserved -- -- Redistribution and use in source and synthezised forms, with or without -- modification, are permitted provided that the following conditions are met: -- -- Redistributions of source code must retain the above copyright notice, -- this list of conditions and the following disclaimer. -- -- Redistributions in synthesized form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- Neither the name of the author nor the names of other contributors may -- be used to endorse or promote products derived from this software without -- specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- Please report bugs to the author, but before you do so, please -- make sure that this is not a derivative work and that -- you have the latest version of this file. -- -- The latest version of this file can be found at: -- http://www.opencores.org/cvsweb.shtml/t400/ -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.t400_opt_pack.all; entity t420 is generic ( opt_ck_div_g : integer := t400_opt_ck_div_8_c; opt_cko_g : integer := t400_opt_cko_crystal_c; opt_l_out_type_7_g : integer := t400_opt_out_type_std_c; opt_l_out_type_6_g : integer := t400_opt_out_type_std_c; opt_l_out_type_5_g : integer := t400_opt_out_type_std_c; opt_l_out_type_4_g : integer := t400_opt_out_type_std_c; opt_l_out_type_3_g : integer := t400_opt_out_type_std_c; opt_l_out_type_2_g : integer := t400_opt_out_type_std_c; opt_l_out_type_1_g : integer := t400_opt_out_type_std_c; opt_l_out_type_0_g : integer := t400_opt_out_type_std_c; opt_microbus_g : integer := t400_opt_no_microbus_c; opt_d_out_type_3_g : integer := t400_opt_out_type_std_c; opt_d_out_type_2_g : integer := t400_opt_out_type_std_c; opt_d_out_type_1_g : integer := t400_opt_out_type_std_c; opt_d_out_type_0_g : integer := t400_opt_out_type_std_c; opt_g_out_type_3_g : integer := t400_opt_out_type_std_c; opt_g_out_type_2_g : integer := t400_opt_out_type_std_c; opt_g_out_type_1_g : integer := t400_opt_out_type_std_c; opt_g_out_type_0_g : integer := t400_opt_out_type_std_c; opt_so_output_type_g : integer := t400_opt_out_type_std_c; opt_sk_output_type_g : integer := t400_opt_out_type_std_c ); port ( ck_i : in std_logic; ck_en_i : in std_logic; reset_n_i : in std_logic; cko_i : in std_logic; io_l_b : inout std_logic_vector(7 downto 0); io_d_o : out std_logic_vector(3 downto 0); io_g_b : inout std_logic_vector(3 downto 0); io_in_i : in std_logic_vector(3 downto 0); si_i : in std_logic; so_o : out std_logic; sk_o : out std_logic ); end t420; use work.t400_system_comp_pack.t420_notri; architecture struct of t420 is signal io_l_from_t420_s, io_l_en_s : std_logic_vector(7 downto 0); signal io_d_from_t420_s, io_d_en_s : std_logic_vector(3 downto 0); signal io_g_from_t420_s, io_g_en_s : std_logic_vector(3 downto 0); signal so_s, so_en_s : std_logic; signal sk_s, sk_en_s : std_logic; begin ----------------------------------------------------------------------------- -- T420 without tri-states ----------------------------------------------------------------------------- t420_notri_b : t420_notri generic map ( opt_type_g => t400_opt_type_420_c, opt_ck_div_g => opt_ck_div_g, opt_cko_g => opt_cko_g, opt_l_out_type_7_g => opt_l_out_type_7_g, opt_l_out_type_6_g => opt_l_out_type_6_g, opt_l_out_type_5_g => opt_l_out_type_5_g, opt_l_out_type_4_g => opt_l_out_type_4_g, opt_l_out_type_3_g => opt_l_out_type_3_g, opt_l_out_type_2_g => opt_l_out_type_2_g, opt_l_out_type_1_g => opt_l_out_type_1_g, opt_l_out_type_0_g => opt_l_out_type_0_g, opt_microbus_g => opt_microbus_g, opt_d_out_type_3_g => opt_d_out_type_3_g, opt_d_out_type_2_g => opt_d_out_type_2_g, opt_d_out_type_1_g => opt_d_out_type_1_g, opt_d_out_type_0_g => opt_d_out_type_0_g, opt_g_out_type_3_g => opt_g_out_type_3_g, opt_g_out_type_2_g => opt_g_out_type_2_g, opt_g_out_type_1_g => opt_g_out_type_1_g, opt_g_out_type_0_g => opt_g_out_type_0_g, opt_so_output_type_g => opt_so_output_type_g, opt_sk_output_type_g => opt_sk_output_type_g ) port map ( ck_i => ck_i, ck_en_i => ck_en_i, reset_n_i => reset_n_i, cko_i => cko_i, io_l_i => io_l_b, io_l_o => io_l_from_t420_s, io_l_en_o => io_l_en_s, io_d_o => io_d_from_t420_s, io_d_en_o => io_d_en_s, io_g_i => io_g_b, io_g_o => io_g_from_t420_s, io_g_en_o => io_g_en_s, io_in_i => io_in_i, si_i => si_i, so_o => so_s, so_en_o => so_en_s, sk_o => sk_s, sk_en_o => sk_en_s ); ----------------------------------------------------------------------------- -- Tri-states for output drivers ----------------------------------------------------------------------------- io_l_tri: for idx in 7 downto 0 generate io_l_b(idx) <= io_l_from_t420_s(idx) when io_l_en_s(idx) = '1' else 'Z'; end generate; -- io_d_tri: for idx in 3 downto 0 generate io_d_o(idx) <= io_d_from_t420_s(idx) when io_d_en_s(idx) = '1' else 'Z'; end generate; -- io_g_tri: for idx in 3 downto 0 generate io_g_b(idx) <= io_g_from_t420_s(idx) when io_g_en_s(idx) = '1' else 'Z'; end generate; -- so_o <= so_s when so_en_s = '1' else 'Z'; -- sk_o <= sk_s when sk_en_s = '1' else 'Z'; end struct; ------------------------------------------------------------------------------- -- File History: -- -- $Log: not supported by cvs2svn $ -- Revision 1.7 2008/08/23 11:19:20 arniml -- added name keyword -- -- Revision 1.6 2006/06/11 13:49:18 arniml -- * hand generic opt_type_g down to t420_notri -- * full generic list -- -- Revision 1.5 2006/06/05 20:04:11 arniml -- connect microbus generic -- -- Revision 1.4 2006/05/23 01:16:05 arniml -- routi CKO to t400_core -- -- Revision 1.3 2006/05/20 02:49:04 arniml -- select CK divide by 8 -- -- Revision 1.2 2006/05/17 00:38:31 arniml -- connect missing input direction for IO G -- -- Revision 1.1 2006/05/14 22:29:01 arniml -- initial check-in -- -------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------- -- -- Title : Two End Point Example for Ring Bus -- Design : Ring Bus -- Author : Zhao Ming -- Company : a4a881d4 -- --------------------------------------------------------------------------------------------------- -- -- File : rbus2.vhd -- Generated : 2013/9/7 -- From : -- By : -- --------------------------------------------------------------------------------------------------- -- -- Description : Ring bus example -- two end point -- -- Rev: 3.1 -- --------------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.rb_config.all; use work.dma_config.all; entity RBUS2 is port( -- system clk : in STD_LOGIC; rst : in STD_LOGIC; -- CPU bus wr : in std_logic; rd : in std_logic; addr : in std_logic_vector( 7 downto 0 ); Din : in std_logic_vector( 7 downto 0 ); Dout : out std_logic_vector( 7 downto 0 ); cpuClk : in std_logic; -- out viewAout : out std_logic_vector( 9 downto 0 ); viewDout : out std_logic_vector( 127 downto 0 ); viewenout : out std_logic ); end RBUS2; architecture behave of RBUS2 is constant Num : natural := 2; constant Bwidth : natural := 128; component blockdram generic( depth: integer := 256; Dwidth: integer := 8; Awidth: integer := 8 ); port( addra: IN std_logic_VECTOR(Awidth-1 downto 0); clka: IN std_logic; addrb: IN std_logic_VECTOR(Awidth-1 downto 0); clkb: IN std_logic; dia: IN std_logic_VECTOR(Dwidth-1 downto 0); wea: IN std_logic; reb: IN std_logic; dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0') ); end component; component DUMMYSRC generic( Awidth : natural; Bwidth : natural ); port( -- system clk : in STD_LOGIC; rst : in STD_LOGIC; Addr : in std_logic_vector( Awidth-1 downto 0 ); Q : out STD_LOGIC_VECTOR( Bwidth-1 downto 0 ); ren : in STD_LOGIC ); end component; signal tx_i : std_logic_vector( Num*Bwidth-1 downto 0 ); signal Req_i : std_logic_vector(Num-1 downto 0):= (others => '0'); signal tx_sop_i : std_logic_vector(Num-1 downto 0):= (others => '0'); signal rx_i : std_logic_vector( Num*Bwidth-1 downto 0 ); signal rx_sop_i : std_logic_vector(Num-1 downto 0):= (others => '0'); signal DMA0H, DMA1H : std_logic_vector( Bwidth-1 downto 0 ) := ( others=>'0' ); signal DMA0A, DMA1A : std_logic_vector( 9 downto 0 ) := ( others=>'0' ); signal DMA0_Req, DMA1_Req : std_logic := '0'; signal DMA0_Busy, DMA1_Busy : std_logic := '0'; signal viewA : std_logic_vector( 9 downto 0 ) := ( others=>'0' ); signal viewD : std_logic_vector( Bwidth-1 downto 0 ) := ( others=>'0' ); signal viewen : std_logic := '0'; signal CS0, CS1 : std_logic := '0'; signal Dout0, Dout1 : std_logic_vector( 7 downto 0 ) := ( others=>'Z' ); signal ramWA, ramRA, dummyA : std_logic_vector( 9 downto 0 ) := ( others=>'0' ); signal ramWD, ramRD, dummyD : std_logic_vector( Bwidth-1 downto 0 ) := ( others=>'0' ); signal ramWen, ramRen, dummyen : std_logic := '0'; begin bus2:RBUS generic map( Bwidth=>128, Num=>2 ) port map( -- system sync =>'0', clk => clk, rst => rst, -- tx tx => tx_i, Req => Req_i, tx_sop => tx_sop_i, -- rx rx_sop => rx_sop_i, rx => rx_i ); outEP0:EPMEMOUT generic map ( Awidth => 10, Bwidth => 128 ) port map( -- system interface clk => clk, rst => rst, -- bus interface tx_sop => tx_sop_i(0), Req => req_i(0), tx => tx_i((0+1)*Bwidth-1 downto 0*Bwidth), -- Mem interface mD => dummyD, mAddr => dummyA, mren => dummyen, -- Local Bus interface header => DMA0H, laddr => DMA0A, Req_in => DMA0_Req, busy => DMA0_busy ); outEP1:EPMEMOUT generic map ( Awidth => 10, Bwidth => 128 ) port map( -- system interface clk => clk, rst => rst, -- bus interface tx_sop => tx_sop_i(1), Req => req_i(1), tx => tx_i((1+1)*Bwidth-1 downto 1*Bwidth), -- Mem interface mD => ramRD, mAddr => ramRA, mren => ramRen, -- Local Bus interface header => DMA1H, laddr => DMA1A, Req_in => DMA1_Req, busy => DMA1_busy ); INEP0:EPMEMIN generic map( Awidth => 10, Bwidth => 128, CS => "00" ) port map( -- system interface clk => clk, rst => rst, -- bus interface rx_sop => rx_sop_i(0), rx => rx_i((0+1)*Bwidth-1 downto 0*Bwidth), -- Mem interface Addr => viewA, D => viewD, wen => viewen -- ); INEP1:EPMEMIN generic map( Awidth => 10, Bwidth => 128, CS => "00" ) port map( -- system interface clk => clk, rst => rst, -- bus interface rx_sop => rx_sop_i(1), rx => rx_i((1+1)*Bwidth-1 downto 1*Bwidth), -- Mem interface Addr => ramWA, D => ramWD, wen => ramWen -- ); DMA0:DMANP generic map( Bwidth => 128, SAwidth => 10, DAwidth => 12, Lwidth => 10 ) port map( -- system signal clk => clk, rst => rst, -- Tx interface header => DMA0H, Req => DMA0_Req, laddr => DMA0A, busy => DMA0_Busy, tx_sop => tx_sop_i(0), -- CPU bus CS => CS0, wr => wr, rd => rd, addr => addr( 3 downto 0 ), Din => Din, Dout => Dout0, cpuClk => cpuClk, -- Priority en => '1' ); DMA1:DMANP generic map( Bwidth => 128, SAwidth => 10, DAwidth => 12, Lwidth => 10 ) port map( -- system signal clk => clk, rst => rst, -- Tx interface header => DMA1H, Req => DMA1_Req, laddr => DMA1A, busy => DMA1_Busy, tx_sop => tx_sop_i(1), -- CPU bus CS => CS1, wr => wr, rd => rd, addr => addr( 3 downto 0 ), Din => Din, Dout => Dout1, cpuClk => cpuClk, -- Priority en => '1' ); ep1ram : blockdram generic map( depth => 1024, Dwidth => 128, Awidth => 10 ) port map( addra => ramWA, clka => clk, addrb => ramRA, clkb => clk, dia => ramWD, wea => ramWen, reb => ramRen, dob => ramRD ); ep0src:DUMMYSRC generic map( Awidth => 10, Bwidth => 128 ) port map( -- system clk => clk, rst => rst, Addr => dummyA, Q => dummyD, ren => dummyen ); viewAout<=viewA; viewDout<=viewD; viewenout <= viewen; cs0<='1' when addr( 7 downto 4 )="0000" else '0'; cs1<='1' when addr( 7 downto 4 )="0001" else '0'; dout<=dout0 when cs0='1' else ( others=>'Z' ); end behave;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.aua_types.all; entity reg is port ( clk : in std_logic; reset : in std_logic; async_rega : in reg_t; async_regb : in reg_t; rega : in reg_t; regb : in reg_t; async_regr : in reg_t; async_valr : in word_t; vala : out word_t; valb : out word_t ); end reg; architecture rtl of reg is component ram is port ( clock : in std_logic; data : in word_t; rdaddress : in reg_t; wraddress : in reg_t; wren : in std_logic; q : out word_t ); end component; signal vala_ram : word_t; signal valb_ram : word_t; signal regr : reg_t; signal valr : word_t; begin cmp_ram_a: ram port map(clk, async_valr, async_rega, async_regr, '1', vala_ram); cmp_ram_b: ram port map(clk, async_valr, async_regb, async_regr, '1', valb_ram); process(rega, regb, regr, valr, vala_ram, valb_ram) begin if(rega = regr) then vala <= valr; else vala <= vala_ram; end if; if(regb = regr) then valb <= valr; else valb <= valb_ram; end if; end process; sync: process (clk, reset) begin if reset = '1' then valr <= (others => '0'); regr <= (others => '0'); elsif rising_edge(clk) then valr <= async_valr; regr <= async_regr; end if; end process; end rtl;
---------------------------------------------------------------------------------- -- Company: Drexel University -- Engineer: Rob Taglang -- -- Module Name: vga_sync - Behavioral -- Description: Create a sync signal for display pixel data ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity vga_sync_reset is generic( -- The default values are for 640x480 H_SIZE : integer := 640; H_FRONT_DELAY : integer := 16; H_BACK_DELAY : integer := 48; H_RETRACE_DELAY : integer := 96; V_SIZE : integer := 480; V_FRONT_DELAY : integer := 10; V_BACK_DELAY : integer := 33; V_RETRACE_DELAY : integer := 2 ); port( clk : in std_logic; rst : in std_logic; active : out std_logic := '0'; hsync : out std_logic := '0'; vsync : out std_logic := '0'; xaddr : out std_logic_vector(9 downto 0); yaddr : out std_logic_vector(9 downto 0) ); end vga_sync_reset; architecture Structural of vga_sync_reset is -- sync counters signal v_count_reg : std_logic_vector(9 downto 0); signal h_count_reg : std_logic_vector(9 downto 0); begin -- registers process (clk) begin if rising_edge(clk) then if rst = '0' then v_count_reg <= (others=>'0'); h_count_reg <= (others=>'0'); vsync <= '1'; hsync <= '1'; active <= '0'; else -- Count the lines and rows if h_count_reg = H_SIZE + H_FRONT_DELAY + H_BACK_DELAY + H_RETRACE_DELAY - 1 then h_count_reg <= (others => '0'); if v_count_reg = V_SIZE + V_FRONT_DELAY + V_BACK_DELAY + V_RETRACE_DELAY - 1 then v_count_reg <= (others => '0'); else v_count_reg <= v_count_reg + 1; end if; else h_count_reg <= h_count_reg + 1; end if; if v_count_reg < V_SIZE and h_count_reg < H_SIZE then active <= '1'; else active <= '0'; end if; if h_count_reg > H_SIZE + H_FRONT_DELAY and h_count_reg <= H_SIZE + H_FRONT_DELAY + H_RETRACE_DELAY then hsync <= '0'; else hsync <= '1'; end if; if v_count_reg >= V_SIZE + V_FRONT_DELAY and v_count_reg < V_SIZE + V_FRONT_DELAY + V_RETRACE_DELAY then vsync <= '0'; else vsync <= '1'; end if; end if; end if; end process; xaddr <= h_count_reg; yaddr <= v_count_reg; end Structural;
---------------------------------------------------------------------------------- -- Company: Drexel University -- Engineer: Rob Taglang -- -- Module Name: vga_sync - Behavioral -- Description: Create a sync signal for display pixel data ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity vga_sync_reset is generic( -- The default values are for 640x480 H_SIZE : integer := 640; H_FRONT_DELAY : integer := 16; H_BACK_DELAY : integer := 48; H_RETRACE_DELAY : integer := 96; V_SIZE : integer := 480; V_FRONT_DELAY : integer := 10; V_BACK_DELAY : integer := 33; V_RETRACE_DELAY : integer := 2 ); port( clk : in std_logic; rst : in std_logic; active : out std_logic := '0'; hsync : out std_logic := '0'; vsync : out std_logic := '0'; xaddr : out std_logic_vector(9 downto 0); yaddr : out std_logic_vector(9 downto 0) ); end vga_sync_reset; architecture Structural of vga_sync_reset is -- sync counters signal v_count_reg : std_logic_vector(9 downto 0); signal h_count_reg : std_logic_vector(9 downto 0); begin -- registers process (clk) begin if rising_edge(clk) then if rst = '0' then v_count_reg <= (others=>'0'); h_count_reg <= (others=>'0'); vsync <= '1'; hsync <= '1'; active <= '0'; else -- Count the lines and rows if h_count_reg = H_SIZE + H_FRONT_DELAY + H_BACK_DELAY + H_RETRACE_DELAY - 1 then h_count_reg <= (others => '0'); if v_count_reg = V_SIZE + V_FRONT_DELAY + V_BACK_DELAY + V_RETRACE_DELAY - 1 then v_count_reg <= (others => '0'); else v_count_reg <= v_count_reg + 1; end if; else h_count_reg <= h_count_reg + 1; end if; if v_count_reg < V_SIZE and h_count_reg < H_SIZE then active <= '1'; else active <= '0'; end if; if h_count_reg > H_SIZE + H_FRONT_DELAY and h_count_reg <= H_SIZE + H_FRONT_DELAY + H_RETRACE_DELAY then hsync <= '0'; else hsync <= '1'; end if; if v_count_reg >= V_SIZE + V_FRONT_DELAY and v_count_reg < V_SIZE + V_FRONT_DELAY + V_RETRACE_DELAY then vsync <= '0'; else vsync <= '1'; end if; end if; end if; end process; xaddr <= h_count_reg; yaddr <= v_count_reg; end Structural;
---------------------------------------------------------------------------------- -- Company: Drexel University -- Engineer: Rob Taglang -- -- Module Name: vga_sync - Behavioral -- Description: Create a sync signal for display pixel data ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity vga_sync_reset is generic( -- The default values are for 640x480 H_SIZE : integer := 640; H_FRONT_DELAY : integer := 16; H_BACK_DELAY : integer := 48; H_RETRACE_DELAY : integer := 96; V_SIZE : integer := 480; V_FRONT_DELAY : integer := 10; V_BACK_DELAY : integer := 33; V_RETRACE_DELAY : integer := 2 ); port( clk : in std_logic; rst : in std_logic; active : out std_logic := '0'; hsync : out std_logic := '0'; vsync : out std_logic := '0'; xaddr : out std_logic_vector(9 downto 0); yaddr : out std_logic_vector(9 downto 0) ); end vga_sync_reset; architecture Structural of vga_sync_reset is -- sync counters signal v_count_reg : std_logic_vector(9 downto 0); signal h_count_reg : std_logic_vector(9 downto 0); begin -- registers process (clk) begin if rising_edge(clk) then if rst = '0' then v_count_reg <= (others=>'0'); h_count_reg <= (others=>'0'); vsync <= '1'; hsync <= '1'; active <= '0'; else -- Count the lines and rows if h_count_reg = H_SIZE + H_FRONT_DELAY + H_BACK_DELAY + H_RETRACE_DELAY - 1 then h_count_reg <= (others => '0'); if v_count_reg = V_SIZE + V_FRONT_DELAY + V_BACK_DELAY + V_RETRACE_DELAY - 1 then v_count_reg <= (others => '0'); else v_count_reg <= v_count_reg + 1; end if; else h_count_reg <= h_count_reg + 1; end if; if v_count_reg < V_SIZE and h_count_reg < H_SIZE then active <= '1'; else active <= '0'; end if; if h_count_reg > H_SIZE + H_FRONT_DELAY and h_count_reg <= H_SIZE + H_FRONT_DELAY + H_RETRACE_DELAY then hsync <= '0'; else hsync <= '1'; end if; if v_count_reg >= V_SIZE + V_FRONT_DELAY and v_count_reg < V_SIZE + V_FRONT_DELAY + V_RETRACE_DELAY then vsync <= '0'; else vsync <= '1'; end if; end if; end if; end process; xaddr <= h_count_reg; yaddr <= v_count_reg; end Structural;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 3.9 -- \ \ Application : MIG -- / / Filename : ddr3_ctrl_spec_bank3_32b_32b.vhd -- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $ -- \ \ / \ Date Created : Jul 03 2009 -- \___\/\___\ -- --Device : Spartan-6 --Design Name : DDR/DDR2/DDR3/LPDDR --Purpose : This is the design top level. which instantiates top wrapper, -- test bench top and infrastructure modules. --Reference : --Revision History : --***************************************************************************** library ieee; use ieee.std_logic_1164.all; entity ddr3_ctrl_spec_bank3_32b_32b is generic ( C3_P0_MASK_SIZE : integer := 4; C3_P0_DATA_PORT_SIZE : integer := 32; C3_P1_MASK_SIZE : integer := 4; C3_P1_DATA_PORT_SIZE : integer := 32; C3_MEMCLK_PERIOD : integer := 3000; -- Memory data transfer clock period. C3_RST_ACT_LOW : integer := 0; -- # = 1 for active low reset, -- # = 0 for active high reset. C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED"; -- input clock type DIFFERENTIAL or SINGLE_ENDED. C3_CALIB_SOFT_IP : string := "TRUE"; -- # = TRUE, Enables the soft calibration logic, -- # = FALSE, Disables the soft calibration logic. C3_SIMULATION : string := "FALSE"; -- # = TRUE, Simulating the design. Useful to reduce the simulation time, -- # = FALSE, Implementing the design. DEBUG_EN : integer := 0; -- # = 1, Enable debug signals/controls, -- = 0, Disable debug signals/controls. C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- The order in which user address is provided to the memory controller, -- ROW_BANK_COLUMN or BANK_ROW_COLUMN. C3_NUM_DQ_PINS : integer := 16; -- External memory data width. C3_MEM_ADDR_WIDTH : integer := 14; -- External memory address width. C3_MEM_BANKADDR_WIDTH : integer := 3 -- External memory bank address width. ); port ( mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0); mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0); mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_reset_n : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_rzq : inout std_logic; mcb3_dram_udm : out std_logic; c3_sys_clk : in std_logic; c3_sys_rst_i : in std_logic; c3_calib_done : out std_logic; c3_clk0 : out std_logic; c3_rst0 : out std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic; c3_p0_cmd_clk : in std_logic; c3_p0_cmd_en : in std_logic; c3_p0_cmd_instr : in std_logic_vector(2 downto 0); c3_p0_cmd_bl : in std_logic_vector(5 downto 0); c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0); c3_p0_cmd_empty : out std_logic; c3_p0_cmd_full : out std_logic; c3_p0_wr_clk : in std_logic; c3_p0_wr_en : in std_logic; c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0); c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0); c3_p0_wr_full : out std_logic; c3_p0_wr_empty : out std_logic; c3_p0_wr_count : out std_logic_vector(6 downto 0); c3_p0_wr_underrun : out std_logic; c3_p0_wr_error : out std_logic; c3_p0_rd_clk : in std_logic; c3_p0_rd_en : in std_logic; c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0); c3_p0_rd_full : out std_logic; c3_p0_rd_empty : out std_logic; c3_p0_rd_count : out std_logic_vector(6 downto 0); c3_p0_rd_overflow : out std_logic; c3_p0_rd_error : out std_logic; c3_p1_cmd_clk : in std_logic; c3_p1_cmd_en : in std_logic; c3_p1_cmd_instr : in std_logic_vector(2 downto 0); c3_p1_cmd_bl : in std_logic_vector(5 downto 0); c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0); c3_p1_cmd_empty : out std_logic; c3_p1_cmd_full : out std_logic; c3_p1_wr_clk : in std_logic; c3_p1_wr_en : in std_logic; c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0); c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0); c3_p1_wr_full : out std_logic; c3_p1_wr_empty : out std_logic; c3_p1_wr_count : out std_logic_vector(6 downto 0); c3_p1_wr_underrun : out std_logic; c3_p1_wr_error : out std_logic; c3_p1_rd_clk : in std_logic; c3_p1_rd_en : in std_logic; c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0); c3_p1_rd_full : out std_logic; c3_p1_rd_empty : out std_logic; c3_p1_rd_count : out std_logic_vector(6 downto 0); c3_p1_rd_overflow : out std_logic; c3_p1_rd_error : out std_logic ); end ddr3_ctrl_spec_bank3_32b_32b; architecture arc of ddr3_ctrl_spec_bank3_32b_32b is component memc3_infrastructure is generic ( C_RST_ACT_LOW : integer; C_INPUT_CLK_TYPE : string; C_CLKOUT0_DIVIDE : integer; C_CLKOUT1_DIVIDE : integer; C_CLKOUT2_DIVIDE : integer; C_CLKOUT3_DIVIDE : integer; C_CLKFBOUT_MULT : integer; C_DIVCLK_DIVIDE : integer; C_INCLK_PERIOD : integer ); port ( sys_clk_p : in std_logic; sys_clk_n : in std_logic; sys_clk : in std_logic; sys_rst_i : in std_logic; clk0 : out std_logic; rst0 : out std_logic; async_rst : out std_logic; sysclk_2x : out std_logic; sysclk_2x_180 : out std_logic; pll_ce_0 : out std_logic; pll_ce_90 : out std_logic; pll_lock : out std_logic; mcb_drp_clk : out std_logic ); end component; component memc3_wrapper is generic ( C_MEMCLK_PERIOD : integer; C_CALIB_SOFT_IP : string; C_SIMULATION : string; C_P0_MASK_SIZE : integer; C_P0_DATA_PORT_SIZE : integer; C_P1_MASK_SIZE : integer; C_P1_DATA_PORT_SIZE : integer; C_ARB_NUM_TIME_SLOTS : integer; C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0); C_MEM_TRAS : integer; C_MEM_TRCD : integer; C_MEM_TREFI : integer; C_MEM_TRFC : integer; C_MEM_TRP : integer; C_MEM_TWR : integer; C_MEM_TRTP : integer; C_MEM_TWTR : integer; C_MEM_ADDR_ORDER : string; C_NUM_DQ_PINS : integer; C_MEM_TYPE : string; C_MEM_DENSITY : string; C_MEM_BURST_LEN : integer; C_MEM_CAS_LATENCY : integer; C_MEM_ADDR_WIDTH : integer; C_MEM_BANKADDR_WIDTH : integer; C_MEM_NUM_COL_BITS : integer; C_MEM_DDR1_2_ODS : string; C_MEM_DDR2_RTT : string; C_MEM_DDR2_DIFF_DQS_EN : string; C_MEM_DDR2_3_PA_SR : string; C_MEM_DDR2_3_HIGH_TEMP_SR : string; C_MEM_DDR3_CAS_LATENCY : integer; C_MEM_DDR3_ODS : string; C_MEM_DDR3_RTT : string; C_MEM_DDR3_CAS_WR_LATENCY : integer; C_MEM_DDR3_AUTO_SR : string; C_MEM_MOBILE_PA_SR : string; C_MEM_MDDR_ODS : string; C_MC_CALIB_BYPASS : string; C_MC_CALIBRATION_MODE : string; C_MC_CALIBRATION_DELAY : string; C_SKIP_IN_TERM_CAL : integer; C_SKIP_DYNAMIC_CAL : integer; C_LDQSP_TAP_DELAY_VAL : integer; C_LDQSN_TAP_DELAY_VAL : integer; C_UDQSP_TAP_DELAY_VAL : integer; C_UDQSN_TAP_DELAY_VAL : integer; C_DQ0_TAP_DELAY_VAL : integer; C_DQ1_TAP_DELAY_VAL : integer; C_DQ2_TAP_DELAY_VAL : integer; C_DQ3_TAP_DELAY_VAL : integer; C_DQ4_TAP_DELAY_VAL : integer; C_DQ5_TAP_DELAY_VAL : integer; C_DQ6_TAP_DELAY_VAL : integer; C_DQ7_TAP_DELAY_VAL : integer; C_DQ8_TAP_DELAY_VAL : integer; C_DQ9_TAP_DELAY_VAL : integer; C_DQ10_TAP_DELAY_VAL : integer; C_DQ11_TAP_DELAY_VAL : integer; C_DQ12_TAP_DELAY_VAL : integer; C_DQ13_TAP_DELAY_VAL : integer; C_DQ14_TAP_DELAY_VAL : integer; C_DQ15_TAP_DELAY_VAL : integer ); port ( mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0); mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0); mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_reset_n : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_rzq : inout std_logic; mcb3_dram_udm : out std_logic; calib_done : out std_logic; async_rst : in std_logic; sysclk_2x : in std_logic; sysclk_2x_180 : in std_logic; pll_ce_0 : in std_logic; pll_ce_90 : in std_logic; pll_lock : in std_logic; mcb_drp_clk : in std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic; p0_cmd_clk : in std_logic; p0_cmd_en : in std_logic; p0_cmd_instr : in std_logic_vector(2 downto 0); p0_cmd_bl : in std_logic_vector(5 downto 0); p0_cmd_byte_addr : in std_logic_vector(29 downto 0); p0_cmd_empty : out std_logic; p0_cmd_full : out std_logic; p0_wr_clk : in std_logic; p0_wr_en : in std_logic; p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0); p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0); p0_wr_full : out std_logic; p0_wr_empty : out std_logic; p0_wr_count : out std_logic_vector(6 downto 0); p0_wr_underrun : out std_logic; p0_wr_error : out std_logic; p0_rd_clk : in std_logic; p0_rd_en : in std_logic; p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0); p0_rd_full : out std_logic; p0_rd_empty : out std_logic; p0_rd_count : out std_logic_vector(6 downto 0); p0_rd_overflow : out std_logic; p0_rd_error : out std_logic; p1_cmd_clk : in std_logic; p1_cmd_en : in std_logic; p1_cmd_instr : in std_logic_vector(2 downto 0); p1_cmd_bl : in std_logic_vector(5 downto 0); p1_cmd_byte_addr : in std_logic_vector(29 downto 0); p1_cmd_empty : out std_logic; p1_cmd_full : out std_logic; p1_wr_clk : in std_logic; p1_wr_en : in std_logic; p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0); p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0); p1_wr_full : out std_logic; p1_wr_empty : out std_logic; p1_wr_count : out std_logic_vector(6 downto 0); p1_wr_underrun : out std_logic; p1_wr_error : out std_logic; p1_rd_clk : in std_logic; p1_rd_en : in std_logic; p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0); p1_rd_full : out std_logic; p1_rd_empty : out std_logic; p1_rd_count : out std_logic_vector(6 downto 0); p1_rd_overflow : out std_logic; p1_rd_error : out std_logic; selfrefresh_enter : in std_logic; selfrefresh_mode : out std_logic ); end component; constant C3_CLKOUT0_DIVIDE : integer := 1; constant C3_CLKOUT1_DIVIDE : integer := 1; constant C3_CLKOUT2_DIVIDE : integer := 16; constant C3_CLKOUT3_DIVIDE : integer := 8; constant C3_CLKFBOUT_MULT : integer := 2; constant C3_DIVCLK_DIVIDE : integer := 1; constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2)); constant C3_ARB_NUM_TIME_SLOTS : integer := 12; constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"01"; constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"10"; constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"01"; constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"10"; constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"01"; constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"10"; constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"01"; constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"10"; constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"01"; constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"10"; constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"01"; constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"10"; constant C3_MEM_TRAS : integer := 36000; constant C3_MEM_TRCD : integer := 13500; constant C3_MEM_TREFI : integer := 7800000; constant C3_MEM_TRFC : integer := 160000; constant C3_MEM_TRP : integer := 13500; constant C3_MEM_TWR : integer := 15000; constant C3_MEM_TRTP : integer := 7500; constant C3_MEM_TWTR : integer := 7500; constant C3_MEM_TYPE : string := "DDR3"; constant C3_MEM_DENSITY : string := "2Gb"; constant C3_MEM_BURST_LEN : integer := 8; constant C3_MEM_CAS_LATENCY : integer := 6; constant C3_MEM_NUM_COL_BITS : integer := 10; constant C3_MEM_DDR1_2_ODS : string := "FULL"; constant C3_MEM_DDR2_RTT : string := "50OHMS"; constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES"; constant C3_MEM_DDR2_3_PA_SR : string := "FULL"; constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL"; constant C3_MEM_DDR3_CAS_LATENCY : integer := 6; constant C3_MEM_DDR3_ODS : string := "DIV6"; constant C3_MEM_DDR3_RTT : string := "DIV4"; constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5; constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED"; constant C3_MEM_MOBILE_PA_SR : string := "FULL"; constant C3_MEM_MDDR_ODS : string := "FULL"; constant C3_MC_CALIB_BYPASS : string := "NO"; constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION"; constant C3_MC_CALIBRATION_DELAY : string := "HALF"; constant C3_SKIP_IN_TERM_CAL : integer := 1; constant C3_SKIP_DYNAMIC_CAL : integer := 0; constant C3_LDQSP_TAP_DELAY_VAL : integer := 0; constant C3_LDQSN_TAP_DELAY_VAL : integer := 0; constant C3_UDQSP_TAP_DELAY_VAL : integer := 0; constant C3_UDQSN_TAP_DELAY_VAL : integer := 0; constant C3_DQ0_TAP_DELAY_VAL : integer := 0; constant C3_DQ1_TAP_DELAY_VAL : integer := 0; constant C3_DQ2_TAP_DELAY_VAL : integer := 0; constant C3_DQ3_TAP_DELAY_VAL : integer := 0; constant C3_DQ4_TAP_DELAY_VAL : integer := 0; constant C3_DQ5_TAP_DELAY_VAL : integer := 0; constant C3_DQ6_TAP_DELAY_VAL : integer := 0; constant C3_DQ7_TAP_DELAY_VAL : integer := 0; constant C3_DQ8_TAP_DELAY_VAL : integer := 0; constant C3_DQ9_TAP_DELAY_VAL : integer := 0; constant C3_DQ10_TAP_DELAY_VAL : integer := 0; constant C3_DQ11_TAP_DELAY_VAL : integer := 0; constant C3_DQ12_TAP_DELAY_VAL : integer := 0; constant C3_DQ13_TAP_DELAY_VAL : integer := 0; constant C3_DQ14_TAP_DELAY_VAL : integer := 0; constant C3_DQ15_TAP_DELAY_VAL : integer := 0; constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device -- as most of them cannot fit the complete example design when the -- Chip scope modules are enabled signal c3_sys_clk_p : std_logic; signal c3_sys_clk_n : std_logic; signal c3_async_rst : std_logic; signal c3_sysclk_2x : std_logic; signal c3_sysclk_2x_180 : std_logic; signal c3_pll_ce_0 : std_logic; signal c3_pll_ce_90 : std_logic; signal c3_pll_lock : std_logic; signal c3_mcb_drp_clk : std_logic; signal c3_cmp_error : std_logic; signal c3_cmp_data_valid : std_logic; signal c3_vio_modify_enable : std_logic; signal c3_error_status : std_logic_vector(127 downto 0); signal c3_vio_data_mode_value : std_logic_vector(2 downto 0); signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0); signal c3_cmp_data : std_logic_vector(31 downto 0); signal c3_selfrefresh_enter : std_logic; signal c3_selfrefresh_mode : std_logic; begin c3_sys_clk_p <= '0'; c3_sys_clk_n <= '0'; c3_selfrefresh_enter <= '0'; c3_selfrefresh_enter <= '0'; memc3_infrastructure_inst : memc3_infrastructure generic map ( C_RST_ACT_LOW => C3_RST_ACT_LOW, C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE, C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE, C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE, C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE, C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE, C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT, C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE, C_INCLK_PERIOD => C3_INCLK_PERIOD ) port map ( sys_clk_p => c3_sys_clk_p, sys_clk_n => c3_sys_clk_n, sys_clk => c3_sys_clk, sys_rst_i => c3_sys_rst_i, clk0 => c3_clk0, rst0 => c3_rst0, async_rst => c3_async_rst, sysclk_2x => c3_sysclk_2x, sysclk_2x_180 => c3_sysclk_2x_180, pll_ce_0 => c3_pll_ce_0, pll_ce_90 => c3_pll_ce_90, pll_lock => c3_pll_lock, mcb_drp_clk => c3_mcb_drp_clk ); -- wrapper instantiation memc3_wrapper_inst : memc3_wrapper generic map ( C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD, C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP, C_SIMULATION => C3_SIMULATION, C_P0_MASK_SIZE => C3_P0_MASK_SIZE, C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE, C_P1_MASK_SIZE => C3_P1_MASK_SIZE, C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE, C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS, C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0, C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1, C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2, C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3, C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4, C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5, C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6, C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7, C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8, C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9, C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10, C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11, C_MEM_TRAS => C3_MEM_TRAS, C_MEM_TRCD => C3_MEM_TRCD, C_MEM_TREFI => C3_MEM_TREFI, C_MEM_TRFC => C3_MEM_TRFC, C_MEM_TRP => C3_MEM_TRP, C_MEM_TWR => C3_MEM_TWR, C_MEM_TRTP => C3_MEM_TRTP, C_MEM_TWTR => C3_MEM_TWTR, C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER, C_NUM_DQ_PINS => C3_NUM_DQ_PINS, C_MEM_TYPE => C3_MEM_TYPE, C_MEM_DENSITY => C3_MEM_DENSITY, C_MEM_BURST_LEN => C3_MEM_BURST_LEN, C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY, C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH, C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH, C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS, C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS, C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT, C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN, C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR, C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR, C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY, C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS, C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT, C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY, C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR, C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR, C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS, C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS, C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE, C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY, C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL, C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL, C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL, C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL, C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL, C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL, C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL, C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL, C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL, C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL, C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL, C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL, C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL, C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL, C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL, C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL, C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL, C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL, C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL, C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL, C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL, C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL ) port map ( mcb3_dram_dq => mcb3_dram_dq, mcb3_dram_a => mcb3_dram_a, mcb3_dram_ba => mcb3_dram_ba, mcb3_dram_ras_n => mcb3_dram_ras_n, mcb3_dram_cas_n => mcb3_dram_cas_n, mcb3_dram_we_n => mcb3_dram_we_n, mcb3_dram_odt => mcb3_dram_odt, mcb3_dram_reset_n => mcb3_dram_reset_n, mcb3_dram_cke => mcb3_dram_cke, mcb3_dram_dm => mcb3_dram_dm, mcb3_dram_udqs => mcb3_dram_udqs, mcb3_dram_udqs_n => mcb3_dram_udqs_n, mcb3_rzq => mcb3_rzq, mcb3_dram_udm => mcb3_dram_udm, calib_done => c3_calib_done, async_rst => c3_async_rst, sysclk_2x => c3_sysclk_2x, sysclk_2x_180 => c3_sysclk_2x_180, pll_ce_0 => c3_pll_ce_0, pll_ce_90 => c3_pll_ce_90, pll_lock => c3_pll_lock, mcb_drp_clk => c3_mcb_drp_clk, mcb3_dram_dqs => mcb3_dram_dqs, mcb3_dram_dqs_n => mcb3_dram_dqs_n, mcb3_dram_ck => mcb3_dram_ck, mcb3_dram_ck_n => mcb3_dram_ck_n, p0_cmd_clk => c3_p0_cmd_clk, p0_cmd_en => c3_p0_cmd_en, p0_cmd_instr => c3_p0_cmd_instr, p0_cmd_bl => c3_p0_cmd_bl, p0_cmd_byte_addr => c3_p0_cmd_byte_addr, p0_cmd_empty => c3_p0_cmd_empty, p0_cmd_full => c3_p0_cmd_full, p0_wr_clk => c3_p0_wr_clk, p0_wr_en => c3_p0_wr_en, p0_wr_mask => c3_p0_wr_mask, p0_wr_data => c3_p0_wr_data, p0_wr_full => c3_p0_wr_full, p0_wr_empty => c3_p0_wr_empty, p0_wr_count => c3_p0_wr_count, p0_wr_underrun => c3_p0_wr_underrun, p0_wr_error => c3_p0_wr_error, p0_rd_clk => c3_p0_rd_clk, p0_rd_en => c3_p0_rd_en, p0_rd_data => c3_p0_rd_data, p0_rd_full => c3_p0_rd_full, p0_rd_empty => c3_p0_rd_empty, p0_rd_count => c3_p0_rd_count, p0_rd_overflow => c3_p0_rd_overflow, p0_rd_error => c3_p0_rd_error, p1_cmd_clk => c3_p1_cmd_clk, p1_cmd_en => c3_p1_cmd_en, p1_cmd_instr => c3_p1_cmd_instr, p1_cmd_bl => c3_p1_cmd_bl, p1_cmd_byte_addr => c3_p1_cmd_byte_addr, p1_cmd_empty => c3_p1_cmd_empty, p1_cmd_full => c3_p1_cmd_full, p1_wr_clk => c3_p1_wr_clk, p1_wr_en => c3_p1_wr_en, p1_wr_mask => c3_p1_wr_mask, p1_wr_data => c3_p1_wr_data, p1_wr_full => c3_p1_wr_full, p1_wr_empty => c3_p1_wr_empty, p1_wr_count => c3_p1_wr_count, p1_wr_underrun => c3_p1_wr_underrun, p1_wr_error => c3_p1_wr_error, p1_rd_clk => c3_p1_rd_clk, p1_rd_en => c3_p1_rd_en, p1_rd_data => c3_p1_rd_data, p1_rd_full => c3_p1_rd_full, p1_rd_empty => c3_p1_rd_empty, p1_rd_count => c3_p1_rd_count, p1_rd_overflow => c3_p1_rd_overflow, p1_rd_error => c3_p1_rd_error, selfrefresh_enter => c3_selfrefresh_enter, selfrefresh_mode => c3_selfrefresh_mode ); end arc;
--***************************************************************************** -- (c) Copyright 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 3.9 -- \ \ Application : MIG -- / / Filename : ddr3_ctrl_spec_bank3_32b_32b.vhd -- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $ -- \ \ / \ Date Created : Jul 03 2009 -- \___\/\___\ -- --Device : Spartan-6 --Design Name : DDR/DDR2/DDR3/LPDDR --Purpose : This is the design top level. which instantiates top wrapper, -- test bench top and infrastructure modules. --Reference : --Revision History : --***************************************************************************** library ieee; use ieee.std_logic_1164.all; entity ddr3_ctrl_spec_bank3_32b_32b is generic ( C3_P0_MASK_SIZE : integer := 4; C3_P0_DATA_PORT_SIZE : integer := 32; C3_P1_MASK_SIZE : integer := 4; C3_P1_DATA_PORT_SIZE : integer := 32; C3_MEMCLK_PERIOD : integer := 3000; -- Memory data transfer clock period. C3_RST_ACT_LOW : integer := 0; -- # = 1 for active low reset, -- # = 0 for active high reset. C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED"; -- input clock type DIFFERENTIAL or SINGLE_ENDED. C3_CALIB_SOFT_IP : string := "TRUE"; -- # = TRUE, Enables the soft calibration logic, -- # = FALSE, Disables the soft calibration logic. C3_SIMULATION : string := "FALSE"; -- # = TRUE, Simulating the design. Useful to reduce the simulation time, -- # = FALSE, Implementing the design. DEBUG_EN : integer := 0; -- # = 1, Enable debug signals/controls, -- = 0, Disable debug signals/controls. C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- The order in which user address is provided to the memory controller, -- ROW_BANK_COLUMN or BANK_ROW_COLUMN. C3_NUM_DQ_PINS : integer := 16; -- External memory data width. C3_MEM_ADDR_WIDTH : integer := 14; -- External memory address width. C3_MEM_BANKADDR_WIDTH : integer := 3 -- External memory bank address width. ); port ( mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0); mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0); mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_reset_n : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_rzq : inout std_logic; mcb3_dram_udm : out std_logic; c3_sys_clk : in std_logic; c3_sys_rst_i : in std_logic; c3_calib_done : out std_logic; c3_clk0 : out std_logic; c3_rst0 : out std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic; c3_p0_cmd_clk : in std_logic; c3_p0_cmd_en : in std_logic; c3_p0_cmd_instr : in std_logic_vector(2 downto 0); c3_p0_cmd_bl : in std_logic_vector(5 downto 0); c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0); c3_p0_cmd_empty : out std_logic; c3_p0_cmd_full : out std_logic; c3_p0_wr_clk : in std_logic; c3_p0_wr_en : in std_logic; c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0); c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0); c3_p0_wr_full : out std_logic; c3_p0_wr_empty : out std_logic; c3_p0_wr_count : out std_logic_vector(6 downto 0); c3_p0_wr_underrun : out std_logic; c3_p0_wr_error : out std_logic; c3_p0_rd_clk : in std_logic; c3_p0_rd_en : in std_logic; c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0); c3_p0_rd_full : out std_logic; c3_p0_rd_empty : out std_logic; c3_p0_rd_count : out std_logic_vector(6 downto 0); c3_p0_rd_overflow : out std_logic; c3_p0_rd_error : out std_logic; c3_p1_cmd_clk : in std_logic; c3_p1_cmd_en : in std_logic; c3_p1_cmd_instr : in std_logic_vector(2 downto 0); c3_p1_cmd_bl : in std_logic_vector(5 downto 0); c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0); c3_p1_cmd_empty : out std_logic; c3_p1_cmd_full : out std_logic; c3_p1_wr_clk : in std_logic; c3_p1_wr_en : in std_logic; c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0); c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0); c3_p1_wr_full : out std_logic; c3_p1_wr_empty : out std_logic; c3_p1_wr_count : out std_logic_vector(6 downto 0); c3_p1_wr_underrun : out std_logic; c3_p1_wr_error : out std_logic; c3_p1_rd_clk : in std_logic; c3_p1_rd_en : in std_logic; c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0); c3_p1_rd_full : out std_logic; c3_p1_rd_empty : out std_logic; c3_p1_rd_count : out std_logic_vector(6 downto 0); c3_p1_rd_overflow : out std_logic; c3_p1_rd_error : out std_logic ); end ddr3_ctrl_spec_bank3_32b_32b; architecture arc of ddr3_ctrl_spec_bank3_32b_32b is component memc3_infrastructure is generic ( C_RST_ACT_LOW : integer; C_INPUT_CLK_TYPE : string; C_CLKOUT0_DIVIDE : integer; C_CLKOUT1_DIVIDE : integer; C_CLKOUT2_DIVIDE : integer; C_CLKOUT3_DIVIDE : integer; C_CLKFBOUT_MULT : integer; C_DIVCLK_DIVIDE : integer; C_INCLK_PERIOD : integer ); port ( sys_clk_p : in std_logic; sys_clk_n : in std_logic; sys_clk : in std_logic; sys_rst_i : in std_logic; clk0 : out std_logic; rst0 : out std_logic; async_rst : out std_logic; sysclk_2x : out std_logic; sysclk_2x_180 : out std_logic; pll_ce_0 : out std_logic; pll_ce_90 : out std_logic; pll_lock : out std_logic; mcb_drp_clk : out std_logic ); end component; component memc3_wrapper is generic ( C_MEMCLK_PERIOD : integer; C_CALIB_SOFT_IP : string; C_SIMULATION : string; C_P0_MASK_SIZE : integer; C_P0_DATA_PORT_SIZE : integer; C_P1_MASK_SIZE : integer; C_P1_DATA_PORT_SIZE : integer; C_ARB_NUM_TIME_SLOTS : integer; C_ARB_TIME_SLOT_0 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_1 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_2 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_3 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_4 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_5 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_6 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_7 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_8 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_9 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_10 : bit_vector(5 downto 0); C_ARB_TIME_SLOT_11 : bit_vector(5 downto 0); C_MEM_TRAS : integer; C_MEM_TRCD : integer; C_MEM_TREFI : integer; C_MEM_TRFC : integer; C_MEM_TRP : integer; C_MEM_TWR : integer; C_MEM_TRTP : integer; C_MEM_TWTR : integer; C_MEM_ADDR_ORDER : string; C_NUM_DQ_PINS : integer; C_MEM_TYPE : string; C_MEM_DENSITY : string; C_MEM_BURST_LEN : integer; C_MEM_CAS_LATENCY : integer; C_MEM_ADDR_WIDTH : integer; C_MEM_BANKADDR_WIDTH : integer; C_MEM_NUM_COL_BITS : integer; C_MEM_DDR1_2_ODS : string; C_MEM_DDR2_RTT : string; C_MEM_DDR2_DIFF_DQS_EN : string; C_MEM_DDR2_3_PA_SR : string; C_MEM_DDR2_3_HIGH_TEMP_SR : string; C_MEM_DDR3_CAS_LATENCY : integer; C_MEM_DDR3_ODS : string; C_MEM_DDR3_RTT : string; C_MEM_DDR3_CAS_WR_LATENCY : integer; C_MEM_DDR3_AUTO_SR : string; C_MEM_MOBILE_PA_SR : string; C_MEM_MDDR_ODS : string; C_MC_CALIB_BYPASS : string; C_MC_CALIBRATION_MODE : string; C_MC_CALIBRATION_DELAY : string; C_SKIP_IN_TERM_CAL : integer; C_SKIP_DYNAMIC_CAL : integer; C_LDQSP_TAP_DELAY_VAL : integer; C_LDQSN_TAP_DELAY_VAL : integer; C_UDQSP_TAP_DELAY_VAL : integer; C_UDQSN_TAP_DELAY_VAL : integer; C_DQ0_TAP_DELAY_VAL : integer; C_DQ1_TAP_DELAY_VAL : integer; C_DQ2_TAP_DELAY_VAL : integer; C_DQ3_TAP_DELAY_VAL : integer; C_DQ4_TAP_DELAY_VAL : integer; C_DQ5_TAP_DELAY_VAL : integer; C_DQ6_TAP_DELAY_VAL : integer; C_DQ7_TAP_DELAY_VAL : integer; C_DQ8_TAP_DELAY_VAL : integer; C_DQ9_TAP_DELAY_VAL : integer; C_DQ10_TAP_DELAY_VAL : integer; C_DQ11_TAP_DELAY_VAL : integer; C_DQ12_TAP_DELAY_VAL : integer; C_DQ13_TAP_DELAY_VAL : integer; C_DQ14_TAP_DELAY_VAL : integer; C_DQ15_TAP_DELAY_VAL : integer ); port ( mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0); mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0); mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0); mcb3_dram_ras_n : out std_logic; mcb3_dram_cas_n : out std_logic; mcb3_dram_we_n : out std_logic; mcb3_dram_odt : out std_logic; mcb3_dram_reset_n : out std_logic; mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_dram_udqs : inout std_logic; mcb3_dram_udqs_n : inout std_logic; mcb3_rzq : inout std_logic; mcb3_dram_udm : out std_logic; calib_done : out std_logic; async_rst : in std_logic; sysclk_2x : in std_logic; sysclk_2x_180 : in std_logic; pll_ce_0 : in std_logic; pll_ce_90 : in std_logic; pll_lock : in std_logic; mcb_drp_clk : in std_logic; mcb3_dram_dqs : inout std_logic; mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic; p0_cmd_clk : in std_logic; p0_cmd_en : in std_logic; p0_cmd_instr : in std_logic_vector(2 downto 0); p0_cmd_bl : in std_logic_vector(5 downto 0); p0_cmd_byte_addr : in std_logic_vector(29 downto 0); p0_cmd_empty : out std_logic; p0_cmd_full : out std_logic; p0_wr_clk : in std_logic; p0_wr_en : in std_logic; p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0); p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0); p0_wr_full : out std_logic; p0_wr_empty : out std_logic; p0_wr_count : out std_logic_vector(6 downto 0); p0_wr_underrun : out std_logic; p0_wr_error : out std_logic; p0_rd_clk : in std_logic; p0_rd_en : in std_logic; p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0); p0_rd_full : out std_logic; p0_rd_empty : out std_logic; p0_rd_count : out std_logic_vector(6 downto 0); p0_rd_overflow : out std_logic; p0_rd_error : out std_logic; p1_cmd_clk : in std_logic; p1_cmd_en : in std_logic; p1_cmd_instr : in std_logic_vector(2 downto 0); p1_cmd_bl : in std_logic_vector(5 downto 0); p1_cmd_byte_addr : in std_logic_vector(29 downto 0); p1_cmd_empty : out std_logic; p1_cmd_full : out std_logic; p1_wr_clk : in std_logic; p1_wr_en : in std_logic; p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0); p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0); p1_wr_full : out std_logic; p1_wr_empty : out std_logic; p1_wr_count : out std_logic_vector(6 downto 0); p1_wr_underrun : out std_logic; p1_wr_error : out std_logic; p1_rd_clk : in std_logic; p1_rd_en : in std_logic; p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0); p1_rd_full : out std_logic; p1_rd_empty : out std_logic; p1_rd_count : out std_logic_vector(6 downto 0); p1_rd_overflow : out std_logic; p1_rd_error : out std_logic; selfrefresh_enter : in std_logic; selfrefresh_mode : out std_logic ); end component; constant C3_CLKOUT0_DIVIDE : integer := 1; constant C3_CLKOUT1_DIVIDE : integer := 1; constant C3_CLKOUT2_DIVIDE : integer := 16; constant C3_CLKOUT3_DIVIDE : integer := 8; constant C3_CLKFBOUT_MULT : integer := 2; constant C3_DIVCLK_DIVIDE : integer := 1; constant C3_INCLK_PERIOD : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2)); constant C3_ARB_NUM_TIME_SLOTS : integer := 12; constant C3_ARB_TIME_SLOT_0 : bit_vector(5 downto 0) := o"01"; constant C3_ARB_TIME_SLOT_1 : bit_vector(5 downto 0) := o"10"; constant C3_ARB_TIME_SLOT_2 : bit_vector(5 downto 0) := o"01"; constant C3_ARB_TIME_SLOT_3 : bit_vector(5 downto 0) := o"10"; constant C3_ARB_TIME_SLOT_4 : bit_vector(5 downto 0) := o"01"; constant C3_ARB_TIME_SLOT_5 : bit_vector(5 downto 0) := o"10"; constant C3_ARB_TIME_SLOT_6 : bit_vector(5 downto 0) := o"01"; constant C3_ARB_TIME_SLOT_7 : bit_vector(5 downto 0) := o"10"; constant C3_ARB_TIME_SLOT_8 : bit_vector(5 downto 0) := o"01"; constant C3_ARB_TIME_SLOT_9 : bit_vector(5 downto 0) := o"10"; constant C3_ARB_TIME_SLOT_10 : bit_vector(5 downto 0) := o"01"; constant C3_ARB_TIME_SLOT_11 : bit_vector(5 downto 0) := o"10"; constant C3_MEM_TRAS : integer := 36000; constant C3_MEM_TRCD : integer := 13500; constant C3_MEM_TREFI : integer := 7800000; constant C3_MEM_TRFC : integer := 160000; constant C3_MEM_TRP : integer := 13500; constant C3_MEM_TWR : integer := 15000; constant C3_MEM_TRTP : integer := 7500; constant C3_MEM_TWTR : integer := 7500; constant C3_MEM_TYPE : string := "DDR3"; constant C3_MEM_DENSITY : string := "2Gb"; constant C3_MEM_BURST_LEN : integer := 8; constant C3_MEM_CAS_LATENCY : integer := 6; constant C3_MEM_NUM_COL_BITS : integer := 10; constant C3_MEM_DDR1_2_ODS : string := "FULL"; constant C3_MEM_DDR2_RTT : string := "50OHMS"; constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES"; constant C3_MEM_DDR2_3_PA_SR : string := "FULL"; constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL"; constant C3_MEM_DDR3_CAS_LATENCY : integer := 6; constant C3_MEM_DDR3_ODS : string := "DIV6"; constant C3_MEM_DDR3_RTT : string := "DIV4"; constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5; constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED"; constant C3_MEM_MOBILE_PA_SR : string := "FULL"; constant C3_MEM_MDDR_ODS : string := "FULL"; constant C3_MC_CALIB_BYPASS : string := "NO"; constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION"; constant C3_MC_CALIBRATION_DELAY : string := "HALF"; constant C3_SKIP_IN_TERM_CAL : integer := 1; constant C3_SKIP_DYNAMIC_CAL : integer := 0; constant C3_LDQSP_TAP_DELAY_VAL : integer := 0; constant C3_LDQSN_TAP_DELAY_VAL : integer := 0; constant C3_UDQSP_TAP_DELAY_VAL : integer := 0; constant C3_UDQSN_TAP_DELAY_VAL : integer := 0; constant C3_DQ0_TAP_DELAY_VAL : integer := 0; constant C3_DQ1_TAP_DELAY_VAL : integer := 0; constant C3_DQ2_TAP_DELAY_VAL : integer := 0; constant C3_DQ3_TAP_DELAY_VAL : integer := 0; constant C3_DQ4_TAP_DELAY_VAL : integer := 0; constant C3_DQ5_TAP_DELAY_VAL : integer := 0; constant C3_DQ6_TAP_DELAY_VAL : integer := 0; constant C3_DQ7_TAP_DELAY_VAL : integer := 0; constant C3_DQ8_TAP_DELAY_VAL : integer := 0; constant C3_DQ9_TAP_DELAY_VAL : integer := 0; constant C3_DQ10_TAP_DELAY_VAL : integer := 0; constant C3_DQ11_TAP_DELAY_VAL : integer := 0; constant C3_DQ12_TAP_DELAY_VAL : integer := 0; constant C3_DQ13_TAP_DELAY_VAL : integer := 0; constant C3_DQ14_TAP_DELAY_VAL : integer := 0; constant C3_DQ15_TAP_DELAY_VAL : integer := 0; constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device -- as most of them cannot fit the complete example design when the -- Chip scope modules are enabled signal c3_sys_clk_p : std_logic; signal c3_sys_clk_n : std_logic; signal c3_async_rst : std_logic; signal c3_sysclk_2x : std_logic; signal c3_sysclk_2x_180 : std_logic; signal c3_pll_ce_0 : std_logic; signal c3_pll_ce_90 : std_logic; signal c3_pll_lock : std_logic; signal c3_mcb_drp_clk : std_logic; signal c3_cmp_error : std_logic; signal c3_cmp_data_valid : std_logic; signal c3_vio_modify_enable : std_logic; signal c3_error_status : std_logic_vector(127 downto 0); signal c3_vio_data_mode_value : std_logic_vector(2 downto 0); signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0); signal c3_cmp_data : std_logic_vector(31 downto 0); signal c3_selfrefresh_enter : std_logic; signal c3_selfrefresh_mode : std_logic; begin c3_sys_clk_p <= '0'; c3_sys_clk_n <= '0'; c3_selfrefresh_enter <= '0'; c3_selfrefresh_enter <= '0'; memc3_infrastructure_inst : memc3_infrastructure generic map ( C_RST_ACT_LOW => C3_RST_ACT_LOW, C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE, C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE, C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE, C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE, C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE, C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT, C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE, C_INCLK_PERIOD => C3_INCLK_PERIOD ) port map ( sys_clk_p => c3_sys_clk_p, sys_clk_n => c3_sys_clk_n, sys_clk => c3_sys_clk, sys_rst_i => c3_sys_rst_i, clk0 => c3_clk0, rst0 => c3_rst0, async_rst => c3_async_rst, sysclk_2x => c3_sysclk_2x, sysclk_2x_180 => c3_sysclk_2x_180, pll_ce_0 => c3_pll_ce_0, pll_ce_90 => c3_pll_ce_90, pll_lock => c3_pll_lock, mcb_drp_clk => c3_mcb_drp_clk ); -- wrapper instantiation memc3_wrapper_inst : memc3_wrapper generic map ( C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD, C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP, C_SIMULATION => C3_SIMULATION, C_P0_MASK_SIZE => C3_P0_MASK_SIZE, C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE, C_P1_MASK_SIZE => C3_P1_MASK_SIZE, C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE, C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS, C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0, C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1, C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2, C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3, C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4, C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5, C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6, C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7, C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8, C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9, C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10, C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11, C_MEM_TRAS => C3_MEM_TRAS, C_MEM_TRCD => C3_MEM_TRCD, C_MEM_TREFI => C3_MEM_TREFI, C_MEM_TRFC => C3_MEM_TRFC, C_MEM_TRP => C3_MEM_TRP, C_MEM_TWR => C3_MEM_TWR, C_MEM_TRTP => C3_MEM_TRTP, C_MEM_TWTR => C3_MEM_TWTR, C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER, C_NUM_DQ_PINS => C3_NUM_DQ_PINS, C_MEM_TYPE => C3_MEM_TYPE, C_MEM_DENSITY => C3_MEM_DENSITY, C_MEM_BURST_LEN => C3_MEM_BURST_LEN, C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY, C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH, C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH, C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS, C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS, C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT, C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN, C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR, C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR, C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY, C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS, C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT, C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY, C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR, C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR, C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS, C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS, C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE, C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY, C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL, C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL, C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL, C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL, C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL, C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL, C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL, C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL, C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL, C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL, C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL, C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL, C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL, C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL, C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL, C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL, C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL, C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL, C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL, C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL, C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL, C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL ) port map ( mcb3_dram_dq => mcb3_dram_dq, mcb3_dram_a => mcb3_dram_a, mcb3_dram_ba => mcb3_dram_ba, mcb3_dram_ras_n => mcb3_dram_ras_n, mcb3_dram_cas_n => mcb3_dram_cas_n, mcb3_dram_we_n => mcb3_dram_we_n, mcb3_dram_odt => mcb3_dram_odt, mcb3_dram_reset_n => mcb3_dram_reset_n, mcb3_dram_cke => mcb3_dram_cke, mcb3_dram_dm => mcb3_dram_dm, mcb3_dram_udqs => mcb3_dram_udqs, mcb3_dram_udqs_n => mcb3_dram_udqs_n, mcb3_rzq => mcb3_rzq, mcb3_dram_udm => mcb3_dram_udm, calib_done => c3_calib_done, async_rst => c3_async_rst, sysclk_2x => c3_sysclk_2x, sysclk_2x_180 => c3_sysclk_2x_180, pll_ce_0 => c3_pll_ce_0, pll_ce_90 => c3_pll_ce_90, pll_lock => c3_pll_lock, mcb_drp_clk => c3_mcb_drp_clk, mcb3_dram_dqs => mcb3_dram_dqs, mcb3_dram_dqs_n => mcb3_dram_dqs_n, mcb3_dram_ck => mcb3_dram_ck, mcb3_dram_ck_n => mcb3_dram_ck_n, p0_cmd_clk => c3_p0_cmd_clk, p0_cmd_en => c3_p0_cmd_en, p0_cmd_instr => c3_p0_cmd_instr, p0_cmd_bl => c3_p0_cmd_bl, p0_cmd_byte_addr => c3_p0_cmd_byte_addr, p0_cmd_empty => c3_p0_cmd_empty, p0_cmd_full => c3_p0_cmd_full, p0_wr_clk => c3_p0_wr_clk, p0_wr_en => c3_p0_wr_en, p0_wr_mask => c3_p0_wr_mask, p0_wr_data => c3_p0_wr_data, p0_wr_full => c3_p0_wr_full, p0_wr_empty => c3_p0_wr_empty, p0_wr_count => c3_p0_wr_count, p0_wr_underrun => c3_p0_wr_underrun, p0_wr_error => c3_p0_wr_error, p0_rd_clk => c3_p0_rd_clk, p0_rd_en => c3_p0_rd_en, p0_rd_data => c3_p0_rd_data, p0_rd_full => c3_p0_rd_full, p0_rd_empty => c3_p0_rd_empty, p0_rd_count => c3_p0_rd_count, p0_rd_overflow => c3_p0_rd_overflow, p0_rd_error => c3_p0_rd_error, p1_cmd_clk => c3_p1_cmd_clk, p1_cmd_en => c3_p1_cmd_en, p1_cmd_instr => c3_p1_cmd_instr, p1_cmd_bl => c3_p1_cmd_bl, p1_cmd_byte_addr => c3_p1_cmd_byte_addr, p1_cmd_empty => c3_p1_cmd_empty, p1_cmd_full => c3_p1_cmd_full, p1_wr_clk => c3_p1_wr_clk, p1_wr_en => c3_p1_wr_en, p1_wr_mask => c3_p1_wr_mask, p1_wr_data => c3_p1_wr_data, p1_wr_full => c3_p1_wr_full, p1_wr_empty => c3_p1_wr_empty, p1_wr_count => c3_p1_wr_count, p1_wr_underrun => c3_p1_wr_underrun, p1_wr_error => c3_p1_wr_error, p1_rd_clk => c3_p1_rd_clk, p1_rd_en => c3_p1_rd_en, p1_rd_data => c3_p1_rd_data, p1_rd_full => c3_p1_rd_full, p1_rd_empty => c3_p1_rd_empty, p1_rd_count => c3_p1_rd_count, p1_rd_overflow => c3_p1_rd_overflow, p1_rd_error => c3_p1_rd_error, selfrefresh_enter => c3_selfrefresh_enter, selfrefresh_mode => c3_selfrefresh_mode ); end arc;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc919.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity c10s03b00x00p14n01i00919ent_a is generic ( x : integer; y : real ); end c10s03b00x00p14n01i00919ent_a; architecture c10s03b00x00p14n01i00919arch_a of c10s03b00x00p14n01i00919ent_a is begin TESTING:PROCESS BEGIN assert NOT( real(x) = y ) report "***PASSED TEST: c10s03b00x00p14n01i00919" severity NOTE; assert ( real(x) = y ) report "***FAILED TEST: c10s03b00x00p14n01i00919 - The named associated local generics can be made visible by selection." severity ERROR; wait; END PROCESS TESTING; end c10s03b00x00p14n01i00919arch_a; ENTITY c10s03b00x00p14n01i00919ent IS END c10s03b00x00p14n01i00919ent; ARCHITECTURE c10s03b00x00p14n01i00919arch OF c10s03b00x00p14n01i00919ent IS component d generic ( a : integer; b : real ); end component; BEGIN instance : d generic map (a => 10, b => 10.0); END c10s03b00x00p14n01i00919arch; configuration c10s03b00x00p14n01i00919cfg of c10s03b00x00p14n01i00919ent is for c10s03b00x00p14n01i00919arch for instance : d use entity work.c10s03b00x00p14n01i00919ent_a(c10s03b00x00p14n01i00919arch_a) generic map ( x => a, y => b); end for; end for; end c10s03b00x00p14n01i00919cfg;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc919.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity c10s03b00x00p14n01i00919ent_a is generic ( x : integer; y : real ); end c10s03b00x00p14n01i00919ent_a; architecture c10s03b00x00p14n01i00919arch_a of c10s03b00x00p14n01i00919ent_a is begin TESTING:PROCESS BEGIN assert NOT( real(x) = y ) report "***PASSED TEST: c10s03b00x00p14n01i00919" severity NOTE; assert ( real(x) = y ) report "***FAILED TEST: c10s03b00x00p14n01i00919 - The named associated local generics can be made visible by selection." severity ERROR; wait; END PROCESS TESTING; end c10s03b00x00p14n01i00919arch_a; ENTITY c10s03b00x00p14n01i00919ent IS END c10s03b00x00p14n01i00919ent; ARCHITECTURE c10s03b00x00p14n01i00919arch OF c10s03b00x00p14n01i00919ent IS component d generic ( a : integer; b : real ); end component; BEGIN instance : d generic map (a => 10, b => 10.0); END c10s03b00x00p14n01i00919arch; configuration c10s03b00x00p14n01i00919cfg of c10s03b00x00p14n01i00919ent is for c10s03b00x00p14n01i00919arch for instance : d use entity work.c10s03b00x00p14n01i00919ent_a(c10s03b00x00p14n01i00919arch_a) generic map ( x => a, y => b); end for; end for; end c10s03b00x00p14n01i00919cfg;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc919.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity c10s03b00x00p14n01i00919ent_a is generic ( x : integer; y : real ); end c10s03b00x00p14n01i00919ent_a; architecture c10s03b00x00p14n01i00919arch_a of c10s03b00x00p14n01i00919ent_a is begin TESTING:PROCESS BEGIN assert NOT( real(x) = y ) report "***PASSED TEST: c10s03b00x00p14n01i00919" severity NOTE; assert ( real(x) = y ) report "***FAILED TEST: c10s03b00x00p14n01i00919 - The named associated local generics can be made visible by selection." severity ERROR; wait; END PROCESS TESTING; end c10s03b00x00p14n01i00919arch_a; ENTITY c10s03b00x00p14n01i00919ent IS END c10s03b00x00p14n01i00919ent; ARCHITECTURE c10s03b00x00p14n01i00919arch OF c10s03b00x00p14n01i00919ent IS component d generic ( a : integer; b : real ); end component; BEGIN instance : d generic map (a => 10, b => 10.0); END c10s03b00x00p14n01i00919arch; configuration c10s03b00x00p14n01i00919cfg of c10s03b00x00p14n01i00919ent is for c10s03b00x00p14n01i00919arch for instance : d use entity work.c10s03b00x00p14n01i00919ent_a(c10s03b00x00p14n01i00919arch_a) generic map ( x => a, y => b); end for; end for; end c10s03b00x00p14n01i00919cfg;