content
stringlengths 1
1.04M
⌀ |
|---|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
--use work.common.all;
ENTITY user_logic_hwtul IS
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
END ENTITY user_logic_hwtul;
ARCHITECTURE IMP OF user_logic_hwtul IS
-- HWTI Declarations.
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESSOF : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
-- STATE DECLARATIONS
constant START_STATE : std_logic_vector(0 to 15) := x"0004";
constant WAIT_STATE : std_logic_vector(0 to 15) := x"0005";
constant FUNCTCALL_STATE : std_logic_vector(0 to 15) := x"0006";
constant BOOTSTRAP0 : std_logic_vector(0 to 15) := x"0007";
constant BOOTSTRAP1 : std_logic_vector(0 to 15) := x"0008";
constant mailbox_write_start : std_logic_vector(0 to 15) := x"0009";
constant mailbox_write_save_0 : std_logic_vector(0 to 15) := x"000A";
constant mailbox_write_save_1 : std_logic_vector(0 to 15) := x"000B";
constant mailbox_write_save_2 : std_logic_vector(0 to 15) := x"000C";
constant mailbox_write_save_3 : std_logic_vector(0 to 15) := x"000D";
constant mailbox_write_save_4 : std_logic_vector(0 to 15) := x"000E";
constant mailbox_write_15_0_0 : std_logic_vector(0 to 15) := x"000F";
constant mailbox_write_15_0_1 : std_logic_vector(0 to 15) := x"0010";
constant mailbox_write_15_1_0 : std_logic_vector(0 to 15) := x"0011";
constant mailbox_write_15_1_1 : std_logic_vector(0 to 15) := x"0012";
constant mailbox_write_15_2_0 : std_logic_vector(0 to 15) := x"0013";
constant mailbox_write_15_3_0 : std_logic_vector(0 to 15) := x"0014";
constant mailbox_write_15_4_0 : std_logic_vector(0 to 15) := x"0015";
constant mailbox_write_15_4_1 : std_logic_vector(0 to 15) := x"0016";
constant mailbox_write_15_4_2 : std_logic_vector(0 to 15) := x"0017";
constant mailbox_write_15_5_0 : std_logic_vector(0 to 15) := x"0018";
constant mailbox_write_15_5_1 : std_logic_vector(0 to 15) := x"0019";
constant mailbox_write_15_6_0 : std_logic_vector(0 to 15) := x"001A";
constant mailbox_write_15_6_1 : std_logic_vector(0 to 15) := x"001B";
constant mailbox_write_15_7_0 : std_logic_vector(0 to 15) := x"001C";
constant mailbox_write_16_0_0 : std_logic_vector(0 to 15) := x"001D";
constant mailbox_write_17_0_0 : std_logic_vector(0 to 15) := x"001E";
constant mailbox_write_18_0_0 : std_logic_vector(0 to 15) := x"001F";
constant mailbox_write_18_1_0 : std_logic_vector(0 to 15) := x"0020";
constant mailbox_write_18_1_1 : std_logic_vector(0 to 15) := x"0021";
constant mailbox_write_18_1_2 : std_logic_vector(0 to 15) := x"0022";
constant mailbox_write_18_1_3 : std_logic_vector(0 to 15) := x"0023";
constant mailbox_write_18_2_0 : std_logic_vector(0 to 15) := x"0024";
constant mailbox_write_18_2_1 : std_logic_vector(0 to 15) := x"0025";
constant mailbox_write_18_3_0 : std_logic_vector(0 to 15) := x"0026";
constant mailbox_write_18_4_0 : std_logic_vector(0 to 15) := x"0027";
constant mailbox_write_18_4_1 : std_logic_vector(0 to 15) := x"0028";
constant mailbox_write_18_5_0 : std_logic_vector(0 to 15) := x"0029";
constant mailbox_write_19_0_0 : std_logic_vector(0 to 15) := x"002A";
constant mailbox_write_20_0_0 : std_logic_vector(0 to 15) := x"002B";
constant mailbox_write_21_0_0 : std_logic_vector(0 to 15) := x"002C";
constant mailbox_write_21_0_1 : std_logic_vector(0 to 15) := x"002D";
constant mailbox_write_21_1_0 : std_logic_vector(0 to 15) := x"002E";
constant mailbox_write_21_2_0 : std_logic_vector(0 to 15) := x"002F";
constant mailbox_write_21_2_1 : std_logic_vector(0 to 15) := x"0030";
constant mailbox_write_21_3_0 : std_logic_vector(0 to 15) := x"0031";
constant mailbox_write_21_3_1 : std_logic_vector(0 to 15) := x"0032";
constant mailbox_write_21_4_0 : std_logic_vector(0 to 15) := x"0033";
constant mailbox_write_21_5_0 : std_logic_vector(0 to 15) := x"0034";
constant mailbox_write_21_6_0 : std_logic_vector(0 to 15) := x"0035";
constant mailbox_write_21_7_0 : std_logic_vector(0 to 15) := x"0036";
constant mailbox_write_21_7_1 : std_logic_vector(0 to 15) := x"0037";
constant mailbox_write_21_8_0 : std_logic_vector(0 to 15) := x"0038";
constant mailbox_write_21_9_0 : std_logic_vector(0 to 15) := x"0039";
constant mailbox_write_21_9_1 : std_logic_vector(0 to 15) := x"003A";
constant mailbox_write_21_10_0 : std_logic_vector(0 to 15) := x"003B";
constant mailbox_write_21_10_1 : std_logic_vector(0 to 15) := x"003C";
constant mailbox_write_21_11_0 : std_logic_vector(0 to 15) := x"003D";
constant mailbox_write_21_12_0 : std_logic_vector(0 to 15) := x"003E";
constant mailbox_write_21_12_1 : std_logic_vector(0 to 15) := x"003F";
constant mailbox_write_21_13_0 : std_logic_vector(0 to 15) := x"0040";
constant mailbox_write_21_14_0 : std_logic_vector(0 to 15) := x"0041";
constant mailbox_write_21_15_0 : std_logic_vector(0 to 15) := x"0042";
constant mailbox_write_21_15_1 : std_logic_vector(0 to 15) := x"0043";
constant mailbox_write_21_15_2 : std_logic_vector(0 to 15) := x"0044";
constant mailbox_write_21_16_0 : std_logic_vector(0 to 15) := x"0045";
constant mailbox_write_21_17_0 : std_logic_vector(0 to 15) := x"0046";
constant mailbox_write_21_17_1 : std_logic_vector(0 to 15) := x"0047";
constant mailbox_write_21_17_2 : std_logic_vector(0 to 15) := x"0048";
constant mailbox_write_21_18_0 : std_logic_vector(0 to 15) := x"0049";
constant mailbox_write_restore_0 : std_logic_vector(0 to 15) := x"004A";
constant mailbox_write_restore_1 : std_logic_vector(0 to 15) := x"004B";
constant mailbox_write_restore_2 : std_logic_vector(0 to 15) := x"004C";
constant mailbox_write_restore_3 : std_logic_vector(0 to 15) := x"004D";
constant mailbox_write_restore_4 : std_logic_vector(0 to 15) := x"004E";
constant mailbox_write_end : std_logic_vector(0 to 15) := x"004F";
constant bubblesort_start : std_logic_vector(0 to 15) := x"0050";
constant bubblesort_save_0 : std_logic_vector(0 to 15) := x"0051";
constant bubblesort_save_1 : std_logic_vector(0 to 15) := x"0052";
constant bubblesort_save_2 : std_logic_vector(0 to 15) := x"0053";
constant bubblesort_save_3 : std_logic_vector(0 to 15) := x"0054";
constant bubblesort_save_4 : std_logic_vector(0 to 15) := x"0055";
constant bubblesort_save_5 : std_logic_vector(0 to 15) := x"0056";
constant bubblesort_save_6 : std_logic_vector(0 to 15) := x"0057";
constant bubblesort_save_7 : std_logic_vector(0 to 15) := x"0058";
constant bubblesort_save_8 : std_logic_vector(0 to 15) := x"0059";
constant bubblesort_0_0_0 : std_logic_vector(0 to 15) := x"005A";
constant bubblesort_0_0_1 : std_logic_vector(0 to 15) := x"005B";
constant bubblesort_0_1_0 : std_logic_vector(0 to 15) := x"005C";
constant bubblesort_0_1_1 : std_logic_vector(0 to 15) := x"005D";
constant bubblesort_0_2_0 : std_logic_vector(0 to 15) := x"005E";
constant bubblesort_0_3_0 : std_logic_vector(0 to 15) := x"005F";
constant bubblesort_0_4_0 : std_logic_vector(0 to 15) := x"0060";
constant bubblesort_0_5_0 : std_logic_vector(0 to 15) := x"0061";
constant bubblesort_0_6_0 : std_logic_vector(0 to 15) := x"0062";
constant bubblesort_1_0_0 : std_logic_vector(0 to 15) := x"0063";
constant bubblesort_1_0_1 : std_logic_vector(0 to 15) := x"0064";
constant bubblesort_1_1_0 : std_logic_vector(0 to 15) := x"0065";
constant bubblesort_1_2_0 : std_logic_vector(0 to 15) := x"0066";
constant bubblesort_1_3_0 : std_logic_vector(0 to 15) := x"0067";
constant bubblesort_1_3_1 : std_logic_vector(0 to 15) := x"0068";
constant bubblesort_1_4_0 : std_logic_vector(0 to 15) := x"0069";
constant bubblesort_1_5_0 : std_logic_vector(0 to 15) := x"006A";
constant bubblesort_1_6_0 : std_logic_vector(0 to 15) := x"006B";
constant bubblesort_1_7_0 : std_logic_vector(0 to 15) := x"006C";
constant bubblesort_1_8_0 : std_logic_vector(0 to 15) := x"006D";
constant bubblesort_1_8_1 : std_logic_vector(0 to 15) := x"006E";
constant bubblesort_1_9_0 : std_logic_vector(0 to 15) := x"006F";
constant bubblesort_2_0_0 : std_logic_vector(0 to 15) := x"0070";
constant bubblesort_3_0_0 : std_logic_vector(0 to 15) := x"0071";
constant bubblesort_4_0_0 : std_logic_vector(0 to 15) := x"0072";
constant bubblesort_4_1_0 : std_logic_vector(0 to 15) := x"0073";
constant bubblesort_4_2_0 : std_logic_vector(0 to 15) := x"0074";
constant bubblesort_4_3_0 : std_logic_vector(0 to 15) := x"0075";
constant bubblesort_4_4_0 : std_logic_vector(0 to 15) := x"0076";
constant bubblesort_5_0_0 : std_logic_vector(0 to 15) := x"0077";
constant bubblesort_6_0_0 : std_logic_vector(0 to 15) := x"0078";
constant bubblesort_7_0_0 : std_logic_vector(0 to 15) := x"0079";
constant bubblesort_8_0_0 : std_logic_vector(0 to 15) := x"007A";
constant bubblesort_9_0_0 : std_logic_vector(0 to 15) := x"007B";
constant bubblesort_10_0_0 : std_logic_vector(0 to 15) := x"007C";
constant bubblesort_11_0_0 : std_logic_vector(0 to 15) := x"007D";
constant bubblesort_12_0_0 : std_logic_vector(0 to 15) := x"007E";
constant bubblesort_12_1_0 : std_logic_vector(0 to 15) := x"007F";
constant bubblesort_12_2_0 : std_logic_vector(0 to 15) := x"0080";
constant bubblesort_12_3_0 : std_logic_vector(0 to 15) := x"0081";
constant bubblesort_13_0_0 : std_logic_vector(0 to 15) := x"0082";
constant bubblesort_restore_0 : std_logic_vector(0 to 15) := x"0083";
constant bubblesort_restore_1 : std_logic_vector(0 to 15) := x"0084";
constant bubblesort_restore_2 : std_logic_vector(0 to 15) := x"0085";
constant bubblesort_restore_3 : std_logic_vector(0 to 15) := x"0086";
constant bubblesort_restore_4 : std_logic_vector(0 to 15) := x"0087";
constant bubblesort_restore_5 : std_logic_vector(0 to 15) := x"0088";
constant bubblesort_restore_6 : std_logic_vector(0 to 15) := x"0089";
constant bubblesort_restore_7 : std_logic_vector(0 to 15) := x"008A";
constant bubblesort_restore_8 : std_logic_vector(0 to 15) := x"008B";
constant bubblesort_end : std_logic_vector(0 to 15) := x"008C";
constant mailbox_read_start : std_logic_vector(0 to 15) := x"008D";
constant mailbox_read_save_0 : std_logic_vector(0 to 15) := x"008E";
constant mailbox_read_save_1 : std_logic_vector(0 to 15) := x"008F";
constant mailbox_read_save_2 : std_logic_vector(0 to 15) := x"0090";
constant mailbox_read_save_3 : std_logic_vector(0 to 15) := x"0091";
constant mailbox_read_save_4 : std_logic_vector(0 to 15) := x"0092";
constant mailbox_read_23_0_0 : std_logic_vector(0 to 15) := x"0093";
constant mailbox_read_23_0_1 : std_logic_vector(0 to 15) := x"0094";
constant mailbox_read_23_1_0 : std_logic_vector(0 to 15) := x"0095";
constant mailbox_read_23_2_0 : std_logic_vector(0 to 15) := x"0096";
constant mailbox_read_23_3_0 : std_logic_vector(0 to 15) := x"0097";
constant mailbox_read_23_3_1 : std_logic_vector(0 to 15) := x"0098";
constant mailbox_read_23_3_2 : std_logic_vector(0 to 15) := x"0099";
constant mailbox_read_23_4_0 : std_logic_vector(0 to 15) := x"009A";
constant mailbox_read_23_4_1 : std_logic_vector(0 to 15) := x"009B";
constant mailbox_read_23_5_0 : std_logic_vector(0 to 15) := x"009C";
constant mailbox_read_24_0_0 : std_logic_vector(0 to 15) := x"009D";
constant mailbox_read_25_0_0 : std_logic_vector(0 to 15) := x"009E";
constant mailbox_read_26_0_0 : std_logic_vector(0 to 15) := x"009F";
constant mailbox_read_26_1_0 : std_logic_vector(0 to 15) := x"00A0";
constant mailbox_read_26_1_1 : std_logic_vector(0 to 15) := x"00A1";
constant mailbox_read_26_1_2 : std_logic_vector(0 to 15) := x"00A2";
constant mailbox_read_26_1_3 : std_logic_vector(0 to 15) := x"00A3";
constant mailbox_read_26_2_0 : std_logic_vector(0 to 15) := x"00A4";
constant mailbox_read_26_2_1 : std_logic_vector(0 to 15) := x"00A5";
constant mailbox_read_26_3_0 : std_logic_vector(0 to 15) := x"00A6";
constant mailbox_read_27_0_0 : std_logic_vector(0 to 15) := x"00A7";
constant mailbox_read_28_0_0 : std_logic_vector(0 to 15) := x"00A8";
constant mailbox_read_29_0_0 : std_logic_vector(0 to 15) := x"00A9";
constant mailbox_read_29_0_1 : std_logic_vector(0 to 15) := x"00AA";
constant mailbox_read_29_1_0 : std_logic_vector(0 to 15) := x"00AB";
constant mailbox_read_29_2_0 : std_logic_vector(0 to 15) := x"00AC";
constant mailbox_read_29_2_1 : std_logic_vector(0 to 15) := x"00AD";
constant mailbox_read_29_3_0 : std_logic_vector(0 to 15) := x"00AE";
constant mailbox_read_29_4_0 : std_logic_vector(0 to 15) := x"00AF";
constant mailbox_read_29_5_0 : std_logic_vector(0 to 15) := x"00B0";
constant mailbox_read_29_5_1 : std_logic_vector(0 to 15) := x"00B1";
constant mailbox_read_29_6_0 : std_logic_vector(0 to 15) := x"00B2";
constant mailbox_read_29_7_0 : std_logic_vector(0 to 15) := x"00B3";
constant mailbox_read_29_7_1 : std_logic_vector(0 to 15) := x"00B4";
constant mailbox_read_29_8_0 : std_logic_vector(0 to 15) := x"00B5";
constant mailbox_read_29_9_0 : std_logic_vector(0 to 15) := x"00B6";
constant mailbox_read_29_10_0 : std_logic_vector(0 to 15) := x"00B7";
constant mailbox_read_29_10_1 : std_logic_vector(0 to 15) := x"00B8";
constant mailbox_read_29_11_0 : std_logic_vector(0 to 15) := x"00B9";
constant mailbox_read_29_11_1 : std_logic_vector(0 to 15) := x"00BA";
constant mailbox_read_29_12_0 : std_logic_vector(0 to 15) := x"00BB";
constant mailbox_read_29_13_0 : std_logic_vector(0 to 15) := x"00BC";
constant mailbox_read_29_13_1 : std_logic_vector(0 to 15) := x"00BD";
constant mailbox_read_29_14_0 : std_logic_vector(0 to 15) := x"00BE";
constant mailbox_read_29_15_0 : std_logic_vector(0 to 15) := x"00BF";
constant mailbox_read_29_16_0 : std_logic_vector(0 to 15) := x"00C0";
constant mailbox_read_29_16_1 : std_logic_vector(0 to 15) := x"00C1";
constant mailbox_read_29_16_2 : std_logic_vector(0 to 15) := x"00C2";
constant mailbox_read_29_17_0 : std_logic_vector(0 to 15) := x"00C3";
constant mailbox_read_29_18_0 : std_logic_vector(0 to 15) := x"00C4";
constant mailbox_read_29_18_1 : std_logic_vector(0 to 15) := x"00C5";
constant mailbox_read_29_18_2 : std_logic_vector(0 to 15) := x"00C6";
constant mailbox_read_29_19_0 : std_logic_vector(0 to 15) := x"00C7";
constant mailbox_read_restore_0 : std_logic_vector(0 to 15) := x"00C8";
constant mailbox_read_restore_1 : std_logic_vector(0 to 15) := x"00C9";
constant mailbox_read_restore_2 : std_logic_vector(0 to 15) := x"00CA";
constant mailbox_read_restore_3 : std_logic_vector(0 to 15) := x"00CB";
constant mailbox_read_restore_4 : std_logic_vector(0 to 15) := x"00CC";
constant mailbox_read_end : std_logic_vector(0 to 15) := x"00CD";
constant sort8k_entry_start : std_logic_vector(0 to 15) := x"00CE";
constant sort8k_entry_save_0 : std_logic_vector(0 to 15) := x"00CF";
constant sort8k_entry_save_1 : std_logic_vector(0 to 15) := x"00D0";
constant sort8k_entry_31_0_0 : std_logic_vector(0 to 15) := x"00D1";
constant sort8k_entry_31_0_1 : std_logic_vector(0 to 15) := x"00D2";
constant sort8k_entry_31_1_0 : std_logic_vector(0 to 15) := x"00D3";
constant sort8k_entry_32_0_0 : std_logic_vector(0 to 15) := x"00D4";
constant sort8k_entry_32_1_0 : std_logic_vector(0 to 15) := x"00D5";
constant sort8k_entry_32_1_1 : std_logic_vector(0 to 15) := x"00D6";
constant sort8k_entry_32_1_2 : std_logic_vector(0 to 15) := x"00D7";
constant sort8k_entry_32_2_0 : std_logic_vector(0 to 15) := x"00D8";
constant sort8k_entry_32_2_1 : std_logic_vector(0 to 15) := x"00D9";
constant sort8k_entry_32_2_2 : std_logic_vector(0 to 15) := x"00DA";
constant sort8k_entry_32_2_3 : std_logic_vector(0 to 15) := x"00DB";
constant sort8k_entry_32_3_0 : std_logic_vector(0 to 15) := x"00DC";
constant sort8k_entry_32_4_0 : std_logic_vector(0 to 15) := x"00DD";
constant sort8k_entry_32_4_1 : std_logic_vector(0 to 15) := x"00DE";
constant sort8k_entry_32_4_2 : std_logic_vector(0 to 15) := x"00DF";
constant sort8k_entry_32_4_3 : std_logic_vector(0 to 15) := x"00E0";
constant sort8k_entry_32_5_0 : std_logic_vector(0 to 15) := x"00E1";
constant sort8k_entry_33_0_0 : std_logic_vector(0 to 15) := x"00E2";
constant sort8k_entry_restore_0 : std_logic_vector(0 to 15) := x"00E3";
constant sort8k_entry_restore_1 : std_logic_vector(0 to 15) := x"00E4";
constant sort8k_entry_end : std_logic_vector(0 to 15) := x"00E5";
constant MULT00 : std_logic_vector(0 to 15) := x"00E6";
constant MULT01 : std_logic_vector(0 to 15) := x"00E7";
constant MULT02 : std_logic_vector(0 to 15) := x"00E8";
constant DIVIDE00 : std_logic_vector(0 to 15) := x"00E9";
constant DIVIDE01 : std_logic_vector(0 to 15) := x"00EA";
constant DIVIDE02 : std_logic_vector(0 to 15) := x"00EB";
constant DIVIDE03 : std_logic_vector(0 to 15) := x"00EC";
constant DIVIDE04 : std_logic_vector(0 to 15) := x"00ED";
constant DIVIDE05 : std_logic_vector(0 to 15) := x"00EE";
-- REGISTER DECLARATIONS
-- Special purpose registers
signal curstate : std_logic_vector(0 to 15) := START_STATE;
signal returnstate : std_logic_vector(0 to 15) := WAIT_STATE;
signal returnVal : std_logic_vector(0 to 31) := x"00000000";
signal stack_mem : std_logic_vector(0 to 31) := x"00000000";
signal params_mem : std_logic_vector(0 to 31) := x"00000000";
-- Caller save registers
signal T1 : std_logic_vector(0 to 31) := x"00000000";
signal T2 : std_logic_vector(0 to 31) := x"00000000";
signal T3 : std_logic_vector(0 to 31) := x"00000000";
signal T4 : std_logic_vector(0 to 31) := x"00000000";
signal T5 : std_logic_vector(0 to 31) := x"00000000";
signal T6 : std_logic_vector(0 to 31) := x"00000000";
-- Callee save registers
signal R4 : std_logic_vector(0 to 31) := x"00000000";
signal R5 : std_logic_vector(0 to 31) := x"00000000";
signal R6 : std_logic_vector(0 to 31) := x"00000000";
signal R7 : std_logic_vector(0 to 31) := x"00000000";
signal R0 : std_logic_vector(0 to 31) := x"00000000";
signal R1 : std_logic_vector(0 to 31) := x"00000000";
signal R2 : std_logic_vector(0 to 31) := x"00000000";
signal R3 : std_logic_vector(0 to 31) := x"00000000";
signal R8 : std_logic_vector(0 to 31) := x"00000000";
BEGIN
state_mach : PROCESS
BEGIN
WAIT UNTIL rising_edge(clock);
IF (intrfc2thrd_goWait = '1') and (intrfc2thrd_function = U_FUNCTION_RESET) THEN
-- Reset event
thrd2intrfc_address <= x"00000000";
thrd2intrfc_value <= x"00000000";
thrd2intrfc_function <= x"0000";
thrd2intrfc_opcode <= "000000";
curstate <= START_STATE;
returnstate <= WAIT_STATE;
returnVal <= x"00000000";
stack_mem <= x"00000000";
params_mem <= x"00000000";
T1 <= x"00000000";
T2 <= x"00000000";
T3 <= x"00000000";
T4 <= x"00000000";
T5 <= x"00000000";
T6 <= x"00000000";
R4 <= x"00000000";
R5 <= x"00000000";
R6 <= x"00000000";
R7 <= x"00000000";
R0 <= x"00000000";
R1 <= x"00000000";
R2 <= x"00000000";
R3 <= x"00000000";
R8 <= x"00000000";
ELSE
IF (intrfc2thrd_goWait = '1') THEN
thrd2intrfc_opcode <= OPCODE_NOOP; --OPCODE IS NOOP BY DEFAULT
CASE curstate IS
-- Start loops while function code is "start"
WHEN START_STATE =>
IF intrfc2thrd_function = U_FUNCTION_START THEN
curstate <= START_STATE;
ELSE
curstate <= BOOTSTRAP0;
END IF;
WHEN BOOTSTRAP0 =>
-- Call addressof to get the stack_mem pointer value.
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_ADDRESSOF;
curstate <= WAIT_STATE;
returnstate <= BOOTSTRAP1;
WHEN BOOTSTRAP1 =>
-- Use the result of the addressof to set stack_mem and params_mem.
-- Also call the declare opcode to initialize the stack for the thread main function.
stack_mem <= intrfc2thrd_value;
params_mem <= intrfc2thrd_value - x"00000010";
thrd2intrfc_value <= x"00000002";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_31_0_0;
-- Begin of function mailbox_write (from mailbox_no_globals.c.hif)
WHEN mailbox_write_start =>
-- Declare the number of stack memory words needed for this function.
thrd2intrfc_value <= x"00000005";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_0;
WHEN mailbox_write_save_0 =>
-- Save register R0 on the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_1;
WHEN mailbox_write_save_1 =>
-- Save register R1 on the stack.
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_2;
WHEN mailbox_write_save_2 =>
-- Save register R2 on the stack.
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_3;
WHEN mailbox_write_save_3 =>
-- Save register R3 on the stack.
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_save_4;
WHEN mailbox_write_save_4 =>
-- Save register R4 on the stack.
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_value <= R4;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_0_0;
WHEN mailbox_write_15_0_0 =>
-- arith2: @readarg R2 0 (296)
thrd2intrfc_value <= x"00000001";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_0_1;
WHEN mailbox_write_15_0_1 =>
-- Capture result of readarg.
R2 <= intrfc2thrd_value;
curstate <= mailbox_write_15_1_0;
WHEN mailbox_write_15_1_0 =>
-- arith2: @readarg R4 1 (297)
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_1_1;
WHEN mailbox_write_15_1_1 =>
-- Capture result of readarg.
R4 <= intrfc2thrd_value;
curstate <= mailbox_write_15_2_0;
WHEN mailbox_write_15_2_0 =>
-- arith3: @add R0 R2 20 (0)
R0 <= R2 + x"00000014";
curstate <= mailbox_write_15_3_0;
WHEN mailbox_write_15_3_0 =>
-- arith2: @mov R3 R0 (320)
R3 <= R0;
curstate <= mailbox_write_15_4_0;
WHEN mailbox_write_15_4_0 =>
-- call hthread_mutex_lock R3 @returnVal @none (321)
-- Push argument 0
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_4_1;
WHEN mailbox_write_15_4_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= x"0000"&mailbox_write_15_4_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_write_15_4_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_write_15_5_0;
WHEN mailbox_write_15_5_0 =>
-- read R0 R2 12 (322)
thrd2intrfc_address <= R2 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_5_1;
WHEN mailbox_write_15_5_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_15_6_0;
WHEN mailbox_write_15_6_0 =>
-- read R1 R2 0 (323)
thrd2intrfc_address <= R2 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_15_6_1;
WHEN mailbox_write_15_6_1 =>
-- Capture result of read.
R1 <= intrfc2thrd_value;
curstate <= mailbox_write_15_7_0;
WHEN mailbox_write_15_7_0 =>
-- if R1 S> R0 goto hif_label0(17) (324)
if (R1 > R0) then
curstate <= mailbox_write_17_0_0;
else
curstate <= mailbox_write_16_0_0;
end if;
WHEN mailbox_write_16_0_0 =>
-- goto HIFL0(18) (325)
curstate <= mailbox_write_18_0_0;
WHEN mailbox_write_17_0_0 =>
-- goto HIFL2(21) (328)
curstate <= mailbox_write_21_0_0;
WHEN mailbox_write_18_0_0 =>
-- arith3: @add R0 R2 32 (0)
R0 <= R2 + x"00000020";
curstate <= mailbox_write_18_1_0;
WHEN mailbox_write_18_1_0 =>
-- call hthread_cond_wait R0 R3 @returnVal @none (333)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_18_1_1;
WHEN mailbox_write_18_1_1 =>
-- Push argument 1
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_18_1_2;
WHEN mailbox_write_18_1_2 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000028";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_WAIT;
thrd2intrfc_value <= x"0000"&mailbox_write_18_1_3;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_write_18_1_3 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000028";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_write_18_2_0;
WHEN mailbox_write_18_2_0 =>
-- read R0 R2 12 (334)
thrd2intrfc_address <= R2 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_18_2_1;
WHEN mailbox_write_18_2_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_18_3_0;
WHEN mailbox_write_18_3_0 =>
-- arith2: @mov R1 R0 (334)
R1 <= R0;
curstate <= mailbox_write_18_4_0;
WHEN mailbox_write_18_4_0 =>
-- read R0 R2 0 (335)
thrd2intrfc_address <= R2 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_18_4_1;
WHEN mailbox_write_18_4_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_18_5_0;
WHEN mailbox_write_18_5_0 =>
-- if R1 S< R0 goto hif_label2(20) (336)
if (R1 < R0) then
curstate <= mailbox_write_20_0_0;
else
curstate <= mailbox_write_19_0_0;
end if;
WHEN mailbox_write_19_0_0 =>
-- goto HIFL0(18) (337)
curstate <= mailbox_write_18_0_0;
WHEN mailbox_write_20_0_0 =>
-- goto HIFL2(21) (340)
curstate <= mailbox_write_21_0_0;
WHEN mailbox_write_21_0_0 =>
-- read R0 R2 16 (344)
thrd2intrfc_address <= R2 + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_0_1;
WHEN mailbox_write_21_0_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_1_0;
WHEN mailbox_write_21_1_0 =>
-- arith2: @mov R1 R0 (344)
R1 <= R0;
curstate <= mailbox_write_21_2_0;
WHEN mailbox_write_21_2_0 =>
-- read R0 R2 8 (345)
thrd2intrfc_address <= R2 + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_2_1;
WHEN mailbox_write_21_2_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_3_0;
WHEN mailbox_write_21_3_0 =>
-- arith3: @mul R0 R0 4 (347)
--call quick function (will set returnVal)
T1 <= x"0000"&mailbox_write_21_3_1; --return address
T2 <= R0; --operand 1
T3 <= x"00000004"; --operand 2
T4 <= T4;
curstate <= MULT00;
WHEN mailbox_write_21_3_1 =>
R0 <= returnVal;
curstate <= mailbox_write_21_4_0;
WHEN mailbox_write_21_4_0 =>
-- arith3: @add R0 R1 R0 (349)
R0 <= R1 + R0;
curstate <= mailbox_write_21_5_0;
WHEN mailbox_write_21_5_0 =>
-- arith2: @mov R1 R4 (350)
R1 <= R4;
curstate <= mailbox_write_21_6_0;
WHEN mailbox_write_21_6_0 =>
-- write R0 0 R1 (350)
thrd2intrfc_address <= R0 + x"00000000";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_7_0;
WHEN mailbox_write_21_7_0 =>
-- read R0 R2 8 (351)
thrd2intrfc_address <= R2 + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_7_1;
WHEN mailbox_write_21_7_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_8_0;
WHEN mailbox_write_21_8_0 =>
-- arith3: @add R1 R0 1 (352)
R1 <= R0 + x"00000001";
curstate <= mailbox_write_21_9_0;
WHEN mailbox_write_21_9_0 =>
-- read R0 R2 0 (353)
thrd2intrfc_address <= R2 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_9_1;
WHEN mailbox_write_21_9_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_10_0;
WHEN mailbox_write_21_10_0 =>
-- arith3: @mod R0 R1 R0 (354)
--call quick function (will set returnVal)
T1 <= x"0000"&mailbox_write_21_10_1; --return address
T2 <= R1; --operand 1
T3 <= R0; --operand 2
T4 <= T4;
curstate <= DIVIDE00;
WHEN mailbox_write_21_10_1 =>
R0 <= T4;
curstate <= mailbox_write_21_11_0;
WHEN mailbox_write_21_11_0 =>
-- write R2 8 R0 (355)
thrd2intrfc_address <= R2 + x"00000008";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_12_0;
WHEN mailbox_write_21_12_0 =>
-- read R0 R2 12 (356)
thrd2intrfc_address <= R2 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_12_1;
WHEN mailbox_write_21_12_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_write_21_13_0;
WHEN mailbox_write_21_13_0 =>
-- arith3: @add R0 R0 1 (357)
R0 <= R0 + x"00000001";
curstate <= mailbox_write_21_14_0;
WHEN mailbox_write_21_14_0 =>
-- write R2 12 R0 (358)
thrd2intrfc_address <= R2 + x"0000000C";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_15_0;
WHEN mailbox_write_21_15_0 =>
-- call hthread_mutex_unlock R3 @returnVal @none (359)
-- Push argument 0
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_15_1;
WHEN mailbox_write_21_15_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= x"0000"&mailbox_write_21_15_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_write_21_15_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_write_21_16_0;
WHEN mailbox_write_21_16_0 =>
-- arith3: @add R0 R2 28 (0)
R0 <= R2 + x"0000001C";
curstate <= mailbox_write_21_17_0;
WHEN mailbox_write_21_17_0 =>
-- call hthread_cond_signal R0 @returnVal @none (361)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_21_17_1;
WHEN mailbox_write_21_17_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= x"0000"&mailbox_write_21_17_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_write_21_17_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_write_21_18_0;
WHEN mailbox_write_21_18_0 =>
-- return 0 (362)
T1 <= x"00000000";
curstate <= mailbox_write_restore_0;
WHEN mailbox_write_restore_0 =>
-- Restore register R0 from the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_restore_1;
WHEN mailbox_write_restore_1 =>
-- Restore register R1 from the stack.
R0 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_restore_2;
WHEN mailbox_write_restore_2 =>
-- Restore register R2 from the stack.
R1 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_restore_3;
WHEN mailbox_write_restore_3 =>
-- Restore register R3 from the stack.
R2 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_restore_4;
WHEN mailbox_write_restore_4 =>
-- Restore register R4 from the stack.
R3 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_write_end;
WHEN mailbox_write_end =>
-- Use the return opcode to jump back to the caller.
R4 <= intrfc2thrd_value;
thrd2intrfc_value <= T1;
thrd2intrfc_opcode <= OPCODE_RETURN;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
-- Begin of function bubblesort (from bubblesort.c.hif)
WHEN bubblesort_start =>
-- Declare the number of stack memory words needed for this function.
thrd2intrfc_value <= x"00000009";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_0;
WHEN bubblesort_save_0 =>
-- Save register R0 on the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_1;
WHEN bubblesort_save_1 =>
-- Save register R1 on the stack.
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_2;
WHEN bubblesort_save_2 =>
-- Save register R2 on the stack.
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_3;
WHEN bubblesort_save_3 =>
-- Save register R3 on the stack.
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_4;
WHEN bubblesort_save_4 =>
-- Save register R4 on the stack.
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_value <= R4;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_5;
WHEN bubblesort_save_5 =>
-- Save register R5 on the stack.
thrd2intrfc_address <= stack_mem + x"00000014";
thrd2intrfc_value <= R5;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_6;
WHEN bubblesort_save_6 =>
-- Save register R6 on the stack.
thrd2intrfc_address <= stack_mem + x"00000018";
thrd2intrfc_value <= R6;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_7;
WHEN bubblesort_save_7 =>
-- Save register R7 on the stack.
thrd2intrfc_address <= stack_mem + x"0000001C";
thrd2intrfc_value <= R7;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_save_8;
WHEN bubblesort_save_8 =>
-- Save register R8 on the stack.
thrd2intrfc_address <= stack_mem + x"00000020";
thrd2intrfc_value <= R8;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_0_0_0;
WHEN bubblesort_0_0_0 =>
-- arith2: @readarg R1 0 (7)
thrd2intrfc_value <= x"00000001";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= bubblesort_0_0_1;
WHEN bubblesort_0_0_1 =>
-- Capture result of readarg.
R1 <= intrfc2thrd_value;
curstate <= bubblesort_0_1_0;
WHEN bubblesort_0_1_0 =>
-- arith2: @readarg R0 1 (8)
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= bubblesort_0_1_1;
WHEN bubblesort_0_1_1 =>
-- Capture result of readarg.
R0 <= intrfc2thrd_value;
curstate <= bubblesort_0_2_0;
WHEN bubblesort_0_2_0 =>
-- arith3: @sub R4 R0 1 (24)
R4 <= R0 - x"00000001";
curstate <= bubblesort_0_3_0;
WHEN bubblesort_0_3_0 =>
-- arith2: @mov R2 R4 (25)
R2 <= R4;
curstate <= bubblesort_0_4_0;
WHEN bubblesort_0_4_0 =>
-- arith2: @mov R8 0 (26)
R8 <= x"00000000";
curstate <= bubblesort_0_5_0;
WHEN bubblesort_0_5_0 =>
-- arith2: @mov R3 0 (27)
R3 <= x"00000000";
curstate <= bubblesort_0_6_0;
WHEN bubblesort_0_6_0 =>
-- goto HIFL9(6) (28)
curstate <= bubblesort_6_0_0;
WHEN bubblesort_1_0_0 =>
-- arith3: @mul R7 R3 4 (30)
--call quick function (will set returnVal)
T1 <= x"0000"&bubblesort_1_0_1; --return address
T2 <= R3; --operand 1
T3 <= x"00000004"; --operand 2
T4 <= T4;
curstate <= MULT00;
WHEN bubblesort_1_0_1 =>
R7 <= returnVal;
curstate <= bubblesort_1_1_0;
WHEN bubblesort_1_1_0 =>
-- arith2: @mov R0 R7 (31)
R0 <= R7;
curstate <= bubblesort_1_2_0;
WHEN bubblesort_1_2_0 =>
-- arith3: @add R6 R0 R1 (32)
R6 <= R0 + R1;
curstate <= bubblesort_1_3_0;
WHEN bubblesort_1_3_0 =>
-- read R0 R6 0 (33)
thrd2intrfc_address <= R6 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_1_3_1;
WHEN bubblesort_1_3_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= bubblesort_1_4_0;
WHEN bubblesort_1_4_0 =>
-- arith2: @mov R5 R0 (33)
R5 <= R0;
curstate <= bubblesort_1_5_0;
WHEN bubblesort_1_5_0 =>
-- arith2: @mov R0 R7 (34)
R0 <= R7;
curstate <= bubblesort_1_6_0;
WHEN bubblesort_1_6_0 =>
-- arith3: @add R0 R1 R0 (35)
R0 <= R1 + R0;
curstate <= bubblesort_1_7_0;
WHEN bubblesort_1_7_0 =>
-- arith3: @add R7 R0 4 (36)
R7 <= R0 + x"00000004";
curstate <= bubblesort_1_8_0;
WHEN bubblesort_1_8_0 =>
-- read R0 R7 0 (37)
thrd2intrfc_address <= R7 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_1_8_1;
WHEN bubblesort_1_8_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= bubblesort_1_9_0;
WHEN bubblesort_1_9_0 =>
-- if R5 U<= R0 goto hif_label0(3) (38)
if (R5 <= R0) then
curstate <= bubblesort_3_0_0;
else
curstate <= bubblesort_2_0_0;
end if;
WHEN bubblesort_2_0_0 =>
-- goto HIFL2(4) (39)
curstate <= bubblesort_4_0_0;
WHEN bubblesort_3_0_0 =>
-- goto HIFL3(5) (42)
curstate <= bubblesort_5_0_0;
WHEN bubblesort_4_0_0 =>
-- write R6 0 R0 (46)
thrd2intrfc_address <= R6 + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_4_1_0;
WHEN bubblesort_4_1_0 =>
-- arith2: @mov R0 R5 (47)
R0 <= R5;
curstate <= bubblesort_4_2_0;
WHEN bubblesort_4_2_0 =>
-- write R7 0 R0 (47)
thrd2intrfc_address <= R7 + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= bubblesort_4_3_0;
WHEN bubblesort_4_3_0 =>
-- arith2: @mov R2 R3 (48)
R2 <= R3;
curstate <= bubblesort_4_4_0;
WHEN bubblesort_4_4_0 =>
-- arith2: @mov R8 1 (49)
R8 <= x"00000001";
curstate <= bubblesort_5_0_0;
WHEN bubblesort_5_0_0 =>
-- arith3: @add R3 R3 1 (51)
R3 <= R3 + x"00000001";
curstate <= bubblesort_6_0_0;
WHEN bubblesort_6_0_0 =>
-- if R3 U>= R4 goto hif_label2(8) (53)
if (R3 >= R4) then
curstate <= bubblesort_8_0_0;
else
curstate <= bubblesort_7_0_0;
end if;
WHEN bubblesort_7_0_0 =>
-- goto HIFL1(1) (54)
curstate <= bubblesort_1_0_0;
WHEN bubblesort_8_0_0 =>
-- goto HIFL6(9) (57)
curstate <= bubblesort_9_0_0;
WHEN bubblesort_9_0_0 =>
-- if R8 S== 0 goto hif_label4(11) (61)
if (R8 = x"00000000") then
curstate <= bubblesort_11_0_0;
else
curstate <= bubblesort_10_0_0;
end if;
WHEN bubblesort_10_0_0 =>
-- goto HIFL12(12) (62)
curstate <= bubblesort_12_0_0;
WHEN bubblesort_11_0_0 =>
-- goto HIFL7(13) (65)
curstate <= bubblesort_13_0_0;
WHEN bubblesort_12_0_0 =>
-- arith2: @mov R4 R2 (69)
R4 <= R2;
curstate <= bubblesort_12_1_0;
WHEN bubblesort_12_1_0 =>
-- arith2: @mov R8 0 (70)
R8 <= x"00000000";
curstate <= bubblesort_12_2_0;
WHEN bubblesort_12_2_0 =>
-- arith2: @mov R3 0 (71)
R3 <= x"00000000";
curstate <= bubblesort_12_3_0;
WHEN bubblesort_12_3_0 =>
-- goto HIFL9(6) (72)
curstate <= bubblesort_6_0_0;
WHEN bubblesort_13_0_0 =>
-- return @none (74)
T1 <= x"00000000";
curstate <= bubblesort_restore_0;
WHEN bubblesort_restore_0 =>
-- Restore register R0 from the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_1;
WHEN bubblesort_restore_1 =>
-- Restore register R1 from the stack.
R0 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_2;
WHEN bubblesort_restore_2 =>
-- Restore register R2 from the stack.
R1 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_3;
WHEN bubblesort_restore_3 =>
-- Restore register R3 from the stack.
R2 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_4;
WHEN bubblesort_restore_4 =>
-- Restore register R4 from the stack.
R3 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_5;
WHEN bubblesort_restore_5 =>
-- Restore register R5 from the stack.
R4 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000014";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_6;
WHEN bubblesort_restore_6 =>
-- Restore register R6 from the stack.
R5 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000018";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_7;
WHEN bubblesort_restore_7 =>
-- Restore register R7 from the stack.
R6 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"0000001C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_restore_8;
WHEN bubblesort_restore_8 =>
-- Restore register R8 from the stack.
R7 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000020";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= bubblesort_end;
WHEN bubblesort_end =>
-- Use the return opcode to jump back to the caller.
R8 <= intrfc2thrd_value;
thrd2intrfc_value <= T1;
thrd2intrfc_opcode <= OPCODE_RETURN;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
-- Begin of function mailbox_read (from mailbox_no_globals.c.hif)
WHEN mailbox_read_start =>
-- Declare the number of stack memory words needed for this function.
thrd2intrfc_value <= x"00000005";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_0;
WHEN mailbox_read_save_0 =>
-- Save register R0 on the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_1;
WHEN mailbox_read_save_1 =>
-- Save register R1 on the stack.
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_2;
WHEN mailbox_read_save_2 =>
-- Save register R2 on the stack.
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_3;
WHEN mailbox_read_save_3 =>
-- Save register R3 on the stack.
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_value <= R3;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_save_4;
WHEN mailbox_read_save_4 =>
-- Save register R4 on the stack.
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_value <= R4;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_23_0_0;
WHEN mailbox_read_23_0_0 =>
-- arith2: @readarg R1 0 (57)
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_23_0_1;
WHEN mailbox_read_23_0_1 =>
-- Capture result of readarg.
R1 <= intrfc2thrd_value;
curstate <= mailbox_read_23_1_0;
WHEN mailbox_read_23_1_0 =>
-- arith3: @add R0 R1 20 (0)
R0 <= R1 + x"00000014";
curstate <= mailbox_read_23_2_0;
WHEN mailbox_read_23_2_0 =>
-- arith2: @mov R2 R0 (78)
R2 <= R0;
curstate <= mailbox_read_23_3_0;
WHEN mailbox_read_23_3_0 =>
-- call hthread_mutex_lock R2 @returnVal @none (79)
-- Push argument 0
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_23_3_1;
WHEN mailbox_read_23_3_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= x"0000"&mailbox_read_23_3_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_read_23_3_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_read_23_4_0;
WHEN mailbox_read_23_4_0 =>
-- read R0 R1 12 (80)
thrd2intrfc_address <= R1 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_23_4_1;
WHEN mailbox_read_23_4_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_23_5_0;
WHEN mailbox_read_23_5_0 =>
-- if R0 S> 0 goto hif_label0(25) (81)
if (R0 > x"00000000") then
curstate <= mailbox_read_25_0_0;
else
curstate <= mailbox_read_24_0_0;
end if;
WHEN mailbox_read_24_0_0 =>
-- goto HIFL0(26) (82)
curstate <= mailbox_read_26_0_0;
WHEN mailbox_read_25_0_0 =>
-- goto HIFL2(29) (85)
curstate <= mailbox_read_29_0_0;
WHEN mailbox_read_26_0_0 =>
-- arith3: @add R0 R1 28 (0)
R0 <= R1 + x"0000001C";
curstate <= mailbox_read_26_1_0;
WHEN mailbox_read_26_1_0 =>
-- call hthread_cond_wait R0 R2 @returnVal @none (90)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_26_1_1;
WHEN mailbox_read_26_1_1 =>
-- Push argument 1
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_26_1_2;
WHEN mailbox_read_26_1_2 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000028";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_WAIT;
thrd2intrfc_value <= x"0000"&mailbox_read_26_1_3;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_read_26_1_3 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000028";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_read_26_2_0;
WHEN mailbox_read_26_2_0 =>
-- read R0 R1 12 (91)
thrd2intrfc_address <= R1 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_26_2_1;
WHEN mailbox_read_26_2_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_26_3_0;
WHEN mailbox_read_26_3_0 =>
-- if R0 S> 0 goto hif_label2(28) (92)
if (R0 > x"00000000") then
curstate <= mailbox_read_28_0_0;
else
curstate <= mailbox_read_27_0_0;
end if;
WHEN mailbox_read_27_0_0 =>
-- goto HIFL0(26) (93)
curstate <= mailbox_read_26_0_0;
WHEN mailbox_read_28_0_0 =>
-- goto HIFL2(29) (96)
curstate <= mailbox_read_29_0_0;
WHEN mailbox_read_29_0_0 =>
-- read R0 R1 16 (100)
thrd2intrfc_address <= R1 + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_0_1;
WHEN mailbox_read_29_0_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_1_0;
WHEN mailbox_read_29_1_0 =>
-- arith2: @mov R4 R0 (100)
R4 <= R0;
curstate <= mailbox_read_29_2_0;
WHEN mailbox_read_29_2_0 =>
-- read R0 R1 4 (101)
thrd2intrfc_address <= R1 + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_2_1;
WHEN mailbox_read_29_2_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_3_0;
WHEN mailbox_read_29_3_0 =>
-- arith2: @mov R3 R0 (101)
R3 <= R0;
curstate <= mailbox_read_29_4_0;
WHEN mailbox_read_29_4_0 =>
-- arith2: @mov R0 R3 (102)
R0 <= R3;
curstate <= mailbox_read_29_5_0;
WHEN mailbox_read_29_5_0 =>
-- arith3: @mul R0 R0 4 (103)
--call quick function (will set returnVal)
T1 <= x"0000"&mailbox_read_29_5_1; --return address
T2 <= R0; --operand 1
T3 <= x"00000004"; --operand 2
T4 <= T4;
curstate <= MULT00;
WHEN mailbox_read_29_5_1 =>
R0 <= returnVal;
curstate <= mailbox_read_29_6_0;
WHEN mailbox_read_29_6_0 =>
-- arith3: @add R0 R4 R0 (105)
R0 <= R4 + R0;
curstate <= mailbox_read_29_7_0;
WHEN mailbox_read_29_7_0 =>
-- read R0 R0 0 (106)
thrd2intrfc_address <= R0 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_7_1;
WHEN mailbox_read_29_7_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_8_0;
WHEN mailbox_read_29_8_0 =>
-- arith2: @mov R4 R0 (106)
R4 <= R0;
curstate <= mailbox_read_29_9_0;
WHEN mailbox_read_29_9_0 =>
-- arith3: @add R3 R3 1 (107)
R3 <= R3 + x"00000001";
curstate <= mailbox_read_29_10_0;
WHEN mailbox_read_29_10_0 =>
-- read R0 R1 0 (108)
thrd2intrfc_address <= R1 + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_10_1;
WHEN mailbox_read_29_10_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_11_0;
WHEN mailbox_read_29_11_0 =>
-- arith3: @mod R0 R3 R0 (109)
--call quick function (will set returnVal)
T1 <= x"0000"&mailbox_read_29_11_1; --return address
T2 <= R3; --operand 1
T3 <= R0; --operand 2
T4 <= T4;
curstate <= DIVIDE00;
WHEN mailbox_read_29_11_1 =>
R0 <= T4;
curstate <= mailbox_read_29_12_0;
WHEN mailbox_read_29_12_0 =>
-- write R1 4 R0 (110)
thrd2intrfc_address <= R1 + x"00000004";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_13_0;
WHEN mailbox_read_29_13_0 =>
-- read R0 R1 12 (111)
thrd2intrfc_address <= R1 + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_13_1;
WHEN mailbox_read_29_13_1 =>
-- Capture result of read.
R0 <= intrfc2thrd_value;
curstate <= mailbox_read_29_14_0;
WHEN mailbox_read_29_14_0 =>
-- arith3: @sub R0 R0 1 (112)
R0 <= R0 - x"00000001";
curstate <= mailbox_read_29_15_0;
WHEN mailbox_read_29_15_0 =>
-- write R1 12 R0 (113)
thrd2intrfc_address <= R1 + x"0000000C";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_16_0;
WHEN mailbox_read_29_16_0 =>
-- call hthread_mutex_unlock R2 @returnVal @none (114)
-- Push argument 0
thrd2intrfc_value <= R2;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_16_1;
WHEN mailbox_read_29_16_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= x"0000"&mailbox_read_29_16_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_read_29_16_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_read_29_17_0;
WHEN mailbox_read_29_17_0 =>
-- arith3: @add R0 R1 32 (0)
R0 <= R1 + x"00000020";
curstate <= mailbox_read_29_18_0;
WHEN mailbox_read_29_18_0 =>
-- call hthread_cond_signal R0 @returnVal @none (116)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_29_18_1;
WHEN mailbox_read_29_18_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000024";
params_mem <= stack_mem + x"00000014";
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= x"0000"&mailbox_read_29_18_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN mailbox_read_29_18_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000024";
params_mem <= stack_mem - x"00000014";
T1 <= intrfc2thrd_value;
curstate <= mailbox_read_29_19_0;
WHEN mailbox_read_29_19_0 =>
-- return R4 (117)
T1 <= R4;
curstate <= mailbox_read_restore_0;
WHEN mailbox_read_restore_0 =>
-- Restore register R0 from the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_restore_1;
WHEN mailbox_read_restore_1 =>
-- Restore register R1 from the stack.
R0 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_restore_2;
WHEN mailbox_read_restore_2 =>
-- Restore register R2 from the stack.
R1 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000008";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_restore_3;
WHEN mailbox_read_restore_3 =>
-- Restore register R3 from the stack.
R2 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"0000000C";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_restore_4;
WHEN mailbox_read_restore_4 =>
-- Restore register R4 from the stack.
R3 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000010";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= mailbox_read_end;
WHEN mailbox_read_end =>
-- Use the return opcode to jump back to the caller.
R4 <= intrfc2thrd_value;
thrd2intrfc_value <= T1;
thrd2intrfc_opcode <= OPCODE_RETURN;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
-- Begin of function sort8k_entry (from sort8k_no_globals.c.hif)
WHEN sort8k_entry_start =>
-- Declare the number of stack memory words needed for this function.
thrd2intrfc_value <= x"00000002";
thrd2intrfc_opcode <= OPCODE_DECLARE;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_save_0;
WHEN sort8k_entry_save_0 =>
-- Save register R0 on the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_save_1;
WHEN sort8k_entry_save_1 =>
-- Save register R1 on the stack.
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_value <= R1;
thrd2intrfc_opcode <= OPCODE_STORE;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_31_0_0;
WHEN sort8k_entry_31_0_0 =>
-- arith2: @readarg R0 0 (7)
thrd2intrfc_value <= x"00000000";
thrd2intrfc_opcode <= OPCODE_POP;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_31_0_1;
WHEN sort8k_entry_31_0_1 =>
-- Capture result of readarg.
R0 <= intrfc2thrd_value;
curstate <= sort8k_entry_31_1_0;
WHEN sort8k_entry_31_1_0 =>
-- arith2: @mov R1 R0 (37)
R1 <= R0;
curstate <= sort8k_entry_32_0_0;
WHEN sort8k_entry_32_0_0 =>
-- arith2: @mov R0 R1 (0)
R0 <= R1;
curstate <= sort8k_entry_32_1_0;
WHEN sort8k_entry_32_1_0 =>
-- call mailbox_read R0 @returnVal R0 (40)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_1_1;
WHEN sort8k_entry_32_1_1 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"00000018";
params_mem <= stack_mem + x"00000008";
thrd2intrfc_function <= mailbox_read_start;
thrd2intrfc_value <= x"0000"&sort8k_entry_32_1_2;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN sort8k_entry_32_1_2 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"00000018";
params_mem <= stack_mem - x"00000008";
R0 <= intrfc2thrd_value;
curstate <= sort8k_entry_32_2_0;
WHEN sort8k_entry_32_2_0 =>
-- call bubblesort R0 2048 @returnVal @none (43)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_2_1;
WHEN sort8k_entry_32_2_1 =>
-- Push argument 1
thrd2intrfc_value <= x"00000800";
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_2_2;
WHEN sort8k_entry_32_2_2 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"0000001C";
params_mem <= stack_mem + x"00000008";
thrd2intrfc_function <= bubblesort_start;
thrd2intrfc_value <= x"0000"&sort8k_entry_32_2_3;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN sort8k_entry_32_2_3 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"0000001C";
params_mem <= stack_mem - x"00000008";
T1 <= intrfc2thrd_value;
curstate <= sort8k_entry_32_3_0;
WHEN sort8k_entry_32_3_0 =>
-- arith3: @add R0 R1 36 (0)
R0 <= R1 + x"00000024";
curstate <= sort8k_entry_32_4_0;
WHEN sort8k_entry_32_4_0 =>
-- call mailbox_write R0 23 @returnVal @none (45)
-- Push argument 0
thrd2intrfc_value <= R0;
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_4_1;
WHEN sort8k_entry_32_4_1 =>
-- Push argument 1
thrd2intrfc_value <= x"00000017";
thrd2intrfc_opcode <= OPCODE_PUSH;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_32_4_2;
WHEN sort8k_entry_32_4_2 =>
-- Set the stack_mem/params_mem pointers for callee and
-- use the call opcode to actually jump to the callee.
stack_mem <= stack_mem + x"0000001C";
params_mem <= stack_mem + x"00000008";
thrd2intrfc_function <= mailbox_write_start;
thrd2intrfc_value <= x"0000"&sort8k_entry_32_4_3;
thrd2intrfc_opcode <= OPCODE_CALL;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
WHEN sort8k_entry_32_4_3 =>
-- Reset the stack/param pointers for caller and capture the return value.
stack_mem <= stack_mem - x"0000001C";
params_mem <= stack_mem - x"00000008";
T1 <= intrfc2thrd_value;
curstate <= sort8k_entry_32_5_0;
WHEN sort8k_entry_32_5_0 =>
-- goto HIFL0(32) (46)
curstate <= sort8k_entry_32_0_0;
WHEN sort8k_entry_33_0_0 =>
-- return @none (0)
T1 <= x"00000000";
curstate <= sort8k_entry_restore_0;
WHEN sort8k_entry_restore_0 =>
-- Restore register R0 from the stack.
thrd2intrfc_address <= stack_mem + x"00000000";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_restore_1;
WHEN sort8k_entry_restore_1 =>
-- Restore register R1 from the stack.
R0 <= intrfc2thrd_value;
thrd2intrfc_address <= stack_mem + x"00000004";
thrd2intrfc_opcode <= OPCODE_LOAD;
curstate <= WAIT_STATE;
returnstate <= sort8k_entry_end;
WHEN sort8k_entry_end =>
-- Use the return opcode to jump back to the caller.
R1 <= intrfc2thrd_value;
thrd2intrfc_value <= T1;
thrd2intrfc_opcode <= OPCODE_RETURN;
curstate <= WAIT_STATE;
returnstate <= FUNCTCALL_STATE;
--multiply quick function
--implements 32 bit multiply
--assumes return address in T1, operands in T2 and T3
WHEN MULT00 =>
T4 <= std_logic_vector(conv_signed(signed(b"00"&T2(16 to 31)) * signed(b"00"&T3(16 to 31)), 32));
returnVal <= std_logic_vector(conv_signed(signed(b"00"&T2(0 to 15)) * signed(b"00"&T3(16 to 31)), 32));
curstate <= MULT01;
WHEN MULT01 =>
T4 <= std_logic_vector(conv_signed(signed(b"00"&T2(16 to 31)) * signed(b"00"&T3(0 to 15)), 32));
returnVal <= T4 + (returnVal(16 to 31)&x"0000");
curstate <= MULT02;
WHEN MULT02 =>
returnVal <= (T4(16 to 31)&x"0000") + returnVal;
curstate <= T1(16 to 31);
-- DIVIDE QUICK FUNCTION
-- inputs
-- T2 - dividend
-- T3 - divisor
-- outputs
-- returnVal - quotient
-- T4 - remainder
-- tmps
-- T5 - tmp_divisor
-- T6 - counter
WHEN DIVIDE00 =>
if (T2 < x"00000000") then -- init quotient
returnVal <= -T2;
else
returnVal <= T2;
end if;
T4 <= x"00000000"; -- init remainder
if (T3 < x"00000000") then -- init tmp_divisor
T5 <= -T3;
else
T5 <= T3;
end if;
T6 <= x"00000000"; -- init counter
curstate <= DIVIDE01;
WHEN DIVIDE01 =>
-- BEGIN LOOP
T6 <= T6 + x"00000001"; -- increment counter
T4 <= T4(1 to 31)&returnVal(0); -- remainder = remainder(1 to 31)"ient(0)
returnVal <= returnVal(1 to 31)&'0'; -- shift quotient left
curstate <= DIVIDE02;
WHEN DIVIDE02 =>
-- if the remainder is greater than tmp_divisor
if (T4 >= T5) then
returnVal(31) <= '1'; -- set lsb of quotient
T4 <= T4 - T5; -- subtract tmp_divisor from remainder
end if;
if (T6 < x"00000020") then -- check loop bound
curstate <= DIVIDE01; -- GO TO NEXT ITERATION
else
curstate <= DIVIDE03; -- LOOP IS DONE
end if;
WHEN DIVIDE03 =>
-- LOOP IS DONE
-- THE FOLLOWING STATES HANDLE THE SIGNED ASPECT
-- if dividend < 0
if (T2 < x"00000000") then
T4 <= -T4; -- remainder = -remainder
curstate <= DIVIDE04;
else
curstate <= DIVIDE05;
end if;
WHEN DIVIDE04 =>
if (T3 > x"00000000") then
returnVal <= -returnVal;
end if;
curstate <= T1(16 to 31); -- return to caller
WHEN DIVIDE05 =>
if (T3 < x"00000000") then
returnVal <= -returnVal; -- negate the quotient
end if;
curstate <= T1(16 to 31); -- return to caller
-- Other states
WHEN WAIT_STATE =>
curstate <= returnstate;
WHEN FUNCTCALL_STATE => -- give the HWTI control over the next state
curstate <= intrfc2thrd_function;
WHEN others => --this case should never be reached
curstate <= START_STATE;
END CASE;
END IF;
END IF;
END PROCESS;
END IMP;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:49:45 06/05/2016
-- Design Name:
-- Module Name: RegistrosAbajo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RegistrosAbajo is
port(
alu_sal : in std_logic_vector(7 downto 0);
clk : in std_logic;
control: in STD_LOGIC_VECTOR(24 DOWNTO 0);
senal_rst : in STD_LOGIC;
ir_sal: out STD_LOGIC_VECTOR(7 downto 0);
mbr_sal: out STD_LOGIC_VECTOR(7 DOWNTO 0);
bus_datos_out : in std_logic_vector(7 downto 0)
);
end RegistrosAbajo;
architecture Behavioral of RegistrosAbajo is
component Register8
port (
d : in STD_LOGIC_VECTOR(7 downto 0); --Input.
load, clr, clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(7 downto 0));
end component;
component Mux2to1_8bit
port(A, B : in std_logic_vector(7 downto 0);
sel : in std_logic;
S : out std_logic_vector(7 downto 0));
end component;
SIGNAL mux_mbr_sal : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL mux_ir_sal: STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
mbr: Register8 port map(mux_mbr_sal, control(15), '0', clk, mbr_sal);
muxmbr: Mux2to1_8bit port map(bus_datos_out, alu_sal, control(4), mux_mbr_sal);
ir: Register8 port map(mux_ir_sal, control(14), '0', clk, ir_sal);
irmux: Mux2to1_8bit port map(bus_datos_out, "10011100", senal_rst, mux_ir_sal);
end Behavioral;
|
-- $Id: pdp11_sys70.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_sys70 - syn
-- Description: pdp11: 11/70 system - single core +rbus,debug,cache
--
-- Dependencies: w11a/pdp11_core_rbus
-- w11a/pdp11_core
-- w11a/pdp11_cache
-- w11a/pdp11_mem70
-- ibus/ibd_ibmon
-- ibus/ibd_ibtst
-- ibus/ib_sres_or_4
-- w11a/pdp11_dmscnt
-- w11a/pdp11_dmcmon
-- w11a/pdp11_dmhpbt
-- w11a/pdp11_dmpcnt
-- rbus/rb_sres_or_4
-- rbus/rb_sres_or_2
-- w11a/pdp11_tmu_sb [sim only]
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.33-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-06-02 1159 1.3.3 use rbaddr_ constants
-- 2019-03-02 1116 1.3.2 add RESET_SYS; fix pdp11_mem70 reset
-- 2019-02-16 1112 1.3.1 add ibd_ibtst
-- 2018-10-13 1055 1.3 drop ITIMER,DM_STAT_DP out ports, use DM_STAT_EXP
-- add PERFEXT in port
-- 2018-10-06 1053 1.2.3 drop DM_STAT_SY; add DM_STAT_CA; use _SE.pcload
-- 2018-09-29 1051 1.2.2 add pdp11_dmpcnt
-- 2017-04-22 884 1.2.1 pdp11_dmcmon: use SNUM and AWIDTH generics
-- 2016-03-22 750 1.2 pdp11_cache now configurable size
-- 2015-11-01 712 1.1.4 use sbcntl_sbf_tmu
-- 2015-07-19 702 1.1.3 use DM_STAT_SE
-- 2015-07-04 697 1.1.2 change DM_STAT_SY setup; add dmcmon, dmhbpt;
-- 2015-06-26 695 1.1.1 add pdp11_dmscnt support
-- 2015-05-09 677 1.1 start/stop/suspend overhaul; reset overhaul
-- 2015-05-01 672 1.0 Initial version (extracted from sys_w11a_*)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.pdp11.all;
use work.iblib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity pdp11_sys70 is -- 11/70 system 1 core +rbus,debug,cache
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus request (slave)
RB_SRES : out rb_sres_type; -- rbus response
RB_STAT : out slv4; -- rbus status flags
RB_LAM_CPU : out slbit; -- rbus lam (cpu)
GRESET : out slbit; -- general reset (from rbus)
CRESET : out slbit; -- cpu reset (from cp)
BRESET : out slbit; -- bus reset (from cp or cpu)
CP_STAT : out cp_stat_type; -- console port status
EI_PRI : in slv3; -- external interrupt priority
EI_VECT : in slv9_2; -- external interrupt vector
EI_ACKM : out slbit; -- external interrupt acknowledge
PERFEXT : in slv8; -- cpu external perf counter signals
IB_MREQ : out ib_mreq_type; -- ibus request (master)
IB_SRES : in ib_sres_type; -- ibus response
MEM_REQ : out slbit; -- memory: request
MEM_WE : out slbit; -- memory: write enable
MEM_BUSY : in slbit; -- memory: controller busy
MEM_ACK_R : in slbit; -- memory: acknowledge read
MEM_ADDR : out slv20; -- memory: address
MEM_BE : out slv4; -- memory: byte enable
MEM_DI : out slv32; -- memory: data in (memory view)
MEM_DO : in slv32; -- memory: data out (memory view)
DM_STAT_EXP : out dm_stat_exp_type -- debug and monitor - sys70 exports
);
end pdp11_sys70;
architecture syn of pdp11_sys70 is
signal RB_SRES_CORE : rb_sres_type := rb_sres_init;
signal RB_SRES_DMSCNT : rb_sres_type := rb_sres_init;
signal RB_SRES_DMPCNT : rb_sres_type := rb_sres_init;
signal RB_SRES_DMHBPT : rb_sres_type := rb_sres_init;
signal RB_SRES_DMCMON : rb_sres_type := rb_sres_init;
signal RB_SRES_DM : rb_sres_type := rb_sres_init;
signal RB_SRES_L : rb_sres_type := rb_sres_init;
signal CP_CNTL : cp_cntl_type := cp_cntl_init;
signal CP_ADDR : cp_addr_type := cp_addr_init;
signal CP_DIN : slv16 := (others=>'0');
signal CP_STAT_L : cp_stat_type := cp_stat_init;
signal CP_DOUT : slv16 := (others=>'0');
signal EI_ACKM_L : slbit := '0';
signal EM_MREQ : em_mreq_type := em_mreq_init;
signal EM_SRES : em_sres_type := em_sres_init;
signal GRESET_L : slbit := '0'; -- general reset (from rbus init)
signal CRESET_L : slbit := '0'; -- cpu reset (from -creset command)
signal BRESET_L : slbit := '0'; -- bus reset (RESET inst or -breset)
signal RESET_SYS : slbit := '0'; -- or of RESET (port) and GRESET (rbus)
signal HM_ENA : slbit := '0';
signal MEM70_FMISS : slbit := '0';
signal CACHE_FMISS : slbit := '0';
signal HBPT : slbit := '0';
signal DM_STAT_SE : dm_stat_se_type := dm_stat_se_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal DM_STAT_VM : dm_stat_vm_type := dm_stat_vm_init;
signal DM_STAT_CO : dm_stat_co_type := dm_stat_co_init;
signal DM_STAT_CA : dm_stat_ca_type := dm_stat_ca_init;
signal IB_MREQ_M : ib_mreq_type := ib_mreq_init;
signal IB_SRES_M : ib_sres_type := ib_sres_init;
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
signal IB_SRES_IBMON : ib_sres_type := ib_sres_init;
signal IB_SRES_IBTST : ib_sres_type := ib_sres_init;
constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx
constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx
begin
RB2CP : pdp11_core_rbus
generic map (
RB_ADDR_CORE => rbaddr_core0,
RB_ADDR_IBUS => rbaddr_ibus0)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CORE,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_CPU,
GRESET => GRESET_L,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT_L,
CP_DOUT => CP_DOUT
);
RESET_SYS <= RESET or GRESET_L; -- use as reset of w11 sub-system
W11A : pdp11_core
port map (
CLK => CLK,
RESET => RESET_SYS,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
CP_DIN => CP_DIN,
CP_STAT => CP_STAT_L,
CP_DOUT => CP_DOUT,
ESUSP_O => open,
ESUSP_I => '0',
HBPT => HBPT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM_L,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
CRESET => CRESET_L,
BRESET => BRESET_L,
IB_MREQ_M => IB_MREQ_M,
IB_SRES_M => IB_SRES_M,
DM_STAT_SE => DM_STAT_SE,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
CACHE: pdp11_cache
generic map (
TWIDTH => sys_conf_cache_twidth)
port map (
CLK => CLK,
GRESET => RESET_SYS,
EM_MREQ => EM_MREQ,
EM_SRES => EM_SRES,
FMISS => CACHE_FMISS,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_CA => DM_STAT_CA
);
MEM70: pdp11_mem70
port map (
CLK => CLK,
CRESET => CRESET_L,
HM_ENA => HM_ENA,
HM_VAL => DM_STAT_CA.rdhit,
CACHE_FMISS => MEM70_FMISS,
IB_MREQ => IB_MREQ_M,
IB_SRES => IB_SRES_MEM70
);
HM_ENA <= EM_SRES.ack_r or EM_SRES.ack_w;
CACHE_FMISS <= MEM70_FMISS or sys_conf_cache_fmiss;
IBMON : if sys_conf_ibmon_awidth > 0 generate
begin
I0 : ibd_ibmon
generic map (
IB_ADDR => slv(to_unsigned(8#160000#,16)),
AWIDTH => sys_conf_ibmon_awidth)
port map (
CLK => CLK,
RESET => RESET_SYS,
IB_MREQ => IB_MREQ_M,
IB_SRES => IB_SRES_IBMON,
IB_SRES_SUM => DM_STAT_VM.ibsres
);
end generate IBMON;
IBTST : if sys_conf_ibtst generate
signal RESET_IBTST : slbit := '0';
begin
RESET_IBTST <= RESET_SYS or BRESET_L;
I0 : ibd_ibtst
generic map (
IB_ADDR => slv(to_unsigned(8#170000#,16)))
port map (
CLK => CLK,
RESET => RESET_IBTST,
IB_MREQ => IB_MREQ_M,
IB_SRES => IB_SRES_IBTST
);
end generate IBTST;
IB_SRES_OR : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_MEM70,
IB_SRES_2 => IB_SRES,
IB_SRES_3 => IB_SRES_IBMON,
IB_SRES_4 => IB_SRES_IBTST,
IB_SRES_OR => IB_SRES_M
);
DMSCNT : if sys_conf_dmscnt generate
begin
I0: pdp11_dmscnt
generic map (
RB_ADDR => rbaddr_dmscnt_off)
port map (
CLK => CLK,
RESET => RESET_SYS,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_DMSCNT,
DM_STAT_SE => DM_STAT_SE,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_CO => DM_STAT_CO
);
end generate DMSCNT;
DMCMON : if sys_conf_dmcmon_awidth > 0 generate
begin
I0: pdp11_dmcmon
generic map (
RB_ADDR => rbaddr_dmcmon_off,
AWIDTH => sys_conf_dmcmon_awidth,
SNUM => sys_conf_dmscnt)
port map (
CLK => CLK,
RESET => RESET_SYS,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_DMCMON,
DM_STAT_SE => DM_STAT_SE,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO
);
end generate DMCMON;
DMHBPT : if sys_conf_dmhbpt_nunit > 0 generate
begin
I0: pdp11_dmhbpt
generic map (
RB_ADDR => rbaddr_dmhbpt_off,
NUNIT => sys_conf_dmhbpt_nunit)
port map (
CLK => CLK,
RESET => RESET_SYS,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_DMHBPT,
DM_STAT_SE => DM_STAT_SE,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
HBPT => HBPT
);
end generate DMHBPT;
DMPCNT : if sys_conf_dmpcnt generate
signal PERFSIG : slv32 := (others=>'0');
begin
proc_sig: process (CP_STAT_L, DM_STAT_SE, DM_STAT_DP, DM_STAT_DP.psw,
DM_STAT_CA, RB_MREQ, RB_SRES_L, EI_ACKM_L,
DM_STAT_VM.ibmreq, DM_STAT_VM.ibsres, PERFEXT)
variable isig : slv32 := (others=>'0');
begin
isig := (others=>'0');
if DM_STAT_SE.cpbusy = '1' then
isig(0) := '1'; -- cpu_cpbusy
elsif CP_STAT_L.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
when c_psw_kmode =>
if CP_STAT_L.cpuwait = '1' then
isig(3) := '1'; -- cpu_km_wait
elsif unsigned(DM_STAT_DP.psw.pri) = 0 then
isig(2) := '1'; -- cpu_km_pri0
else
isig(1) := '1'; -- cpu_km_prix
end if;
when c_psw_smode =>
isig(4) := '1'; -- cpu_sm
when c_psw_umode =>
isig(5) := '1'; -- cpu_um
when others => null;
end case;
end if;
isig(6) := DM_STAT_SE.idec; -- cpu_idec
isig(7) := DM_STAT_SE.pcload; -- cpu_pcload
isig(8) := DM_STAT_SE.vfetch; -- cpu_vfetch
isig(9) := EI_ACKM_L; -- cpu_irupt (not counting PIRQ!)
isig(10) := DM_STAT_CA.rd; -- ca_rd
isig(11) := DM_STAT_CA.wr; -- ca_wr
isig(12) := DM_STAT_CA.rdhit; -- ca_rdhit
isig(13) := DM_STAT_CA.wrhit; -- ca_wrhit
isig(14) := DM_STAT_CA.rdmem; -- ca_rdmem
isig(15) := DM_STAT_CA.wrmem; -- ca_wrmem
isig(16) := DM_STAT_CA.rdwait; -- ca_rdwait
isig(17) := DM_STAT_CA.wrwait; -- ca_wrwait
if DM_STAT_VM.ibmreq.aval='1' then
if DM_STAT_VM. ibsres.busy='0' then
isig(18) := DM_STAT_VM.ibmreq.re; -- ib_rd
isig(19) := DM_STAT_VM.ibmreq.we; -- ib_wr
else
isig(20) := DM_STAT_VM.ibmreq.re or DM_STAT_VM.ibmreq.we; -- ib_busy
end if;
end if;
-- a hack too, for 1 core systems is addr(15)='0' when CPU addressed
if RB_MREQ.aval='1' and RB_MREQ.addr(15)='0' then
if RB_SRES_L.busy='0' then
isig(21) := RB_MREQ.re; -- rb_rd
isig(22) := RB_MREQ.we; -- rb_wr
else
isig(23) := RB_MREQ.re or RB_MREQ.we; -- rb_busy
end if;
end if;
isig(24) := PERFEXT(0); -- ext_rdrhit
isig(25) := PERFEXT(1); -- ext_wrrhit
isig(26) := PERFEXT(2); -- ext_wrflush
isig(27) := PERFEXT(3); -- ext_rlrxact
isig(28) := PERFEXT(4); -- ext_rlrxback
isig(29) := PERFEXT(5); -- ext_rltxact
isig(30) := PERFEXT(6); -- ext_rltxback
isig(31) := PERFEXT(7); -- ext_usec
PERFSIG <= isig;
end process proc_sig;
I0: pdp11_dmpcnt
generic map (
RB_ADDR => rbaddr_dmpcnt_off, -- rbus address
VERS => slv(to_unsigned(1, 8)), -- counter layout version
-- 33222222222211111111110000000000
-- 10987654321098765432109876543210
CENA => "11111111111111111111111111111111") -- counter enables
port map (
CLK => CLK,
RESET => RESET_SYS,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_DMPCNT,
PERFSIG => PERFSIG
);
end generate DMPCNT;
RB_SRES_DMOR : rb_sres_or_4
port map (
RB_SRES_1 => RB_SRES_DMSCNT,
RB_SRES_2 => RB_SRES_DMPCNT,
RB_SRES_3 => RB_SRES_DMHBPT,
RB_SRES_4 => RB_SRES_DMCMON,
RB_SRES_OR => RB_SRES_DM
);
RB_SRES_OR : rb_sres_or_2
port map (
RB_SRES_1 => RB_SRES_CORE,
RB_SRES_2 => RB_SRES_DM,
RB_SRES_OR => RB_SRES_L
);
RB_SRES <= RB_SRES_L; -- setup output signals
IB_MREQ <= IB_MREQ_M;
GRESET <= GRESET_L;
CRESET <= CRESET_L;
BRESET <= BRESET_L;
CP_STAT <= CP_STAT_L;
EI_ACKM <= EI_ACKM_L;
DM_STAT_EXP.dp_psw <= DM_STAT_DP.psw;
DM_STAT_EXP.dp_pc <= DM_STAT_DP.pc;
DM_STAT_EXP.dp_dsrc <= DM_STAT_DP.dsrc;
DM_STAT_EXP.se_idec <= DM_STAT_SE.idec;
DM_STAT_EXP.se_itimer <= DM_STAT_SE.itimer;
-- synthesis translate_off
TMU : pdp11_tmu_sb
generic map (
ENAPIN => sbcntl_sbf_tmu)
port map (
CLK => CLK,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_CA => DM_STAT_CA
);
-- synthesis translate_on
end syn;
|
entity hintbug is
end entity;
architecture test of hintbug is
function func(x : bit) return bit_vector is
begin
return x & '1';
end function;
begin
process is
variable v : bit_vector(1 downto 0);
variable x : bit := '1';
begin
v := func(x); -- Will create an unused storage hint
assert v = x & '0'; -- Will incorrectly use above hint
wait;
end process;
end architecture;
|
---------------------------------------------------------------------
---- clock_divide_both.vhdl ----
---- ----
---- DOES NOT GIVE GOOD SYNTHESIS RESULTS: DUTYCYCLE != 50%
---- Divides ck_in by factor of divider.
----
---------------------------------------------------------------------
---- This program is free software: you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software ----
---- Foundation, either version 3 of the License, or (at your ----
---- option) any later version. ----
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_divide_both is
port(ck_in: in STD_LOGIC; divider: in integer; ck_out: out STD_LOGIC);
end clock_divide_both;
architecture Behavioral of clock_divide_both is
signal counter: integer := 0;
signal clk_out: STD_LOGIC := '0';
begin
process (ck_in)
begin
if rising_edge(ck_in) then
if counter = divider - 1 then
counter <= 0;
clk_out <= not clk_out;
else
counter <= counter + 1;
end if;
end if;
if falling_edge(ck_in) then
if counter = divider - 1 then
counter <= 0;
clk_out <= not clk_out;
else
counter <= counter + 1;
end if;
end if;
end process;
ck_out <= clk_out;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.BusMasters.all;
entity MAX6682_tb is
end MAX6682_tb;
architecture behavior of MAX6682_tb is
component MAX6682
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
MAX6682CS_n_o : out std_logic;
SPI_Data_i : in std_logic_vector(7 downto 0);
SPI_Write_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_Data_o : out std_logic_vector(7 downto 0);
SPI_FIFOFull_i : in std_logic;
SPI_FIFOEmpty_i : in std_logic;
SPI_Transmission_i : in std_logic;
PeriodCounterPresetH_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetL_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
SPI_CPOL_o : out std_logic;
SPI_CPHA_o : out std_logic;
SPI_LSBFE_o : out std_logic
);
end component;
component MAX6682_Model
port (
ChipSelect_n_i : in std_logic;
SCLK_i : in std_logic;
SO_o : out std_logic;
Value_i : in std_logic_vector(10 downto 0)
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal Enable_i : std_logic;
signal CpuIntr_o : std_logic;
signal MAX6682CS_n_o : std_logic;
signal SPI_Data_i : std_logic_vector(7 downto 0);
signal SPI_Write_o : std_logic;
signal SPI_ReadNext_o : std_logic;
signal SPI_Data_o : std_logic_vector(7 downto 0);
signal SPI_FIFOFull_i : std_logic;
signal SPI_FIFOEmpty_i : std_logic;
signal SPI_Transmission_i : std_logic;
signal PeriodCounterPreset_i : std_logic_vector(31 downto 0);
signal SensorValue_o : std_logic_vector(15 downto 0);
signal Threshold_i : std_logic_vector(15 downto 0);
signal SPI_SPPR_SPR : std_logic_vector(7 downto 0);
constant ClkPeriode : time := 10 ns;
signal SPI_CPOL_o : std_logic;
signal SPI_CPHA_o : std_logic;
signal SPI_LSBFE_o : std_logic;
constant SPPRWidth : integer := 4;
constant SPRWidth : integer := 4;
constant DataWidth : integer := 8;
constant SPIFIFOReadWidth : integer := 4;
constant SPIFIFOWriteWidth : integer := 4;
-- SPI signals
signal SPI_SCK_s : std_logic;
signal SPI_MOSI_s : std_logic;
signal SPI_MISO_s : std_logic;
signal SPI_ScanEnable_s : std_logic;
signal SPI_ScanClk_s : std_logic;
signal SPI_ScanDataIn_s : std_logic;
signal SPI_ScanDataOut_s : std_logic;
-- MAX6682 simulation
signal MAX6682Value : unsigned(10 downto 0);
begin
DUT: MAX6682
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Enable_i => Enable_i,
CpuIntr_o => CpuIntr_o,
MAX6682CS_n_o => MAX6682CS_n_o,
SPI_Data_i => SPI_Data_i,
SPI_Write_o => SPI_Write_o,
SPI_ReadNext_o => SPI_ReadNext_o,
SPI_Data_o => SPI_Data_o,
SPI_FIFOFull_i => SPI_FIFOFull_i,
SPI_FIFOEmpty_i => SPI_FIFOEmpty_i,
SPI_Transmission_i => SPI_Transmission_i,
PeriodCounterPresetH_i => PeriodCounterPreset_i(31 downto 16),
PeriodCounterPresetL_i => PeriodCounterPreset_i(15 downto 0),
SensorValue_o => SensorValue_o,
Threshold_i => Threshold_i,
SPI_CPOL_o => SPI_CPOL_o,
SPI_CPHA_o => SPI_CPHA_o,
SPI_LSBFE_o => SPI_LSBFE_o
);
spi_master_1: spi_master
generic map (
DataWidth => DataWidth,
SPPRWidth => SPPRWidth,
SPRWidth => SPRWidth,
FIFOReadWidth => SPIFIFOReadWidth,
FIFOWriteWidth => SPIFIFOWriteWidth
)
port map (
Reset_n => Reset_n_i,
Clk => Clk_i,
-- IO
SCK_o => SPI_SCK_s,
MOSI_o => SPI_MOSI_s,
MISO_i => SPI_MISO_s,
-- control signals
CPOL_i => SPI_CPOL_o,
CPHA_i => SPI_CPHA_o,
LSBFE_i => SPI_LSBFE_o,
SPPR_i => SPI_SPPR_SPR(7 downto 4),
SPR_i => SPI_SPPR_SPR(3 downto 0),
Transmission_o => SPI_Transmission_i,
Write_i => SPI_Write_o,
ReadNext_i => SPI_ReadNext_o,
Data_i => SPI_Data_o,
Data_o => SPI_Data_i,
FIFOFull_o => SPI_FIFOFull_i,
FIFOEmpty_o => SPI_FIFOEmpty_i,
ScanEnable_i => SPI_ScanEnable_s,
ScanClk_i => SPI_ScanClk_s,
ScanDataIn_i => SPI_ScanDataIn_s,
ScanDataOut_o => SPI_ScanDataOut_s
);
MAX6682_1: MAX6682_Model
port map (
ChipSelect_n_i => MAX6682CS_n_o,
SCLK_i => SPI_SCK_s,
SO_o => SPI_MISO_s,
Value_i => std_logic_vector(MAX6682Value));
-- constant value for reconfig signal
SPI_SPPR_SPR <= "00000000";
-- SPI MISO Pull-down
SPI_MISO_s <= 'L';
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
Enable_i <= '0';
PeriodCounterPreset_i <= "00000000000000000000000000001010";
Threshold_i <= "0000000000001010";
MAX6682Value <= (others => '0');
-- Check constant values of dynamic signals coming out of the application modules
wait for 0.1*ClkPeriode;
assert SPI_CPOL_o = '0'
report "Dynamic signal SPI_CPOL should have constant value '0'" severity failure;
assert SPI_CPHA_o = '0'
report "Dynamic signal SPI_CPHA should have constant value '0'" severity failure;
assert SPI_LSBFE_o = '0'
report "Dynamic signal SPI_LSBFE should have constant value '0'" severity failure;
wait for 2.2*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
-- enable SensorFSM
Enable_i <= '1';
wait for 9*ClkPeriode; -- 9 cycles
assert MAX6682CS_n_o = '1' report "CS_n should be '1'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert MAX6682CS_n_o = '0' report "CS_n should be '0' after 10 cycles" severity error;
wait for 35*ClkPeriode; -- 35 cycles
assert MAX6682CS_n_o = '0' report "CS_n should still be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(0,16)) report "SensorValue_o should be 0" severity error;
-- new sensor value: 38 -> large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(38,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
wait for 1*ClkPeriode; -- 1 more cycle if notification happened
-- new sensor value: 30 -> small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(30,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
-- new sensor value: 28 -> small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(28,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
-- new sensor value: 27 -> large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
MAX6682Value <= to_unsigned(27,11);
wait for 43*ClkPeriode; -- 43 cycle
assert MAX6682CS_n_o = '1' report "CS_n should be '1' after 16 SPI bits" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(27,16)) report "SensorValue_o should be 27" severity error;
wait for 1*ClkPeriode; -- 1 more cycle if notification happened
assert CpuIntr_o = '0' report "CpuIntr should be '0'" severity error;
wait for 10*ClkPeriode;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
-- use VHDL implementation of the MAX6682 application
configuration MAX6682_tb_vhdl_cfg of MAX6682_tb is
for behavior
for DUT : MAX6682
use entity work.MAX6682(rtl);
end for;
end for;
end MAX6682_tb_vhdl_cfg;
-- use Verilog implementation of the MAX6682 application
configuration MAX6682_tb_verilog_cfg of MAX6682_tb is
for behavior
for DUT : MAX6682
-- doesn't work???
-- use entity work.MAX6682(verilog);
use configuration work.MAX6682Verilog;
end for;
end for;
end MAX6682_tb_verilog_cfg;
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 18:48:32 03/05/2013
-- Design Name:
-- Module Name: rgbLed - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents the controller for the RGB Leds. It uses three PWM components
-- to generate the sweeping RGB colors and four debouncers for the incoming buttons
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity RgbLed is
port(
clk_i : in std_logic;
rstn_i : in std_logic;
-- Command button signals
btnl_i : in std_logic;
btnc_i : in std_logic;
btnr_i : in std_logic;
btnd_i : in std_logic;
-- LD16 PWM output signals
pwm1_red_o : out std_logic;
pwm1_green_o : out std_logic;
pwm1_blue_o : out std_logic;
-- LD17 PWM output signals
pwm2_red_o : out std_logic;
pwm2_green_o : out std_logic;
pwm2_blue_o : out std_logic;
-- R, G and B signals connecting to the VGA controller
-- to be displayed on the screen
RED_OUT : out std_logic_vector(7 downto 0);
GREEN_OUT : out std_logic_vector(7 downto 0);
BLUE_OUT : out std_logic_vector(7 downto 0)
);
end RgbLed;
architecture Behavioral of RgbLed is
----------------------------------------------------------------------------------
-- Component Declarations
----------------------------------------------------------------------------------
-- Pwm generator
component Pwm is
port(
clk_i : in std_logic;
data_i : in std_logic_vector(7 downto 0);
pwm_o : out std_logic);
end component;
-- Debouncer for the buttons
component Dbncr is
generic(
NR_OF_CLKS : integer := 4095);
port(
clk_i : in std_logic;
sig_i : in std_logic;
pls_o : out std_logic);
end component;
-- Clock divider, will determine the frequency at which
-- the color components will increase/decrease
-- 100MHz/10000000 = 10Hz
constant CLK_DIV : integer := 10000000;
--Clock divider counter and signal
signal clkCnt : integer := 0;
signal slowClk : std_logic;
-- colorCnt will determine the PWM values to be sent to the RGB Led color components
-- colorCnt(9 downto 5) will be increasing and colorCnt(4 downto 0) will be decreasing
signal colorCnt : std_logic_vector(9 downto 0) := "0000011111";
-- specCnt determines which color components are swept
-- 0: decrease Red, increase Green
-- 1: decrease Green, increase Blue
-- 2: decrease Blue, increase Red
signal specCnt : integer range 0 to 2 := 0;
-- Red, Green and Blue data signals
signal red, green, blue : std_logic_vector(7 downto 0);
-- PWM Red, Green and BLue signals going to the RGB Leds
signal pwm_red, pwm_green, pwm_blue : std_logic;
-- Debounced button signals
signal btnl, btnc, btnr, btnd : std_logic;
-- Signals that turn off LD16 and/or LD17
signal fLed2Off, fLed1Off : std_logic;
-- State machine states definition
type state_type is (stIdle, -- Both Leds are on, show sweeping color
stRed, -- Show Red color only
stGreen, -- Show Green color only
stBlue, -- Show Blue color only
stLed2Off, -- Turn off Ld17
stLed1Off, -- Turn off Ld16
stLed12Off -- Turn off both Leds
);
-- State machine signal definitions
signal state, nState : state_type;
begin
-- Assign outputs
pwm1_red_o <= pwm_red when fLed1Off = '0' else '0';
pwm1_green_o <= pwm_green when fLed1Off = '0' else '0';
pwm1_blue_o <= pwm_blue when fLed1Off = '0' else '0';
pwm2_red_o <= pwm_red when fLed2Off = '0' else '0';
pwm2_green_o <= pwm_green when fLed2Off = '0' else '0';
pwm2_blue_o <= pwm_blue when fLed2Off = '0' else '0';
RegisterOutputs: process(clk_i, red, green, blue)
begin
if rising_edge(clk_i) then
RED_OUT <= red;
GREEN_OUT <= green;
BLUE_OUT <= blue;
end if;
end process RegisterOutputs;
-- PWM generators:
PwmRed: Pwm
port map(
clk_i => clk_i,
data_i => red,
pwm_o => pwm_red);
PwmGreen: Pwm
port map(
clk_i => clk_i,
data_i => green,
pwm_o => pwm_green);
PwmBlue: Pwm
port map(
clk_i => clk_i,
data_i => blue,
pwm_o => pwm_blue);
-- Button Debouncers:
Btn1: Dbncr
generic map(
NR_OF_CLKS => 4095)
port map(
clk_i => clk_i,
sig_i => btnl_i,
pls_o => btnl);
Btn2: Dbncr
generic map(
NR_OF_CLKS => 4095)
port map(
clk_i => clk_i,
sig_i => btnc_i,
pls_o => btnc);
Btn3: Dbncr
generic map(
NR_OF_CLKS => 4095)
port map(
clk_i => clk_i,
sig_i => btnr_i,
pls_o => btnr);
Btn4: Dbncr
generic map(
NR_OF_CLKS => 4095)
port map(
clk_i => clk_i,
sig_i => btnd_i,
pls_o => btnd);
-- State machine registerred process
SYNC_PROC: process(clk_i)
begin
if rising_edge(clk_i) then
if rstn_i = '0' then
state <= stIdle;
else
state <= nState;
end if;
end if;
end process;
-- Next State decode process
NEXT_STATE_DECODE: process(state, btnl, btnc, btnr, btnd)
begin
nState <= state; -- Default: Stay in the current state
case state is
when stIdle => -- show sweeping color
if btnl = '1' then
nState <= stRed;
elsif btnc = '1' then
nState <= stGreen;
elsif btnr = '1' then
nState <= stBlue;
elsif btnd = '1' then
nState <= stLed2Off;
end if;
when stRed => -- show red only
if btnc = '1' then
nState <= stGreen;
elsif btnr = '1' then
nState <= stBlue;
elsif btnd = '1' then
nState <= stIdle;
end if;
when stGreen => -- show green only
if btnl = '1' then
nState <= stRed;
elsif btnr = '1' then
nState <= stBlue;
elsif btnd = '1' then
nState <= stIdle;
end if;
when stBlue => -- show blue only
if btnl = '1' then
nState <= stRed;
elsif btnc = '1' then
nState <= stGreen;
elsif btnd = '1' then
nState <= stIdle;
end if;
when stLed2Off => -- turn off Ld17
if btnd = '1' then
nState <= stLed1Off;
end if;
when stLed1Off => -- turn off Ld16
if btnd = '1' then
nState <= stLed12Off;
end if;
when stLed12Off => -- turn off both Ld16 and Ld17
if btnd = '1' then
nState <= stIdle;
end if;
when others => nState <= stIdle;
end case;
end process;
-- clock prescaler
Prescaller: process(clk_i)
begin
if rising_edge(clk_i) then
if rstn_i = '0' then
clkCnt <= 0;
elsif clkCnt = CLK_DIV-1 then
clkCnt <= 0;
else
clkCnt <= clkCnt + 1;
end if;
end if;
end process Prescaller;
slowClk <= '1' when clkCnt = CLK_DIV-1 else '0';
process(clk_i)
begin
if rising_edge(clk_i) then
if rstn_i = '0' then
colorCnt <= b"0000011111";
specCnt <= 0;
elsif slowClk = '1' then
if colorCnt = b"1111000001" then -- at the end of the color sweeping,
colorCnt <= b"0000011111"; -- start over and change the colors which are swept
if specCnt = 2 then
specCnt <= 0;
else
specCnt <= specCnt + 1;
end if;
else -- colorCnt (9 downto 5) will be increasing
-- and colorCnt(4 downto 0) will be decreasing
colorCnt <= colorCnt + b"0000011111";
end if;
end if;
end if;
end process;
process(state, colorCnt, specCnt, btnl, btnc, btnr)
begin
if state = stRed then
red <= b"000" & b"11111";
green <= b"0000" & b"0000";
blue <= b"0000" & b"0000";
elsif state = stGreen then
red <= b"0000" & b"0000";
green <= b"000" & b"11111";
blue <= b"0000" & b"0000";
elsif state = stBlue then
red <= b"0000" & b"0000";
green <= b"0000" & b"0000";
blue <= b"000" & b"11111";
else
case specCnt is
when 0 =>
red <= b"000" & colorCnt(4 downto 0); -- Decrease Red, increase Green
green <= b"000" & colorCnt(9 downto 5);
blue <= b"0000" & b"0000";
when 1 =>
red <= b"0000" & b"0000";
green <= b"000" & colorCnt(4 downto 0); -- Decrease Green, increase Blue
blue <= b"000" & colorCnt(9 downto 5);
when 2 =>
red <= b"000" & colorCnt(9 downto 5); -- Decrease Blue, increase Red
green <= b"0000" & b"0000";
blue <= b"000" & colorCnt(4 downto 0);
when others =>
red <= b"0000" & b"0000";
green <= b"0000" & b"0000";
blue <= b"0000" & b"0000";
end case;
end if;
if state = stLed2Off then
fLed2Off <= '1';
fLed1Off <= '0';
elsif state = stLed1Off then
fLed2Off <= '0';
fLed1Off <= '1';
elsif state = stLed12Off then
fLed2Off <= '1';
fLed1Off <= '1';
else
fLed2Off <= '0';
fLed1Off <= '0';
end if;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad
-- File: toutpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: tri-state output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of toutpad is
signal oen : std_ulogic;
signal padx, gnd : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
u0 : unisim_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
u0 : apa3_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
igl2 : if (tech = igloo2) generate
u0 : igloo2_toutpad port map (pad, i, oen);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
atc : if (tech = atc18s) generate
u0 : atc18_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
atcrh : if (tech = atc18rha) generate
u0 : atc18rha_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
um : if (tech = umc) generate
u0 : umc_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
rhu : if (tech = rhumc) generate
u0 : rhumc_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
saed : if (tech = saed32) generate
u0 : saed32_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
rhs : if (tech = rhs65) generate
u0 : rhs65_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen, cfgi(0), cfgi(2), cfgi(1));
end generate;
dar : if (tech = dare) generate
u0 : dare_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
ihp : if (tech = ihp25) generate
u0 : ihp25_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
ihprh : if (tech = ihp25rh) generate
u0 : ihp25rh_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
rh18t : if (tech = rhlib18t) generate
u0 : rh_lib18t_iopad generic map (strength) port map (padx, i, oen, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
u0 : ut025crh_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
ut13 : if (tech = ut130) generate
u0 : ut130hbd_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
pere : if (tech = peregrine) generate
u0 : peregrine_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
nex : if (tech = easic90) generate
u0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen, cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10), cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
ut90nhbd : if (tech = ut90) generate
u0 : ut90nhbd_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen, cfgi(0));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000"
);
end;
architecture rtl of toutpadv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en, cfgi);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of toutpadvv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en(j), cfgi);
end generate;
end;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:56 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: tx_ll_datapath_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- TX_LL_DATAPATH
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- Description: This module pipelines the data path while handling the PAD
-- character placement and valid data flags.
--
-- This module supports 1 2-byte lane designs
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TX_LL_DATAPATH is
port (
-- LocalLink PDU Interface
TX_D : in std_logic_vector(0 to 15);
TX_REM : in std_logic;
TX_SRC_RDY_N : in std_logic;
TX_SOF_N : in std_logic;
TX_EOF_N : in std_logic;
-- Aurora Lane Interface
TX_PE_DATA_V : out std_logic;
GEN_PAD : out std_logic;
TX_PE_DATA : out std_logic_vector(0 to 15);
-- TX_LL Control Module Interface
HALT_C : in std_logic;
TX_DST_RDY_N : in std_logic;
-- System Interface
CHANNEL_UP : in std_logic;
USER_CLK : in std_logic
);
end TX_LL_DATAPATH;
architecture RTL of TX_LL_DATAPATH is
-- Parameter Declarations --
constant DLY : time := 1 ns;
-- External Register Declarations --
signal TX_PE_DATA_V_Buffer : std_logic;
signal GEN_PAD_Buffer : std_logic;
signal TX_PE_DATA_Buffer : std_logic_vector(0 to 15);
-- Internal Register Declarations --
signal in_frame_r : std_logic;
signal storage_r : std_logic_vector(0 to 15);
signal storage_v_r : std_logic;
signal storage_pad_r : std_logic;
signal tx_pe_data_r : std_logic_vector(0 to 15);
signal valid_c : std_logic;
signal tx_pe_data_v_r : std_logic;
signal gen_pad_c : std_logic;
signal gen_pad_r : std_logic;
-- Internal Wire Declarations --
signal ll_valid_c : std_logic;
signal in_frame_c : std_logic;
begin
TX_PE_DATA_V <= TX_PE_DATA_V_Buffer;
GEN_PAD <= GEN_PAD_Buffer;
TX_PE_DATA <= TX_PE_DATA_Buffer;
-- Main Body of Code --
-- LocalLink input is only valid when TX_SRC_RDY_N and TX_DST_RDY_N are both asserted
ll_valid_c <= not TX_SRC_RDY_N and not TX_DST_RDY_N;
-- Data must only be read if it is within a frame. If a frame will last multiple cycles
-- we assert in_frame_r as long as the frame is open.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
in_frame_r <= '0' after DLY;
elsif(ll_valid_c = '1') then
if( (TX_SOF_N = '0') and (TX_EOF_N = '1') ) then
in_frame_r <= '1' after DLY;
elsif( TX_EOF_N = '0') then
in_frame_r <= '0' after DLY;
end if;
end if;
end if;
end process;
in_frame_c <= ll_valid_c and (in_frame_r or not TX_SOF_N);
-- The data from the LocalLink interface must be delayed one cycle to
-- make room for the SCP code group in the channel.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (HALT_C = '0') then
storage_r <= TX_D after DLY;
end if;
end if;
end process;
-- This pipeline register aligns the data with the control path.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (HALT_C = '0') then
tx_pe_data_r <= storage_r after DLY;
end if;
end if;
end process;
-- We generate the valid_c signal based on the REM signal and the EOF signal.
process (TX_EOF_N, TX_REM)
begin
if (TX_EOF_N = '1') then
valid_c <= '1';
else
case TX_REM is
when '0' => valid_c <= '1';
when '1' => valid_c <= '1';
when others => valid_c <= '1';
end case;
end if;
end process;
-- If the word is valid, it is placed in the storage register and storage_v_r is
-- asserted to indicate the data is valid. Note that data is only moved to storage
-- if the PDU datapath is not halted, the data is valid and both TX_SRC_RDY_N and
-- TX_DST_RDY_N are asserted.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (HALT_C = '0') then
storage_v_r <= valid_c and in_frame_c after DLY;
end if;
end if;
end process;
-- Register the tx_pe_data_valid signal. All data is moved from the storage register
-- to the tx_pe_data register for transmission when the datapath is not halted. If the
-- storage register contains valid PDU data, the tx_pe_data register is marked as
-- containing valid PDU data
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (HALT_C = '0') then
tx_pe_data_v_r <= storage_v_r after DLY;
end if;
end if;
end process;
-- We generate the gen_pad_c signal based on the REM signal and the EOF signal.
process (TX_EOF_N, TX_REM)
begin
if (TX_EOF_N = '1') then
gen_pad_c <= '0';
else
case TX_REM is
when '0' => gen_pad_c <= '1';
when '1' => gen_pad_c <= '0';
when others => gen_pad_c <= '0';
end case;
end if;
end process;
-- Store padded data when padded and TX_SRC_RDY_N and TX_DST_RDY_N are both asserted.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (HALT_C = '0') then
storage_pad_r <= gen_pad_c and in_frame_c after DLY;
end if;
end if;
end process;
-- Register the gen_pad signal.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (HALT_C = '0') then
gen_pad_r <= storage_pad_r after DLY;
end if;
end if;
end process;
-- Implement the data out register.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
TX_PE_DATA_Buffer <= tx_pe_data_r after DLY;
TX_PE_DATA_V_Buffer <= tx_pe_data_v_r and not HALT_C after DLY;
GEN_PAD_Buffer <= gen_pad_r and not HALT_C after DLY;
end if;
end process;
end RTL;
|
--
-- Project: Aurora Module Generator version 2.4
--
-- Date: $Date: 2005/11/07 21:30:56 $
-- Tag: $Name: i+IP+98818 $
-- File: $RCSfile: tx_ll_datapath_vhd.ejava,v $
-- Rev: $Revision: 1.1.2.4 $
--
-- Company: Xilinx
-- Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--
-- TX_LL_DATAPATH
--
-- Author: Nigel Gulstone
-- Xilinx - Embedded Networking System Engineering Group
--
-- Description: This module pipelines the data path while handling the PAD
-- character placement and valid data flags.
--
-- This module supports 1 2-byte lane designs
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TX_LL_DATAPATH is
port (
-- LocalLink PDU Interface
TX_D : in std_logic_vector(0 to 15);
TX_REM : in std_logic;
TX_SRC_RDY_N : in std_logic;
TX_SOF_N : in std_logic;
TX_EOF_N : in std_logic;
-- Aurora Lane Interface
TX_PE_DATA_V : out std_logic;
GEN_PAD : out std_logic;
TX_PE_DATA : out std_logic_vector(0 to 15);
-- TX_LL Control Module Interface
HALT_C : in std_logic;
TX_DST_RDY_N : in std_logic;
-- System Interface
CHANNEL_UP : in std_logic;
USER_CLK : in std_logic
);
end TX_LL_DATAPATH;
architecture RTL of TX_LL_DATAPATH is
-- Parameter Declarations --
constant DLY : time := 1 ns;
-- External Register Declarations --
signal TX_PE_DATA_V_Buffer : std_logic;
signal GEN_PAD_Buffer : std_logic;
signal TX_PE_DATA_Buffer : std_logic_vector(0 to 15);
-- Internal Register Declarations --
signal in_frame_r : std_logic;
signal storage_r : std_logic_vector(0 to 15);
signal storage_v_r : std_logic;
signal storage_pad_r : std_logic;
signal tx_pe_data_r : std_logic_vector(0 to 15);
signal valid_c : std_logic;
signal tx_pe_data_v_r : std_logic;
signal gen_pad_c : std_logic;
signal gen_pad_r : std_logic;
-- Internal Wire Declarations --
signal ll_valid_c : std_logic;
signal in_frame_c : std_logic;
begin
TX_PE_DATA_V <= TX_PE_DATA_V_Buffer;
GEN_PAD <= GEN_PAD_Buffer;
TX_PE_DATA <= TX_PE_DATA_Buffer;
-- Main Body of Code --
-- LocalLink input is only valid when TX_SRC_RDY_N and TX_DST_RDY_N are both asserted
ll_valid_c <= not TX_SRC_RDY_N and not TX_DST_RDY_N;
-- Data must only be read if it is within a frame. If a frame will last multiple cycles
-- we assert in_frame_r as long as the frame is open.
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK = '1') then
if(CHANNEL_UP = '0') then
in_frame_r <= '0' after DLY;
elsif(ll_valid_c = '1') then
if( (TX_SOF_N = '0') and (TX_EOF_N = '1') ) then
in_frame_r <= '1' after DLY;
elsif( TX_EOF_N = '0') then
in_frame_r <= '0' after DLY;
end if;
end if;
end if;
end process;
in_frame_c <= ll_valid_c and (in_frame_r or not TX_SOF_N);
-- The data from the LocalLink interface must be delayed one cycle to
-- make room for the SCP code group in the channel.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (HALT_C = '0') then
storage_r <= TX_D after DLY;
end if;
end if;
end process;
-- This pipeline register aligns the data with the control path.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (HALT_C = '0') then
tx_pe_data_r <= storage_r after DLY;
end if;
end if;
end process;
-- We generate the valid_c signal based on the REM signal and the EOF signal.
process (TX_EOF_N, TX_REM)
begin
if (TX_EOF_N = '1') then
valid_c <= '1';
else
case TX_REM is
when '0' => valid_c <= '1';
when '1' => valid_c <= '1';
when others => valid_c <= '1';
end case;
end if;
end process;
-- If the word is valid, it is placed in the storage register and storage_v_r is
-- asserted to indicate the data is valid. Note that data is only moved to storage
-- if the PDU datapath is not halted, the data is valid and both TX_SRC_RDY_N and
-- TX_DST_RDY_N are asserted.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (HALT_C = '0') then
storage_v_r <= valid_c and in_frame_c after DLY;
end if;
end if;
end process;
-- Register the tx_pe_data_valid signal. All data is moved from the storage register
-- to the tx_pe_data register for transmission when the datapath is not halted. If the
-- storage register contains valid PDU data, the tx_pe_data register is marked as
-- containing valid PDU data
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (HALT_C = '0') then
tx_pe_data_v_r <= storage_v_r after DLY;
end if;
end if;
end process;
-- We generate the gen_pad_c signal based on the REM signal and the EOF signal.
process (TX_EOF_N, TX_REM)
begin
if (TX_EOF_N = '1') then
gen_pad_c <= '0';
else
case TX_REM is
when '0' => gen_pad_c <= '1';
when '1' => gen_pad_c <= '0';
when others => gen_pad_c <= '0';
end case;
end if;
end process;
-- Store padded data when padded and TX_SRC_RDY_N and TX_DST_RDY_N are both asserted.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (HALT_C = '0') then
storage_pad_r <= gen_pad_c and in_frame_c after DLY;
end if;
end if;
end process;
-- Register the gen_pad signal.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
if (HALT_C = '0') then
gen_pad_r <= storage_pad_r after DLY;
end if;
end if;
end process;
-- Implement the data out register.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
TX_PE_DATA_Buffer <= tx_pe_data_r after DLY;
TX_PE_DATA_V_Buffer <= tx_pe_data_v_r and not HALT_C after DLY;
GEN_PAD_Buffer <= gen_pad_r and not HALT_C after DLY;
end if;
end process;
end RTL;
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.zyehw_pkg.all;
entity fifo_reader is
port (
clk: in std_logic;
fitness_wr: in std_logic;
eval_start: in std_logic;
fifo_rdy: in std_logic;
fifo_almostfull: in std_logic;
frame_count: out frame_count_t;
fifo_rden: out std_logic;
ram_wren: out std_logic;
ram_wraddr: out img_addr_t;
start_en: out std_logic
);
end fifo_reader;
architecture behav_fifo_reader of fifo_reader is
component counter is
generic (
BITS: integer
);
port (
clk: in std_logic;
en: in std_logic;
rst: in std_logic;
count: out std_logic_vector(BITS-1 downto 0)
);
end component;
type state_t is (
wait_fifo_rdy,
first_wait_fifo_almostfull,
first_transfer,
wait_fillup,
transfer,
frame
);
constant zero: std_logic:= '0';
signal state: state_t:= wait_fifo_rdy;
signal next_state: state_t;
signal tmp_fifo_rden: std_logic_vector(1 downto 0):= (others => '0');
signal tmp_ram_wren: std_logic_vector(3 downto 0):= (others => '0');
signal tmp_start_en: std_logic_vector(1 downto 0):= (others => '0');
signal pix_count_en, frame_count_en: std_logic;
signal pix_count, pix_count_del1, pix_count_del2: img_addr_t;
signal frames: frame_count_t;
begin
pixel_counter: counter
generic map (
BITS => img_addr_size
)
port map (
clk => clk,
en => pix_count_en,
rst => zero,
count => pix_count
);
frame_counter: counter
generic map (
BITS => frame_counter_bits
)
port map (
clk => clk,
en => frame_count_en,
rst => zero,
count => frames
);
next_state_p: process (state, pix_count, fifo_rdy, fifo_almostfull,
eval_start)
begin
case state is
when wait_fifo_rdy =>
if fifo_rdy = '1' then
next_state <= first_wait_fifo_almostfull;
else
next_state <= wait_fifo_rdy;
end if;
when first_wait_fifo_almostfull =>
if fifo_almostfull = '1' then
next_state <= first_transfer;
else
next_state <= first_wait_fifo_almostfull;
end if;
when first_transfer =>
if pix_count = std_logic_vector(to_unsigned(img_pixels-1,
img_addr_size)) then
next_state <= wait_fillup;
else
next_state <= first_transfer;
end if;
when wait_fillup =>
if fifo_almostfull = '1' and eval_start = '1' then
next_state <= transfer;
else
next_state <= wait_fillup;
end if;
when transfer =>
if pix_count = std_logic_vector(to_unsigned(img_pixels-1,
img_addr_size)) then
next_state <= frame;
else
next_state <= transfer;
end if;
when frame =>
next_state <= wait_fillup;
end case;
end process;
output_p: process (state)
begin
tmp_fifo_rden(0) <= '0';
tmp_ram_wren(0) <= '0';
tmp_start_en(0) <= '1';
pix_count_en <= '0';
frame_count_en <= '0';
case state is
when wait_fifo_rdy =>
tmp_start_en(0) <= '0';
when first_wait_fifo_almostfull =>
tmp_start_en(0) <= '0';
when first_transfer =>
tmp_fifo_rden(0) <= '1';
tmp_ram_wren(0) <= '1';
tmp_start_en(0) <= '0';
pix_count_en <= '1';
when wait_fillup =>
when transfer =>
tmp_fifo_rden(0) <= '1';
tmp_ram_wren(0) <= '1';
pix_count_en <= '1';
when frame =>
frame_count_en <= '1';
end case;
end process;
process (clk)
begin
if clk'event and clk = '1' then
state <= next_state;
tmp_fifo_rden(1) <= tmp_fifo_rden(0);
tmp_start_en(1) <= tmp_start_en(0);
tmp_ram_wren(1) <= tmp_ram_wren(0);
tmp_ram_wren(2) <= tmp_ram_wren(1);
tmp_ram_wren(3) <= tmp_ram_wren(2);
pix_count_del1 <= pix_count;
pix_count_del2 <= pix_count_del1;
ram_wraddr <= pix_count_del2;
if fitness_wr = '1' then
frame_count <= frames;
end if;
end if;
end process;
fifo_rden <= tmp_fifo_rden(1);
ram_wren <= tmp_ram_wren(3);
start_en <= tmp_start_en(1);
end behav_fifo_reader;
|
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file mem_ins.vhd when simulating
-- the core, mem_ins. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY mem_ins IS
port (
a: in std_logic_vector(5 downto 0);
spo: out std_logic_vector(31 downto 0));
END mem_ins;
ARCHITECTURE mem_ins_a OF mem_ins IS
-- synthesis translate_off
component wrapped_mem_ins
port (
a: in std_logic_vector(5 downto 0);
spo: out std_logic_vector(31 downto 0));
end component;
-- Configuration specification
for all : wrapped_mem_ins use entity XilinxCoreLib.dist_mem_gen_v5_1(behavioral)
generic map(
c_has_clk => 0,
c_has_qdpo_clk => 0,
c_has_qdpo_ce => 0,
c_parser_type => 1,
c_has_d => 0,
c_has_spo => 1,
c_read_mif => 1,
c_has_qspo => 0,
c_width => 32,
c_reg_a_d_inputs => 0,
c_has_we => 0,
c_pipeline_stages => 0,
c_has_qdpo_rst => 0,
c_reg_dpra_input => 0,
c_qualify_we => 0,
c_family => "spartan3",
c_sync_enable => 1,
c_depth => 64,
c_has_qspo_srst => 0,
c_has_qdpo_srst => 0,
c_has_dpra => 0,
c_qce_joined => 0,
c_mem_type => 0,
c_has_i_ce => 0,
c_has_dpo => 0,
c_mem_init_file => "mem_ins.mif",
c_default_data => "0",
c_has_spra => 0,
c_has_qspo_ce => 0,
c_addr_width => 6,
c_has_qspo_rst => 0,
c_has_qdpo => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_mem_ins
port map (
a => a,
spo => spo);
-- synthesis translate_on
END mem_ins_a;
|
------------------------------------------------------
-- A four level, round-robin arbiter. This was
-- orginally coded by WD Peterson in VHDL.
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity arbiter is
port (
clk, rst :in std_logic;
req0, req1 :in std_logic;
req2, req3 :in std_logic;
gnt0, gnt1 :out std_logic;
gnt2, gnt3 :out std_logic
);
end entity;
architecture behavior of arbiter is
----------------Internal Registers-----------------
signal gnt, lgnt :std_logic_vector (1 downto 0);
signal comreq, lcomreq :std_logic;
signal beg, ledge :std_logic;
signal lgnt0, lgnt1 :std_logic;
signal lgnt2, lgnt3 :std_logic;
signal lmask0, lmask1 :std_logic;
signal lasmask :std_logic;
begin
----------------Code Starts Here------------------
process (clk)
begin
if (rising_edge(clk)) then
if (rst = '1') then
lgnt0 <= '0';
lgnt1 <= '0';
lgnt2 <= '0';
lgnt3 <= '0';
else
lgnt0 <=(not lcomreq and not lmask1 and not lmask0 and
not req3 and not req2 and not req1 and req0)
or (not lcomreq and not lmask1 and lmask0 and
not req3 and not req2 and req0)
or (not lcomreq and lmask1 and not lmask0 and
not req3 and req0)
or (not lcomreq and lmask1 and lmask0 and req0)
or (lcomreq and lgnt0);
lgnt1 <=(not lcomreq and not lmask1 and not lmask0 and req1)
or (not lcomreq and not lmask1 and lmask0 and
not req3 and not req2 and req1 and not req0)
or (not lcomreq and lmask1 and not lmask0 and
not req3 and req1 and not req0)
or (not lcomreq and lmask1 and lmask0 and
req1 and not req0)
or (lcomreq and lgnt1);
lgnt2 <=(not lcomreq and not lmask1 and not lmask0 and
req2 and not req1)
or (not lcomreq and not lmask1 and lmask0 and req2)
or (not lcomreq and lmask1 and not lmask0 and
not req3 and req2 and not req1 and not req0)
or (not lcomreq and lmask1 and lmask0 and
req2 and not req1 and not req0)
or (lcomreq and lgnt2);
lgnt3 <=(not lcomreq and not lmask1 and not lmask0 and
req3 and not req2 and not req1)
or (not lcomreq and not lmask1 and lmask0 and
req3 and not req2)
or (not lcomreq and lmask1 and not lmask0 and req3)
or (not lcomreq and lmask1 and lmask0 and
req3 and not req2 and not req1 and not req0)
or (lcomreq and lgnt3);
end if;
end if;
end process;
------------------------------------------------------
-- lasmask state machine.
------------------------------------------------------
beg <= (req3 or req2 or req1 or req0) and not lcomreq;
process (clk)
begin
if (rising_edge(clk)) then
lasmask <= (beg and not ledge and not lasmask);
ledge <= (beg and not ledge and lasmask)
or (beg and ledge and not lasmask);
end if;
end process;
------------------------------------------------------
-- comreq logic.
------------------------------------------------------
lcomreq <= (req3 and lgnt3)
or (req2 and lgnt2)
or (req1 and lgnt1)
or (req0 and lgnt0);
------------------------------------------------------
-- Encoder logic.
------------------------------------------------------
lgnt <= ((lgnt3 or lgnt2) & (lgnt3 or lgnt1));
------------------------------------------------------
-- lmask register.
------------------------------------------------------
process (clk)
begin
if (rising_edge(clk)) then
if (rst = '1') then
lmask1 <= '0';
lmask0 <= '0';
elsif (lasmask = '1') then
lmask1 <= lgnt(1);
lmask0 <= lgnt(0);
else
lmask1 <= lmask1;
lmask0 <= lmask0;
end if;
end if;
end process;
comreq <= lcomreq;
gnt <= lgnt;
------------------------------------------------------
-- Drive the outputs
------------------------------------------------------
gnt3 <= lgnt3;
gnt2 <= lgnt2;
gnt1 <= lgnt1;
gnt0 <= lgnt0;
end architecture;
------------------------------------------------------
-- Arbiter test bench
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity arbiter_tb is
end entity;
architecture test of arbiter_tb is
signal clk :std_logic := '0';
signal rst :std_logic := '1';
signal req0, req1 :std_logic := '0';
signal req2, req3 :std_logic := '0';
signal gnt0, gnt1 :std_logic := '0';
signal gnt2, gnt3 :std_logic := '0';
component arbiter is
port (
clk, rst :in std_logic;
req0, req1 :in std_logic;
req2, req3 :in std_logic;
gnt0, gnt1 :out std_logic;
gnt2, gnt3 :out std_logic
);
end component;
constant PERIOD :time := 20 ns;
begin
-- Clock generator
clk <= not clk after PERIOD/2;
rst <= '0' after PERIOD;
req0 <= '1' after PERIOD*1, '0' after PERIOD*2,
'1' after PERIOD*3, '0' after PERIOD*7;
req1 <= '1' after PERIOD*3, '0' after PERIOD*4;
req2 <= '1' after PERIOD*4, '0' after PERIOD*5;
req3 <= '1' after PERIOD*5, '0' after PERIOD*6;
-- Connect the DUT
Inst_arbiter : arbiter
port map (
clk => clk,
rst => rst,
req0 => req0,
req1 => req1,
req2 => req2,
req3 => req3,
gnt0 => gnt0,
gnt1 => gnt1,
gnt2 => gnt2,
gnt3 => gnt3
);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- sewuence generator
-- note: cos,sin output on negative edge before pha, sync.
-- pha on positive edge, sync on positive edge
entity ram_lut is
port( nreset,clk,wstb,rstb: in std_logic;
cmd: in std_logic_vector(2 downto 0); -- control
din: in std_logic_vector(7 downto 0);
dout: out std_logic_vector(7 downto 0);
pos_ctr: out std_logic_vector(9 downto 0);
sin,cos,indo,pha,sync:out std_logic);
end ram_lut;
architecture rtl of ram_lut is
component ram2k8 is
port( clk,WEn,CSn: in std_logic; -- clk rising edge, WEn & CSn are active low
ADDR: in std_logic_vector(10 downto 0);
dw: in std_logic_vector(7 downto 0); -- write data
dr: out std_logic_vector(7 downto 0) -- read data
);
end component;
-- signals for memory
signal mCLK,mWEn,mCEn: std_logic;
signal mA11: std_logic_vector(10 downto 0); -- address for the 2k mem
signal mA: std_logic_vector(8 downto 0); -- normal address
signal mD: std_logic_vector(7 downto 0);
signal mQ: std_logic_vector(7 downto 0);
signal mQr: std_logic_vector(7 downto 0); -- register to hold data
-- signals for sequence generator
signal ctr_lim: unsigned(8 downto 0); -- final byte address
signal dib_ctr: unsigned(1 downto 0);
signal sini,cosi,indoi,phai,synci: std_logic;
signal pos_ctri:unsigned(9 downto 0);
signal lut_ctl: std_logic_vector(7 downto 0); -- see below:
alias lut_run: std_logic is lut_ctl(7);
alias lut_3ph: std_logic is lut_ctl(5);
alias indo_def: std_logic is lut_ctl(4);
alias dib_lim: std_logic_vector(1 downto 0) is lut_ctl(2 downto 1);
signal rd,csgen,csregen:std_logic; -- mem rd, controls for generator
signal mxo:std_logic_vector(2 downto 0);-- mux of data
begin
pos_ctr<=std_logic_vector(pos_ctri);
sync<=synci;
sin<=sini;
cos<=cosi;
pha<=phai;
indo<=indoi;
-- dout
dout<= mQ when cmd="000" else
std_logic_vector(ctr_lim(7 downto 0)) when cmd="010" else
lut_ctl when cmd="011" else
"01111110"; -- 7e
mD<=din; --always
-- modified controls
-- cmd: 000 read or write mem, autoinc
-- 001 zero address - wstb
-- 010 ctr_lim(7 downto 0) - wstb, rstb
-- 011 lut_ctl - wstb,rstb
-- 101
--
-- lut_ctl: run,0,3pha,set_indo,0,dib_lim1,dib_lim0.ctr_lim(8)
mCEn<='0' when ((cmd="000") and ((wstb='1') or (rstb='1'))) else
'0' when rd='1' else
'1'; -- 1 cycle long
mWEn<='0' when ((cmd="000") and ((wstb='1')))
else '1';
mCLK<=not(clk) and not(mCEn); -- only clock when necessary
process(mQ,dib_ctr) begin -- set mxo(2 downto 0) to indoi,mxo(1),mxo(0)
if lut_3ph='0' then
mxo(2)<=indo_def; -- per lut_ctl
case dib_ctr is
when "00"=>
mxo(0)<=mQ(0);
mxo(1)<=mQ(1);
when "01"=>
mxo(0)<=mQ(2);
mxo(1)<=mQ(3);
when "10"=>
mxo(0)<=mQ(4);
mxo(1)<=mQ(5);
when others=>
mxo(0)<=mQ(6);
mxo(1)<=mQ(7);
end case;
else -- lut_3ph='1'
case dib_ctr is
when "00"=>
mxo(0)<=mQ(0);
mxo(1)<=mQ(1);
mxo(2)<=mq(2);
when others=>
mxo(0)<=mQ(4);
mxo(1)<=mQ(5);
mxo(2)<=mq(6);
end case;
end if;
end process;
process (nreset,clk) -- generator
begin
if nreset='0' then
synci<='0';
cosi<='0';
sini<='0';
phai<='0';
pos_ctri<=(others=>'0');
csgen<='0'; -- 1 when running
csregen<='0'; -- 1 when output cos,sin to register
dib_ctr<=(others=>'0');
mQr<=(others=>'0');
rd<='0'; -- read data byte
elsif clk'event and clk='1' then
synci<='0'; -- will give a pulse at adr 0
rd<='0'; -- pulse
if mCEn='0' then -- always autoinc at end of access.
mQr<=mQ;
mA<=std_logic_vector(unsigned(mA) + 1);
end if;
if lut_run='0' then -- hold in reset
if ((cmd="001") and (wstb='1')) then -- handle table write from spi
mA<=(others=>'0'); -- separate or part of cycle
elsif (mCEn='0') then
mA<=std_logic_vector(unsigned(mA) + 1);
end if;
dib_ctr<=(others=>'0');
phai<='0';
pos_ctri<=(others=>'0');
else -- lut_run='1'
if csregen='1' then -- timing: pha follows cos,sin output
phai<=not(phai);
end if;
if rd='1' then
mQr<=mQ;
mA<=std_logic_vector(unsigned(mA) + 1);
end if;
if csgen='0' then
mA<=(others=>'0'); -- separate or part of cycle
synci<='1';
rd<='1';
else -- csgen='1';
dib_ctr<=dib_ctr+1;
if ((pos_ctri=ctr_lim) and (dib_ctr=unsigned(dib_lim))) then
dib_ctr<="00";
pos_ctri<=(others=>'0');
mA<=(others=>'0');
rd<='1';
synci<='1';
elsif dib_ctr="11" then
dib_ctr<="00";
rd<='1';
end if;
end if;
end if;
elsif clk'event and clk='0' then -- to get cos,sin on negedge
if lut_run='0' then
csregen<='0';
elsif csregen='0' then
if rd='1' then csregen<='1'; end if; -- set it once
else -- normal running
cosi<=mxo(0);
sini<=mxo(1);
indoi<=mxo(2);
end if;
end if;
end process;
process (nreset,clk) -- handle setting things per cmd
begin
if nreset='0' then
ctr_lim<=(others=>'0');
lut_ctl<=(others=>'0');
elsif clk'event and clk='1' then
if wstb='1' then
case cmd is
when "010"=> -- load ctr_lim
ctr_lim<=unsigned(lut_ctl(0) & din); -- so load lut ctl first
when "011"=> -- load cmd
lut_ctl<=din;
dib_lim<=unsigned(din(2 downto 1));
ctr_lim(8)<=din(0);
when others=>
end case;
end if;
end if;
end process;
-- this is based on 512 bytes so we do not need 2 upper bits
mA11<=("00" & mA);
-- based on ram2k8.vhp in vhdl_ip.
-- need to move this RAM out so we just have ports.
-- target -Dxfab 512x8 for asic
-- -Dghdl model for simulation
-- -Dxilinx model for fpga
r1:ram2k8 port map(
mCLK,mWEn,mCEn,
mA11, mD, mQ);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- sewuence generator
-- note: cos,sin output on negative edge before pha, sync.
-- pha on positive edge, sync on positive edge
entity ram_lut is
port( nreset,clk,wstb,rstb: in std_logic;
cmd: in std_logic_vector(2 downto 0); -- control
din: in std_logic_vector(7 downto 0);
dout: out std_logic_vector(7 downto 0);
pos_ctr: out std_logic_vector(9 downto 0);
sin,cos,indo,pha,sync:out std_logic);
end ram_lut;
architecture rtl of ram_lut is
component ram2k8 is
port( clk,WEn,CSn: in std_logic; -- clk rising edge, WEn & CSn are active low
ADDR: in std_logic_vector(10 downto 0);
dw: in std_logic_vector(7 downto 0); -- write data
dr: out std_logic_vector(7 downto 0) -- read data
);
end component;
-- signals for memory
signal mCLK,mWEn,mCEn: std_logic;
signal mA11: std_logic_vector(10 downto 0); -- address for the 2k mem
signal mA: std_logic_vector(8 downto 0); -- normal address
signal mD: std_logic_vector(7 downto 0);
signal mQ: std_logic_vector(7 downto 0);
signal mQr: std_logic_vector(7 downto 0); -- register to hold data
-- signals for sequence generator
signal ctr_lim: unsigned(8 downto 0); -- final byte address
signal dib_ctr: unsigned(1 downto 0);
signal sini,cosi,indoi,phai,synci: std_logic;
signal pos_ctri:unsigned(9 downto 0);
signal lut_ctl: std_logic_vector(7 downto 0); -- see below:
alias lut_run: std_logic is lut_ctl(7);
alias lut_3ph: std_logic is lut_ctl(5);
alias indo_def: std_logic is lut_ctl(4);
alias dib_lim: std_logic_vector(1 downto 0) is lut_ctl(2 downto 1);
signal rd,csgen,csregen:std_logic; -- mem rd, controls for generator
signal mxo:std_logic_vector(2 downto 0);-- mux of data
begin
pos_ctr<=std_logic_vector(pos_ctri);
sync<=synci;
sin<=sini;
cos<=cosi;
pha<=phai;
indo<=indoi;
-- dout
dout<= mQ when cmd="000" else
std_logic_vector(ctr_lim(7 downto 0)) when cmd="010" else
lut_ctl when cmd="011" else
"01111110"; -- 7e
mD<=din; --always
-- modified controls
-- cmd: 000 read or write mem, autoinc
-- 001 zero address - wstb
-- 010 ctr_lim(7 downto 0) - wstb, rstb
-- 011 lut_ctl - wstb,rstb
-- 101
--
-- lut_ctl: run,0,3pha,set_indo,0,dib_lim1,dib_lim0.ctr_lim(8)
mCEn<='0' when ((cmd="000") and ((wstb='1') or (rstb='1'))) else
'0' when rd='1' else
'1'; -- 1 cycle long
mWEn<='0' when ((cmd="000") and ((wstb='1')))
else '1';
mCLK<=not(clk) and not(mCEn); -- only clock when necessary
process(mQ,dib_ctr) begin -- set mxo(2 downto 0) to indoi,mxo(1),mxo(0)
if lut_3ph='0' then
mxo(2)<=indo_def; -- per lut_ctl
case dib_ctr is
when "00"=>
mxo(0)<=mQ(0);
mxo(1)<=mQ(1);
when "01"=>
mxo(0)<=mQ(2);
mxo(1)<=mQ(3);
when "10"=>
mxo(0)<=mQ(4);
mxo(1)<=mQ(5);
when others=>
mxo(0)<=mQ(6);
mxo(1)<=mQ(7);
end case;
else -- lut_3ph='1'
case dib_ctr is
when "00"=>
mxo(0)<=mQ(0);
mxo(1)<=mQ(1);
mxo(2)<=mq(2);
when others=>
mxo(0)<=mQ(4);
mxo(1)<=mQ(5);
mxo(2)<=mq(6);
end case;
end if;
end process;
process (nreset,clk) -- generator
begin
if nreset='0' then
synci<='0';
cosi<='0';
sini<='0';
phai<='0';
pos_ctri<=(others=>'0');
csgen<='0'; -- 1 when running
csregen<='0'; -- 1 when output cos,sin to register
dib_ctr<=(others=>'0');
mQr<=(others=>'0');
rd<='0'; -- read data byte
elsif clk'event and clk='1' then
synci<='0'; -- will give a pulse at adr 0
rd<='0'; -- pulse
if mCEn='0' then -- always autoinc at end of access.
mQr<=mQ;
mA<=std_logic_vector(unsigned(mA) + 1);
end if;
if lut_run='0' then -- hold in reset
if ((cmd="001") and (wstb='1')) then -- handle table write from spi
mA<=(others=>'0'); -- separate or part of cycle
elsif (mCEn='0') then
mA<=std_logic_vector(unsigned(mA) + 1);
end if;
dib_ctr<=(others=>'0');
phai<='0';
pos_ctri<=(others=>'0');
else -- lut_run='1'
if csregen='1' then -- timing: pha follows cos,sin output
phai<=not(phai);
end if;
if rd='1' then
mQr<=mQ;
mA<=std_logic_vector(unsigned(mA) + 1);
end if;
if csgen='0' then
mA<=(others=>'0'); -- separate or part of cycle
synci<='1';
rd<='1';
else -- csgen='1';
dib_ctr<=dib_ctr+1;
if ((pos_ctri=ctr_lim) and (dib_ctr=unsigned(dib_lim))) then
dib_ctr<="00";
pos_ctri<=(others=>'0');
mA<=(others=>'0');
rd<='1';
synci<='1';
elsif dib_ctr="11" then
dib_ctr<="00";
rd<='1';
end if;
end if;
end if;
elsif clk'event and clk='0' then -- to get cos,sin on negedge
if lut_run='0' then
csregen<='0';
elsif csregen='0' then
if rd='1' then csregen<='1'; end if; -- set it once
else -- normal running
cosi<=mxo(0);
sini<=mxo(1);
indoi<=mxo(2);
end if;
end if;
end process;
process (nreset,clk) -- handle setting things per cmd
begin
if nreset='0' then
ctr_lim<=(others=>'0');
lut_ctl<=(others=>'0');
elsif clk'event and clk='1' then
if wstb='1' then
case cmd is
when "010"=> -- load ctr_lim
ctr_lim<=unsigned(lut_ctl(0) & din); -- so load lut ctl first
when "011"=> -- load cmd
lut_ctl<=din;
dib_lim<=unsigned(din(2 downto 1));
ctr_lim(8)<=din(0);
when others=>
end case;
end if;
end if;
end process;
-- this is based on 512 bytes so we do not need 2 upper bits
mA11<=("00" & mA);
-- based on ram2k8.vhp in vhdl_ip.
-- need to move this RAM out so we just have ports.
-- target -Dxfab 512x8 for asic
-- -Dghdl model for simulation
-- -Dxilinx model for fpga
r1:ram2k8 port map(
mCLK,mWEn,mCEn,
mA11, mD, mQ);
end rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:01:02 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_stub.vhdl
-- Design : system_clock_splitter_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_clock_splitter_0_0 is
Port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end system_clock_splitter_0_0;
architecture stub of system_clock_splitter_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_in,latch_edge,clk_out";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "clock_splitter,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:01:02 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_stub.vhdl
-- Design : system_clock_splitter_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_clock_splitter_0_0 is
Port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end system_clock_splitter_0_0;
architecture stub of system_clock_splitter_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_in,latch_edge,clk_out";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "clock_splitter,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 21:01:02 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_stub.vhdl
-- Design : system_clock_splitter_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_clock_splitter_0_0 is
Port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end system_clock_splitter_0_0;
architecture stub of system_clock_splitter_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_in,latch_edge,clk_out";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "clock_splitter,Vivado 2016.4";
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1291.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01291ent IS
END c08s04b00x00p04n01i01291ent;
ARCHITECTURE c08s04b00x00p04n01i01291arch OF c08s04b00x00p04n01i01291ent IS
signal S1 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
hr <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01291 - A unit name (of a physical literal) cannot be the name used on the left-hand side of a signal assignment"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01291arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1291.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01291ent IS
END c08s04b00x00p04n01i01291ent;
ARCHITECTURE c08s04b00x00p04n01i01291arch OF c08s04b00x00p04n01i01291ent IS
signal S1 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
hr <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01291 - A unit name (of a physical literal) cannot be the name used on the left-hand side of a signal assignment"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01291arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1291.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b00x00p04n01i01291ent IS
END c08s04b00x00p04n01i01291ent;
ARCHITECTURE c08s04b00x00p04n01i01291arch OF c08s04b00x00p04n01i01291ent IS
signal S1 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
hr <= S1;
assert FALSE
report "***FAILED TEST: c08s04b00x00p04n01i01291 - A unit name (of a physical literal) cannot be the name used on the left-hand side of a signal assignment"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p04n01i01291arch;
|
library ieee ;
use ieee.std_logic_1164.all ;
use std.textio.all ;
entity cond_assign_proc is
end entity cond_assign_proc ;
architecture doit of cond_assign_proc is
signal Clk : std_logic := '0' ;
signal Y : std_logic ;
begin
Clk <= not Clk after 10 ns ;
process (Clk)
variable A : std_logic ;
begin
A := 'H' when Clk = '1' else 'L' ;
Y <= A ;
-- Y <= 'H' when Clk = '1' else 'L' ;
end process ;
-- Y <= 'H' when Clk = '1' else 'L' ;
process
begin
wait for 500 ns ;
std.env.stop ;
end process ;
end architecture doit ;
|
library ieee ;
use ieee.std_logic_1164.all ;
use std.textio.all ;
entity cond_assign_proc is
end entity cond_assign_proc ;
architecture doit of cond_assign_proc is
signal Clk : std_logic := '0' ;
signal Y : std_logic ;
begin
Clk <= not Clk after 10 ns ;
process (Clk)
variable A : std_logic ;
begin
A := 'H' when Clk = '1' else 'L' ;
Y <= A ;
-- Y <= 'H' when Clk = '1' else 'L' ;
end process ;
-- Y <= 'H' when Clk = '1' else 'L' ;
process
begin
wait for 500 ns ;
std.env.stop ;
end process ;
end architecture doit ;
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
-- ================================================================================
-- Legal Notice: Copyright (C) 1991-2006 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
-- ================================================================================
--
-- Generated by: FIR Compiler 9.0
-- Generated on: 2015-11-11 15:52:10
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity tb_matchfilter is
--START MEGAWIZARD INSERT CONSTANTS
constant FIR_INPUT_FILE_c : string := "matchfilter_input.txt";
constant FIR_OUTPUT_FILE_c : string := "matchfilter_output.txt";
constant NUM_OF_CHANNELS_c : natural := 1;
constant DATA_WIDTH_c : natural := 15;
constant CHANNEL_OUT_WIDTH_c : natural := 0;
constant OUT_WIDTH_c : natural := 30;
constant COEF_SET_ADDRESS_WIDTH_c : natural := 0;
constant COEF_RELOAD_BIT_WIDTH_c : natural := 11;
--END MEGAWIZARD INSERT CONSTANTS
end entity tb_matchfilter;
--library work;
--library auk_dspip_lib;
-------------------------------------------------------------------------------
architecture rtl of tb_matchfilter is
signal ast_sink_data : std_logic_vector (DATA_WIDTH_c-1 downto 0) := (others => '0');
signal ast_source_data : std_logic_vector (OUT_WIDTH_c-1 downto 0);
signal ast_sink_error : std_logic_vector (1 downto 0) := (others => '0');
signal ast_source_error : std_logic_vector (1 downto 0);
signal ast_sink_valid : std_logic := '0';
signal ast_source_valid : std_logic;
signal ast_source_ready : std_logic := '0';
signal clk : std_logic := '0';
signal reset_testbench : std_logic := '0';
signal reset_design : std_logic;
signal eof : std_logic;
signal ast_sink_ready : std_logic;
signal start : std_logic;
signal cnt : natural range 0 to NUM_OF_CHANNELS_c;
constant tclk : time := 10 ns;
constant time_lapse_max : time := 60 us;
signal time_lapse : time;
begin
DUT : entity work.matchfilter
port map (
clk => clk,
reset_n => reset_design,
ast_sink_ready => ast_sink_ready,
ast_sink_data => ast_sink_data,
ast_source_data => ast_source_data,
ast_sink_valid => ast_sink_valid,
ast_source_valid => ast_source_valid,
ast_source_ready => ast_source_ready,
ast_sink_error => ast_sink_error,
ast_source_error => ast_source_error);
-- for example purposes, the ready signal is always asserted.
ast_source_ready <= '1';
-- no input error
ast_sink_error <= (others => '0');
-- start valid for first cycle to indicate that the file reading should start.
start_p : process (clk, reset_testbench)
begin
if reset_testbench = '0' then
start <= '1';
elsif rising_edge(clk) then
if ast_sink_valid = '1' and ast_sink_ready = '1' then
start <= '0';
end if;
end if;
end process start_p;
-----------------------------------------------------------------------------------------------
-- Read input data from file
-----------------------------------------------------------------------------------------------
source_model : process(clk) is
file in_file : text open read_mode is FIR_INPUT_FILE_c;
variable data_in : integer;
variable indata : line;
begin
if rising_edge(clk) then
if(reset_testbench = '0') then
ast_sink_data <= std_logic_vector(to_signed(0, DATA_WIDTH_c)) after tclk/4;
ast_sink_valid <= '0' after tclk/4;
eof <= '0';
else
if not endfile(in_file) and (eof = '0') then
eof <= '0';
if((ast_sink_valid = '1' and ast_sink_ready = '1') or
(start = '1'and not (ast_sink_valid = '1' and ast_sink_ready = '0'))) then
readline(in_file, indata);
read(indata, data_in);
ast_sink_valid <= '1' after tclk/4;
ast_sink_data <= std_logic_vector(to_signed(data_in, DATA_WIDTH_c)) after tclk/4;
else
ast_sink_valid <= '1' after tclk/4;
ast_sink_data <= ast_sink_data after tclk/4;
end if;
else
eof <= '1';
ast_sink_valid <= '0' after tclk/4;
ast_sink_data <= std_logic_vector(to_signed(0, DATA_WIDTH_c)) after tclk/4;
end if;
end if;
end if;
end process source_model;
---------------------------------------------------------------------------------------------
-- Write FIR output to file
---------------------------------------------------------------------------------------------
sink_model : process(clk) is
file ro_file : text open write_mode is FIR_OUTPUT_FILE_c;
variable rdata : line;
variable data_r : integer;
begin
if rising_edge(clk) then
if(ast_source_valid = '1' and ast_source_ready = '1') then
data_r := to_integer(signed(ast_source_data));
write(rdata, data_r);
writeline(ro_file, rdata);
end if;
end if;
end process sink_model;
-------------------------------------------------------------------------------
-- clock generator
-------------------------------------------------------------------------------
clkgen : process
begin -- process clkgen
if eof = '1' then
clk <= '0';
assert FALSE
report "NOTE: Stimuli ended" severity note;
wait;
elsif time_lapse >= time_lapse_max then
clk <= '0';
assert FALSE
report "ERROR: Reached time_lapse_max without activity, probably simulation is stuck!" severity Error;
wait;
else
clk <= '0';
wait for tclk/2;
clk <= '1';
wait for tclk/2;
end if;
end process clkgen;
monitor_toggling_activity : process(clk, reset_testbench,
ast_source_data, ast_source_valid)
begin
if reset_testbench = '0' then
time_lapse <= 0 ns;
elsif ast_source_data'event or ast_source_valid'event then
time_lapse <= 0 ns;
elsif rising_edge(clk) then
if time_lapse < time_lapse_max then
time_lapse <= time_lapse + tclk;
end if;
end if;
end process monitor_toggling_activity;
-------------------------------------------------------------------------------
-- reset generator
-------------------------------------------------------------------------------
reset_testbench_gen : process
begin -- process resetgen
reset_testbench <= '1';
wait for tclk/4;
reset_testbench <= '0';
wait for tclk*2;
reset_testbench <= '1';
wait;
end process reset_testbench_gen;
reset_design_gen : process
begin -- process resetgen
reset_design <= '1';
wait for tclk/4;
reset_design <= '0';
wait for tclk*2;
reset_design <= '1';
wait for tclk*80;
reset_design <= '1';
wait for tclk*81*2;
reset_design <= '1';
wait;
end process reset_design_gen;
-------------------------------------------------------------------------------
-- control signals
-------------------------------------------------------------------------------
end architecture rtl;
|
--------------------------------------------------------------------------------
--
-- Design unit generated by Aldec IP Core Generator, version 8.2.
-- Copyright (c) 1997 - 2009 by Aldec, Inc. All rights reserved.
--
--------------------------------------------------------------------------------
--
-- Created on Saturday 2010-08-14, 17:08:02
--
--------------------------------------------------------------------------------
-- Details:
-- Type: First In - First Out (FIFO) Memory
-- Data width: 16
-- Depth: 16
-- Clock input CLK active high
-- Synchronous Clear input CLR active high
-- Read input RD active high
-- Write input WR active high
-- Empty flag output EMPTY active high
-- Full flag output FULL active high
--------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {fifo} architecture {fifo_arch}}
library IEEE;
use IEEE.std_logic_1164.all;
entity fifo is
port(
CLR : in std_logic;
CLK : in std_logic;
RD : in std_logic;
WR : in std_logic;
DATA : in std_logic_vector(15 downto 0);
EMPTY : out std_logic;
FULL : out std_logic;
Q : out std_logic_vector(15 downto 0)
);
end entity;
--}} End of automatically maintained section
library IEEE;
use IEEE.std_logic_unsigned.all;
architecture fifo_arch of fifo is
type fifo_array_type is array (15 downto 0) of std_logic_vector(15 downto 0);
signal fifo_array : fifo_array_type;
signal WR_PTR : INTEGER range 0 to 15;
signal RD_PTR : INTEGER range 0 to 15;
begin
process (CLK)
begin
if rising_edge(CLK) then
if CLR = '1' then
for INDEX in 15 downto 0 loop
fifo_array(INDEX) <= (others => '0');
end loop;
elsif WR = '1' then
fifo_array(WR_PTR) <= DATA;
end if;
end if;
end process;
process (CLK)
variable PTR : INTEGER range 0 to 16;
begin
if rising_edge(CLK) then
if CLR = '1' then
WR_PTR <= 0;
RD_PTR <= 0;
EMPTY <= '1';
FULL <= '0';
PTR := 0;
elsif WR = '1' and PTR < 16 then
if WR_PTR < 15 then
WR_PTR <= WR_PTR + 1;
elsif WR_PTR = 15 then
WR_PTR <= 0;
end if;
PTR := PTR + 1;
elsif RD = '1' and PTR > 0 then
if RD_PTR<15 then
RD_PTR <= RD_PTR + 1;
elsif RD_PTR = 15 then
RD_PTR <= 0;
end if;
PTR := PTR - 1;
end if;
if PTR = 0 then
EMPTY <= '1';
else
EMPTY <= '0';
end if;
if PTR = 16 then
FULL<= '1';
else
FULL <= '0';
end if;
end if;
end process;
Q <= fifo_array(RD_PTR) when RD = '1' else (others => 'Z');
end architecture;
|
entity tb_ram4 is
end tb_ram4;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ram4 is
signal clk : std_logic;
signal en : std_logic;
signal we : std_logic;
signal addr : std_logic_vector(5 downto 0);
signal rdat : std_logic_vector(31 downto 0);
signal wdat : std_logic_vector(31 downto 0);
begin
dut: entity work.ram4
port map (clkB => clk, enB => en, weB => we, addrB => addr,
diB => wdat, doB => rdat);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
en <= '1';
we <= '1';
addr <= b"00_0000";
wdat <= x"11_22_33_f0";
pulse;
assert rdat = x"11_22_33_f0" severity failure;
addr <= b"00_0001";
wdat <= x"11_22_33_f1";
pulse;
assert rdat = x"11_22_33_f1" severity failure;
-- Read.
we <= '0';
addr <= b"00_0000";
wdat <= x"ff_22_33_f1";
pulse;
assert rdat = x"11_22_33_f0" severity failure;
addr <= b"00_0001";
wdat <= x"ff_22_33_f1";
pulse;
assert rdat = x"11_22_33_f1" severity failure;
-- Disable.
en <= '0';
we <= '1';
addr <= b"00_0000";
wdat <= x"11_22_33_f0";
pulse;
assert rdat = x"11_22_33_f1" severity failure;
wait;
end process;
end behav;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (10);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := (2500);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#6#;
constant CFG_GRGPIO_WIDTH : integer := (3);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00510
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.1.1 (11)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00510)
-- ENT00510_Test_Bench(ARCH00510_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00510 of E00000 is
procedure proc ( n : in integer ;
b : in boolean ;
x,y : out t_int1 ) is
subtype ary is t_arr1 (lowb to n) ;
type rec is record
bo : boolean ;
a : ary ;
end record ;
variable rr : rec ;
function record_func ( n : integer; r : rec ) return t_int1 is
begin
if r.bo then
return r.a(n) ;
else
return r.a(n) + 20;
end if ;
end record_func ;
function array_func ( n : integer; a : ary ) return t_int1 is
begin
return a(n-1) + a(n) ;
end array_func ;
begin
rr.bo := b ;
for i in lowb to n loop
rr.a(i) := t_int1(i + 10) ;
end loop ;
x := record_func(n, rr) ;
y := array_func(n, rr.a) ;
end proc ;
begin
P :
process
variable x1,y1,x2,y2 : t_int1 ;
begin
proc ( 5, true, x1, y1 ) ;
proc ( 5, false, x2, y2 ) ;
test_report ( "ARCH00510" ,
"Parameters can be dynamically sized" ,
(x1 = 5+10) and
(y1 = 4+10 + 5+10) and
(x2 = x1+20) and
(y2 = y1)
) ;
wait ;
end process P ;
end ARCH00510 ;
entity ENT00510_Test_Bench is
end ENT00510_Test_Bench ;
architecture ARCH00510_Test_Bench of ENT00510_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00510 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00510_Test_Bench ;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: netcomp
-- File: netcomp.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Delcation of netlists componnets
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use work.gencomp.all;
package netcomp is
---------------------------------------------------------------------------
-- netlists ---------------------------------------------------------------
---------------------------------------------------------------------------
component usbhc_net is
generic (
tech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end component;
component grspwc_net
generic(
tech : integer := 0;
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grlfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component leon3ft_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic
);
end component;
component ftmctrl_net
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
tech : integer := 0
);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
memi_data: in Std_Logic_Vector(31 downto 0);
memi_brdyn: in Std_Logic;
memi_bexcn: in Std_Logic;
memi_writen: in Std_Logic;
memi_wrn: in Std_Logic_Vector(3 downto 0);
memi_bwidth: in Std_Logic_Vector(1 downto 0);
memi_sd: in Std_Logic_Vector(63 downto 0);
memi_cb: in Std_Logic_Vector(7 downto 0);
memi_scb: in Std_Logic_Vector(7 downto 0);
memi_edac: in Std_Logic;
memo_address: out Std_Logic_Vector(31 downto 0);
memo_data: out Std_Logic_Vector(31 downto 0);
memo_sddata: out Std_Logic_Vector(63 downto 0);
memo_ramsn: out Std_Logic_Vector(7 downto 0);
memo_ramoen: out Std_Logic_Vector(7 downto 0);
memo_ramn: out Std_ULogic;
memo_romn: out Std_ULogic;
memo_mben: out Std_Logic_Vector(3 downto 0);
memo_iosn: out Std_Logic;
memo_romsn: out Std_Logic_Vector(7 downto 0);
memo_oen: out Std_Logic;
memo_writen: out Std_Logic;
memo_wrn: out Std_Logic_Vector(3 downto 0);
memo_bdrive: out Std_Logic_Vector(3 downto 0);
memo_vbdrive: out Std_Logic_Vector(31 downto 0);
memo_svbdrive: out Std_Logic_Vector(63 downto 0);
memo_read: out Std_Logic;
memo_sa: out Std_Logic_Vector(14 downto 0);
memo_cb: out Std_Logic_Vector(7 downto 0);
memo_scb: out Std_Logic_Vector(7 downto 0);
memo_vcdrive: out Std_Logic_Vector(7 downto 0);
memo_svcdrive: out Std_Logic_Vector(7 downto 0);
memo_ce: out Std_ULogic;
sdo_sdcke: out Std_Logic_Vector( 1 downto 0);
sdo_sdcsn: out Std_Logic_Vector( 1 downto 0);
sdo_sdwen: out Std_ULogic;
sdo_rasn: out Std_ULogic;
sdo_casn: out Std_ULogic;
sdo_dqm: out Std_Logic_Vector( 7 downto 0);
wpo_wprothit: in Std_ULogic);
end component;
component ssrctrl_net
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hcache: in Std_Logic;
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hcache: out Std_Logic;
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: netcomp
-- File: netcomp.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Delcation of netlists componnets
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use work.gencomp.all;
package netcomp is
---------------------------------------------------------------------------
-- netlists ---------------------------------------------------------------
---------------------------------------------------------------------------
component usbhc_net is
generic (
tech : integer := 0;
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end component;
component grspwc_net
generic(
tech : integer := 0;
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 1 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
di : in std_logic_vector(1 downto 0);
si : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
nrxclki : in std_logic_vector(1 downto 0);
rxclko : out std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grlfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component grfpw_net
generic (tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 2 := 1;
disas : integer range 0 to 2 := 0;
pipe : integer range 0 to 2 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi_flush : in std_ulogic; -- pipeline flush
cpi_exack : in std_ulogic; -- FP exception acknowledge
cpi_a_rs1 : in std_logic_vector(4 downto 0);
cpi_d_pc : in std_logic_vector(31 downto 0);
cpi_d_inst : in std_logic_vector(31 downto 0);
cpi_d_cnt : in std_logic_vector(1 downto 0);
cpi_d_trap : in std_ulogic;
cpi_d_annul : in std_ulogic;
cpi_d_pv : in std_ulogic;
cpi_a_pc : in std_logic_vector(31 downto 0);
cpi_a_inst : in std_logic_vector(31 downto 0);
cpi_a_cnt : in std_logic_vector(1 downto 0);
cpi_a_trap : in std_ulogic;
cpi_a_annul : in std_ulogic;
cpi_a_pv : in std_ulogic;
cpi_e_pc : in std_logic_vector(31 downto 0);
cpi_e_inst : in std_logic_vector(31 downto 0);
cpi_e_cnt : in std_logic_vector(1 downto 0);
cpi_e_trap : in std_ulogic;
cpi_e_annul : in std_ulogic;
cpi_e_pv : in std_ulogic;
cpi_m_pc : in std_logic_vector(31 downto 0);
cpi_m_inst : in std_logic_vector(31 downto 0);
cpi_m_cnt : in std_logic_vector(1 downto 0);
cpi_m_trap : in std_ulogic;
cpi_m_annul : in std_ulogic;
cpi_m_pv : in std_ulogic;
cpi_x_pc : in std_logic_vector(31 downto 0);
cpi_x_inst : in std_logic_vector(31 downto 0);
cpi_x_cnt : in std_logic_vector(1 downto 0);
cpi_x_trap : in std_ulogic;
cpi_x_annul : in std_ulogic;
cpi_x_pv : in std_ulogic;
cpi_lddata : in std_logic_vector(31 downto 0); -- load data
cpi_dbg_enable : in std_ulogic;
cpi_dbg_write : in std_ulogic;
cpi_dbg_fsr : in std_ulogic; -- FSR access
cpi_dbg_addr : in std_logic_vector(4 downto 0);
cpi_dbg_data : in std_logic_vector(31 downto 0);
cpo_data : out std_logic_vector(31 downto 0); -- store data
cpo_exc : out std_logic; -- FP exception
cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes
cpo_ccv : out std_ulogic; -- FP condition codes valid
cpo_ldlock : out std_logic; -- FP pipeline hold
cpo_holdn : out std_ulogic;
cpo_dbg_data : out std_logic_vector(31 downto 0);
rfi1_rd1addr : out std_logic_vector(3 downto 0);
rfi1_rd2addr : out std_logic_vector(3 downto 0);
rfi1_wraddr : out std_logic_vector(3 downto 0);
rfi1_wrdata : out std_logic_vector(31 downto 0);
rfi1_ren1 : out std_ulogic;
rfi1_ren2 : out std_ulogic;
rfi1_wren : out std_ulogic;
rfi2_rd1addr : out std_logic_vector(3 downto 0);
rfi2_rd2addr : out std_logic_vector(3 downto 0);
rfi2_wraddr : out std_logic_vector(3 downto 0);
rfi2_wrdata : out std_logic_vector(31 downto 0);
rfi2_ren1 : out std_ulogic;
rfi2_ren2 : out std_ulogic;
rfi2_wren : out std_ulogic;
rfo1_data1 : in std_logic_vector(31 downto 0);
rfo1_data2 : in std_logic_vector(31 downto 0);
rfo2_data1 : in std_logic_vector(31 downto 0);
rfo2_data2 : in std_logic_vector(31 downto 0)
);
end component;
component leon3ft_net
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic
);
end component;
component ftmctrl_net
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
tech : integer := 0
);
port (
rst: in Std_ULogic;
clk: in Std_ULogic;
ahbsi: in ahb_slv_in_type;
ahbso: out ahb_slv_out_type;
apbi: in apb_slv_in_type;
apbo: out apb_slv_out_type;
memi_data: in Std_Logic_Vector(31 downto 0);
memi_brdyn: in Std_Logic;
memi_bexcn: in Std_Logic;
memi_writen: in Std_Logic;
memi_wrn: in Std_Logic_Vector(3 downto 0);
memi_bwidth: in Std_Logic_Vector(1 downto 0);
memi_sd: in Std_Logic_Vector(63 downto 0);
memi_cb: in Std_Logic_Vector(7 downto 0);
memi_scb: in Std_Logic_Vector(7 downto 0);
memi_edac: in Std_Logic;
memo_address: out Std_Logic_Vector(31 downto 0);
memo_data: out Std_Logic_Vector(31 downto 0);
memo_sddata: out Std_Logic_Vector(63 downto 0);
memo_ramsn: out Std_Logic_Vector(7 downto 0);
memo_ramoen: out Std_Logic_Vector(7 downto 0);
memo_ramn: out Std_ULogic;
memo_romn: out Std_ULogic;
memo_mben: out Std_Logic_Vector(3 downto 0);
memo_iosn: out Std_Logic;
memo_romsn: out Std_Logic_Vector(7 downto 0);
memo_oen: out Std_Logic;
memo_writen: out Std_Logic;
memo_wrn: out Std_Logic_Vector(3 downto 0);
memo_bdrive: out Std_Logic_Vector(3 downto 0);
memo_vbdrive: out Std_Logic_Vector(31 downto 0);
memo_svbdrive: out Std_Logic_Vector(63 downto 0);
memo_read: out Std_Logic;
memo_sa: out Std_Logic_Vector(14 downto 0);
memo_cb: out Std_Logic_Vector(7 downto 0);
memo_scb: out Std_Logic_Vector(7 downto 0);
memo_vcdrive: out Std_Logic_Vector(7 downto 0);
memo_svcdrive: out Std_Logic_Vector(7 downto 0);
memo_ce: out Std_ULogic;
sdo_sdcke: out Std_Logic_Vector( 1 downto 0);
sdo_sdcsn: out Std_Logic_Vector( 1 downto 0);
sdo_sdwen: out Std_ULogic;
sdo_rasn: out Std_ULogic;
sdo_casn: out Std_ULogic;
sdo_dqm: out Std_Logic_Vector( 7 downto 0);
wpo_wprothit: in Std_ULogic);
end component;
component ssrctrl_net
generic (
tech: Integer := 0;
bus16: Integer := 1);
port (
rst: in Std_Logic;
clk: in Std_Logic;
n_ahbsi_hsel: in Std_Logic_Vector(0 to 15);
n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hwrite: in Std_Logic;
n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0);
n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0);
n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0);
n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hready: in Std_Logic;
n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0);
n_ahbsi_hmastlock:in Std_Logic;
n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3);
n_ahbsi_hcache: in Std_Logic;
n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0);
n_ahbso_hready: out Std_Logic;
n_ahbso_hresp: out Std_Logic_Vector(1 downto 0);
n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0);
n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0);
n_ahbso_hcache: out Std_Logic;
n_ahbso_hirq: out Std_Logic_Vector(31 downto 0);
n_apbi_psel: in Std_Logic_Vector(0 to 15);
n_apbi_penable: in Std_Logic;
n_apbi_paddr: in Std_Logic_Vector(31 downto 0);
n_apbi_pwrite: in Std_Logic;
n_apbi_pwdata: in Std_Logic_Vector(31 downto 0);
n_apbi_pirq: in Std_Logic_Vector(31 downto 0);
n_apbo_prdata: out Std_Logic_Vector(31 downto 0);
n_apbo_pirq: out Std_Logic_Vector(31 downto 0);
n_sri_data: in Std_Logic_Vector(31 downto 0);
n_sri_brdyn: in Std_Logic;
n_sri_bexcn: in Std_Logic;
n_sri_writen: in Std_Logic;
n_sri_wrn: in Std_Logic_Vector(3 downto 0);
n_sri_bwidth: in Std_Logic_Vector(1 downto 0);
n_sri_sd: in Std_Logic_Vector(63 downto 0);
n_sri_cb: in Std_Logic_Vector(7 downto 0);
n_sri_scb: in Std_Logic_Vector(7 downto 0);
n_sri_edac: in Std_Logic;
n_sro_address: out Std_Logic_Vector(31 downto 0);
n_sro_data: out Std_Logic_Vector(31 downto 0);
n_sro_sddata: out Std_Logic_Vector(63 downto 0);
n_sro_ramsn: out Std_Logic_Vector(7 downto 0);
n_sro_ramoen: out Std_Logic_Vector(7 downto 0);
n_sro_ramn: out Std_Logic;
n_sro_romn: out Std_Logic;
n_sro_mben: out Std_Logic_Vector(3 downto 0);
n_sro_iosn: out Std_Logic;
n_sro_romsn: out Std_Logic_Vector(7 downto 0);
n_sro_oen: out Std_Logic;
n_sro_writen: out Std_Logic;
n_sro_wrn: out Std_Logic_Vector(3 downto 0);
n_sro_bdrive: out Std_Logic_Vector(3 downto 0);
n_sro_vbdrive: out Std_Logic_Vector(31 downto 0);
n_sro_svbdrive: out Std_Logic_Vector(63 downto 0);
n_sro_read: out Std_Logic;
n_sro_sa: out Std_Logic_Vector(14 downto 0);
n_sro_cb: out Std_Logic_Vector(7 downto 0);
n_sro_scb: out Std_Logic_Vector(7 downto 0);
n_sro_vcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_svcdrive: out Std_Logic_Vector(7 downto 0);
n_sro_ce: out Std_Logic);
end component;
end;
|
----------------------------------------------------------------------------------
-- Óñòðîéñòâî: êíîïêè
-- Êîä: 0x03
-- --------- ---------- ---------- --------- ------- ------- ------- -------
-- | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
-- |-------------------------------------------------------------------------|
-- | PB_WEST | PB_SOUTH | PB_NORTH | PB_EAST | SW[3] | SW[2] | SW[1] | SW[0] |
-- --------- ---------- ---------- --------- ------- ------- ------- -------
-- PB - push button; SW - switch button
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity web_button is
port (
data_o: out std_logic_vector(7 downto 0); -- âûâîäèò ñîñòîÿíèÿ êíîïîê
rs232_data_i: in std_logic_vector(7 downto 0); -- äàííûå, îò êíîïîê ñ êîì ïîðòà
physical_data_i: in std_logic_vector(7 downto 0); -- äàííûå ñ ôèçè÷åñêèõ êíîïîê
rst_i: in std_logic;
clk: in std_logic
);
end web_button;
architecture BtnArch of web_button is
signal physical_data_r0, physical_data_r1: std_logic_vector(7 downto 0);
begin
proc: process(clk, rst_i)
variable store_rs232_data_i: integer := 0;
variable store_physical_data_i: integer := 0;
--variable init_flag: boolean := true;
begin
if rst_i = '1' then
--init_flag := false;
store_rs232_data_i := to_integer(unsigned(rs232_data_i));
store_physical_data_i := to_integer(unsigned(physical_data_r1));
physical_data_r0 <= (others =>'0');
physical_data_r1 <= (others =>'0');
elsif rising_edge(clk) then
physical_data_r0 <= physical_data_i;
physical_data_r1<=physical_data_r0;
-- åñëè äàííûå äëÿ êíîïîê ïðèøëè ñ êîì ïîðòà
if store_rs232_data_i /= to_integer(unsigned(rs232_data_i)) then
store_rs232_data_i := to_integer(unsigned(rs232_data_i));
data_o <= rs232_data_i;
-- èíà÷å åñëè äàííûå ïðèøëè îò ôèçè÷åñêèõ êíîïîê
elsif store_physical_data_i /= to_integer(unsigned(physical_data_r1)) then
store_physical_data_i := to_integer(unsigned(physical_data_r1));
data_o <= physical_data_r1;
end if;
end if;
end process;
end BtnArch; |
architecture RTL of BLOCK_EXAMPLE is
begin
-- correct block format
BLK : block is
generic (
A : std_logic;
B : integer;
E, F : positive
);
generic map (
A => B,
B => C,
E => X,
F => Z
);
port (
A : std_logic;
B : integer;
E, F : positive
);
port map (
A => B,
B => C,
E => X,
F => Z
);
begin
end block BLK;
-- correct block format
BLK : block is
generic map (
A => B,
B => C,
E => X,
F => Z
);
port (
A : std_logic;
B : integer;
E, F : positive
);
port map (
A => B,
B => C,
E => X,
F => Z
);
begin
end block BLK;
-- correct block format
BLK : block is
generic (
A : std_logic;
B : integer;
E, F : positive
);
port (
A : std_logic;
B : integer;
E, F : positive
);
port map (
A => B,
B => C,
E => X,
F => Z
);
begin
end block BLK;
-- correct block format
BLK : block is
generic (
A : std_logic;
B : integer;
E, F : positive
);
generic map (
A => B,
B => C,
E => X,
F => Z
);
port map (
A => B,
B => C,
E => X,
F => Z
);
begin
end block BLK;
-- correct block format
BLK : block is
generic (
A : std_logic;
B : integer;
E, F : positive
);
generic map (
A => B,
B => C,
E => X,
F => Z
);
port (
A : std_logic;
B : integer;
E, F : positive
);
begin
end block BLK;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
entity tdp_ram is
generic (
ADDRWIDTH_A : positive := 12;
WIDTH_A : positive := 8;
ADDRWIDTH_B : positive := 10;
WIDTH_B : positive := 32;
COL_WIDTH : positive := 8
);
port (
clk_a : in std_logic;
read_a : in std_logic;
write_a : in std_logic;
byteen_a : in std_logic_vector(WIDTH_A/COL_WIDTH - 1 downto 0);
addr_a : in std_logic_vector(ADDRWIDTH_A - 1 downto 0);
data_read_a : out std_logic_vector(WIDTH_A - 1 downto 0);
data_write_a : in std_logic_vector(WIDTH_A - 1 downto 0);
clk_b : in std_logic;
read_b : in std_logic;
write_b : in std_logic;
byteen_b : in std_logic_vector(WIDTH_B/COL_WIDTH - 1 downto 0);
addr_b : in std_logic_vector(ADDRWIDTH_B - 1 downto 0);
data_read_b : out std_logic_vector(WIDTH_B - 1 downto 0);
data_write_b : in std_logic_vector(WIDTH_B - 1 downto 0)
);
end tdp_ram;
architecture behavioral of tdp_ram is
function log2(val : INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2 ** i)) then
res := i;
exit;
end if;
end loop;
return res;
end function log2;
function eq_assert(x : integer; y : integer) return integer is
begin
assert x = y;
return x;
end function eq_assert;
constant COLS_A : positive := WIDTH_A / COL_WIDTH;
constant COLS_B : positive := WIDTH_B / COL_WIDTH;
constant TOTAL_COLS : positive := eq_assert(COLS_A * 2 ** ADDRWIDTH_A, COLS_B * 2 ** ADDRWIDTH_B);
constant EXTRA_ADDR_BITS_A : positive := log2(COLS_A);
constant EXTRA_ADDR_BITS_B : positive := log2(COLS_B);
type ram_t is array(0 to TOTAL_COLS - 1) of std_logic_vector(COL_WIDTH - 1 downto 0);
shared variable store : ram_t := (others => (others => '0'));
signal reg_a : std_logic_vector(WIDTH_A - 1 downto 0);
signal reg_b : std_logic_vector(WIDTH_B - 1 downto 0);
begin
assert WIDTH_A mod COL_WIDTH = 0 and
WIDTH_B mod COL_WIDTH = 0 and
2 ** (ADDRWIDTH_A + EXTRA_ADDR_BITS_A) = TOTAL_COLS and
2 ** (ADDRWIDTH_B + EXTRA_ADDR_BITS_B) = TOTAL_COLS
report "Both WIDTH_A and WIDTH_B have to be a power-of-two multiple of COL_WIDTH"
severity failure;
process(clk_a)
begin
if rising_edge(clk_a) then
for i in 0 to COLS_A - 1 loop
if write_a = '1' and byteen_a(i) = '1' then
store(to_integer(unsigned(addr_a) & to_unsigned(i, EXTRA_ADDR_BITS_A))) :=
data_write_a((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH);
end if;
if read_a = '1' then
reg_a((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH) <=
store(to_integer(unsigned(addr_a) & to_unsigned(i, EXTRA_ADDR_BITS_A)));
end if;
end loop;
data_read_a <= reg_a;
end if;
end process;
process(clk_b)
begin
if rising_edge(clk_b) then
for i in 0 to COLS_B - 1 loop
if write_b = '1' and byteen_b(i) = '1' then
store(to_integer(unsigned(addr_b) & to_unsigned(i, EXTRA_ADDR_BITS_B))) :=
data_write_b((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH);
end if;
if read_b = '1' then
reg_b((i+1) * COL_WIDTH - 1 downto i * COL_WIDTH) <=
store(to_integer(unsigned(addr_b) & to_unsigned(i, EXTRA_ADDR_BITS_B)));
end if;
end loop;
data_read_b <= reg_b;
end if;
end process;
end behavioral;
|
--
-- 16-bit Timer for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
entity timer is
generic (
TSCENABLED: boolean := false;
PWMCOUNT: integer range 1 to 8 := 2;
WIDTH: integer range 1 to 32 := 16;
PRESCALER_ENABLED: boolean := true;
BUFFERS: boolean := true
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(5 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o: out std_logic;
pwm_out: out std_logic_vector(PWMCOUNT-1 downto 0)
);
end entity timer;
architecture behave of timer is
component prescaler is
port (
clk: in std_logic;
rst: in std_logic;
prescale: in std_logic_vector(2 downto 0);
event: out std_logic
);
end component prescaler;
type singlepwmregs is record
cmplow: unsigned(WIDTH-1 downto 0);
cmphigh: unsigned(WIDTH-1 downto 0);
en: std_logic;
end record;
type pwmregs is array(PWMCOUNT-1 downto 0) of singlepwmregs;
type timerregs is record
cnt: unsigned(WIDTH-1 downto 0); -- current timer counter value
cmp: unsigned(WIDTH-1 downto 0); -- top timer compare value
ccm: std_logic; -- clear on compare match
en: std_logic; -- enable
dir: std_logic; -- direction
ien: std_logic; -- interrupt enable
intr: std_logic; -- interrupt
pres: std_logic_vector(2 downto 0); -- Prescaler
updp: std_logic_vector(1 downto 0);
presrst: std_logic;
pwmr: pwmregs;
pwmrb:pwmregs;
end record;
constant UPDATE_NOW: std_logic_vector(1 downto 0) := "00";
constant UPDATE_ZERO_SYNC: std_logic_vector(1 downto 0) := "01";
constant UPDATE_LATER: std_logic_vector(1 downto 0) := "10";
signal tmr0_prescale_rst: std_logic;
--signal tmr0_prescale: std_logic_vector(2 downto 0);
signal tmr0_prescale_event: std_logic;
signal TSC_q: unsigned(wordSize-1 downto 0);
signal tmrr: timerregs;
function eq(a:std_logic_vector; b:std_logic_vector) return std_logic is
begin
if a=b then
return '1';
else
return '0';
end if;
end function;
signal do_interrupt: std_logic;
begin
wb_inta_o <= tmrr.intr;
-- comp <= tmrr.cout;
wb_ack_o <= wb_cyc_i and wb_stb_i;
pr: if PRESCALER_ENABLED generate
tmr0prescale_inst: prescaler
port map (
clk => wb_clk_i,
rst => tmrr.presrst,
prescale=> tmrr.pres,
event => tmr0_prescale_event
);
end generate;
npr: if not PRESCALER_ENABLED generate
tmr0_prescale_event<='1';
end generate;
tsc_process: if TSCENABLED generate
TSCgen: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
TSC_q <= (others => '0');
else
TSC_q <= TSC_q + 1;
end if;
end if;
end process;
end generate;
-- Read
process(wb_adr_i, tmrr,TSC_q)
begin
case wb_adr_i(1 downto 0) is
when "00" =>
wb_dat_o <= (others => Undefined);
wb_dat_o(0) <= tmrr.en;
wb_dat_o(1) <= tmrr.ccm;
wb_dat_o(2) <= tmrr.dir;
wb_dat_o(3) <= tmrr.ien;
wb_dat_o(6 downto 4) <= tmrr.pres;
wb_dat_o(7) <= tmrr.intr;
wb_dat_o(10 downto 9) <= tmrr.updp;
when "01" =>
wb_dat_o <= (others => '0');
wb_dat_o(WIDTH-1 downto 0) <= std_logic_vector(tmrr.cnt);
when "10" =>
wb_dat_o <= (others => '0');
wb_dat_o(WIDTH-1 downto 0) <= std_logic_vector(tmrr.cmp);
when others =>
if TSCENABLED then
wb_dat_o <= (others => '0');
wb_dat_o <= std_logic_vector(TSC_q);
else
wb_dat_o <= (others => DontCareValue );
end if;
end case;
end process;
process(wb_clk_i, tmrr, wb_rst_i,wb_cyc_i,wb_stb_i,wb_we_i,wb_adr_i,wb_dat_i,tmrr,do_interrupt,tmr0_prescale_event)
variable w: timerregs;
variable write_ctrl: std_logic;
variable write_cmp: std_logic;
variable write_cnt: std_logic;
variable write_pwm: std_logic;
variable ovf: std_logic;
variable pwmindex: integer;
begin
w := tmrr;
-- These are just helpers
write_ctrl := wb_cyc_i and wb_stb_i and wb_we_i and eq(wb_adr_i,"000000");
write_cnt := wb_cyc_i and wb_stb_i and wb_we_i and eq(wb_adr_i,"000001");
write_cmp := wb_cyc_i and wb_stb_i and wb_we_i and eq(wb_adr_i,"000010");
write_pwm := wb_cyc_i and wb_stb_i and wb_we_i and wb_adr_i(5);
ovf:='0';
if tmrr.cnt = tmrr.cmp then
ovf:='1';
end if;
do_interrupt <= '0';
if wb_rst_i='1' then
w.en := '0';
w.ccm := '0';
w.dir := '0';
w.ien := '0';
w.pres := (others => '0');
w.presrst := '1';
w.updp := UPDATE_ZERO_SYNC;
for i in 0 to PWMCOUNT-1 loop
w.pwmrb(i).en :='0';
w.pwmr(i).en :='0';
end loop;
else
if do_interrupt='1' then
w.intr := '1';
end if;
w.presrst := '0';
-- Wishbone access
if write_ctrl='1' then
w.en := wb_dat_i(0);
w.ccm := wb_dat_i(1);
w.dir := wb_dat_i(2);
w.ien := wb_dat_i(3);
w.pres:= wb_dat_i(6 downto 4);
w.updp := wb_dat_i(10 downto 9);
if wb_dat_i(7)='0' then
w.intr:='0';
end if;
end if;
if write_cmp='1' then
w.cmp := unsigned(wb_dat_i(WIDTH-1 downto 0));
end if;
if write_cnt='1' then
w.cnt := unsigned(wb_dat_i(WIDTH-1 downto 0));
else
if tmrr.en='1' and tmr0_prescale_event='1' then
-- If output matches, set interrupt
if ovf='1' then
if tmrr.ien='1' then
do_interrupt<='1';
end if;
end if;
-- CCM
if tmrr.ccm='1' and ovf='1' then
w.cnt := (others => '0');
else
if tmrr.dir='1' then
w.cnt := tmrr.cnt + 1;
else
w.cnt := tmrr.cnt - 1;
end if;
end if;
end if;
end if;
end if;
if write_pwm='1' then
for i in 0 to PWMCOUNT-1 loop
if wb_adr_i(4 downto 2) = std_logic_vector(to_unsigned(i,3)) then
if BUFFERS then
-- Write values to this PWM
case wb_adr_i(1 downto 0) is
when "00" =>
w.pwmrb(i).cmplow := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "01" =>
w.pwmrb(i).cmphigh := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "10" =>
w.pwmrb(i).en := wb_dat_i(0);
when "11" =>
-- This is sync pulse for UPDATE_LATER
when others =>
end case;
else
-- Write values to this PWM
case wb_adr_i(1 downto 0) is
when "00" =>
w.pwmr(i).cmplow := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "01" =>
w.pwmr(i).cmphigh := unsigned(wb_dat_i(WIDTH-1 downto 0));
when "10" =>
w.pwmr(i).en := wb_dat_i(0);
when "11" =>
-- This is sync pulse for UPDATE_LATER
when others =>
end case;
end if;
end if;
end loop;
end if;
if BUFFERS then
for i in 0 to PWMCOUNT-1 loop
case tmrr.updp is
when UPDATE_NOW =>
w.pwmr(i) := tmrr.pwmrb(i);
when UPDATE_ZERO_SYNC =>
if ovf='1' then
w.pwmr(i) := tmrr.pwmrb(i);
end if;
when UPDATE_LATER =>
--if wb_adr_i(3 downto 2) = std_logic_vector(to_unsigned(i,2)) then
-- if wb_adr_i(1 downto 0)="11" then
-- w.pwmr(i) := tmrr.pwmrb(i);
-- end if;
-- end if;
when others =>
--w.pwmr(i) := tmrr.pwmrb(i);
end case;
end loop;
end if;
if rising_edge(wb_clk_i) then
tmrr <= w;
for i in 0 to PWMCOUNT-1 loop
if tmrr.pwmr(i).en='1' then
if tmrr.cnt >= tmrr.pwmr(i).cmplow and tmrr.cnt<tmrr.pwmr(i).cmphigh then
pwm_out(i) <= '1';
else
pwm_out(i) <= '0';
end if;
else
pwm_out(i)<='0';
end if;
end loop;
end if;
end process;
end behave;
|
-- NEED RESULT: ARCH00406.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00406.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00406.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00406: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00406: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00406: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00406: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00406: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00406: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00406: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00406: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00406: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00406: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00406: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00406: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00406
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00406(ARCH00406)
-- ENT00406_Test_Bench(ARCH00406_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00406 is
end ENT00406 ;
--
--
architecture ARCH00406 of ENT00406 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec2_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec3_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_rec2_vector_select : select_type := 1 ;
signal st_rec3_vector_select : select_type := 1 ;
--
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_2(lowb).f2 after 10 ns,
-- c_st_rec1_vector_1(lowb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00406.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec1_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_1(lowb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00406" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 4 ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_1(lowb).f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00406" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 5 ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec1_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00406" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_1(lowb).f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00406" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00406" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
wait until (not s_st_rec1_vector(lowb).f2'Quiet) and
(s_st_rec1_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_2(lowb).f2 after 10 ns,
c_st_rec1_vector_1(lowb).f2 after 20 ns
when st_rec1_vector_select = 1 else
--
c_st_rec1_vector_2(lowb).f2 after 10 ns ,
c_st_rec1_vector_1(lowb).f2 after 20 ns ,
c_st_rec1_vector_2(lowb).f2 after 30 ns ,
c_st_rec1_vector_1(lowb).f2 after 40 ns
when st_rec1_vector_select = 2 else
--
c_st_rec1_vector_1(lowb).f2 after 5 ns
when st_rec1_vector_select = 3 else
--
c_st_rec1_vector_1(lowb).f2 after 100 ns
when st_rec1_vector_select = 4 else
--
c_st_rec1_vector_2(lowb).f2 after 10 ns ,
c_st_rec1_vector_1(lowb).f2 after 20 ns ,
c_st_rec1_vector_2(lowb).f2 after 30 ns ,
c_st_rec1_vector_1(lowb).f2 after 40 ns
when st_rec1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_rec1_vector_1(lowb).f2 after 40 ns ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_rec2_vector_cnt is
when 0
=> null ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_2(lowb).f2 after 10 ns,
-- c_st_rec2_vector_1(lowb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00406.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_vector_select <= transport 2 ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec2_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec2_vector_select <= transport 3 ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_1(lowb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00406" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_vector_select <= transport 4 ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_1(lowb).f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00406" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec2_vector_select <= transport 5 ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec2_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00406" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_1(lowb).f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00406" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00406" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec2_vector_savt <= transport Std.Standard.Now ;
chk_st_rec2_vector <= transport s_st_rec2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_vector_cnt <= transport s_st_rec2_vector_cnt + 1 ;
wait until (not s_st_rec2_vector(lowb).f2'Quiet) and
(s_st_rec2_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_2(lowb).f2 after 10 ns,
c_st_rec2_vector_1(lowb).f2 after 20 ns
when st_rec2_vector_select = 1 else
--
c_st_rec2_vector_2(lowb).f2 after 10 ns ,
c_st_rec2_vector_1(lowb).f2 after 20 ns ,
c_st_rec2_vector_2(lowb).f2 after 30 ns ,
c_st_rec2_vector_1(lowb).f2 after 40 ns
when st_rec2_vector_select = 2 else
--
c_st_rec2_vector_1(lowb).f2 after 5 ns
when st_rec2_vector_select = 3 else
--
c_st_rec2_vector_1(lowb).f2 after 100 ns
when st_rec2_vector_select = 4 else
--
c_st_rec2_vector_2(lowb).f2 after 10 ns ,
c_st_rec2_vector_1(lowb).f2 after 20 ns ,
c_st_rec2_vector_2(lowb).f2 after 30 ns ,
c_st_rec2_vector_1(lowb).f2 after 40 ns
when st_rec2_vector_select = 5 else
--
-- Last transaction above is marked
c_st_rec2_vector_1(lowb).f2 after 40 ns ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_rec3_vector_cnt is
when 0
=> null ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_2(highb).f3 after 10 ns,
-- c_st_rec3_vector_1(highb).f3 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_2(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00406.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_vector_select <= transport 2 ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_2(highb).f3 after 10 ns ,
-- c_st_rec3_vector_1(highb).f3 after 20 ns ,
-- c_st_rec3_vector_2(highb).f3 after 30 ns ,
-- c_st_rec3_vector_1(highb).f3 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_2(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec3_vector_select <= transport 3 ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_1(highb).f3 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00406" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_vector_select <= transport 4 ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_1(highb).f3 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00406" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_vector_select <= transport 5 ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_2(highb).f3 after 10 ns ,
-- c_st_rec3_vector_1(highb).f3 after 20 ns ,
-- c_st_rec3_vector_2(highb).f3 after 30 ns ,
-- c_st_rec3_vector_1(highb).f3 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_2(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00406" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_1(highb).f3 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00406" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00406" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_vector_savt <= transport Std.Standard.Now ;
chk_st_rec3_vector <= transport s_st_rec3_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_vector_cnt <= transport s_st_rec3_vector_cnt + 1 ;
wait until (not s_st_rec3_vector(highb).f3'Quiet) and
(s_st_rec3_vector_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_rec3_vector(highb).f3 <=
c_st_rec3_vector_2(highb).f3 after 10 ns,
c_st_rec3_vector_1(highb).f3 after 20 ns
when st_rec3_vector_select = 1 else
--
c_st_rec3_vector_2(highb).f3 after 10 ns ,
c_st_rec3_vector_1(highb).f3 after 20 ns ,
c_st_rec3_vector_2(highb).f3 after 30 ns ,
c_st_rec3_vector_1(highb).f3 after 40 ns
when st_rec3_vector_select = 2 else
--
c_st_rec3_vector_1(highb).f3 after 5 ns
when st_rec3_vector_select = 3 else
--
c_st_rec3_vector_1(highb).f3 after 100 ns
when st_rec3_vector_select = 4 else
--
c_st_rec3_vector_2(highb).f3 after 10 ns ,
c_st_rec3_vector_1(highb).f3 after 20 ns ,
c_st_rec3_vector_2(highb).f3 after 30 ns ,
c_st_rec3_vector_1(highb).f3 after 40 ns
when st_rec3_vector_select = 5 else
--
-- Last transaction above is marked
c_st_rec3_vector_1(highb).f3 after 40 ns ;
--
end ARCH00406 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00406_Test_Bench is
end ENT00406_Test_Bench ;
--
--
architecture ARCH00406_Test_Bench of ENT00406_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00406 ( ARCH00406 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00406_Test_Bench ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity func08b is
port (v : std_ulogic_vector (3 downto 0);
r : out integer);
end func08b;
architecture behav of func08b is
function fls (val: std_ulogic_vector(3 downto 0)) return integer is
variable ret: integer;
begin
ret := 4;
for i in val'range loop
if val(i) = '1' then
ret := 3 - i;
exit;
end if;
end loop;
return ret;
end;
begin
r <= fls(v);
end behav;
|
-------------------------------------------------------------------------------
--! @file openmac-rtl-ea.vhd
--
--! @brief openMAC core
--
--! @details This is the openMAC core file implementing the MAC functionality.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2009
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity openmac is
generic (
--! Dma address high bit
gDmaHighAddr : in integer := 16;
--! Enable MAC timer
gTimerEnable : in boolean := false;
--! Enable Timer triggered Tx
gTimerTrigTx : in boolean := false;
--! Enable Auto-response delay
gAutoTxDel : in boolean := false
);
port (
--! Reset
iRst : in std_logic;
--! Clock (RMII, 50 MHz)
iClk : in std_logic;
--! Write to RAM or content (low-active)
inWrite : in std_logic;
--! Select RAM (descriptor and Rx filter)
iSelectRam : in std_logic;
--! Select content (Tx/Rx status/control registers)
iSelectCont : in std_logic;
--! Byteenable (low-active)
inByteenable : in std_logic_vector(1 downto 0);
--! Address for RAM or content
iAddress : in std_logic_vector(10 downto 1);
--! Writedata to RAM or content
iWritedata : in std_logic_vector(15 downto 0);
--! Readdata from RAM or content
oReaddata : out std_logic_vector(15 downto 0);
--! Tx interrupt request (low-active)
onTxIrq : out std_logic;
--! Rx interrupt request (low-active)
onRxIrq : out std_logic;
--! Tx begin interrupt request (low-active)
onTxBegIrq : out std_logic;
--! DMA read transfer for frame done
oDmaReadDone : out std_logic;
--! DMA write transfer for frame done
oDmaWriteDone : out std_logic;
--! DMA request strobe
oDmaReq : out std_logic;
--! DMA write strobe (low-active)
onDmaWrite : out std_logic;
--! DMA acknowledge input
iDmaAck : in std_logic;
--! DMA request overflow flag
oDmaReqOverflow : out std_logic;
--! DMA read request length
oDmaReadLength : out std_logic_vector(11 downto 0);
--! DMA address
oDmaAddress : out std_logic_vector(gDmaHighAddr downto 1);
--! DMA writedata
oDmaWritedata : out std_logic_vector(15 downto 0);
--! DMA readdata
iDmaReaddata : in std_logic_vector(15 downto 0);
--! RMII Rx data
iRxData : in std_logic_vector(1 downto 0);
--! RMII Rx data valid
iRxDv : in std_logic;
--! RMII Tx data
oTxData : out std_logic_vector(1 downto 0);
--! RMII Tx enable
oTxEn : out std_logic;
--! Hub Rx port (connect to openHUB)
iHubRxPort : in std_logic_vector(1 downto 0);
--! MAC Time
oMacTime : out std_logic_vector(31 downto 0)
);
end entity openmac;
architecture struct OF openmac is
signal Rx_Dv : std_logic;
signal R_Req : std_logic;
signal Auto_Desc : std_logic_vector( 3 downto 0);
signal Zeit : std_logic_vector(31 downto 0);
signal Tx_Dma_Req : std_logic;
signal Rx_Dma_Req : std_logic;
signal Tx_Dma_Ack : std_logic;
signal Rx_Dma_Ack : std_logic;
signal Tx_Ram_Dat : std_logic_vector(15 downto 0);
signal Rx_Ram_Dat : std_logic_vector(15 downto 0);
signal Tx_Dma_Len : std_logic_vector(11 downto 0);
signal Tx_Reg : std_logic_vector(15 downto 0);
signal Rx_Reg : std_logic_vector(15 downto 0);
signal Dma_Tx_Addr : std_logic_vector(oDmaAddress'range);
signal Dma_Rx_Addr : std_logic_vector(oDmaAddress'range);
signal Dma_Req_s : std_logic;
signal Dma_Rw_s : std_logic;
signal halfDuplex : std_logic; -- cActivated ... MAC in half-duplex mode
signal Tx_Active : std_logic; -- cActivated ... TX = Data or CRC
signal Tx_Dma_Very1stOverflow : std_logic; -- cActivated ... very first TX DMA overflow
signal Tx_Col : std_logic;
signal Sel_Tx_Ram : std_logic;
signal Sel_Tx_Reg : std_logic;
signal Tx_LatchH : std_logic_vector(7 downto 0);
signal Tx_LatchL : std_logic_vector(7 downto 0);
begin
oReaddata <= Tx_Ram_Dat when iSelectRam = '1' and Sel_Tx_Ram = '1' else
Rx_Ram_Dat when iSelectRam = '1' else
Tx_Reg when iSelectCont = '1' and Sel_Tx_Reg = '1' else
Rx_Reg;
oMacTime <= Zeit;
oDmaReadLength <= Tx_Dma_Len + 4;
b_DmaObserver : block
signal dmaObserverCounter, dmaObserverCounterNext : std_logic_vector(2 downto 0);
constant cDmaObserverCounterHalf : std_logic_vector(dmaObserverCounter'range) := "110"; --every 8th cycle
constant cDmaObserverCounterFull : std_logic_vector(dmaObserverCounter'range) := "010"; --every 4th cycle
begin
process(iClk, iRst)
begin
if iRst = '1' then
dmaObserverCounter <= (others => cInactivated);
elsif rising_edge(iClk) then
dmaObserverCounter <= dmaObserverCounterNext;
end if;
end process;
oDmaReqOverflow <= --very first TX Dma transfer
Dma_Req_s when Tx_Dma_Very1stOverflow = cActivated and Tx_Active = cInactivated else
--RX Dma transfers and TX Dma transfers without the very first
Dma_Req_s when dmaObserverCounterNext = cDmaObserverCounterHalf and halfDuplex = cActivated else
Dma_Req_s when dmaObserverCounterNext = cDmaObserverCounterFull and halfDuplex = cInactivated else
cInactivated;
dmaObserverCounterNext <= --increment counter if DMA Read req (TX) during data and crc
dmaObserverCounter + 1 when Dma_Req_s = cActivated and Dma_Rw_s = cActivated
and Tx_Active = cActivated else
--increment counter if DMA Write req (RX)
dmaObserverCounter + 1 when Dma_Req_s = cActivated and Dma_Rw_s = cInactivated else
(others => cInactivated); --reset DmaObserverCounter if no oDmaReq
end block;
b_Dma: block
signal Rx_Dma : std_logic;
signal Tx_Dma : std_logic;
begin
oDmaReq <= Dma_Req_s;
Dma_Req_s <= '1' when (Tx_Dma_Req = '1' and Tx_Dma_Ack = '0') or Rx_Dma_Req = '1' else '0';
onDmaWrite <= Dma_Rw_s;
Dma_Rw_s <= '1' when (Rx_Dma = '0' and Tx_Dma_Req = '1' and Tx_Dma_Ack = '0') or Tx_Dma = '1' else '0';
oDmaAddress <= Dma_Tx_Addr when (Rx_Dma = '0' and Tx_Dma_Req = '1' and Tx_Dma_Ack = '0') or Tx_Dma = '1' else Dma_Rx_Addr;
Rx_Dma_Ack <= '1' when Rx_Dma = '1' and iDmaAck = '1' else '0';
pDmaArb: process( iClk, iRst ) is
begin
if iRst = '1' then
Rx_Dma <= '0'; Tx_Dma <= '0'; Tx_Dma_Ack <= '0';
Tx_LatchH <= (others => '0'); Tx_LatchL <= (others => '0');
Zeit <= (others => '0');
elsif rising_edge( iClk ) then
if gTimerEnable then
Zeit <= Zeit + 1;
end if;
Sel_Tx_Ram <= iAddress(8);
Sel_Tx_Reg <= not iAddress(3);
if iDmaAck = '0' then
if Rx_Dma = '0' and Tx_Dma_Req = '1' and Tx_Dma_Ack = '0' then Tx_Dma <= '1';
elsif Tx_Dma = '0' and Rx_Dma_Req = '1' then Rx_Dma <= '1';
end if;
else
if Rx_Dma = '1' and Tx_Dma_Req = '1' and Tx_Dma_Ack = '0' then Tx_Dma <= '1'; Rx_Dma <= '0';
elsif Tx_Dma = '1' and Rx_Dma_Req = '1' then Tx_Dma <= '0'; Rx_Dma <= '1';
else Tx_Dma <= '0'; Rx_Dma <= '0';
end if;
end if;
if Tx_Dma = '1' and iDmaAck = '1' then Tx_Dma_Ack <= '1';
else Tx_Dma_Ack <= '0';
end if;
if Tx_Dma_Ack = '1' then Tx_LatchL <= iDmaReaddata(15 downto 8);
Tx_LatchH <= iDmaReaddata( 7 downto 0);
end if;
end if;
end process pDmaArb;
end block b_Dma;
b_Full_Tx : block
type tTxState is (
sIdle,
sBop,
sPre,
sTxd,
sCrc,
sCol,
sJam
);
signal Sm_Tx : tTxState;
signal Start_Tx : std_logic;
signal ClrCol : std_logic;
signal Tx_On : std_logic;
signal Dibl_Cnt : std_logic_vector(1 downto 0);
signal F_End : std_logic;
signal Was_Col : std_logic;
signal Block_Col : std_logic;
signal Ipg_Cnt : std_logic_vector(7 downto 0);
signal Tx_Timer : std_logic_vector(7 downto 0);
alias Ipg : std_logic is Ipg_Cnt(7);
alias Tx_Time : std_logic is Tx_Timer(7);
signal Tx_Ipg : std_logic_vector(5 downto 0);
signal Tx_Count : std_logic_vector(11 downto 0);
signal Tx_En : std_logic;
signal F_Val : std_logic;
signal Tx_Half : std_logic;
signal Tx_Sr : std_logic_vector(7 downto 0);
signal F_TxB : std_logic_vector(7 downto 0);
signal Crc : std_logic_vector(31 downto 0);
signal CrcDin : std_logic_vector(1 downto 0);
signal Tx_Dat : std_logic_vector(1 downto 0);
signal Col_Cnt : std_logic_vector(3 downto 0);
signal Auto_Coll : std_logic;
signal Rnd_Num : std_logic_vector(9 downto 0);
signal Retry_Cnt : std_logic_vector(9 downto 0);
signal Max_Retry : std_logic_vector(3 downto 0);
begin
oTxEn <= Tx_En;
oTxData <= Tx_Dat;
halfDuplex <= Tx_Half;
Tx_Active <= cActivated when Sm_Tx = sTxd or Sm_Tx = sCrc else cInactivated;
pTxSm: process ( iClk, iRst ) is
begin
if iRst = '1' then
Sm_Tx <= sIdle;
elsif rising_edge( iClk ) then
if Sm_Tx = sIdle or Sm_Tx = sBop or Dibl_Cnt = "11" then
case Sm_Tx is
when sIdle => if Start_Tx = '1'
and (Tx_Half = '0' or Rx_Dv = '0')
and Ipg = '0' then Sm_Tx <= sBop; end if;
when sBop => Sm_Tx <= sPre;
when sPre => if Tx_Time = '1' then Sm_Tx <= sTxd; end if;
when sTxd => if Was_Col = '1' then Sm_Tx <= sCol;
elsif Tx_Count = 0 then Sm_Tx <= sCrc; end if;
when sCol => Sm_Tx <= sJam;
when sJam => if Tx_Time = '1' then Sm_Tx <= sIdle;
end if;
when sCrc => if Was_Col = '1' then Sm_Tx <= sCol;
elsif Tx_Time = '1' then Sm_Tx <= sIdle; end if;
when others => NULL;
end case;
end if;
end if;
end process pTxSm;
pTxCtl: process ( iClk, iRst ) is
variable vPreload : std_logic_vector(Tx_Timer'range);
variable vLoad : std_logic;
begin
if iRst = '1' then
Tx_Dat <= "00"; Tx_En <= '0'; Dibl_Cnt <= "00"; F_End <= '0'; F_Val <= '0'; Tx_Col <= '0'; Was_Col <= '0'; Block_Col <= '0';
Ipg_Cnt <= (others => '0'); Tx_Timer <= (others => '0'); Tx_Sr <= (others => '0');
elsif rising_edge( iClk ) then
if Sm_Tx = sBop then Dibl_Cnt <= "00";
else Dibl_Cnt <= Dibl_Cnt + 1;
end if;
if Tx_En = '1' then Ipg_Cnt <= "1" & conv_std_logic_vector( 44, 7);
elsif Rx_Dv = '1' and Tx_Half = '1' then Ipg_Cnt <= "10" & Tx_Ipg;
elsif Ipg = '1' then Ipg_Cnt <= Ipg_Cnt - 1;
end if;
if Dibl_Cnt = "11" and Sm_Tx = sCrc and Tx_Time = '1' then F_End <= '1';
elsif Dibl_Cnt = "11" and Sm_Tx = sCol then
if Col_Cnt = (Max_Retry - 1) then F_End <= '1';
elsif Col_Cnt < x"E" then Tx_Col <= '1';
else F_End <= '1';
end if;
else F_End <= '0';
Tx_Col <= '0';
end if;
if Tx_Half = '1' and Rx_Dv = '1'
and (Sm_Tx = sPre or Sm_Tx = sTxd) then Was_Col <= '1';
elsif Sm_Tx = sCol then Was_Col <= '0';
end if;
if Sm_Tx = sCol then Block_Col <= '1';
elsif Auto_Coll = '1' then Block_Col <= '0';
elsif Retry_Cnt = 0 then Block_Col <= '0';
end if;
if Dibl_Cnt = "10" and Sm_Tx = sPre and Tx_Time = '1' then F_Val <= '1';
elsif Dibl_Cnt = "10" and Sm_Tx = sTxd then F_Val <= '1';
else F_Val <= '0';
end if;
vLoad := '0';
if Sm_Tx = sBop then vPreload := x"06"; vLoad := '1';
elsif Sm_Tx = sTxd then vPreload := x"02"; vLoad := '1';
elsif Sm_Tx = sCol then vPreload := x"01"; vLoad := '1';
elsif Tx_Time = '1' then vPreload := x"3e"; vLoad := '1';
end if;
if Dibl_Cnt = "11" or Sm_Tx = sBop then
if vLoad = '1' then Tx_Timer <= vPreload;
else Tx_Timer <= Tx_Timer - 1;
end if;
end if;
if F_Val = '1' then Tx_Sr <= F_TxB;
else Tx_Sr <= "00" & Tx_Sr(7 downto 2);
end if;
if Sm_Tx = sPre then Tx_En <= '1';
elsif Sm_Tx = sIdle or (Sm_Tx = sJam and Tx_Time = '1') then Tx_En <= '0';
end if;
if Sm_Tx = sPre and Tx_Time = '1' and Dibl_Cnt = "11" then Tx_Dat <= "11";
elsif Sm_Tx = sPre then Tx_Dat <= "01";
elsif Sm_Tx = sTxd then Tx_Dat <= CrcDin;
elsif Sm_Tx = sCrc then Tx_Dat <= not Crc(30) & not Crc(31);
elsif Sm_Tx = sCol or Sm_Tx = sJam then Tx_Dat <= "11";
else Tx_Dat <= "00";
end if;
end if;
end process pTxCtl;
pBackDel: process ( iClk, iRst ) is
begin
if iRst = '1' then
Rnd_Num <= (others => '0');
Col_Cnt <= (others => '0');
Retry_Cnt <= (others => '0');
elsif rising_edge( iClk ) then
Rnd_Num <= Rnd_Num(8 downto 0) & (Rnd_Num(9) xor not Rnd_Num(2));
if ClrCol = '1' then Col_Cnt <= x"0";
elsif Dibl_Cnt = "11" and Sm_Tx = sCol then Col_Cnt <= Col_Cnt + 1;
end if;
if Dibl_Cnt = "11" then
if Tx_On = '0' or Auto_Coll = '1' then Retry_Cnt <= (others => '0');
elsif Sm_Tx = sCol then
for i in 0 to 9 loop
if Col_Cnt >= i then Retry_Cnt(i) <= Rnd_Num(i);
else Retry_Cnt(i) <= '0';
end if;
end loop;
elsif Sm_Tx /= sJam and Tx_Time = '1' and Retry_Cnt /= 0 then Retry_Cnt <= Retry_Cnt - 1;
end if;
end if;
end if;
end process pBackDel;
CrcDin <= Tx_Sr(1 downto 0);
Calc: process ( iClk, Crc, CrcDin, Sm_Tx ) is
variable H : std_logic_vector(1 downto 0);
begin
H(0) := Crc(31) xor CrcDin(0);
H(1) := Crc(30) xor CrcDin(1);
if rising_edge( iClk ) then
if Sm_Tx = sPre then Crc <= x"FFFFFFFF";
elsif Sm_Tx = sCrc then Crc <= Crc(29 downto 0) & "00";
else
Crc( 0) <= H(1);
Crc( 1) <= H(0) xor H(1);
Crc( 2) <= Crc( 0) xor H(0) xor H(1);
Crc( 3) <= Crc( 1) xor H(0) ;
Crc( 4) <= Crc( 2) xor H(1);
Crc( 5) <= Crc( 3) xor H(0) xor H(1);
Crc( 6) <= Crc( 4) xor H(0) ;
Crc( 7) <= Crc( 5) xor H(1);
Crc( 8) <= Crc( 6) xor H(0) xor H(1);
Crc( 9) <= Crc( 7) xor H(0) ;
Crc(10) <= Crc( 8) xor H(1);
Crc(11) <= Crc( 9) xor H(0) xor H(1);
Crc(12) <= Crc(10) xor H(0) xor H(1);
Crc(13) <= Crc(11) xor H(0) ;
Crc(14) <= Crc(12) ;
Crc(15) <= Crc(13) ;
Crc(16) <= Crc(14) xor H(1);
Crc(17) <= Crc(15) xor H(0) ;
Crc(18) <= Crc(16) ;
Crc(19) <= Crc(17) ;
Crc(20) <= Crc(18) ;
Crc(21) <= Crc(19) ;
Crc(22) <= Crc(20) xor H(1);
Crc(23) <= Crc(21) xor H(0) xor H(1);
Crc(24) <= Crc(22) xor H(0) ;
Crc(25) <= Crc(23) ;
Crc(26) <= Crc(24) xor H(1);
Crc(27) <= Crc(25) xor H(0) ;
Crc(28) <= Crc(26) ;
Crc(29) <= Crc(27) ;
Crc(30) <= Crc(28) ;
Crc(31) <= Crc(29) ;
end if;
end if;
end process Calc;
bTxDesc: block
type tDescState is (
sIdle,
sLen,
sTimL,
sTimH,
sAdrH,
sAdrL,
sReq,
sBegL,
sBegH,
sDel,
sData,
sStat,
sColl
);
signal Dsm : tDescState;
signal Tx_Dsm_Next : tDescState;
signal DescRam_Out : std_logic_vector(15 downto 0);
signal DescRam_In : std_logic_vector(15 downto 0);
alias TX_LEN : std_logic_vector(11 downto 0) is DescRam_Out(11 downto 0);
alias TX_OWN : std_logic is DescRam_Out(8);
alias TX_LAST : std_logic is DescRam_Out(9);
alias TX_READY : std_logic is DescRam_Out(10);
alias TX_BEGDEL : std_logic is DescRam_Out(12);
alias TX_BEGON : std_logic is DescRam_Out(13);
alias TX_TIME : std_logic is DescRam_Out(14);
alias TX_RETRY : std_logic_vector( 3 downto 0) is DescRam_Out(3 downto 0);
signal Ram_Be : std_logic_vector( 1 downto 0);
signal Ram_Wr : std_logic;
signal Desc_We : std_logic;
signal Desc_Addr : std_logic_vector( 7 downto 0);
signal DescIdx : std_logic_vector( 2 downto 0);
signal Last_Desc : std_logic;
signal ZeitL : std_logic_vector(15 downto 0);
signal Tx_Ie : std_logic;
signal Tx_Wait : std_logic;
signal Tx_BegInt : std_logic;
signal Tx_BegSet : std_logic;
signal Tx_Early : std_logic;
signal Tx_Del : std_logic;
signal Ext_Tx : std_logic;
signal Ext_Ack : std_logic;
signal Tx_Desc : std_logic_vector( 3 downto 0);
signal Tx_Desc_One : std_logic_vector( 3 downto 0);
signal Ext_Desc : std_logic_vector( 3 downto 0);
signal Tx_Icnt : std_logic_vector( 4 downto 0);
signal Tx_SoftInt : std_logic;
signal Sel_TxH : std_logic;
signal Sel_TxL : std_logic;
signal H_Byte : std_logic;
signal Tx_Buf : std_logic_vector( 7 downto 0);
signal Tx_Idle : std_logic;
signal TxInt : std_logic;
signal Tx_Beg : std_logic;
signal Tx_Sync : std_logic;
signal Tx_Ident : std_logic_vector( 1 downto 0);
signal Tx_Cmp_High : std_logic_vector(15 downto 0);
signal Start_TxS : std_logic;
signal Tx_Dma_Out : std_logic;
signal Tx_Del_Cnt : std_logic_vector(32 downto 0);
alias Tx_Del_End : std_logic is Tx_Del_Cnt(Tx_Del_Cnt'high);
signal Tx_Del_Run : std_logic;
signal Tx_Done : std_logic;
begin
oDmaReadDone <= Tx_Done;
Tx_Done <= '1' when Dsm = sStat or Dsm = sColl else '0';
Tx_Dma_Very1stOverflow <= cActivated when Dibl_Cnt = "01" and Sm_Tx = sPre and Tx_Timer(7) = '1' else cInactivated;
Ram_Wr <= '1' when inWrite = '0' and iSelectRam = '1' and iAddress(10) = '1' else '0';
Ram_Be(1) <= '1' when inWrite = '1' or inByteenable(1) = '0' else '0';
Ram_Be(0) <= '1' when inWrite = '1' or inByteenable(0) = '0' else '0';
DescIdx <= "000" when Desc_We = '0' and Tx_Dsm_Next = sIdle else
"000" when Desc_We = '1' and Dsm = sIdle else
"001" when Desc_We = '0' and Tx_Dsm_Next = sLen else
"001" when Desc_We = '1' and Dsm = sLen else
"010" when Desc_We = '0' and Tx_Dsm_Next = sAdrH else
"010" when Desc_We = '1' and Dsm = sAdrH else
"011" when Desc_We = '0' and Tx_Dsm_Next = sAdrL else
"011" when Desc_We = '1' and Dsm = sAdrL else
"100" when Desc_We = '0' and Tx_Dsm_Next = sBegH else
"100" when Desc_We = '1' and Dsm = sBegH else
"101" when Desc_We = '0' and Tx_Dsm_Next = sBegL else
"101" when Desc_We = '1' and Dsm = sBegL else
"110" when Desc_We = '0' and Tx_Dsm_Next = sTimH else
"110" when Desc_We = '1' and Dsm = sTimH else
"111" when Desc_We = '0' and Tx_Dsm_Next = sTimL else
"111" when Desc_We = '1' and Dsm = sTimL else
"111" when Desc_We = '0' and Tx_Dsm_Next = sData else
"111" when Desc_We = '1' and Dsm = sData else
"000";
Desc_We <= '1' when Dsm = sTimL or Dsm = sTimH or Dsm = sStat else '0';
Desc_Addr <= '1' & Tx_Desc & DescIdx when Ext_Tx = '0' else
'1' & Ext_Desc & DescIdx;
gTxTime: if gTimerEnable generate
DescRam_In <= Zeit(15 downto 0) when Dsm = sTimH else
ZeitL when Dsm = sTimL else
x"000" & "01" & Tx_Ident when Dsm = sBegL else
Tx_Dma_Out & Tx_Sync & "00" & "0100" & "00" & "0" & "0" & Col_Cnt;
end generate;
gnTxTime: if not gTimerEnable generate
DescRam_In <= x"000" & "01" & Tx_Ident when Dsm = sBegL else
Tx_Dma_Out & Tx_Sync & "00" & "0100" & "00" & "0" & "0" & Col_Cnt;
end generate;
--! This DPRAM holds the Tx descriptor accessible by the host and the DMA.
TXRAM : entity work.dpRamOpenmac
generic map (
gWordWidth => iWritedata'length,
gNumberOfWords => 256,
gInitFile => "UNUSED"
)
port map (
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => Ram_Wr,
iAddress_A => iAddress(8 downto 1),
iByteenable_A => Ram_Be,
iWritedata_A => iWritedata,
oReaddata_A => Tx_Ram_Dat,
iClk_B => iClk,
iEnable_B => cActivated,
iWriteEnable_B => Desc_We,
iByteenable_B => (others => cActivated),
iAddress_B => Desc_Addr,
iWritedata_B => DescRam_In,
oReaddata_B => DescRam_Out
);
assert not( gTimerTrigTx and not gTimerEnable )
report "Time Triggered Tx needs Timer!"
severity failure;
pTxSm: process( Dsm,
Tx_On, TX_OWN, Retry_Cnt, Ext_Tx, Tx_Wait,
Tx_Sync, Sm_Tx, F_End, Tx_Col, Ext_Ack, Tx_Del, Tx_Beg, Tx_Half, Tx_Del_End,
iRxDv )
begin
Tx_Dsm_Next <= Dsm;
case Dsm is
when sIdle => if Tx_On = '1' and TX_OWN = '1' and Retry_Cnt = 0 then
if (Ext_Tx = '1' and Ext_Ack = '0') or Tx_Wait = '0' then
Tx_Dsm_Next <= sAdrH; --sLen;
end if;
end if;
when sLen => if Tx_Sync = '0' then Tx_Dsm_Next <= sReq; --sAdrH;
else Tx_Dsm_Next <= sBegH;
end if;
when sBegH => Tx_Dsm_Next <= sBegL;
when sBegL => if Tx_On = '0' then Tx_Dsm_Next <= sIdle;
elsif Tx_Sync = '0' then
if Tx_Del = '1' then Tx_Dsm_Next <= sDel;
elsif Sm_Tx = sPre then
Tx_Dsm_Next <= sTimH;
end if;
elsif Tx_Sync = '1' and Tx_Beg = '1' and Tx_Half = '1' and iRxDv = '1' then
Tx_Dsm_Next <= sColl;
elsif Tx_Beg = '1' then Tx_Dsm_Next <= sReq;
end if;
when sDel => if Tx_On = '0' then Tx_Dsm_Next <= sIdle; --avoid FSM hang
elsif Tx_Del_End = '1' then Tx_Dsm_Next <= sTimH;
end if;
when sAdrH => Tx_Dsm_Next <= sAdrL;
when sAdrL => Tx_Dsm_Next <= sLen; --sReq;
--leaving sAdrL and entering sReq leads to the very first Tx_Dma_Req
-- this enables early dma req at the beginning of IPG (auto-resp)
when sReq => if Tx_On = '0' then Tx_Dsm_Next <= sIdle;
elsif Tx_Del = '1' then Tx_Dsm_Next <= sBegH;
elsif Tx_Sync = '0' then Tx_Dsm_Next <= sBegL;
elsif Sm_Tx = sBop then Tx_Dsm_Next <= sTimH;
end if;
when sTimH => Tx_Dsm_Next <= sTimL;
when sTimL => Tx_Dsm_Next <= sData;
when sData => if F_End = '1' then Tx_Dsm_Next <= sStat;
elsif Tx_Col = '1' then Tx_Dsm_Next <= sColl;
end if;
when sStat => Tx_Dsm_Next <= sIdle;
when sColl => if sm_tx = sIdle then
if Tx_Sync = '1' then Tx_Dsm_Next <= sStat;
else Tx_Dsm_Next <= sIdle;
end if;
end if;
when others =>
end case;
end process pTxSm;
pTxSmClk : process(iRst, iClk)
begin
if iRst = cActivated then
Dsm <= sIdle;
elsif rising_edge(iClk) then
Dsm <= Tx_Dsm_Next;
end if;
end process pTxSmClk;
pTxControl: process( iRst, iClk )
begin
if iRst = '1' then
Last_Desc <= '0'; Start_TxS <= '0'; Tx_Dma_Req <= '0'; H_Byte <= '0';
Tx_Beg <= '0'; Tx_BegSet <= '0'; Tx_Early <= '0'; Auto_Coll <= '0'; Tx_Dma_Out <= '0';
Ext_Tx <= '0'; Ext_Ack <= '0'; ClrCol <= '0'; Ext_Desc <= (others => '0'); Tx_Sync <= '0'; Max_Retry <= (others => '0');
ZeitL <= (others => '0'); Tx_Count <= (others => '0'); Tx_Ident <= "00";
Dma_Tx_Addr <= (others => '0'); Tx_Cmp_High <= (others => '0');
Tx_Del_Run <= '0';
Tx_Del <= '0'; Tx_Del_Cnt <= (others => '0'); Tx_Dma_Len <= (others => '0');
elsif rising_edge( iClk ) then
if gTimerTrigTx = true then
if Tx_Sync = '1' and Dsm = sBegL and (DescRam_Out & Tx_Cmp_High ) = Zeit then Tx_Beg <= '1';
else Tx_Beg <= '0';
end if;
end if;
if Dsm = sStat and Desc_We = '1' then ClrCol <= '1';
else ClrCol <= '0';
end if;
if gTimerEnable then
if Dsm = sTimH then ZeitL <= Zeit(31 downto 16);
end if;
end if;
if Ext_Ack = '0' and R_Req = '1' then Ext_Desc <= Auto_Desc;
Ext_Ack <= '1';
elsif Ext_Tx = '1' or Tx_On = '0' then Ext_Ack <= '0';
end if;
if Dsm = sIdle and Ext_Ack = '1' then Ext_Tx <= '1';
elsif Dsm = sStat or Tx_Col = '1' or Tx_On = '0' then Ext_Tx <= '0';
end if;
if (F_End = '1' or Tx_On = '0'
or (Tx_Col = '1' and Ext_Tx = '1' )
or dsm = sColl ) then Start_TxS <= '0';
Auto_Coll <= Auto_Coll or (Tx_Col and Ext_Tx);
elsif Dsm = sReq and Tx_Del = '0' then Start_TxS <= '1';
elsif Dsm = sDel and Tx_Del_End = '1' then Start_TxS <= '1';
elsif Sm_Tx = sIdle then Auto_Coll <= '0';
end if;
if Dsm = sIdle then Last_Desc <= TX_LAST;
end if;
if Dsm = sLen then Tx_Count <= TX_LEN; Tx_Dma_Len <= TX_LEN; --add CRC
elsif F_Val = '1' then Tx_Count <= Tx_Count - 1;
end if;
if Dsm = sBegH then Tx_Cmp_High <= DescRam_Out;
end if;
if Dsm = sIdle and Tx_On = '1' and TX_OWN = '1' and Retry_Cnt = 0 then
if Ext_Tx = '1' or Tx_Wait = '0' then
if gTimerTrigTx then Tx_Sync <= TX_TIME;
else Tx_Sync <= '0';
end if;
Max_Retry <= TX_RETRY;
Tx_Early <= TX_BEGON;
if gAutoTxDel = true then Tx_Del <= TX_BEGDEL;
end if;
end if;
elsif Dsm = sTimH then Tx_BegSet <= Tx_Early;
elsif Dsm = sTimL then Tx_BegSet <= '0';
elsif Dsm = sIdle then Tx_Del <= '0';
end if;
if gAutoTxDel = true and Tx_Del = '1' then
if Dsm = sBegH then Tx_Del_Cnt(Tx_Del_Cnt'high) <= '0';
Tx_Del_Cnt(15 downto 0) <= DescRam_Out;
elsif Dsm = sBegL then Tx_Del_Cnt(31 downto 16) <= DescRam_Out;
elsif Dsm = sDel and Tx_Del_Run = '1' then Tx_Del_Cnt <= Tx_Del_Cnt - 1;
end if;
if Tx_Del_Run = '0' and Dsm = sDel then Tx_Del_Run <= '1'; --don't consider Ipg
elsif Tx_Del_End = '1' then Tx_Del_Run <= '0';
end if;
end if;
if Dsm = sAdrL then --Dma_Tx_Addr(15 downto 1) <= DescRam_Out(15 downto 1);
Dma_Tx_Addr(oDmaAddress'high downto 16) <= DescRam_Out(oDmaAddress'high-16 downto 0);
Tx_Ident <= DescRam_Out(15 downto 14);
elsif Tx_Dma_Ack = '1' then Dma_Tx_Addr(15 downto 1) <= Dma_Tx_Addr(15 downto 1) + 1;
end if;
if Dsm = sAdrH then Dma_Tx_Addr(15 downto 1) <= DescRam_Out(15 downto 1);
-- Dma_Tx_Addr(oDmaAddress'high downto 16) <= DescRam_Out(oDmaAddress'high-16 downto 0);
-- Tx_Ident <= DescRam_Out(15 downto 14);
elsif Tx_Dma_Ack = '1' and Dma_Tx_Addr(15 downto 1) = x"FFF" & "111" then
Dma_Tx_Addr(oDmaAddress'high downto 16) <= Dma_Tx_Addr(oDmaAddress'high downto 16) + 1;
end if;
if DSM = sAdrL
or (F_Val = '1' and H_Byte = '0') then Tx_Dma_Req <= '1';
elsif Tx_Dma_Ack = '1' then Tx_Dma_Req <= '0';
end if;
if Sm_Tx = sBop then H_Byte <= '0';
elsif F_Val = '1' then H_Byte <= not H_Byte;
end if;
if F_Val = '1' then Tx_Buf <= Tx_LatchL;
end if;
if H_Byte = '0' and F_Val = '1' and Tx_Dma_Req = '1' then Tx_Dma_Out <= '1';
elsif Sm_Tx = sBop then Tx_Dma_Out <= '0';
end if;
end if;
end process pTxControl;
Start_Tx <= '1' when Start_TxS = '1' and Block_Col = '0' else
'1' when not gAutoTxDel and not gTimerTrigTx and R_Req = '1' else
'0';
F_TxB <= Tx_LatchH when H_Byte = '0' else
Tx_Buf;
onTxIrq <= '1' when (Tx_Icnt = 0 and Tx_SoftInt = '0') or Tx_Ie = '0' else '0';
Tx_Idle <= '1' when Sm_Tx = sIdle and Dsm = sIdle else '0';
Tx_Reg(15 downto 4) <= Tx_Ie & Tx_SoftInt & Tx_Half & Tx_Wait & (Tx_Icnt(4) or Tx_Icnt(3)) & Tx_Icnt(2 downto 0)
& Tx_On & Tx_BegInt & Tx_Idle & "0" ;
Tx_Reg( 3 downto 0) <= Tx_Desc;
Sel_TxH <= '1' when inWrite = '0' and iSelectCont = '1' and iAddress(3) = '0' and Ram_Be(1) = '1' else '0';
Sel_TxL <= '1' when inWrite = '0' and iSelectCont = '1' and iAddress(3) = '0' and Ram_Be(0) = '1' else '0';
Tx_Desc <= Tx_Desc_One;
Tx_SoftInt <= '0';
pTxRegs: process( iRst, iClk )
begin
if iRst = '1' then
Tx_On <= '0'; Tx_Ie <= '0'; Tx_Half <= '0'; Tx_Wait <= '0'; onTxBegIrq <= '0';
Tx_Desc_One <= (others => '0');
Tx_Icnt <= (others => '0'); TxInt <= '0'; Tx_BegInt <= '0';
Tx_Ipg <= conv_std_logic_vector( 42, 6);
elsif rising_edge( iClk ) then
if Sel_TxL = '1' then
if iAddress(2 downto 1) = "00" then Tx_On <= iWritedata( 7);
elsif iAddress(2 downto 1) = "01" and iWritedata( 7) = '1' then Tx_On <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata( 7) = '1' then Tx_On <= '0';
end if;
end if;
if Tx_BegSet = '1' and Tx_Ie = '1' then Tx_BegInt <= '1';
elsif Sel_TxL = '1' and iAddress(2 downto 1) = "01" and iWritedata( 6) = '1' then Tx_BegInt <= '1';
elsif Sel_TxL = '1' and iAddress(2 downto 1) = "10" and iWritedata( 6) = '1' then Tx_BegInt <= '0';
end if;
onTxBegIrq <= not Tx_BegInt;
if Sel_TxL = '1' and iAddress(2 downto 1) = "11" then Tx_Desc_One <= iWritedata( 3 downto 0);
elsif Dsm = sStat and Ext_Tx = '0' then
if Last_Desc = '1' then Tx_Desc_One <= x"0";
else Tx_Desc_One <= Tx_Desc + 1;
end if;
end if;
if Sel_TxH = '1' then
if iAddress(2 downto 1) = "00" then Tx_Ie <= iWritedata(15);
elsif iAddress(2 downto 1) = "01" and iWritedata(15) = '1' then Tx_Ie <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(15) = '1' then Tx_Ie <= '0';
end if;
end if;
if Sel_TxH = '1' then
if iAddress(2 downto 1) = "00" then Tx_Half <= iWritedata(13);
elsif iAddress(2 downto 1) = "01" and iWritedata(13) = '1' then Tx_Half <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(13) = '1' then Tx_Half <= '0';
end if;
end if;
if Sel_TxH = '1' then
if iAddress(2 downto 1) = "00" then Tx_Wait <= iWritedata(12);
elsif iAddress(2 downto 1) = "01" and iWritedata(12) = '1' then Tx_Wait <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(12) = '1' then Tx_Wait <= '0';
end if;
end if;
if Sel_TxH = '1' then
if iAddress(2 downto 1) = "11" and iWritedata(14) = '1' then Tx_Ipg <= iWritedata(13 downto 8);
end if;
end if;
if Tx_Ie = '1' and Dsm = sStat and Desc_We = '1' then TxInt <= '1';
else TxInt <= '0';
end if;
if Sel_TxH = '1' and iAddress(2 downto 1) = "10" and iWritedata(8) = '1'
and Tx_Icnt /= 0 then Tx_Icnt <= Tx_Icnt - not TxInt;
elsif TxInt = '1' and Tx_Icnt /= "11111" then Tx_Icnt <= Tx_Icnt + 1;
end if;
end if;
end process pTxRegs;
end block bTxDesc;
end block b_Full_Tx;
b_Full_Rx: block
type tRxState is (
sIdle,
sSof,
sRxd
);
signal Sm_Rx : tRxState;
signal Rx_Dat : std_logic_vector(1 downto 0);
signal Rx_DatL : std_logic_vector(1 downto 0);
signal Tx_Timer : std_logic_vector(7 downto 0);
signal Dibl_Cnt : std_logic_vector(1 downto 0);
signal Crc : std_logic_vector(31 downto 0);
signal nCrc : std_logic_vector(31 downto 0);
signal CrcDin : std_logic_vector(1 downto 0);
signal F_Err : std_logic;
signal P_Err : std_logic;
signal N_Err : std_logic;
signal A_Err : std_logic;
signal F_End : std_logic;
signal F_Val : std_logic;
signal Rx_Beg : std_logic;
signal Rx_Sr : std_logic_vector(7 downto 0);
signal nCrc_Ok : std_logic;
signal Crc_Ok : std_logic;
signal WrDescStat : std_logic;
signal PreCount : std_logic_vector(4 downto 0);
signal PreBeg : std_logic;
signal PreErr : std_logic;
signal Rx_DvL : std_logic;
signal Diag : std_logic;
begin
Rx_Beg <= '1' when Rx_Dv = '1' and Sm_Rx = sSof and Rx_Dat = "11" else '0';
nCrc_Ok <= '1' when nCrc = x"C704DD7B" else '0';
rxsm: process ( iClk, iRst ) is
begin
if iRst = '1' then
Sm_Rx <= sIdle;
elsif rising_edge( iClk ) then
if Sm_Rx = sIdle or Sm_Rx = sRxd or Sm_Rx = sSof or Dibl_Cnt = "11" then
case Sm_Rx is
when sIdle => if Rx_Dv = '1' then Sm_Rx <= sSof; end if;
when sSof => if Rx_Dat = "11" then Sm_Rx <= sRxd;
elsif Rx_Dv = '0' then Sm_Rx <= sIdle; end if;
when sRxd => if Rx_Dv = '0' then Sm_Rx <= sIdle; end if;
when others => NULL;
end case;
end if;
end if;
end process rxsm;
pRxCtl: process ( iClk, iRst ) is
variable vPreload : std_logic_vector(Tx_Timer'range);
variable vLoad : std_logic;
begin
if iRst = '1' then
Rx_DatL <= "00"; Rx_Dat <= "00"; Rx_Dv <= '0'; Dibl_Cnt <= "00"; PreCount <= (others => '0');
F_End <= '0'; F_Err <= '0'; F_Val <= '0'; Crc_Ok <= '0';
A_Err <= '0'; N_Err <= '0'; P_Err <= '0'; PreBeg <= '0'; PreErr <= '0';
elsif rising_edge( iClk ) then
Rx_DatL <= iRxData;
Rx_Dat <= Rx_DatL;
if Rx_Dv = '0' and iRxDv = '1' then Rx_Dv <= '1';
elsif Rx_Dv = '1' and iRxDv = '0' and Dibl_Cnt(0) = '1' then Rx_Dv <= '0';
end if;
if Rx_Beg = '1' then Dibl_Cnt <= "00";
else Dibl_Cnt <= Dibl_Cnt + 1;
end if;
Crc_Ok <= nCrc_Ok;
if (Sm_Rx = sRxd and Rx_Dv = '0') then F_End <= '1';
F_Err <= not Crc_Ok;
else F_End <= '0';
end if;
if Dibl_Cnt = "11" and Sm_Rx = sRxd then F_Val <= '1';
else F_Val <= '0';
end if;
if WrDescStat = '1' then A_Err <= '0';
elsif F_End = '1' and Dibl_Cnt /= 1 then A_Err <= '1';
end if;
if Rx_Dv = '0' or Rx_Dat(0) = '0' then PreCount <= (others => '1');
else PreCount <= PreCount - 1;
end if;
if Rx_Dv = '0' then PreBeg <= '0';
elsif Rx_Dat = "01" then PreBeg <= '1';
end if;
if WrDescStat = '1' then N_Err <= '0';
elsif Sm_Rx = sSof and Rx_Dv = '0' then N_Err <= '1';
end if;
if Rx_DvL = '0' then PreErr <= '0';
elsif PreBeg = '0' and (Rx_Dat = "10" or Rx_Dat = "11") then PreErr <= '1';
elsif PreBeg = '1' and (Rx_Dat = "10" or Rx_Dat = "00") then PreErr <= '1';
end if;
if WrDescStat = '1' then P_Err <= '0';
elsif Rx_Beg = '1' and PreErr = '1' then P_Err <= '1';
elsif Rx_Beg = '1' and PreCount /= 0 then P_Err <= '1';
end if;
Rx_Sr <= Rx_Dat(1) & Rx_Dat(0) & Rx_Sr(7 downto 2);
Rx_DvL <= Rx_Dv;
end if;
end process pRxCtl;
CrcDin <= Rx_Dat;
Calc: process ( iClk, Crc, nCrc, CrcDin, Sm_Rx ) is
variable H : std_logic_vector(1 downto 0);
begin
H(0) := Crc(31) xor CrcDin(0);
H(1) := Crc(30) xor CrcDin(1);
if Sm_Rx = sSof then nCrc <= x"FFFFFFFF";
else
nCrc( 0) <= H(1);
nCrc( 1) <= H(0) xor H(1);
nCrc( 2) <= Crc( 0) xor H(0) xor H(1);
nCrc( 3) <= Crc( 1) xor H(0) ;
nCrc( 4) <= Crc( 2) xor H(1);
nCrc( 5) <= Crc( 3) xor H(0) xor H(1);
nCrc( 6) <= Crc( 4) xor H(0) ;
nCrc( 7) <= Crc( 5) xor H(1);
nCrc( 8) <= Crc( 6) xor H(0) xor H(1);
nCrc( 9) <= Crc( 7) xor H(0) ;
nCrc(10) <= Crc( 8) xor H(1);
nCrc(11) <= Crc( 9) xor H(0) xor H(1);
nCrc(12) <= Crc(10) xor H(0) xor H(1);
nCrc(13) <= Crc(11) xor H(0) ;
nCrc(14) <= Crc(12) ;
nCrc(15) <= Crc(13) ;
nCrc(16) <= Crc(14) xor H(1);
nCrc(17) <= Crc(15) xor H(0) ;
nCrc(18) <= Crc(16) ;
nCrc(19) <= Crc(17) ;
nCrc(20) <= Crc(18) ;
nCrc(21) <= Crc(19) ;
nCrc(22) <= Crc(20) xor H(1);
nCrc(23) <= Crc(21) xor H(0) xor H(1);
nCrc(24) <= Crc(22) xor H(0) ;
nCrc(25) <= Crc(23) ;
nCrc(26) <= Crc(24) xor H(1);
nCrc(27) <= Crc(25) xor H(0) ;
nCrc(28) <= Crc(26) ;
nCrc(29) <= Crc(27) ;
nCrc(30) <= Crc(28) ;
nCrc(31) <= Crc(29) ;
end if;
if rising_edge( iClk ) then
Crc <= nCrc;
end if;
end process Calc;
bRxDesc: block
type tDescState is (
sIdle,
sLen,
sTimL,
sTimH,
sAdrH,
sAdrL,
sData,
sOdd,
sStat,
sLenW
);
signal Dsm : tDescState;
signal Rx_Dsm_Next : tDescState;
signal Rx_Buf : std_logic_vector(7 downto 0);
signal Rx_LatchH : std_logic_vector(7 downto 0);
signal Rx_LatchL : std_logic_vector(7 downto 0);
signal Rx_Ovr : std_logic;
signal DescRam_Out : std_logic_vector(15 downto 0);
signal DescRam_In : std_logic_vector(15 downto 0);
alias RX_LEN : std_logic_vector(11 downto 0) is DescRam_Out(11 downto 0);
alias RX_OWN : std_logic is DescRam_Out(8);
alias RX_LAST : std_logic is DescRam_Out(9);
signal Ram_Be : std_logic_vector(1 downto 0);
signal Ram_Wr : std_logic;
signal Desc_We : std_logic;
signal Desc_Addr : std_logic_vector(7 downto 0);
signal ZeitL : std_logic_vector(15 downto 0);
signal Rx_On : std_logic;
signal Rx_Ie : std_logic;
signal Sel_RxH : std_logic;
signal Sel_RxL : std_logic;
signal Rx_Desc : std_logic_vector(3 downto 0);
signal Match_Desc : std_logic_vector(3 downto 0);
signal Rx_Icnt : std_logic_vector(4 downto 0);
signal Rx_Lost : std_logic;
signal Last_Desc : std_logic;
signal Answer_Tx : std_logic;
signal DescIdx : std_logic_vector( 2 downto 0);
signal Rx_Count : std_logic_vector(11 downto 0);
signal Rx_Limit : std_logic_vector(11 downto 0);
signal Match : std_logic;
signal Filt_Cmp : std_logic;
signal Rx_Idle : std_logic;
signal RxInt : std_logic;
signal Hub_Rx_L : std_logic_vector(1 downto 0);
signal Rx_Dma_Out : std_logic;
signal Rx_Done : std_logic;
begin
process(iRst, iClk)
variable doPulse : std_logic;
begin
if iRst = cActivated then
Rx_Done <= cInactivated;
doPulse := cInactivated;
elsif rising_edge(iClk) then
Rx_Done <= cInactivated;
if Dsm /= sIdle and Rx_Dsm_Next = sIdle then
-- RX is done
doPulse := cActivated;
end if;
if doPulse = cActivated and Rx_Dma_Req = cInactivated and Rx_Count = 0 then
-- RX is done and there is no dma request
Rx_Done <= cActivated;
doPulse := cInactivated;
end if;
end if;
end process;
oDmaWriteDone <= Rx_Done;
WrDescStat <= '1' when Dsm = sStat else '0';
Ram_Wr <= '1' when inWrite = '0' and iSelectRam = '1' and iAddress(10) = '1' else '0';
Ram_Be(1) <= '1' when inWrite = '1' or inByteenable(1) = '0' else '0';
Ram_Be(0) <= '1' when inWrite = '1' or inByteenable(0) = '0' else '0';
DescIdx <= "001" when Desc_We = '0' and (Rx_Dsm_Next = sLen or Rx_Dsm_Next = sLenW) else
"001" when Desc_We = '1' and (Dsm = sLen or Dsm = sLenW) else
"010" when Desc_We = '0' and Rx_Dsm_Next = sAdrH else
"010" when Desc_We = '1' and Dsm = sAdrH else
"011" when Desc_We = '0' and Rx_Dsm_Next = sAdrL else
"011" when Desc_We = '1' and Dsm = sAdrL else
"110" when Desc_We = '0' and Rx_Dsm_Next = sTimH else
"110" when Desc_We = '1' and Dsm = sTimH else
"111" when Desc_We = '0' and Rx_Dsm_Next = sTimL else
"111" when Desc_We = '1' and Dsm = sTimL else
"000";
Desc_We <= '1' when Dsm = sTimL or Dsm = sTimH else
'1' when (Dsm = sLenW or Dsm = sStat) and Match = '1' else '0';
Desc_Addr <= "0" & Rx_Desc & DescIdx;
gRxTime: if gTimerEnable generate
DescRam_In <= Zeit(15 downto 0) when Dsm = sTimH else
ZeitL when Dsm = sTimL else
x"0" & Rx_Count when Dsm = sLenW else
Rx_Dma_Out & '0' & "0" & A_Err & Hub_Rx_L & "00" & Match_Desc & N_Err & P_Err & Rx_Ovr & F_Err;
end generate;
ngRxTime: if not gTimerEnable generate
DescRam_In <= x"0" & Rx_Count when Dsm = sLenW else
Rx_Dma_Out & '0' & "0" & A_Err & Hub_Rx_L & "00" & Match_Desc & N_Err & P_Err & Rx_Ovr & F_Err;
end generate;
--! This DPRAM holds the Rx descriptor accessible by the host and the DMA.
RXRAM : entity work.dpRamOpenmac
generic map (
gWordWidth => iWritedata'length,
gNumberOfWords => 256,
gInitFile => "UNUSED"
)
port map (
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => Ram_Wr,
iAddress_A => iAddress(8 downto 1),
iByteenable_A => Ram_Be,
iWritedata_A => iWritedata,
oReaddata_A => Rx_Ram_Dat,
iClk_B => iClk,
iEnable_B => cActivated,
iWriteEnable_B => Desc_We,
iByteenable_B => (others => cActivated),
iAddress_B => Desc_Addr,
iWritedata_B => DescRam_In,
oReaddata_B => DescRam_Out
);
pRxSm: process( Dsm,
Rx_Beg, Rx_On, RX_OWN, F_End, F_Err, Diag, Rx_Count )
begin
Rx_Dsm_Next <= Dsm;
case Dsm is
when sIdle => if Rx_Beg = '1' and Rx_On = '1' and RX_OWN = '1' then
Rx_Dsm_Next <= sLen;
end if;
when sLen => Rx_Dsm_Next <= sAdrH;
when sAdrH => Rx_Dsm_Next <= sAdrL;
when sAdrL => Rx_Dsm_Next <= sTimH;
when sTimH => Rx_Dsm_Next <= sTimL;
when sTimL => Rx_Dsm_Next <= sData;
when sData => if F_End = '1' then
if F_Err = '0'
or Diag = '1' then Rx_Dsm_Next <= sStat;
else Rx_Dsm_Next <= sIdle;
end if;
end if;
when sStat => Rx_Dsm_Next <= sLenW;
when sLenW => if Rx_Count(0) = '0' then
Rx_Dsm_Next <= sIdle;
else Rx_Dsm_Next <= sOdd;
end if;
when sOdd => Rx_Dsm_Next <= sIdle;
when others =>
end case;
end process pRxSm;
pRxSmClk : process(iRst, iClk)
begin
if iRst = cActivated then
Dsm <= sIdle;
elsif rising_edge(iClk) then
Dsm <= Rx_Dsm_Next;
end if;
end process pRxSmClk;
pRxControl: process( iRst, iClk )
begin
if iRst = '1' then
Rx_Ovr <= '0'; Rx_Dma_Req <= '0'; Last_Desc <= '0'; Rx_Dma_Out <= '0';
Rx_Count <= (others => '0');
Rx_Buf <= (others => '0'); Rx_LatchL <= (others => '0'); Rx_LatchH <= (others => '0');
Dma_Rx_Addr <= (others => '0');
elsif rising_edge( iClk ) then
if gTimerEnable then
if Dsm = sTimH then ZeitL <= Zeit(31 downto 16);
end if;
end if;
if Dsm = sIdle then Rx_Count <= (others => '0');
Last_Desc <= RX_LAST;
elsif F_Val = '1' then Rx_Count <= Rx_Count + 1;
end if;
if Dsm = sLen then Rx_Limit <= RX_LEN;
Hub_Rx_L <= iHubRxPort;
end if;
if F_Val = '1' then Rx_Buf <= Rx_Sr;
end if;
if (F_Val = '1' and Rx_Count(0) = '1') or Dsm = sStat then Rx_LatchH <= Rx_Buf;
Rx_LatchL <= Rx_Sr;
if Rx_Dma_Req = '1' and Sm_Rx /= sIdle then Rx_Dma_Out <= '1';
end if;
elsif Dsm = sLen then Rx_Dma_Out <= '0';
end if;
if Dsm = sLen then Rx_Ovr <= '0';
elsif F_Val = '1' and Rx_Limit = Rx_Count then Rx_Ovr <= '1';
end if;
if Dsm = sAdrL then --Dma_Rx_Addr(15 downto 1) <= DescRam_Out(15 downto 1);
Dma_Rx_Addr(oDmaAddress'high downto 16) <= DescRam_Out(oDmaAddress'high-16 downto 0);
elsif Rx_Dma_Ack = '1' then Dma_Rx_Addr(15 downto 1) <= Dma_Rx_Addr(15 downto 1) + 1;
end if;
if Dsm = sAdrH then Dma_Rx_Addr(15 downto 1) <= DescRam_Out(15 downto 1);
--Dma_Rx_Addr(oDmaAddress'high downto 16) <= DescRam_Out(oDmaAddress'high-16 downto 0);
elsif Rx_Dma_Ack = '1' and Dma_Rx_Addr(15 downto 1) = x"FFF" & "111" then
Dma_Rx_Addr(oDmaAddress'high downto 16) <= Dma_Rx_Addr(oDmaAddress'high downto 16) + 1;
end if;
if Filt_Cmp = '0' and Match ='0' then Rx_Dma_Req <= '0';
elsif (Dsm = sOdd and Rx_Ovr = '0')
or (Dsm = sData and Rx_Ovr = '0' and F_Val = '1' and Rx_Count(0) = '1') then Rx_Dma_Req <= '1';
elsif Rx_Dma_Ack = '1' then Rx_Dma_Req <= '0';
end if;
end if;
end process pRxControl;
oDmaWritedata <= Rx_LatchL & Rx_LatchH; --Rx_LatchH & Rx_LatchL;
onRxIrq <= '1' when Rx_Icnt = 0 or Rx_Ie = '0' else '0';
Rx_Idle <= '1' when Sm_Rx = sIdle else '0';
Rx_Reg(15 downto 4) <= Rx_Ie & '0' & "0" & '0' & (Rx_Icnt(4) or Rx_Icnt(3)) & Rx_Icnt(2 downto 0)
& Rx_On & "0" & Rx_Idle & Rx_Lost;
Rx_Reg( 3 downto 0) <= Rx_Desc;
bFilter: block
signal Ram_Addr : std_logic_vector(7 downto 0);
signal Ram_BeH : std_logic_vector(1 downto 0);
signal Ram_BeL : std_logic_vector(1 downto 0);
signal Ram_Wr : std_logic;
signal Filter_Addr : std_logic_vector(6 downto 0);
signal Filter_Out_H : std_logic_vector(31 downto 0);
signal Filter_Out_L : std_logic_vector(31 downto 0);
alias DIRON_0 : std_logic is Filter_Out_H(11);
alias DIRON_1 : std_logic is Filter_Out_H(27);
alias DIRON_2 : std_logic is Filter_Out_L(11);
alias DIRON_3 : std_logic is Filter_Out_L(27);
alias TX_0 : std_logic is Filter_Out_H(7);
alias TX_1 : std_logic is Filter_Out_H(23);
alias TX_2 : std_logic is Filter_Out_L(7);
alias TX_3 : std_logic is Filter_Out_L(23);
alias ON_0 : std_logic is Filter_Out_H(6);
alias ON_1 : std_logic is Filter_Out_H(22);
alias ON_2 : std_logic is Filter_Out_L(6);
alias ON_3 : std_logic is Filter_Out_L(22);
alias DESC_0 : std_logic_vector(3 downto 0) is Filter_Out_H(3 downto 0);
alias DESC_1 : std_logic_vector(3 downto 0) is Filter_Out_H(19 downto 16);
alias DESC_2 : std_logic_vector(3 downto 0) is Filter_Out_L(3 downto 0);
alias DESC_3 : std_logic_vector(3 downto 0) is Filter_Out_L(19 downto 16);
signal Byte_Cnt : std_logic_vector(4 downto 0) := (others => '0');
signal Erg0 : std_logic_vector(7 downto 0);
signal Erg1 : std_logic_vector(7 downto 0);
signal Erg2 : std_logic_vector(7 downto 0);
signal Erg3 : std_logic_vector(7 downto 0);
signal Mat_Reg : std_logic_vector(15 downto 0);
signal Filt_Idx : std_logic_vector(1 downto 0);
signal Mat_Sel : std_logic_vector(3 downto 0);
signal M_Prio : std_logic_vector(2 downto 0);
alias Found : std_logic is M_Prio(2);
begin
Ram_Addr <= iAddress(9 downto 8) & iAddress(5 downto 1) & iAddress(6);
Ram_Wr <= '1' when inWrite = '0' and iSelectRam = '1' and iAddress(10) = '0' else '0';
Ram_BeH(1) <= '1' when inWrite = '1' or (inByteenable(1) = '0' and iAddress(7) = '0') else '0';
Ram_BeH(0) <= '1' when inWrite = '1' or (inByteenable(0) = '0' and iAddress(7) = '0') else '0';
Ram_BeL(1) <= '1' when inWrite = '1' or (inByteenable(1) = '0' and iAddress(7) = '1') else '0';
Ram_BeL(0) <= '1' when inWrite = '1' or (inByteenable(0) = '0' and iAddress(7) = '1') else '0';
Filter_Addr <= Dibl_Cnt & Byte_Cnt;
--! This simplex DPRAM holds the higher dword for the Rx packet filters.
FILTERRAMHIGH : entity work.dpRamSplx
generic map (
gWordWidthA => iWritedata'length,
gByteenableWidthA => Ram_BeH'length,
gNumberOfWordsA => 256,
gWordWidthB => Filter_Out_H'length,
gNumberOfWordsB => 128,
gInitFile => "UNUSED"
)
port map (
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => Ram_Wr,
iAddress_A => Ram_Addr,
iByteenable_A => Ram_BeH,
iWritedata_A => iWritedata,
iClk_B => iClk,
iEnable_B => cActivated,
iAddress_B => Filter_Addr,
oReaddata_B => Filter_Out_H
);
--! This simplex DPRAM holds the lower dword for the Rx packet filters.
FILTERRAMLOW : entity work.dpRamSplx
generic map (
gWordWidthA => iWritedata'length,
gByteenableWidthA => Ram_BeL'length,
gNumberOfWordsA => 256,
gWordWidthB => Filter_Out_H'length,
gNumberOfWordsB => 128,
gInitFile => "UNUSED"
)
port map (
iClk_A => iClk,
iEnable_A => cActivated,
iWriteEnable_A => Ram_Wr,
iAddress_A => Ram_Addr,
iByteenable_A => Ram_BeL,
iWritedata_A => iWritedata,
iClk_B => iClk,
iEnable_B => cActivated,
iAddress_B => Filter_Addr,
oReaddata_B => Filter_Out_L
);
Erg0 <= (Rx_Buf xor Filter_Out_H( 7 downto 0)) and Filter_Out_H(15 downto 8);
Erg1 <= (Rx_Buf xor Filter_Out_H(23 downto 16)) and Filter_Out_H(31 downto 24);
Erg2 <= (Rx_Buf xor Filter_Out_L( 7 downto 0)) and Filter_Out_L(15 downto 8);
Erg3 <= (Rx_Buf xor Filter_Out_L(23 downto 16)) and Filter_Out_L(31 downto 24);
genMatSel: for i in 0 to 3 generate
Mat_Sel(i) <= Mat_Reg( 0 + i) when Filt_Idx = "00" else
Mat_Reg( 4 + i) when Filt_Idx = "01" else
Mat_Reg( 8 + i) when Filt_Idx = "10" else
Mat_Reg(12 + i); -- when Filt_Idx = "11";
end generate;
M_Prio <= "000" when Filt_Cmp = '0' or Match = '1' else
"100" when Mat_Sel(0) = '1' and On_0 = '1' and (DIRON_0 = '0') else
"101" when Mat_Sel(1) = '1' and On_1 = '1' and (DIRON_1 = '0') else
"110" when Mat_Sel(2) = '1' and On_2 = '1' and (DIRON_2 = '0') else
"111" when Mat_Sel(3) = '1' and On_3 = '1' and (DIRON_3 = '0') else
"000";
pFilter: process( iRst, iClk )
begin
if iRst = '1' then
Filt_Idx <= "00"; Match <= '0';
Filt_Cmp <= '0'; Mat_Reg <= (others => '0'); Byte_Cnt <= (others =>'0');
Match_Desc <= (others => '0');Auto_Desc <= (others =>'0'); Answer_Tx <= '0';
elsif rising_edge( iClk ) then
Filt_Idx <= Dibl_Cnt;
if Dibl_Cnt = "11" and Rx_Count(5) = '0' then Byte_Cnt <= Rx_Count(Byte_Cnt'range);
end if;
if Dsm = sTiml then Filt_Cmp <= '1';
elsif Rx_Dv = '0' or (F_Val = '1' and Rx_Count(5) = '1') then Filt_Cmp <= '0';
end if;
if Dsm = sTimL then Mat_Reg <= (others => '1');
else
for i in 0 to 3 loop
if Erg0 /= 0 and conv_integer(Filt_Idx) = i then Mat_Reg(4*i + 0) <= '0'; end if;
if Erg1 /= 0 and conv_integer(Filt_Idx) = i then Mat_Reg(4*i + 1) <= '0'; end if;
if Erg2 /= 0 and conv_integer(Filt_Idx) = i then Mat_Reg(4*i + 2) <= '0'; end if;
if Erg3 /= 0 and conv_integer(Filt_Idx) = i then Mat_Reg(4*i + 3) <= '0'; end if;
end loop;
end if;
if Dsm = sTimL then Match <= '0';
elsif Found = '1' then Match <= '1'; Match_Desc <= Filt_Idx & M_Prio(1 downto 0);
if M_Prio(1 downto 0) = "00" then Answer_Tx <= TX_0; Auto_Desc <= DESC_0;
elsif M_Prio(1 downto 0) = "01" then Answer_Tx <= TX_1; Auto_Desc <= DESC_1;
elsif M_Prio(1 downto 0) = "10" then Answer_Tx <= TX_2; Auto_Desc <= DESC_2;
elsif M_Prio(1 downto 0) = "11" then Answer_Tx <= TX_3; Auto_Desc <= DESC_3;
end if;
elsif F_End = '1' then Answer_Tx <= '0';
end if;
end if;
end process pFilter;
R_Req <= Answer_Tx when F_End = '1' and F_Err = '0' else '0';
end block bFilter;
Sel_RxH <= '1' when inWrite = '0' and iSelectCont = '1' and iAddress(3) = '1' and inByteenable(1) = '0' else '0';
Sel_RxL <= '1' when inWrite = '0' and iSelectCont = '1' and iAddress(3) = '1' and inByteenable(0) = '0' else '0';
pRxRegs: process( iRst, iClk )
begin
if iRst = '1' then
Rx_Desc <= (others => '0'); Rx_On <= '0';
Rx_Ie <= '0'; Rx_Lost <= '0'; Rx_Icnt <= (others => '0'); RxInt <= '0'; Diag <= '0';
elsif rising_edge( iClk ) then
if Sel_RxH = '1' then
if iAddress(2 downto 1) = "00" then Rx_Ie <= iWritedata(15);
elsif iAddress(2 downto 1) = "01" and iWritedata(15) = '1' then Rx_Ie <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(15) = '1' then Rx_Ie <= '0';
end if;
end if;
if Sel_RxH = '1' then
if iAddress(2 downto 1) = "00" then Diag <= iWritedata(12);
elsif iAddress(2 downto 1) = "01" and iWritedata(12) = '1' then Diag <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata(12) = '1' then Diag <= '0';
end if;
end if;
if Sel_RxL = '1' then
if iAddress(2 downto 1) = "00" then Rx_On <= iWritedata( 7);
elsif iAddress(2 downto 1) = "01" and iWritedata( 7) = '1' then Rx_On <= '1';
elsif iAddress(2 downto 1) = "10" and iWritedata( 7) = '1' then Rx_On <= '0';
end if;
end if;
if Rx_Beg = '1' and (RX_OWN = '0' or Rx_On = '0') then Rx_Lost <= '1';
elsif Sel_RxL = '1' and iAddress(2 downto 1) = "10" and iWritedata( 4) = '1' then Rx_Lost <= '0';
end if;
if Sel_RxL = '1' and iAddress(2 downto 1) = "11" then Rx_Desc <= iWritedata( 3 downto 0);
elsif Dsm = sLenW and Desc_We = '1' then
if Last_Desc = '1' then Rx_Desc <= x"0";
else Rx_Desc <= Rx_Desc + 1;
end if;
end if;
if Rx_Ie = '1' and Desc_We = '1' and Dsm = sStat then RxInt <= '1';
else RxInt <= '0';
end if;
if Sel_RxH = '1' and iAddress(2 downto 1) = "10" and iWritedata(8) = '1'
and Rx_Icnt /= 0 then Rx_Icnt <= Rx_Icnt - not RxInt;
elsif RxInt = '1' and Rx_Icnt /= "11111" then Rx_Icnt <= Rx_Icnt + 1;
end if;
end if;
end process pRxRegs;
end block bRxDesc;
end block b_Full_Rx;
end architecture struct; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity FIFO is
generic(
-- øèíà àäðåñà
m: integer := 2;
-- øèíà äàííûõ
n: integer := 2
);
port (
-- ñèíõðîíèçàöèÿ
CLK: in std_logic;
-- ñèãíàë óïðàâëåíèÿ ÷òåíèåì/çàïèñüþ
WR: in std_logic;
-- äâóíàïðàâëåííàÿ øèíà äàííûõ
DB: inout std_logic_vector (n-1 downto 0);
EMPTY: out std_logic;
FULL: out std_logic
);
end FIFO;
architecture Beh of FIFO is
-- òèï õðàíèìîãî ñëîâà
subtype word is std_logic_vector (n-1 downto 0);
-- íåïîñðåäñòâåííî òèï õðàíèëèùà äàííûõ
type tram is array (0 to 2**m - 1) of word;
signal sRAM: tram;
signal head: integer := 0;
constant Limit: integer := 2 ** m -1;
Begin
SH: process (CLK)
begin
if rising_edge(CLK) then
if (WR = '0') then
if (head <= Limit) then
head <= head + 1;
end if;
elsif (WR = '1') then
if (head > 0) then
head <= head - 1;
end if;
end if;
end if;
if (head = 0) then
empty <= '1';
full <= '0';
elsif (head = Limit + 1) then
empty <= '0';
full <= '1';
else
empty <= '0';
full <= '0';
end if;
end process;
WRP: process (head)
begin
if WR = '0' then
if (head > 0 and head <= Limit + 1) then
sRAM(head - 1) <= DB;
end if;
end if;
end process;
RDP: process(head)
begin
if WR = '1' then
if (head >= 0 and head <= Limit) then
DB <= sRAM (head);
end if;
else
DB <= (others => 'Z');
end if;
end process;
end Beh; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:52:25 03/11/2014
-- Design Name:
-- Module Name: BaudRateGenerator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BaudRateGenerator is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
tick : out STD_LOGIC);
end BaudRateGenerator;
architecture Behavioral of BaudRateGenerator is
signal brojac, brojacNext : unsigned (7 downto 0);
begin
process (clk, rst)
begin
if(rst = '1') then
brojac <= "00000000";
else
if (clk'event and clk = '1') then
brojac <= brojacNext;
end if;
end if;
end process;
brojacNext <= "00000000" when brojac = 176 else
brojac + 1;
tick <= '1' when brojac = 176 else '0';
end Behavioral;
|
---------------------------------------------------------------------------------
-- TZX player
-- by György Szombathelyi
-- basic idea for the structure based on c1530 tap player by darfpga
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity tzxplayer is
generic (
TZX_MS : integer := 64000; -- CE periods for one milliseconds
-- Default: ZX Spectrum
NORMAL_PILOT_LEN : integer := 2168;
NORMAL_SYNC1_LEN : integer := 667;
NORMAL_SYNC2_LEN : integer := 735;
NORMAL_ZERO_LEN : integer := 855;
NORMAL_ONE_LEN : integer := 1710;
NORMAL_PILOT_PULSES : integer := 4031
-- Amstrad CPC
--NORMAL_PILOT_LEN : integer := 2000;
--NORMAL_SYNC1_LEN : integer := 855;
--NORMAL_SYNC2_LEN : integer := 855;
--NORMAL_ZERO_LEN : integer := 855;
--NORMAL_ONE_LEN : integer := 1710;
--NORMAL_PILOT_PULSES : integer := 4096;
);
port(
clk : in std_logic;
ce : in std_logic;
restart_tape : in std_logic;
host_tap_in : in std_logic_vector(7 downto 0); -- 8bits fifo input
tzx_req : buffer std_logic; -- request for new byte (edge trigger)
tzx_ack : in std_logic; -- new data available
loop_start : out std_logic; -- active for one clock if a loop starts
loop_next : out std_logic; -- active for one clock at the next iteration
stop : out std_logic; -- tape should be stopped
stop48k : out std_logic; -- tape should be stopped in 48k mode
cass_read : buffer std_logic; -- tape read signal
cass_motor : in std_logic -- 1 = tape motor is powered
);
end tzxplayer;
architecture struct of tzxplayer is
signal tap_fifo_do : std_logic_vector(7 downto 0);
signal tick_cnt : std_logic_vector(16 downto 0);
signal wave_cnt : std_logic_vector(15 downto 0);
signal wave_period : std_logic;
signal skip_bytes : std_logic;
signal playing : std_logic; -- 1 = tap or wav file is playing
signal bit_cnt : std_logic_vector(2 downto 0);
type tzx_state_t is (
TZX_HEADER,
TZX_NEWBLOCK,
TZX_LOOP_START,
TZX_LOOP_END,
TZX_PAUSE,
TZX_PAUSE2,
TZX_STOP48K,
TZX_HWTYPE,
TZX_TEXT,
TZX_MESSAGE,
TZX_ARCHIVE_INFO,
TZX_CUSTOM_INFO,
TZX_GLUE,
TZX_TONE,
TZX_PULSES,
TZX_DATA,
TZX_NORMAL,
TZX_TURBO,
TZX_PLAY_TONE,
TZX_PLAY_SYNC1,
TZX_PLAY_SYNC2,
TZX_PLAY_TAPBLOCK,
TZX_PLAY_TAPBLOCK2,
TZX_PLAY_TAPBLOCK3,
TZX_PLAY_TAPBLOCK4,
TZX_DIRECT,
TZX_DIRECT2,
TZX_DIRECT3);
signal tzx_state: tzx_state_t;
signal tzx_offset : std_logic_vector( 7 downto 0);
signal pause_len : std_logic_vector(15 downto 0);
signal ms_counter : std_logic_vector(15 downto 0);
signal pilot_l : std_logic_vector(15 downto 0);
signal sync1_l : std_logic_vector(15 downto 0);
signal sync2_l : std_logic_vector(15 downto 0);
signal zero_l : std_logic_vector(15 downto 0);
signal one_l : std_logic_vector(15 downto 0);
signal pilot_pulses : std_logic_vector(15 downto 0);
signal last_byte_bits : std_logic_vector( 3 downto 0);
signal data_len : std_logic_vector(23 downto 0);
signal pulse_len : std_logic_vector(15 downto 0);
signal end_period : std_logic;
signal cass_motor_D : std_logic;
signal motor_counter : std_logic_vector(21 downto 0);
signal loop_iter : std_logic_vector(15 downto 0);
signal data_len_dword : std_logic_vector(31 downto 0);
begin
tap_fifo_do <= host_tap_in;
process(clk)
begin
if rising_edge(clk) then
if restart_tape = '1' then
tzx_offset <= (others => '0');
tzx_state <= TZX_HEADER;
pulse_len <= (others => '0');
motor_counter <= (others => '0');
wave_period <= '0';
playing <= '0';
tzx_req <= tzx_ack;
loop_start <= '0';
loop_next <= '0';
loop_iter <= (others => '0');
else
-- simulate tape motor momentum
-- don't change the playing state if the motor is switched in 50 ms
-- Opera Soft K17 protection needs this!
cass_motor_D <= cass_motor;
if cass_motor_D /= cass_motor then
motor_counter <= CONV_STD_LOGIC_VECTOR(50*TZX_MS, motor_counter'length);
elsif motor_counter /= 0 then
if ce = '1' then motor_counter <= motor_counter - 1; end if;
else
playing <= cass_motor;
end if;
if playing = '0' then
--cass_read <= '1';
end if;
if pulse_len /= 0 then
if ce = '1' then
tick_cnt <= tick_cnt + 3500;
if tick_cnt >= (TZX_MS - 3500) then
tick_cnt <= tick_cnt - (TZX_MS - 3500);
wave_cnt <= wave_cnt + 1;
if wave_cnt = pulse_len then
wave_cnt <= (others => '0');
cass_read <= wave_period;
wave_period <= not wave_period;
if wave_period = end_period then
pulse_len <= (others => '0');
end if;
end if;
end if;
end if;
else
tick_cnt <= (others => '0');
wave_cnt <= (others => '0');
end if;
loop_start <= '0';
loop_next <= '0';
stop <= '0';
stop48k <= '0';
if playing = '1' and pulse_len = 0 and tzx_req = tzx_ack then
tzx_req <= not tzx_ack; -- default request for new data
case tzx_state is
when TZX_HEADER =>
cass_read <= '1';
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"0A" then -- skip 9 bytes, offset lags 1
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_NEWBLOCK =>
tzx_offset <= (others=>'0');
ms_counter <= (others=>'0');
case tap_fifo_do is
when x"10" => tzx_state <= TZX_NORMAL;
when x"11" => tzx_state <= TZX_TURBO;
when x"12" => tzx_state <= TZX_TONE;
when x"13" => tzx_state <= TZX_PULSES;
when x"14" => tzx_state <= TZX_DATA;
when x"15" => tzx_state <= TZX_DIRECT;
when x"18" => null; -- CSW recording (not implemented)
when x"19" => null; -- Generalized data block (not implemented)
when x"20" => tzx_state <= TZX_PAUSE;
when x"21" => tzx_state <= TZX_TEXT; -- Group start
when x"22" => null; -- Group end
when x"23" => null; -- Jump to block (not implemented)
when x"24" => tzx_state <= TZX_LOOP_START;
when x"25" => tzx_state <= TZX_LOOP_END;
when x"26" => null; -- Call sequence (not implemented)
when x"27" => null; -- Return from sequence (not implemented)
when x"28" => null; -- Select block (not implemented)
when x"2A" => tzx_state <= TZX_STOP48K;
when x"2B" => null; -- Set signal level (not implemented)
when x"30" => tzx_state <= TZX_TEXT;
when x"31" => tzx_state <= TZX_MESSAGE;
when x"32" => tzx_state <= TZX_ARCHIVE_INFO;
when x"33" => tzx_state <= TZX_HWTYPE;
when x"35" => tzx_state <= TZX_CUSTOM_INFO;
when x"5A" => tzx_state <= TZX_GLUE;
when others => null;
end case;
when TZX_LOOP_START =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then loop_iter( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then
loop_iter(15 downto 8) <= tap_fifo_do;
tzx_state <= TZX_NEWBLOCK;
loop_start <= '1';
end if;
when TZX_LOOP_END =>
if loop_iter > 1 then
loop_iter <= loop_iter - 1;
loop_next <= '1';
else
tzx_req <= tzx_ack; -- don't request new byte
end if;
tzx_state <= TZX_NEWBLOCK;
when TZX_PAUSE =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then
pause_len(7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then
pause_len(15 downto 8) <= tap_fifo_do;
tzx_state <= TZX_PAUSE2;
if pause_len(7 downto 0) = 0 and tap_fifo_do = 0 then
stop <= '1';
end if;
end if;
when TZX_PAUSE2 =>
tzx_req <= tzx_ack; -- don't request new byte
if ms_counter /= 0 then
if ce = '1' then
ms_counter <= ms_counter - 1;
-- Set pulse level to low after 1 ms
if ms_counter = 1 then
wave_period <= '0';
end_period <= '0';
cass_read <= '0';
end if;
end if;
elsif pause_len /= 0 then
pause_len <= pause_len - 1;
ms_counter <= conv_std_logic_vector(TZX_MS, 16);
else
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_STOP48K =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"03" then
stop48k <= '1';
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_HWTYPE =>
tzx_offset <= tzx_offset + 1;
-- 0, 1-3, 1-3, ...
if tzx_offset = x"00" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then
if data_len(7 downto 0) = x"01" then
tzx_state <= TZX_NEWBLOCK;
else
data_len(7 downto 0) <= data_len(7 downto 0) - 1;
tzx_offset <= x"01";
end if;
end if;
when TZX_MESSAGE =>
-- skip display time, then then same as TEXT DESRCRIPTION
tzx_state <= TZX_TEXT;
when TZX_TEXT =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = data_len(7 downto 0) then
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_ARCHIVE_INFO =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then data_len(15 downto 8) <= tap_fifo_do;
else
tzx_offset <= x"02";
data_len <= data_len - 1;
if data_len = 1 then
tzx_state <= TZX_NEWBLOCK;
end if;
end if;
when TZX_CUSTOM_INFO =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"10" then data_len_dword( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"11" then data_len_dword(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"12" then data_len_dword(23 downto 16) <= tap_fifo_do;
elsif tzx_offset = x"13" then data_len_dword(31 downto 24) <= tap_fifo_do;
elsif tzx_offset = x"14" then
tzx_offset <= x"14";
if data_len_dword = 1 then
tzx_state <= TZX_NEWBLOCK;
else
data_len_dword <= data_len_dword - 1;
end if;
end if;
when TZX_GLUE =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"08" then
tzx_state <= TZX_NEWBLOCK;
end if;
when TZX_TONE =>
tzx_offset <= tzx_offset + 1;
-- 0, 1, 2, 3, 4, 4, 4, ...
if tzx_offset = x"00" then pilot_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then pilot_l(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then pilot_pulses( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then
tzx_req <= tzx_ack; -- don't request new byte
pilot_pulses(15 downto 8) <= tap_fifo_do;
else
tzx_offset <= x"04";
tzx_req <= tzx_ack; -- don't request new byte
if pilot_pulses = 0 then
tzx_req <= not tzx_ack; -- default request for new data
tzx_state <= TZX_NEWBLOCK;
else
pilot_pulses <= pilot_pulses - 1;
end_period <= wave_period;
pulse_len <= pilot_l;
end if;
end if;
when TZX_PULSES =>
tzx_offset <= tzx_offset + 1;
-- 0, 1-2+3, 1-2+3, ...
if tzx_offset = x"00" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then one_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"02" then
tzx_req <= tzx_ack; -- don't request new byte
end_period <= wave_period;
pulse_len <= tap_fifo_do & one_l( 7 downto 0);
elsif tzx_offset = x"03" then
if data_len(7 downto 0) = x"01" then
tzx_state <= TZX_NEWBLOCK;
else
data_len(7 downto 0) <= data_len(7 downto 0) - 1;
tzx_offset <= x"01";
end if;
end if;
when TZX_DATA =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then zero_l ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then zero_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then one_l ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then one_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"04" then last_byte_bits <= tap_fifo_do(3 downto 0);
elsif tzx_offset = x"05" then pause_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"06" then pause_len(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"07" then data_len ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"08" then data_len (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"09" then
tzx_req <= tzx_ack; -- don't request new byte
data_len (23 downto 16) <= tap_fifo_do;
tzx_state <= TZX_PLAY_TAPBLOCK;
end if;
when TZX_NORMAL =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then pause_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then pause_len(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then data_len ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then
tzx_req <= tzx_ack; -- don't request new byte
data_len(15 downto 8) <= tap_fifo_do;
data_len(23 downto 16) <= (others => '0');
pilot_l <= conv_std_logic_vector(NORMAL_PILOT_LEN, 16);
sync1_l <= conv_std_logic_vector(NORMAL_SYNC1_LEN, 16);
sync2_l <= conv_std_logic_vector(NORMAL_SYNC2_LEN, 16);
zero_l <= conv_std_logic_vector(NORMAL_ZERO_LEN, 16);
one_l <= conv_std_logic_vector(NORMAL_ONE_LEN, 16);
pilot_pulses <= conv_std_logic_vector(NORMAL_PILOT_PULSES, 16);
last_byte_bits <= "1000";
tzx_state <= TZX_PLAY_TONE;
end if;
when TZX_TURBO =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then pilot_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"01" then pilot_l(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then sync1_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then sync1_l(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"04" then sync2_l( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"05" then sync2_l(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"06" then zero_l ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"07" then zero_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"08" then one_l ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"09" then one_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"0A" then pilot_pulses( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"0B" then pilot_pulses(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"0C" then last_byte_bits <= tap_fifo_do(3 downto 0);
elsif tzx_offset = x"0D" then pause_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"0E" then pause_len(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"0F" then data_len ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"10" then data_len (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"11" then
tzx_req <= tzx_ack; -- don't request new byte
data_len (23 downto 16) <= tap_fifo_do;
tzx_state <= TZX_PLAY_TONE;
end if;
when TZX_PLAY_TONE =>
tzx_req <= tzx_ack; -- don't request new byte
end_period <= not wave_period;
pulse_len <= pilot_l;
if pilot_pulses /= 0 then
pilot_pulses <= pilot_pulses - 1;
else
tzx_state <= TZX_PLAY_SYNC1;
end if;
when TZX_PLAY_SYNC1 =>
tzx_req <= tzx_ack; -- don't request new byte
end_period <= wave_period;
pulse_len <= sync1_l;
tzx_state <= TZX_PLAY_SYNC2;
when TZX_PLAY_SYNC2 =>
tzx_req <= tzx_ack; -- don't request new byte
end_period <= wave_period;
pulse_len <= sync2_l;
tzx_state <= TZX_PLAY_TAPBLOCK;
when TZX_PLAY_TAPBLOCK =>
bit_cnt <= "111";
tzx_state <= TZX_PLAY_TAPBLOCK2;
when TZX_PLAY_TAPBLOCK2 =>
tzx_req <= tzx_ack; -- don't request new byte
bit_cnt <= bit_cnt - 1;
if bit_cnt = "000" or (data_len = 1 and ((bit_cnt = (8 - last_byte_bits)) or (last_byte_bits = 0))) then
data_len <= data_len - 1;
tzx_state <= TZX_PLAY_TAPBLOCK3;
end if;
end_period <= not wave_period;
if tap_fifo_do(CONV_INTEGER(bit_cnt)) = '0' then
pulse_len <= zero_l;
else
pulse_len <= one_l;
end if;
when TZX_PLAY_TAPBLOCK3 =>
if data_len = 0 then
tzx_state <= TZX_PAUSE2;
else
tzx_state <= TZX_PLAY_TAPBLOCK4;
end if;
when TZX_PLAY_TAPBLOCK4 =>
tzx_req <= tzx_ack; -- don't request new byte
tzx_state <= TZX_PLAY_TAPBLOCK2;
when TZX_DIRECT =>
tzx_offset <= tzx_offset + 1;
if tzx_offset = x"00" then zero_l ( 7 downto 0) <= tap_fifo_do; -- here this is used for one bit, too
elsif tzx_offset = x"01" then zero_l (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"02" then pause_len ( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"03" then pause_len (15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"04" then last_byte_bits <= tap_fifo_do(3 downto 0);
elsif tzx_offset = x"05" then data_len( 7 downto 0) <= tap_fifo_do;
elsif tzx_offset = x"06" then data_len(15 downto 8) <= tap_fifo_do;
elsif tzx_offset = x"07" then
data_len(23 downto 16) <= tap_fifo_do;
tzx_state <= TZX_DIRECT2;
bit_cnt <= "111";
end if;
when TZX_DIRECT2 =>
tzx_req <= tzx_ack; -- don't request new byte
bit_cnt <= bit_cnt - 1;
if bit_cnt = "000" or (data_len = 1 and ((bit_cnt = (8 - last_byte_bits)) or (last_byte_bits = 0))) then
data_len <= data_len - 1;
tzx_state <= TZX_DIRECT3;
end if;
pulse_len <= zero_l;
cass_read <= tap_fifo_do(CONV_INTEGER(bit_cnt));
wave_period <= tap_fifo_do(CONV_INTEGER(bit_cnt));
end_period <= tap_fifo_do(CONV_INTEGER(bit_cnt));
when TZX_DIRECT3 =>
if data_len = 0 then
tzx_state <= TZX_PAUSE2;
else
tzx_state <= TZX_DIRECT2;
end if;
when others => null;
end case;
end if; -- play tzx
end if;
end if; -- clk
end process;
end struct;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbmst
-- File: ahbmst.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Generic AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbmst is
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in ahb_dma_in_type;
dmao : out ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture rtl of ahbmst is
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( venid, devid, 0, version, 0),
others => zero32);
type reg_type is record
start : std_ulogic;
retry : std_ulogic;
grant : std_ulogic;
active : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type := ('0', '0', '0', '0');
signal r, rin : reg_type;
begin
comb : process(ahbi, dmai, rst, r)
variable v : reg_type;
variable ready : std_ulogic;
variable retry : std_ulogic;
variable mexc : std_ulogic;
variable inc : std_logic_vector(5 downto 0); -- address increment
variable haddr : std_logic_vector(31 downto 0); -- AHB address
variable hwdata : std_logic_vector(AHBDW-1 downto 0); -- AHB write data
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable newaddr : std_logic_vector(9 downto 0); -- next sequential address
variable hbusreq : std_ulogic; -- bus request
variable hprot : std_logic_vector(3 downto 0); -- transfer type
variable xhirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; ready := '0'; mexc := '0'; retry := '0'; inc := (others => '0');
hprot := conv_std_logic_vector(chprot, 4); -- non-cached supervisor data
xhirq := (others => '0'); xhirq(hirq) := dmai.irq;
haddr := dmai.address; hbusreq := dmai.start;
hwdata := dmai.wdata;
newaddr := dmai.address(9 downto 0);
if INCADDR > 0 then
inc(conv_integer(dmai.size)) := '1';
newaddr := haddr(9 downto 0) + inc;
end if;
if dmai.burst = '0' then hburst := HBURST_SINGLE;
else hburst := HBURST_INCR; end if;
if dmai.start = '1' then
if (r.active and dmai.burst and not r.retry) = '1' then
haddr(9 downto 0) := newaddr;
if dmai.busy = '1' then htrans := HTRANS_BUSY;
else htrans := HTRANS_SEQ; end if;
hburst := HBURST_INCR;
else htrans := HTRANS_NONSEQ; end if;
else htrans := HTRANS_IDLE; end if;
if r.active = '1' then
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => ready := '1';
when HRESP_RETRY | HRESP_SPLIT=> retry := '1';
when others => ready := '1'; mexc := '1';
end case;
end if;
if ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT)) then
v.retry := not ahbi.hready;
else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
v.start := '0';
if ahbi.hready = '1' then
v.grant := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) or (htrans = HTRANS_BUSY) then
v.active := r.grant; v.start := r.grant;
else
v.active := '0';
end if;
end if;
if (not RESET_ALL) and (rst = '0') then
v.retry := RES.retry; v.active := RES.active;
end if;
rin <= v;
ahbo.haddr <= haddr;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= hwdata;
ahbo.hconfig <= hconfig;
ahbo.hlock <= '0';
ahbo.hwrite <= dmai.write;
ahbo.hsize <= dmai.size;
ahbo.hburst <= hburst;
ahbo.hprot <= hprot;
ahbo.hirq <= xhirq;
ahbo.hindex <= hindex;
dmao.start <= r.start;
dmao.active <= r.active;
dmao.ready <= ready;
dmao.mexc <= mexc;
dmao.retry <= retry;
dmao.haddr <= newaddr;
dmao.rdata <= ahbi.hrdata;
end process;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
end;
|
----------------------------------------------------------------------------------
-- Author: Jonny Doin, [email protected], [email protected]
--
-- Create Date: 01:21:32 06/30/2011
-- Design Name:
-- Module Name: spi_master_atlys_top
-- Project Name: spi_master_slave
-- Target Devices: Spartan-6 LX45
-- Tool versions: ISE 13.1
-- Description:
-- This is a verification project for the Digilent Atlys board, to test the SPI_MASTER, SPI_SLAVE and GRP_DEBOUNCE cores.
-- It uses the board's 100MHz clock input, and clocks all sequential logic at this clock.
--
-- See the "spi_master_atlys.ucf" file for pin assignments.
-- The test circuit uses the VHDCI connector on the Atlys to implement a 16-pin debug port to be used
-- with a Tektronix MSO2014. The 16 debug pins are brought to 2 8x2 headers that form a umbilical
-- digital pod port.
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/07/02 v0.01.0010 [JD] implemented a wire-through from switches to LEDs, just to test the toolchain. It worked!
-- 2011/07/03 v0.01.0020 [JD] added clock input, and a simple LED blinker for each LED.
-- 2011/07/03 v0.01.0030 [JD] added clear input, and instantiated a SPI_MASTER from my OpenCores project.
-- 2011/07/04 v0.01.0040 [JD] changed all clocks to clock enables, and use the 100MHz board pclk_i to clock all registers.
-- this change made the design go up to 288MHz, after synthesis.
-- 2011/07/07 v0.03.0050 [JD] implemented a 16pin umbilical port for the MSO2014 in the Atlys VmodBB board, and moved all
-- external monitoring pins to the VHDCI ports.
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 7.1428MHz,
-- 6.25MHz, 1MHz and 500kHz
-- 2011/07/29 v1.12.0105 [JD] spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug.
-- 2011/08/02 v1.13.0110 [JD] testbed for continuous transfer in FPGA hardware.
--
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity spi_master_atlys_top is
Generic (
N : positive := 8; -- 8bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 3; -- prefetch lookahead cycles
CLK_PERIOD : time := 10 ns; -- clock period for pclk_i (default 100MHz)
DEBOUNCE_TIME : time := 2 us); -- switch debounce time (use 200 us for silicon, 2 us for simulation)
Port (
sclk_i : in std_logic := 'X'; -- board clock input 100MHz
pclk_i : in std_logic := 'X'; -- board clock input 100MHz
--- SPI interface ---
spi_ssel_o : out std_logic; -- spi port SSEL
spi_sck_o : out std_logic; -- spi port SCK
spi_mosi_o : out std_logic; -- spi port MOSI
spi_miso_o : out std_logic; -- spi port MISO
--- input slide switches ---
sw_i : in std_logic_vector (7 downto 0); -- 8 input slide switches
--- input buttons ---
btn_i : in std_logic_vector (5 downto 0); -- 6 input push buttons
--- output LEDs ----
led_o : out std_logic_vector (7 downto 0); -- output leds
--- debug outputs ---
s_do_o : out std_logic_vector (7 downto 0);
m_do_o : out std_logic_vector (7 downto 0);
m_state_o : out std_logic_vector (3 downto 0); -- master spi fsm state
s_state_o : out std_logic_vector (3 downto 0); -- slave spi fsm state
dbg_o : out std_logic_vector (11 downto 0) -- 12 generic debug pins
);
end spi_master_atlys_top;
architecture rtl of spi_master_atlys_top is
--=============================================================================================
-- Constants
--=============================================================================================
-- clock divider count values from pclk_i (100MHz board clock)
-- these constants shall not be zero
constant FSM_CE_DIV : integer := 1; -- fsm operates at 100MHz
constant SPI_2X_CLK_DIV : integer := 1; -- 50MHz SPI clock
constant SAMP_CE_DIV : integer := 1; -- board signals sampled at 100MHz
-- button definitions
constant btRESET : integer := 0; -- these are constants to use as btn_i(x)
constant btUP : integer := 1;
constant btLEFT : integer := 2;
constant btDOWN : integer := 3;
constant btRIGHT : integer := 4;
constant btCENTER : integer := 5;
--=============================================================================================
-- Type definitions
--=============================================================================================
type fsm_master_write_state_type is
(st_reset, st_wait_spi_idle, st_wait_new_switch, st_send_spi_data_sw, st_wait_spi_ack_sw,
st_send_spi_data_1, st_wait_spi_ack_1, st_wait_spi_di_req_2, st_wait_spi_ack_2,
st_wait_spi_di_req_3, st_wait_spi_ack_3);
type fsm_slave_write_state_type is
(st_reset, st_wait_spi_start, st_wait_spi_di_req_2, st_wait_spi_ack_2, st_wait_spi_do_valid_1,
st_wait_spi_di_req_3, st_wait_spi_ack_3, st_wait_spi_end);
type fsm_slave_read_state_type is
(st_reset, st_wait_spi_do_valid_1, st_wait_spi_n_do_valid_1, st_wait_spi_do_valid_2,
st_wait_spi_n_do_valid_2, st_wait_spi_do_valid_3, st_wait_spi_n_do_valid_3);
--=============================================================================================
-- Signals for state machine control
--=============================================================================================
signal m_wr_st_reg : fsm_master_write_state_type := st_reset;
signal m_wr_st_next : fsm_master_write_state_type := st_reset;
signal s_wr_st_reg : fsm_slave_write_state_type := st_reset;
signal s_wr_st_next : fsm_slave_write_state_type := st_reset;
signal s_rd_st_reg : fsm_slave_read_state_type := st_reset;
signal s_rd_st_next : fsm_slave_read_state_type := st_reset;
--=============================================================================================
-- Signals for internal operation
--=============================================================================================
--- clock enable signals ---
signal samp_ce : std_logic := '1'; -- clock enable for sample inputs
signal fsm_ce : std_logic := '1'; -- clock enable for fsm logic
--- switch debouncer signals ---
signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- debounced switch data
signal sw_reg : std_logic_vector (7 downto 0) := (others => '0'); -- registered switch data
signal sw_next : std_logic_vector (7 downto 0) := (others => '0'); -- combinatorial switch data
signal new_switch : std_logic := '0'; -- detector for new switch data
--- pushbutton debouncer signals ---
signal btn_data : std_logic_vector (5 downto 0) := (others => '0'); -- debounced state of pushbuttons
signal btn_reg : std_logic_vector (5 downto 0) := (others => '0'); -- registered button data
signal btn_next : std_logic_vector (5 downto 0) := (others => '0'); -- combinatorial button data
signal new_button : std_logic := '0'; -- detector for new button data
--- spi port signals ---
-- spi bus wires
signal spi_ssel : std_logic;
signal spi_sck : std_logic;
signal spi_mosi : std_logic;
signal spi_miso : std_logic;
-- spi master port control signals
signal spi_rst_reg : std_logic := '1';
signal spi_rst_next : std_logic := '1';
signal spi_ssel_reg : std_logic;
signal spi_wren_reg_m : std_logic := '0';
signal spi_wren_next_m : std_logic := '0';
-- spi master port flow control flags
signal spi_di_req_m : std_logic;
signal spi_do_valid_m : std_logic;
-- spi master port parallel data bus
signal spi_di_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_di_next_m : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_do_m : std_logic_vector (N-1 downto 0);
signal spi_wr_ack_m : std_logic;
-- spi slave port control signals
signal spi_wren_reg_s : std_logic := '1';
signal spi_wren_next_s : std_logic := '1';
-- spi slave port flow control flags
signal spi_di_req_s : std_logic;
signal spi_do_valid_s : std_logic;
-- spi slave port parallel data bus
signal spi_di_reg_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_di_next_s : std_logic_vector (N-1 downto 0) := (others => '0');
signal spi_do_s : std_logic_vector (N-1 downto 0);
signal spi_wr_ack_s : std_logic;
signal spi_rx_bit_s : std_logic;
-- spi debug data --
signal spi_state_m : std_logic_vector (3 downto 0);
signal spi_state_s : std_logic_vector (3 downto 0);
-- slave data output regs --
signal s_do_1_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_1_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_2_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_2_next : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_3_reg : std_logic_vector (N-1 downto 0) := (others => '0');
signal s_do_3_next : std_logic_vector (N-1 downto 0) := (others => '0');
-- other signals
signal clear : std_logic := '0';
-- debug output signals
signal leds_reg : std_logic_vector (7 downto 0);
signal leds_next : std_logic_vector (7 downto 0) := (others => '0');
signal dbg : std_logic_vector (11 downto 0) := (others => '0');
begin
--=============================================================================================
-- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
--=============================================================================================
-- spi master port: data and control signals driven by the master fsm
Inst_spi_master_port: entity work.spi_master(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
port map(
sclk_i => sclk_i, -- system clock is used for serial and parallel ports
pclk_i => pclk_i,
rst_i => spi_rst_reg,
spi_ssel_o => spi_ssel,
spi_sck_o => spi_sck,
spi_mosi_o => spi_mosi,
spi_miso_i => spi_miso, -- driven by the spi slave
di_req_o => spi_di_req_m,
di_i => spi_di_reg_m,
wren_i => spi_wren_reg_m,
wr_ack_o => spi_wr_ack_m,
do_valid_o => spi_do_valid_m,
do_o => spi_do_m,
------------ debug pins ------------
state_dbg_o => spi_state_m -- debug: internal state register
);
-- spi slave port: data and control signals driven by the slave fsm
Inst_spi_slave_port: entity work.spi_slave(rtl)
generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH)
port map(
clk_i => pclk_i,
spi_ssel_i => spi_ssel, -- driven by the spi master
spi_sck_i => spi_sck, -- driven by the spi master
spi_mosi_i => spi_mosi, -- driven by the spi master
spi_miso_o => spi_miso,
di_req_o => spi_di_req_s,
di_i => spi_di_reg_s,
wren_i => spi_wren_reg_s,
wr_ack_o => spi_wr_ack_s,
do_valid_o => spi_do_valid_s,
do_o => spi_do_s,
------------ debug pins ------------
state_dbg_o => spi_state_s -- debug: internal state register
);
-- debounce for the input switches, with new data strobe output
Inst_sw_debouncer: entity work.grp_debouncer(rtl)
generic map (N => 8, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 8 inputs with selected settling time
port map(
clk_i => pclk_i, -- system clock
data_i => sw_i, -- noisy input data
data_o => sw_data -- registered stable output data
);
-- debounce for the input pushbuttons, with new data strobe output
Inst_btn_debouncer: entity work.grp_debouncer(rtl)
generic map (N => 6, CNT_VAL => DEBOUNCE_TIME / CLK_PERIOD) -- debounce 6 inputs with selected settling time
port map(
clk_i => pclk_i, -- system clock
data_i => btn_i, -- noisy input data
data_o => btn_data -- registered stable output data
);
--=============================================================================================
-- CONSTANTS CONSTRAINTS CHECKING
--=============================================================================================
-- clock dividers shall not be zero
assert FSM_CE_DIV > 0
report "Constant 'FSM_CE_DIV' should not be zero"
severity FAILURE;
-- minimum prefetch lookahead check
assert SPI_2X_CLK_DIV > 0
report "Constant 'SPI_2X_CLK_DIV' should not be zero"
severity FAILURE;
-- maximum prefetch lookahead check
assert SAMP_CE_DIV > 0
report "Constant 'SAMP_CE_DIV' should not be zero"
severity FAILURE;
--=============================================================================================
-- CLOCK GENERATION
--=============================================================================================
-- All registers are clocked directly from the 100MHz system clock.
-- The clock generation block derives 2 clock enable signals, divided down from the 100MHz input
-- clock.
-- input sample clock enable,
-- fsm clock enable,
-----------------------------------------------------------------------------------------------
-- generate the sampling clock enable from the 100MHz board input clock
samp_ce_gen_proc: process (pclk_i) is
variable clk_cnt : integer range SAMP_CE_DIV-1 downto 0 := 0;
begin
if pclk_i'event and pclk_i = '1' then
if clk_cnt = SAMP_CE_DIV-1 then
samp_ce <= '1'; -- generate a single pulse every SAMP_CE_DIV clocks
clk_cnt := 0;
else
samp_ce <= '0';
clk_cnt := clk_cnt + 1;
end if;
end if;
end process samp_ce_gen_proc;
-- generate the fsm clock enable from the 100MHz board input clock
fsm_ce_gen_proc: process (pclk_i) is
variable clk_cnt : integer range FSM_CE_DIV-1 downto 0 := 0;
begin
if pclk_i'event and pclk_i = '1' then
if clk_cnt = FSM_CE_DIV-1 then
fsm_ce <= '1'; -- generate a single pulse every FSM_CE_DIV clocks
clk_cnt := 0;
else
fsm_ce <= '0';
clk_cnt := clk_cnt + 1;
end if;
end if;
end process fsm_ce_gen_proc;
--=============================================================================================
-- INPUTS LOGIC
--=============================================================================================
-- registered inputs
samp_inputs_proc: process (pclk_i) is
begin
if pclk_i'event and pclk_i = '1' then
if samp_ce = '1' then
clear <= btn_data(btUP); -- clear is button UP
leds_reg <= leds_next; -- update LEDs with spi_slave received data
end if;
end if;
end process samp_inputs_proc;
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the system clock
fsm_reg_proc : process (pclk_i) is
begin
-- FFD registers clocked on rising edge and cleared on sync 'clear'
if pclk_i'event and pclk_i = '1' then
if clear = '1' then -- sync reset
m_wr_st_reg <= st_reset; -- only provide local reset for the state registers
else
if fsm_ce = '1' then
m_wr_st_reg <= m_wr_st_next; -- master write state register update
end if;
end if;
end if;
-- FFD registers clocked on rising edge and cleared on ssel = '1'
if pclk_i'event and pclk_i = '1' then
if spi_ssel = '1' then -- sync reset
s_wr_st_reg <= st_reset; -- only provide local reset for the state registers
s_rd_st_reg <= st_reset;
else
if fsm_ce = '1' then
s_wr_st_reg <= s_wr_st_next; -- slave write state register update
s_rd_st_reg <= s_rd_st_next; -- slave read state register update
end if;
end if;
end if;
-- FFD registers clocked on rising edge, with no reset
if pclk_i'event and pclk_i = '1' then
if fsm_ce = '1' then
--------- master write fsm signals -----------
spi_wren_reg_m <= spi_wren_next_m;
spi_di_reg_m <= spi_di_next_m;
spi_rst_reg <= spi_rst_next;
spi_ssel_reg <= spi_ssel;
sw_reg <= sw_next;
btn_reg <= btn_next;
--------- slave write fsm signals -----------
spi_wren_reg_s <= spi_wren_next_s;
spi_di_reg_s <= spi_di_next_s;
--------- slave read fsm signals -----------
s_do_1_reg <= s_do_1_next;
s_do_2_reg <= s_do_2_next;
s_do_3_reg <= s_do_3_next;
end if;
end if;
end process fsm_reg_proc;
--=============================================================================================
-- COMBINATORIAL NEXT-STATE LOGIC PROCESSES
--=============================================================================================
-- edge detector for new switch data
new_switch_proc: new_switch <= '1' when sw_data /= sw_reg else '0'; -- '1' for change edge
-- edge detector for new button data
new_button_proc: new_button <= '1' when btn_data /= btn_reg else '0'; -- '1' for change edge
-- master port write fsmd logic
fsm_m_wr_combi_proc: process ( m_wr_st_reg, spi_wren_reg_m, spi_di_reg_m, spi_di_req_m, spi_wr_ack_m,
spi_ssel_reg, spi_rst_reg, sw_data, sw_reg, new_switch, btn_data, btn_reg,
new_button, clear) is
begin
spi_rst_next <= spi_rst_reg;
spi_di_next_m <= spi_di_reg_m;
spi_wren_next_m <= spi_wren_reg_m;
sw_next <= sw_reg;
btn_next <= btn_reg;
m_wr_st_next <= m_wr_st_reg;
case m_wr_st_reg is
when st_reset =>
spi_rst_next <= '1'; -- place spi interface on reset
spi_di_next_m <= (others => '0'); -- clear spi data port
spi_wren_next_m <= '0'; -- deassert write enable
m_wr_st_next <= st_wait_spi_idle;
when st_wait_spi_idle =>
spi_wren_next_m <= '0'; -- remove write strobe on next clock
if spi_ssel_reg = '1' then
spi_rst_next <= '0'; -- remove reset when interface is idle
m_wr_st_next <= st_wait_new_switch;
end if;
when st_wait_new_switch =>
if new_switch = '1' then -- wait for new stable switch data
sw_next <= sw_data; -- load new switch data (end the mismatch condition)
m_wr_st_next <= st_send_spi_data_sw;
elsif new_button = '1' then
btn_next <= btn_data; -- load new button data (end the mismatch condition)
if clear = '0' then
if btn_data(btDOWN) = '1' then
m_wr_st_next <= st_send_spi_data_sw;
elsif btn_data(btLEFT) = '1' then
m_wr_st_next <= st_send_spi_data_1;
elsif btn_data(btCENTER) = '1' then
m_wr_st_next <= st_send_spi_data_1;
elsif btn_data(btRIGHT) = '1' then
m_wr_st_next <= st_send_spi_data_1;
end if;
end if;
end if;
when st_send_spi_data_sw =>
spi_di_next_m <= sw_reg; -- load switch register to the spi port
spi_wren_next_m <= '1'; -- write data on next clock
m_wr_st_next <= st_wait_spi_ack_sw;
when st_wait_spi_ack_sw => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_di_req_2;
end if;
when st_send_spi_data_1 =>
spi_di_next_m <= X"A1"; -- load switch register to the spi port
spi_wren_next_m <= '1'; -- write data on next clock
m_wr_st_next <= st_wait_spi_ack_1;
when st_wait_spi_ack_1 => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_di_req_2;
end if;
when st_wait_spi_di_req_2 =>
if spi_di_req_m = '1' then
spi_di_next_m <= X"A2";
spi_wren_next_m <= '1';
m_wr_st_next <= st_wait_spi_ack_2;
end if;
when st_wait_spi_ack_2 => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_di_req_3;
end if;
when st_wait_spi_di_req_3 =>
if spi_di_req_m = '1' then
spi_di_next_m <= X"A3";
spi_wren_next_m <= '1';
m_wr_st_next <= st_wait_spi_ack_3;
end if;
when st_wait_spi_ack_3 => -- the actual write happens on this state
if spi_wr_ack_m = '1' then
spi_wren_next_m <= '0'; -- remove write strobe on next clock
m_wr_st_next <= st_wait_spi_idle; -- wait transmission end
end if;
when others =>
m_wr_st_next <= st_reset; -- state st_reset is safe state
end case;
end process fsm_m_wr_combi_proc;
-- slave port write fsmd logic
fsm_s_wr_combi_proc: process ( s_wr_st_reg, spi_di_req_s, spi_wr_ack_s, spi_do_valid_s,
spi_di_reg_s, spi_wren_reg_s, spi_ssel_reg) is
begin
spi_wren_next_s <= spi_wren_reg_s;
spi_di_next_s <= spi_di_reg_s;
s_wr_st_next <= s_wr_st_reg;
case s_wr_st_reg is
when st_reset =>
spi_di_next_s <= X"51"; -- write first data word
spi_wren_next_s <= '1'; -- set write enable
s_wr_st_next <= st_wait_spi_start;
when st_wait_spi_start =>
if spi_ssel_reg = '0' then -- wait for slave select
spi_wren_next_s <= '0'; -- remove write enable
s_wr_st_next <= st_wait_spi_di_req_2;
end if;
when st_wait_spi_di_req_2 =>
if spi_di_req_s = '1' then
-- spi_di_next_s <= X"D2"; -- do not write on this cycle (cycle miss)
-- spi_wren_next_s <= '1';
-- s_wr_st_next <= st_wait_spi_ack_2;
s_wr_st_next <= st_wait_spi_do_valid_1;
end if;
when st_wait_spi_ack_2 => -- the actual write happens on this state
if spi_wr_ack_s = '1' then
spi_wren_next_s <= '0'; -- remove write strobe on next clock
s_wr_st_next <= st_wait_spi_di_req_3;
end if;
when st_wait_spi_do_valid_1 =>
if spi_do_valid_s = '1' then
s_wr_st_next <= st_wait_spi_di_req_3;
end if;
when st_wait_spi_di_req_3 =>
if spi_di_req_s = '1' then
spi_di_next_s <= X"D3";
spi_wren_next_s <= '1';
s_wr_st_next <= st_wait_spi_ack_3;
end if;
when st_wait_spi_ack_3 => -- the actual write happens on this state
if spi_wr_ack_s = '1' then
spi_wren_next_s <= '0'; -- remove write strobe on next clock
s_wr_st_next <= st_wait_spi_end; -- wait transmission end
end if;
when st_wait_spi_end => -- wait interface to be deselected
if spi_ssel_reg = '1' then
s_wr_st_next <= st_reset; -- wait transmission start
end if;
when others =>
s_wr_st_next <= st_reset; -- state st_reset is safe state
end case;
end process fsm_s_wr_combi_proc;
-- slave port read fsmd logic
fsm_s_rd_combi_proc: process ( s_rd_st_reg, spi_do_valid_s, spi_do_s, s_do_1_reg, s_do_2_reg, s_do_3_reg) is
begin
s_do_1_next <= s_do_1_reg;
s_do_2_next <= s_do_2_reg;
s_do_3_next <= s_do_3_reg;
s_rd_st_next <= s_rd_st_reg;
case s_rd_st_reg is
when st_reset =>
s_rd_st_next <= st_wait_spi_do_valid_1;
when st_wait_spi_do_valid_1 =>
if spi_do_valid_s = '1' then -- wait for receive data ready
s_do_1_next <= spi_do_s; -- read data from output port
s_rd_st_next <= st_wait_spi_n_do_valid_1;
end if;
when st_wait_spi_n_do_valid_1 =>
if spi_do_valid_s = '0' then
s_rd_st_next <= st_wait_spi_do_valid_2;
end if;
when st_wait_spi_do_valid_2 =>
if spi_do_valid_s = '1' then -- wait for receive data ready
s_do_2_next <= spi_do_s; -- read data from output port
s_rd_st_next <= st_wait_spi_n_do_valid_2;
end if;
when st_wait_spi_n_do_valid_2 =>
if spi_do_valid_s = '0' then
s_rd_st_next <= st_wait_spi_do_valid_3;
end if;
when st_wait_spi_do_valid_3 =>
if spi_do_valid_s = '1' then -- wait for receive data ready
s_do_3_next <= spi_do_s; -- read data from output port
s_rd_st_next <= st_wait_spi_n_do_valid_3;
end if;
when st_wait_spi_n_do_valid_3 =>
if spi_do_valid_s = '0' then
s_rd_st_next <= st_reset;
end if;
when others =>
s_rd_st_next <= st_reset; -- state st_reset is safe state
end case;
end process fsm_s_rd_combi_proc;
leds_combi_proc: process (btn_data, leds_reg, s_do_1_reg, s_do_2_reg, s_do_3_reg) is
begin
leds_next <= leds_reg;
if btn_data(btRIGHT) = '1' then
leds_next <= s_do_3_reg;
elsif btn_data(btCENTER) = '1' then
leds_next <= s_do_2_reg;
elsif btn_data(btLEFT) = '1' then
leds_next <= s_do_1_reg;
elsif btn_data(btDOWN) = '1' then
leds_next <= s_do_1_reg;
end if;
end process leds_combi_proc;
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
-- connect the spi output wires
spi_ssel_o_proc: spi_ssel_o <= spi_ssel;
spi_sck_o_proc: spi_sck_o <= spi_sck;
spi_mosi_o_proc: spi_mosi_o <= spi_mosi;
spi_miso_o_proc: spi_miso_o <= spi_miso;
-- connect leds_reg signal to LED outputs
led_o_proc: led_o <= leds_reg;
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- connect the debug vector outputs
dbg_o_proc: dbg_o <= dbg;
-- connect debug port pins to spi ports instances interface signals
-- master signals mapped on dbg
dbg(11) <= spi_wren_reg_m;
dbg(10) <= spi_wr_ack_m;
dbg(9) <= spi_di_req_m;
dbg(8) <= spi_do_valid_m;
-- slave signals mapped on dbg
dbg(7) <= spi_wren_reg_s;
dbg(6) <= spi_wr_ack_s;
dbg(5) <= spi_di_req_s;
dbg(4) <= spi_do_valid_s;
dbg(3 downto 0) <= spi_state_s;
-- specific ports to test on testbench
s_do_o <= spi_do_s;
m_do_o <= spi_do_m;
m_state_o <= spi_state_m; -- master spi fsm state
s_state_o <= spi_state_s; -- slave spi fsm state
end rtl;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:10:22 11/17/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282/My_32bitAdder_tb_948282.vhd
-- Project Name: Mips32_948282
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: My_32bitAdder_948282
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY My_32bitAdder_tb_948282 IS
END My_32bitAdder_tb_948282;
ARCHITECTURE behavior OF My_32bitAdder_tb_948282 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT My_32bitAdder_948282
PORT(
A_reg : IN std_logic_vector(31 downto 0);
B_reg : IN std_logic_vector(31 downto 0);
CarryIn : IN std_logic;
CarryOut : OUT std_logic;
Result : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal A_reg : std_logic_vector(31 downto 0) := (others => '0');
signal B_reg : std_logic_vector(31 downto 0) := (others => '0');
signal CarryIn : std_logic := '0';
signal CarryOut : std_logic := '0';
--Outputs
signal Result : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: My_32bitAdder_948282 PORT MAP (
A_reg => A_reg,
B_reg => B_reg,
CarryIn => CarryIn,
CarryOut => CarryOut,
Result => Result
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
CarryIn<='0';
A_reg<="00000000000000000000000000000001";
B_reg<="00000000000000000000000000000100";
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test_xor_32_bits is
end test_xor_32_bits;
architecture behavior of test_xor_32_bits is
signal data_in: std_logic_vector(0 to 31);
signal key: std_logic_vector(0 to 31);
signal data_out: std_logic_vector(0 to 31);
begin
uut: entity xor_32_bits port map (data_in,key,data_out);
testprocess: process is
begin
data_in<="01100000000000000000000000000001";
key<="10100000000000000000000000000000";
wait for 10 ns;
end process testprocess;
end architecture behavior;
|
-- niosii_system_width_adapter_005.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_width_adapter_005 is
generic (
IN_PKT_ADDR_H : integer := 33;
IN_PKT_ADDR_L : integer := 9;
IN_PKT_DATA_H : integer := 7;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 8;
IN_PKT_BYTEEN_L : integer := 8;
IN_PKT_BYTE_CNT_H : integer := 42;
IN_PKT_BYTE_CNT_L : integer := 40;
IN_PKT_TRANS_COMPRESSED_READ : integer := 34;
IN_PKT_BURSTWRAP_H : integer := 45;
IN_PKT_BURSTWRAP_L : integer := 43;
IN_PKT_BURST_SIZE_H : integer := 48;
IN_PKT_BURST_SIZE_L : integer := 46;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 39;
IN_PKT_BURST_TYPE_H : integer := 50;
IN_PKT_BURST_TYPE_L : integer := 49;
IN_ST_DATA_W : integer := 73;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 69;
OUT_PKT_BYTE_CNT_L : integer := 67;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 61;
OUT_PKT_BURST_SIZE_H : integer := 75;
OUT_PKT_BURST_SIZE_L : integer := 73;
OUT_PKT_RESPONSE_STATUS_H : integer := 99;
OUT_PKT_RESPONSE_STATUS_L : integer := 98;
OUT_PKT_TRANS_EXCLUSIVE : integer := 66;
OUT_PKT_BURST_TYPE_H : integer := 77;
OUT_PKT_BURST_TYPE_L : integer := 76;
OUT_ST_DATA_W : integer := 100;
ST_CHANNEL_W : integer := 13;
OPTIMIZE_FOR_RSP : integer := 1;
RESPONSE_PATH : integer := 1
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(12 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(72 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(99 downto 0); -- .data
out_channel : out std_logic_vector(12 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity niosii_system_width_adapter_005;
architecture rtl of niosii_system_width_adapter_005 is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(99 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter_005 : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of niosii_system_width_adapter_005
|
entity comp1_bot is
port (
x : in integer;
y : out integer );
end entity;
architecture rtl of comp1_bot is
begin
y <= x + 1;
end architecture;
-------------------------------------------------------------------------------
entity comp1 is
end entity;
architecture rtl of comp1 is
signal a, b : integer;
component comp1_bot is
port (
x : in integer;
y : out integer );
end component;
begin
c1: component comp1_bot
port map ( 1, a );
c2: comp1_bot
port map ( 2, b );
process is
begin
wait for 1 ns;
assert a = 2;
assert b = 3;
wait;
end process;
end architecture;
|
entity comp1_bot is
port (
x : in integer;
y : out integer );
end entity;
architecture rtl of comp1_bot is
begin
y <= x + 1;
end architecture;
-------------------------------------------------------------------------------
entity comp1 is
end entity;
architecture rtl of comp1 is
signal a, b : integer;
component comp1_bot is
port (
x : in integer;
y : out integer );
end component;
begin
c1: component comp1_bot
port map ( 1, a );
c2: comp1_bot
port map ( 2, b );
process is
begin
wait for 1 ns;
assert a = 2;
assert b = 3;
wait;
end process;
end architecture;
|
entity comp1_bot is
port (
x : in integer;
y : out integer );
end entity;
architecture rtl of comp1_bot is
begin
y <= x + 1;
end architecture;
-------------------------------------------------------------------------------
entity comp1 is
end entity;
architecture rtl of comp1 is
signal a, b : integer;
component comp1_bot is
port (
x : in integer;
y : out integer );
end component;
begin
c1: component comp1_bot
port map ( 1, a );
c2: comp1_bot
port map ( 2, b );
process is
begin
wait for 1 ns;
assert a = 2;
assert b = 3;
wait;
end process;
end architecture;
|
entity comp1_bot is
port (
x : in integer;
y : out integer );
end entity;
architecture rtl of comp1_bot is
begin
y <= x + 1;
end architecture;
-------------------------------------------------------------------------------
entity comp1 is
end entity;
architecture rtl of comp1 is
signal a, b : integer;
component comp1_bot is
port (
x : in integer;
y : out integer );
end component;
begin
c1: component comp1_bot
port map ( 1, a );
c2: comp1_bot
port map ( 2, b );
process is
begin
wait for 1 ns;
assert a = 2;
assert b = 3;
wait;
end process;
end architecture;
|
entity comp1_bot is
port (
x : in integer;
y : out integer );
end entity;
architecture rtl of comp1_bot is
begin
y <= x + 1;
end architecture;
-------------------------------------------------------------------------------
entity comp1 is
end entity;
architecture rtl of comp1 is
signal a, b : integer;
component comp1_bot is
port (
x : in integer;
y : out integer );
end component;
begin
c1: component comp1_bot
port map ( 1, a );
c2: comp1_bot
port map ( 2, b );
process is
begin
wait for 1 ns;
assert a = 2;
assert b = 3;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : Finite Impulse Response Filter
-- Author : Steiger Martin <[email protected]>
-------------------------------------------------------------------------------
-- Description : Simple FIR filter structure for damping, amplifying and
-- compounding audio signals
-------------------------------------------------------------------------------
architecture Rtl of FIR is
constant sfixed_high : integer := 0;
constant sfixed_low : integer := -(gDataWidth-1);
constant sfixed_no_ovf : integer := -(gDataWidth/2 -1);
type aCoeffArray is array (gMaxNumCoeffs - 1 downto 0) of sfixed(sfixed_high downto sfixed_low);
subtype aStageAddr is integer range 0 to gMaxNumCoeffs -1;
type aStage is array(0 to gMaxNumCoeffs -1) of sfixed(sfixed_high downto sfixed_low); -- register array for input values
-- *************************
-- FSM STATE DEFINES
-- *************************
type aFilterState is (IDLE, MULT);
-- *************************
-- RECORDS
-- *************************
type filt_record is record
FiltData : sfixed(sfixed_high downto sfixed_low); -- filtered data
MovSample : sfixed(sfixed_high downto sfixed_low);
StageCnt : integer range 0 to gMaxNumCoeffs; -- stage index
CoeffCnt : integer range 0 to gMaxNumCoeffs; -- coeff index
State : aFilterState; -- FSM state
valid : std_ulogic; -- valid signal if filtering for current input value is finished
WriteIndex : integer range 0 to gMaxNumCoeffs; -- write index for stage ring buffer
ReadIndex : integer range 0 to gMaxNumCoeffs; -- read index for stage ring buffer
NumOfReads : integer; -- check signal for number of reads from stages and coeffs
FiltOut : sfixed(sfixed_high downto sfixed_low); -- filter output data
end record;
-- *************************
-- DEFAULT RECORD VALUES
-- *************************
constant filt_def_config : filt_record := (
to_sfixed(0.0, sfixed_high, sfixed_low),
to_sfixed(0.0, sfixed_high, sfixed_low),
0,
0,
IDLE,
--(others => to_sfixed(0.0, sfixed_high, sfixed_low)),
cInactivated,
0,
1,
0,
to_sfixed(0.0, sfixed_high, sfixed_low)
);
-- create the ram memory for the coefficients and the stages (the delayed values z^-1)
signal Coeff : aCoeffArray;
signal Stages : aStage ;
-- create the structures for the FSM
signal R, NxR : filt_record;
subtype result_type is std_logic_vector (gDataWidth-1 downto 0); -- for casting sfixed to std_logic_vector
begin
-- ******************************************************************************
-- READ FROM AND WRITE INTO COEFFICIENT RAM AREA
-- ******************************************************************************
RAMReadWrite: process(csi_clk)
begin
if (rising_edge(csi_clk)) then
if(avs_s0_write = cActivated) then
if(unsigned(avs_s0_address)) < gMaxNumCoeffs then -- write into RAM
Coeff(to_integer(unsigned(avs_s0_address))) <= to_sfixed(avs_s0_writedata(gDataWidth - 1 downto 0), sfixed_high, sfixed_low);
end if;
end if;
avs_s0_readdata(gDataWidth-1 downto 0) <= result_type(Coeff(to_integer(unsigned(avs_s0_address))));
end if;
end process;
-- ******************************************************************************
-- REGISTER PROCESS FOR FILTER
-- ******************************************************************************
REG: process(csi_clk, rsi_reset_n)
begin
if (rsi_reset_n = cnActivated) then
R <= filt_def_config;
elsif (rising_edge(csi_clk)) then
R <= NxR;
end if;
end process;
-- ******************************************************************************
-- COMBINATORICAL PROCESS: FOR MULTIPLICATION AND STORING WITHIN THE STAGES
-- ******************************************************************************
COMB: process(R, asi_valid, asi_data, Coeff)
-- TEMPORARY VARIABLES, NO STORING FUNCTION
variable tmp : sfixed(sfixed_high downto sfixed_low);
variable tmp_b : sfixed(sfixed_high downto sfixed_low);
variable tmp_stages : sfixed(sfixed_high downto sfixed_low);
variable tmp_coeffs : sfixed(sfixed_high downto sfixed_low);
begin
-- default assignments
NxR <= R;
tmp := to_sfixed(0.0, sfixed_high, sfixed_low);
tmp_b := to_sfixed(0.0, sfixed_high, sfixed_low);
tmp_stages := to_sfixed(0.0, sfixed_high, sfixed_low);
tmp_coeffs := to_sfixed(0.0, sfixed_high, sfixed_low);
case(R.State) is
when IDLE => -- wait until input data is valid
if asi_valid = cActivated then
NxR.FiltOut <= R.FiltData;
NxR.FiltData <= to_sfixed(0.0, sfixed_high, sfixed_low); -- reset tmp filter data
NxR.MovSample <= to_sfixed(asi_data, sfixed_high, sfixed_low);
NxR.State <= MULT; -- set next stage
NxR.StageCnt <= R.ReadIndex;
NxR.NumOfReads <= 0;
NxR.CoeffCnt <= 0; -- reset the sub FSM
end if;
NxR.valid <= cInactivated;
when MULT => -- multiply stages and coefficients
-- NxR.valid <= cInactivated;
Stages(R.WriteIndex) <= R.MovSample; --to_sfixed(asi_data, sfixed_high, sfixed_low); -- write new data into stages
-- TODO: do exchange stages value and movSample
--NxR.MovSample <= Stage
--TODO: check the overflow of stagecnt
if (R.CoeffCnt < gMaxNumCoeffs ) then --and R.StageCnt < gNumberOfCoeffs) then --multiply (ATTENTION: size <= 32 Bit)
-- do multiplication of one sample
tmp_coeffs := Coeff(R.CoeffCnt);
tmp_stages := Stages(R.StageCnt);
tmp := resize((tmp_coeffs *tmp_stages), tmp);
--tmp_b := resize(tmp + resize(R.FiltData, tmp), tmp_b);
-- do the addition of all coefficients
NxR.FiltData <= resize(tmp + R.FiltData, NxR.FiltData);
-- NxR.FiltData <= tmp_b;
NxR.CoeffCnt <= R.CoeffCnt + 1;
NxR.StageCnt <= R.StageCnt + 1;
NxR.NumOfReads <= R.NumOfReads + 1;
end if;
if (R.StageCnt >= gMaxNumCoeffs-1) then -- restart (ringbuffer read not finished)
NxR.StageCnt <= 0;
end if;
if (R.NumOfReads >= gMaxNumCoeffs-1) then -- stages finished
if(R.WriteIndex >= gMaxNumCoeffs-1) then
NxR.WriteIndex <= 0;
else
NxR.WriteIndex <= R.WriteIndex + 1;
end if;
if(R.ReadIndex >= gMaxNumCoeffs-1) then
NxR.ReadIndex <= 0;
else
NxR.ReadIndex <= R.ReadIndex + 1;
end if;
NxR.valid <= cActivated;
NxR.State <= IDLE;
end if;
when others => NxR.State <= IDLE;
end case;
end process;
--aso_valid <= asi_valid;
aso_valid <= R.valid;
aso_data <= to_slv(R.FiltOut); --when R.valid = cActivated else to_slv(R.LastFiltered);
end architecture Rtl;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
begin
process is
-- code from book:
type coordinate is array (1 to 3) of real;
type coordinate_ptr is access coordinate;
variable origin : coordinate_ptr := new coordinate'(0.0, 0.0, 0.0);
type time_array is array (positive range <>) of time;
variable activation_times : time_array(1 to 100);
-- end of code from book
begin
report real'image( origin(1) );
report real'image( origin(2) );
report real'image( origin(3) );
report real'image( origin.all(1) );
wait;
end process;
process is
type time_array is array (positive range <>) of time;
-- code from book:
type time_array_ptr is access time_array;
variable activation_times : time_array_ptr;
-- end of code from book
begin
-- code from book:
activation_times := new time_array'(10 us, 15 us, 40 us);
activation_times := new time_array'( activation_times.all
& time_array'(70 us, 100 us) );
activation_times := new time_array(1 to 10);
-- end of code from book
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
begin
process is
-- code from book:
type coordinate is array (1 to 3) of real;
type coordinate_ptr is access coordinate;
variable origin : coordinate_ptr := new coordinate'(0.0, 0.0, 0.0);
type time_array is array (positive range <>) of time;
variable activation_times : time_array(1 to 100);
-- end of code from book
begin
report real'image( origin(1) );
report real'image( origin(2) );
report real'image( origin(3) );
report real'image( origin.all(1) );
wait;
end process;
process is
type time_array is array (positive range <>) of time;
-- code from book:
type time_array_ptr is access time_array;
variable activation_times : time_array_ptr;
-- end of code from book
begin
-- code from book:
activation_times := new time_array'(10 us, 15 us, 40 us);
activation_times := new time_array'( activation_times.all
& time_array'(70 us, 100 us) );
activation_times := new time_array(1 to 10);
-- end of code from book
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_05 is
end entity inline_05;
----------------------------------------------------------------
architecture test of inline_05 is
begin
process is
-- code from book:
type coordinate is array (1 to 3) of real;
type coordinate_ptr is access coordinate;
variable origin : coordinate_ptr := new coordinate'(0.0, 0.0, 0.0);
type time_array is array (positive range <>) of time;
variable activation_times : time_array(1 to 100);
-- end of code from book
begin
report real'image( origin(1) );
report real'image( origin(2) );
report real'image( origin(3) );
report real'image( origin.all(1) );
wait;
end process;
process is
type time_array is array (positive range <>) of time;
-- code from book:
type time_array_ptr is access time_array;
variable activation_times : time_array_ptr;
-- end of code from book
begin
-- code from book:
activation_times := new time_array'(10 us, 15 us, 40 us);
activation_times := new time_array'( activation_times.all
& time_array'(70 us, 100 us) );
activation_times := new time_array(1 to 10);
-- end of code from book
wait;
end process;
end architecture test;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity threshold_process is
generic (
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
threshold_reg : in std_logic_vector(31 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end threshold_process;
architecture rtl of threshold_process is
begin
data_process : process (clk_proc, reset_n)
begin
if(reset_n='0') then
out_data <= (others => '0');
out_dv <= '0';
out_fv <= '0';
elsif(rising_edge(clk_proc)) then
out_dv <= in_dv;
out_fv <= in_fv;
if(in_dv='1' and in_fv='1') then
if(in_data >= threshold_reg(IN_SIZE-1 downto 0)) then
out_data <= (others => '1');
else
out_data <= (others => '0');
end if;
end if;
end if;
end process;
end rtl;
|
------------------------------------------------------------------------------
-- add_sub_core - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: add_sub_core
-- Version: 1.00.a
-- Description: Example FSL core (VHDL).
-- Date: Thu Aug 9 10:06:10 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_three is
port
(
Tintrfc2thrd_value : out std_logic_vector(0 to 31);
Tintrfc2thrd_function : out std_logic_vector(0 to 15);
Tintrfc2thrd_goWait : out std_logic;
Tthrd2intrfc_address : out std_logic_vector(0 to 31);
Tthrd2intrfc_value : out std_logic_vector(0 to 31);
Tthrd2intrfc_function : out std_logic_vector(0 to 15);
Tthrd2intrfc_opcode : out std_logic_vector(0 to 5);
Ttimer : out std_logic_vector( 0 to 31);
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
FSL1_M_Write : out std_logic;
FSL1_M_Data : out std_logic_vector(0 to 31);
FSL1_M_Full : in std_logic;
FSL2_M_Write : out std_logic;
FSL2_M_Data : out std_logic_vector(0 to 31);
FSL2_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
end hw_acc_three;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_three is
component user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic ;
full : in std_logic ;
Ttimer : out std_logic_vector( 0 to 31)
);
end component user_logic_hwtul;
signal intrfc2thrd : std_logic_vector(0 to 63);
signal thrd2intrfc : std_logic_vector( 0 to 95);
signal rd : std_logic;
signal wr : std_logic;
signal exist : std_logic;
signal full : std_logic;
signal timer : std_logic_vector( 0 to 31) ;
-- Architecture Section
begin
Tintrfc2thrd_value <= intrfc2thrd(0 to 31) ;
Tintrfc2thrd_function <= intrfc2thrd (32 to 47);
Tintrfc2thrd_goWait <= exist ;
Tthrd2intrfc_address <= thrd2intrfc (32 to 63);
Tthrd2intrfc_value <= thrd2intrfc (0 to 31) ;
Tthrd2intrfc_function <= thrd2intrfc (64 to 79);
Tthrd2intrfc_opcode <= thrd2intrfc (80 to 85);
Ttimer <= timer;
intrfc2thrd <= FSL0_S_Data & FSL1_S_Data;
FSL0_M_Data <= thrd2intrfc(0 to 31);
FSL1_M_Data <= thrd2intrfc(32 to 63);
FSL2_M_Data <= thrd2intrfc(64 to 95);
--=======================================================
full <= FSL0_M_Full or FSL1_M_Full or FSL2_M_Full;
exist <= FSL0_S_Exists and FSL1_S_Exists ;
--=======================================================
FSL0_S_Read <= rd;
FSL1_S_Read <= rd;
FSL0_M_Write <= wr;
FSL1_M_Write <= wr;
FSL2_M_Write <= wr;
USER_LOGIC_HWTUL_I : user_logic_hwtul
port map
(
clock => FSL_Clk,
intrfc2thrd => intrfc2thrd,
thrd2intrfc => thrd2intrfc,
rd => rd,
wr => wr,
exist => exist,
full => full,
Ttimer => timer
);
end architecture implementation;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY image_processing_2d_design_proc_sys_reset_0_1 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END image_processing_2d_design_proc_sys_reset_0_1;
ARCHITECTURE image_processing_2d_design_proc_sys_reset_0_1_arch OF image_processing_2d_design_proc_sys_reset_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF image_processing_2d_design_proc_sys_reset_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF image_processing_2d_design_proc_sys_reset_0_1_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF image_processing_2d_design_proc_sys_reset_0_1_arch : ARCHITECTURE IS "image_processing_2d_design_proc_sys_reset_0_1,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF image_processing_2d_design_proc_sys_reset_0_1_arch: ARCHITECTURE IS "image_processing_2d_design_proc_sys_reset_0_1,proc_sys_reset,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=16,C_AUX_RST_WIDTH=16,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 16,
C_AUX_RST_WIDTH => 16,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END image_processing_2d_design_proc_sys_reset_0_1_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test_logic is
port(sum:in std_logic_vector(3 downto 0);
d7,d711,d2312:out bit);
end test_logic;
architecture test of test_logic is
begin
process(sum)
begin
if sum="0111" then
d7<='1';
else d7<='0';
end if;
if sum="0111" or sum="1011" then
d711<='1';
else d711<='0';
end if;
if sum="0010" or sum="0011" or sum="1100" then
d2312<='1';
else d2312<='0';
end if;
end process;
end test; |
-- Copyright 2018 Google LLC
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cpu_socket_fpga is
port (
c1_1 : inout std_logic;
c1_2 : inout std_logic;
c1_3 : inout std_logic;
c1_5 : inout std_logic;
c1_6 : inout std_logic;
c1_7 : inout std_logic;
c1_9 : inout std_logic;
c1_10 : inout std_logic;
c1_11 : inout std_logic;
c1_12 : inout std_logic;
c1_13 : inout std_logic;
c1_14 : inout std_logic;
c1_16 : inout std_logic;
c1_17 : inout std_logic;
c1_18 : in std_logic; -- ext_GP6
c1_19 : inout std_logic; -- BAD
c1_20 : in std_logic; -- ext_GP0
c1_22 : in std_logic; -- ext_GP8
c1_23 : in std_logic; -- ext_GP2
c1_24 : out std_logic; -- ext_GP1
c1_25 : in std_logic; -- ext_GP10
c1_26 : in std_logic; -- ext_GP7
c1_27 : out std_logic; -- ext_GP4
c1_28 : out std_logic; -- ext_GP3
c1_29 : out std_logic; -- ext_GP11
c1_30 : in std_logic; -- ext_GP9
c1_31 : out std_logic; -- ext_GP5
c1_33 : inout std_logic; -- ext_D2
c1_34 : inout std_logic; -- ext_D0
c1_36 : in std_logic; -- ext_GP12
c1_37 : inout std_logic; -- ext_D3
c1_38 : inout std_logic; -- ext_D1
c2_1 : inout std_logic;
c2_3 : inout std_logic;
c2_4 : inout std_logic;
c2_5 : inout std_logic;
c2_8 : inout std_logic;
c2_12 : inout std_logic;
c3_1 : inout std_logic; -- ext_D4
c3_2_CLK3n : inout std_logic; -- ext_D5
c3_3 : inout std_logic; -- ext_D6
c3_4 : inout std_logic; -- ext_D7
c3_5_CLK3p : in std_logic; -- ext_A0
c3_6 : in std_logic; -- ext_A1
c3_7 : in std_logic; -- ext_A2
c3_8 : in std_logic; -- ext_A3
c3_9 : in std_logic; -- ext_A4
c3_10 : in std_logic; -- ext_A5
c3_11 : in std_logic; -- ext_A6
c3_12 : in std_logic; -- ext_A7
c4_3_VREFB2N0 : inout std_logic;
c4_4 : inout std_logic;
c4_6 : inout std_logic;
c4_7 : inout std_logic;
c4_8 : inout std_logic;
c4_10 : inout std_logic;
c4_11 : inout std_logic;
c4_12 : inout std_logic;
c4_13 : inout std_logic;
c4_14 : inout std_logic;
c4_15_DPCLK1 : inout std_logic;
c4_16_DPCLK0 : inout std_logic;
c4_17 : inout std_logic;
c4_18 : inout std_logic;
c4_19 : inout std_logic;
c4_20 : inout std_logic;
c4_21 : inout std_logic;
c4_22 : inout std_logic;
c4_23 : inout std_logic;
c4_24 : inout std_logic;
c4_25 : inout std_logic;
c4_26 : inout std_logic;
c4_27 : inout std_logic;
c4_28 : out std_logic; -- ext_uart_txd (plug in white cable from Adafruit adapter)
c4_30 : inout std_logic;
c4_31 : inout std_logic; -- ext_A11 on first try board, which has bad c4_39
c4_32 : in std_logic; -- ext_uart_rxd (plug in green cable from Adafruit adapter)
c4_33 : in std_logic; -- ext_A14
c4_34 : in std_logic; -- ext_A12
c4_35 : in std_logic; -- ext_A10
c4_36 : in std_logic; -- ext_A8
c4_37 : in std_logic; -- ext_A15
c4_38 : in std_logic; -- ext_A13
c4_39 : in std_logic; -- ext_A11, bad on first try board
c4_40 : in std_logic -- ext_A9
);
end cpu_socket_fpga;
architecture rtl of cpu_socket_fpga is
component main_to_elk is
port (
debug_uart_txd : out std_logic;
debug_a : out std_logic;
debug_b : out std_logic;
ext_uart_rxd : in std_logic;
ext_uart_txd : out std_logic;
fast_clock : in std_logic; -- pass through for FPGA's internal flash
-- connections to the cpu_socket_expansion board
ext_A : in std_logic_vector(15 downto 0);
ext_D : inout std_logic_vector(7 downto 0);
ext_GP0 : in std_logic; -- PHI2
ext_GP1 : out std_logic; -- n_global_enable
ext_GP2 : in std_logic; -- 16MHz
ext_GP3 : out std_logic; -- dbuf_nOE
ext_GP4 : out std_logic; -- n_accessing_shadow_ram
ext_GP5 : out std_logic; -- n_cpu_is_external
ext_GP6 : in std_logic; -- RnW
ext_GP7 : in std_logic; -- nRESET
ext_GP8 : in std_logic; -- READY
ext_GP9 : in std_logic; -- /NMI
ext_GP10 : in std_logic; -- /IRQ
ext_GP11 : out std_logic; -- dbuf_driven_by_cpu
ext_GP12 : in std_logic
);
end component;
component internal_osc is
port (
clkout : out std_logic; -- clkout.clk
oscena : in std_logic := '0' -- oscena.oscena
);
end component;
signal clk : std_logic; -- 55-115MHz clock from internal oscillator
signal clk_div_count : std_logic_vector(26 downto 0) := (others => '0');
signal slow_clk : std_logic; -- clk/(128*1024*1024), 0.4-0.85 Hz
begin
elk0: component main_to_elk port map (
debug_uart_txd => c2_1,
debug_a => c2_3,
debug_b => c2_5,
ext_uart_txd => c4_28,
ext_uart_rxd => c4_32,
fast_clock => clk,
-- fast_clock => clk_div_count(0),
ext_A(0) => c3_5_CLK3p,
ext_A(1) => c3_6,
ext_A(2) => c3_7,
ext_A(3) => c3_8,
ext_A(4) => c3_9,
ext_A(5) => c3_10,
ext_A(6) => c3_11,
ext_A(7) => c3_12,
ext_A(8) => c4_36,
ext_A(9) => c4_40,
ext_A(10) => c4_35,
ext_A(11) => c4_39, -- c4_31 on first try board, c4_39 on second
ext_A(12) => c4_34,
ext_A(13) => c4_38,
ext_A(14) => c4_33,
ext_A(15) => c4_37,
ext_D(0) => c1_34,
ext_D(1) => c1_38,
ext_D(2) => c1_33,
ext_D(3) => c1_37,
ext_D(4) => c3_1,
ext_D(5) => c3_2_CLK3n,
ext_D(6) => c3_3,
ext_D(7) => c3_4,
ext_GP0 => c1_20,
ext_GP1 => c1_24,
ext_GP2 => c1_23,
ext_GP3 => c1_28,
ext_GP4 => c1_27,
ext_GP5 => c1_31,
ext_GP6 => c1_18,
ext_GP7 => c1_26,
ext_GP8 => c1_22,
ext_GP9 => c1_30,
ext_GP10 => c1_25,
ext_GP11 => c1_29,
ext_GP12 => c1_36
);
-- Max 10 internal oscillator
int_osc_0 : component internal_osc port map (
oscena => '1',
clkout => clk
);
-- Divide clock down to ~1Hz
process (clk)
begin
if rising_edge(clk) then
clk_div_count <= std_logic_vector(unsigned(clk_div_count) + 1);
if unsigned(clk_div_count) = 0 then
slow_clk <= not slow_clk;
end if;
end if;
end process;
-- Output 1Hz clock on all unused pins
c1_1 <= slow_clk;
c1_2 <= 'Z'; -- poor solder connection, tristate so we can patch
c1_3 <= slow_clk;
c1_5 <= slow_clk;
c1_6 <= slow_clk;
c1_7 <= slow_clk;
c1_9 <= slow_clk;
c1_10 <= slow_clk;
c1_11 <= slow_clk;
c1_12 <= slow_clk;
c1_13 <= slow_clk;
c1_14 <= slow_clk;
c1_16 <= slow_clk;
c1_17 <= slow_clk;
-- c1_18 <= slow_clk;
c1_19 <= 'Z'; -- poor solder connection, tristate so we can patch
-- c1_20 <= slow_clk;
-- c1_22 <= slow_clk;
-- c1_23 <= slow_clk;
-- c1_24 <= slow_clk;
-- c1_25 <= slow_clk;
-- c1_26 <= slow_clk;
-- c1_27 <= slow_clk;
-- c1_28 <= slow_clk;
-- c1_29 <= slow_clk;
-- c1_30 <= slow_clk;
-- c1_31 <= slow_clk;
-- c1_33 <= slow_clk;
-- c1_34 <= slow_clk;
-- c1_36 <= slow_clk;
-- c1_37 <= slow_clk;
-- c1_38 <= slow_clk;
-- c2_1 <= slow_clk; -- debug uart tx
-- c2_3 <= slow_clk; -- debug a
c2_4 <= slow_clk;
-- c2_5 <= slow_clk; -- debug b
c2_8 <= slow_clk;
c2_12 <= slow_clk;
-- c3_1 <= slow_clk;
-- c3_2_CLK3n <= slow_clk;
-- c3_3 <= slow_clk;
-- c3_4 <= slow_clk;
-- c3_5_CLK3p <= slow_clk;
-- c3_6 <= slow_clk;
-- c3_7 <= slow_clk;
-- c3_8 <= slow_clk;
-- c3_9 <= slow_clk;
-- c3_10 <= slow_clk;
-- c3_11 <= slow_clk;
-- c3_12 <= slow_clk;
c4_3_VREFB2N0 <= slow_clk;
c4_4 <= slow_clk;
c4_6 <= slow_clk;
c4_7 <= slow_clk;
c4_8 <= slow_clk;
c4_10 <= slow_clk;
c4_11 <= slow_clk;
c4_12 <= slow_clk;
c4_13 <= slow_clk;
c4_14 <= slow_clk;
c4_15_DPCLK1 <= slow_clk;
c4_16_DPCLK0 <= slow_clk;
c4_17 <= 'Z'; -- poor solder connection, tristate so we can patch
c4_18 <= slow_clk;
c4_19 <= slow_clk;
c4_20 <= slow_clk;
c4_21 <= slow_clk;
c4_22 <= slow_clk;
c4_23 <= 'Z'; -- poor solder connection, tristate so we can patch
c4_24 <= slow_clk;
c4_25 <= slow_clk;
c4_26 <= slow_clk;
c4_27 <= slow_clk;
-- c4_28 <= 'Z'; -- poor solder connection, tristate so we can patch
c4_30 <= slow_clk;
c4_31 <= 'Z'; -- patched over c4_39 on first try board; leaving Z in case i program the old board by mistake
-- c4_32 <= slow_clk;
-- c4_33 <= slow_clk;
-- c4_34 <= slow_clk;
-- c4_35 <= slow_clk;
-- c4_36 <= slow_clk;
-- c4_37 <= slow_clk;
-- c4_38 <= slow_clk;
-- c4_39 <= 'Z'; -- poor solder connection on try 1 board, tristated so we can patch
-- c4_40 <= slow_clk;
end rtl;
|
-------------------------------------------------------------------------------
-- Title : UART package
-------------------------------------------------------------------------------
-- Standard : VHDL'x
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Fabian Greif
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package uart_pkg is
-- UART transmitter
component uart_tx
port (
txd_p : out std_logic; -- Output pin (active low)
busy_p : out std_logic; -- High if a transmission is in progress
-- FIFO interface
data_p : in std_logic_vector(7 downto 0);
empty_p : in std_logic; -- Set if the FIFO is empty
re_p : out std_logic; -- Read enable
clk_tx_en : in std_logic; -- Enable pulse for the bitrate
clk : in std_logic);
end component;
-- UART receiver
component uart_rx
port (
rxd_p : in std_logic; -- Input pin
-- Set high to disable the reception of any data. Aborts any
-- incoming transmission.
disable_p : in std_logic;
-- FIFO interface
data_p : out std_logic_vector(7 downto 0);
we_p : out std_logic; -- Write enable
error_p : out std_logic; -- Framing or parity error
full_p : in std_logic; -- Set if FIFO is full and can't receive any further data
-- Enable pulse for the rx bitrate, needs to be five timer higher
-- than the actual bitrate
clk_rx_en : in std_logic;
clk : in std_logic);
end component;
-- UART receiver/transmitter
--
-- Module with echo rejection.
component uart
port(
txd_p : out std_logic; -- Output pin (active low)
rxd_p : in std_logic; -- Input pin
-- FIFO transmit interface
din_p : in std_logic_vector(7 downto 0);
empty_p : in std_logic; -- Set if the FIFO is empty
re_p : out std_logic; -- Read enable
-- FIFO receive interface
dout_p : out std_logic_vector(7 downto 0);
we_p : out std_logic; -- Write enable
error_p : out std_logic; -- Framing or parity error
-- Set if FIFO is full and can't receive any further data
full_p : in std_logic;
-- Enable pulse for the rx bitrate, needs to be five timer higher
-- than the actual bitrate
clk_en : in std_logic;
clk : in std_logic);
end component;
end uart_pkg;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_bit.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_counter_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-- DET 2002-02-24
-- - Changed to call out proc_common_v1_00_b library.
-- - Changed the use of MUXCY_L to MUXCY.
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed to call out proc_common_v2_00_a library.
-- ^^^^^^
--
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_bit is
port (
Clk : in std_logic;
Rst : In std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"36C6"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => count_AddSub,
--- xst wrk around I0 => Count_In,
--- xst wrk around I1 => Count_Down,
--- xst wrk around I2 => Count_Load,
--- xst wrk around I3 => Load_In);
I_ALU_LUT : entity opb_v20_v1_10_d.inferred_lut4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub,
I0 => Count_In,
I1 => Count_Down,
I2 => Count_Load,
I3 => Load_In);
MUXCY_I : MUXCY
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
O => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg,
C => Clk,
CE => Clock_Enable,
D => count_Result,
R => Rst
);
Result <= count_Result_Reg;
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_bit.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_counter_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-- DET 2002-02-24
-- - Changed to call out proc_common_v1_00_b library.
-- - Changed the use of MUXCY_L to MUXCY.
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed to call out proc_common_v2_00_a library.
-- ^^^^^^
--
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_bit is
port (
Clk : in std_logic;
Rst : In std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"36C6"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => count_AddSub,
--- xst wrk around I0 => Count_In,
--- xst wrk around I1 => Count_Down,
--- xst wrk around I2 => Count_Load,
--- xst wrk around I3 => Load_In);
I_ALU_LUT : entity opb_v20_v1_10_d.inferred_lut4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub,
I0 => Count_In,
I1 => Count_Down,
I2 => Count_Load,
I3 => Load_In);
MUXCY_I : MUXCY
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
O => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg,
C => Clk,
CE => Clock_Enable,
D => count_Result,
R => Rst
);
Result <= count_Result_Reg;
end implementation;
|
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo Display.vhd
-- Versione 1.03 - 21.03.2013
-- **********************************************************
-- **********************************************************
-- Gestisce il display su VGA 320x240.
-- 1 bit per pixel (monocromatico).
-- **********************************************************
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity Display is
generic (
sweep_delay : std_logic_vector(31 downto 0) := "00000000000000000010011100010000"; -- 10000
xmax : std_logic_vector(8 downto 0) := "100111111"; -- 319; // Massimo degli x
ymax : std_logic_vector(7 downto 0) := "11101111"; -- 239; // Massimo degli y
st_ploty : std_logic := '0';
st_done : std_logic := '1'
);
port (
clock : in std_logic;
reset : in std_logic;
freeze : in std_logic;
data : in std_logic_vector(15 downto 0);
x : inout std_logic_vector(8 downto 0);
y : inout std_logic_vector(7 downto 0);
color : inout std_logic;
plot : inout std_logic
);
end Display;
architecture behaviour of Display is
signal delay_counter : std_logic_vector(31 downto 0);
signal st : std_logic;
signal streg : std_logic;
signal buff_sig : std_logic_vector(8 downto 0);
begin
---------------------------------------------------------------------------------------------
---------------------------------------------------------------------------- FSM gestione VGA
---------------------------------------------------------------------------------------------
process (all)
begin
st <= streg;
case streg is
when st_ploty =>
if y = ymax then
st <= st_done;
end if;
when st_done =>
IF (freeze = '0') AND (delay_counter = sweep_delay) then
st <= st_ploty;
end if;
end case;
end process;
process (clock)
begin
if rising_edge(clock) then
if (reset = '1') then
streg <= st_done;
else
streg <= st;
end if;
end if;
end process;
buff_sig <= "000000000" when (x = xmax) else x + "000000001";
-- Contatore X
process (clock)
begin
if (rising_edge(clock)) then
if (reset = '1') then
delay_counter <= "00000000000000000000000000000000";
x <= "000000000";
elsif (streg = st_done) then
if (delay_counter = sweep_delay) then
delay_counter <= "00000000000000000000000000000000";
x <= buff_sig;
else
delay_counter <= delay_counter + "00000000000000000000000000000001";
end if;
end if;
end if;
end process;
-- Contatore Y
process (clock)
begin
if (rising_edge(clock)) then
if (reset = '1' or (streg = st_done)) then
y <= "00000000";
elsif (y < ymax) then
y <= y + "00000001";
end if;
end if;
end process;
-- Sincronizzazione
plot <= '1' when (streg = st_ploty) else '0';
-- Determino se devo visualizzare o no il pixel
-- 01111000 = 120 --> riga centrale del display
-- data(15) = segno
color <= '1' when (y= "01111000" + (data(15)
& data(14) & data(12) & data(10) & data(8) & data(6) & data(4) & data(2))) else '0';
--color <= '1' when (y= "01111000" + (data(15) & data(6 downto 0))) else '0';
end behaviour; |
library ieee ;
use ieee.std_logic_1164.all;
package mypackage is
type myarray2dim is array(1 downto 0, 1 downto 0) of bit;
type myarray1 is array(1 downto 0) of bit_vector(1 downto 0);
end package;
library ieee ;
use ieee.std_logic_1164.all;
use work.mypackage.all;
entity myentity is
generic (
genarr2dim: in myarray2dim := (('0', '0'), ('1', '1'));
genarray1: in myarray1 := ("10", "10")
);
port (
portarr2dim: in myarray2dim;
portarray1: in myarray1
);
end myentity;
architecture arch of myentity is
signal sigarray2dim: myarray2dim;
signal constarray2dim: myarray2dim := (('0', '0'), ('1', '1'));
signal sigarray1: myarray1;
signal constarray1: myarray1 := ("10", "10");
begin
end arch;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 12 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 12 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 12 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 12 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 12 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 12 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 12 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 12 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 12 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 12 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:18:38 09/28/2017
-- Design Name:
-- Module Name: C:/Users/utp/Desktop/TEMPORAL/ALU/MUX_tb.vhd
-- Project Name: ALU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MUX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MUX_tb IS
END MUX_tb;
ARCHITECTURE behavior OF MUX_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MUX
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm13 : IN std_logic_vector(31 downto 0);
i : IN std_logic;
Oper2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Crs2 : std_logic_vector(31 downto 0) := (others => '0');
signal SEUimm13 : std_logic_vector(31 downto 0) := (others => '0');
signal i : std_logic := '0';
--Outputs
signal Oper2 : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MUX PORT MAP (
Crs2 => Crs2,
SEUimm13 => SEUimm13,
i => i,
Oper2 => Oper2
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
Crs2 <= "00000000000000001110000000000111";
SEUimm13 <= "00000000000000000000111010000111";
i <= '1';
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:18:38 09/28/2017
-- Design Name:
-- Module Name: C:/Users/utp/Desktop/TEMPORAL/ALU/MUX_tb.vhd
-- Project Name: ALU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MUX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MUX_tb IS
END MUX_tb;
ARCHITECTURE behavior OF MUX_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MUX
PORT(
Crs2 : IN std_logic_vector(31 downto 0);
SEUimm13 : IN std_logic_vector(31 downto 0);
i : IN std_logic;
Oper2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Crs2 : std_logic_vector(31 downto 0) := (others => '0');
signal SEUimm13 : std_logic_vector(31 downto 0) := (others => '0');
signal i : std_logic := '0';
--Outputs
signal Oper2 : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MUX PORT MAP (
Crs2 => Crs2,
SEUimm13 => SEUimm13,
i => i,
Oper2 => Oper2
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
Crs2 <= "00000000000000001110000000000111";
SEUimm13 <= "00000000000000000000111010000111";
i <= '1';
-- insert stimulus here
wait;
end process;
END;
|
architecture RTL of ENTITY_NAME is
begin
process
begin
FORCE_LABEL : sig1 <= force in a + b - c after 10 ns, d + e after 25 ns;
FORCE_LABEL : sig1 <= force out a + b - c after 10 ns, d + e after 25 ns;
FORCE_LABEL : sig1 <= force a + b - c after 10 ns, d + e after 25 ns;
FORCE_LABEL : sig1 <= force a + b - c, d + e;
FORCE_LABEL : sig1 <= force a + b - c;
FORCE_LABEL : sig2 <= force a;
sig2 <= force a;
end process;
end architecture RTL;
|
-- file: nbit_register_pack.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- Solution to MC613 - Lab06.Q2.A
--
-- This package contains the following components:
--
-- * nbit_register:
-- A n bit register
library ieee ;
use ieee.std_logic_1164.all ;
package nbit_register_pack is
component nbit_register
generic ( n : integer := 8) ;
port ( x : in std_logic_vector (n-1 downto 0) ; -- Load input
y : out std_logic_vector (n-1 downto 0) ; -- Stored value
ld : in std_logic ; -- Load control bit
clr : in std_logic ; -- Clear control bit
clk : in std_logic -- Clock
) ;
end component ;
end nbit_register_pack ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
generic
(
NUM_STAGES : natural := 10
);
port
(
clk : in std_logic;
enable : in std_logic;
rst_n : in std_logic;
clear : in std_logic;
cnt_out: out std_logic_vector((NUM_STAGES-1) downto 0)
);
end entity;
architecture rtl of counter is
signal cnt : std_logic_vector((NUM_STAGES-1) downto 0);
begin
process (clk, rst_n)
begin
if (rst_n = '0') then
cnt <= (others => '0');
elsif (rising_edge(clk)) then
if (clear = '1') then
cnt <= (others => '0');
elsif (enable = '1') then
-- count up
cnt <= std_logic_vector(unsigned(cnt) + 1);
end if;
end if;
end process;
cnt_out <= cnt;
end rtl;
|
entity ent is
end entity;
architecture a of ent is
procedure proc(s : string) is
begin
report integer'image(s'left);
report integer'image(s'right);
report s;
end procedure;
begin
main : process
begin
proc(s(4 to 15) => "Hello world!");
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
procedure proc(s : string) is
begin
report integer'image(s'left);
report integer'image(s'right);
report s;
end procedure;
begin
main : process
begin
proc(s(4 to 15) => "Hello world!");
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
procedure proc(s : string) is
begin
report integer'image(s'left);
report integer'image(s'right);
report s;
end procedure;
begin
main : process
begin
proc(s(4 to 15) => "Hello world!");
wait;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 13:21:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -variant Calculate -nodelta ../../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.1 2007/03/05 13:22:44 wig Exp $
-- $Date: 2007/03/05 13:22:44 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.1 2007/03/05 13:22:44 wig
-- Added testcase for selection of macros with ::variant switch
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
#
# Generated Constant Declarations
#
#
# Generated Components
#
component inst_1_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_1_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_1_e
);
end component;
# ---------
component inst_10_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_10_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_10_e
);
end component;
# ---------
component inst_2_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_2_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_2_e
);
end component;
# ---------
component inst_6_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_6_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_6_e
);
end component;
# ---------
component inst_7_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_7_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_7_e
);
end component;
# ---------
component inst_8_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_8_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_8_e
);
end component;
# ---------
component inst_9_e
generic (
# __E_MISSING_GET_INTERFACE for changed_gen );
port (
# Generated Port for Entity inst_9_e
# __E_MISSING_GET_INTERFACE for changed_gen # End of Generated Port for Entity inst_9_e
);
end component;
# ---------
#
# Generated Signal List
#
#
# End of Generated Signal List
#
begin
--
-- Generated Concurrent Statements
--
#
# Generated Signal Assignments
#
#
# Generated Instances and Port Mappings
#
# Generated Instance Port Map for inst_1
inst_1: inst_1_e
;
# End of Generated Instance Port Map for inst_1
# Generated Instance Port Map for inst_10
inst_10: inst_10_e
;
# End of Generated Instance Port Map for inst_10
# Generated Instance Port Map for inst_2
inst_2: inst_2_e
;
# End of Generated Instance Port Map for inst_2
# Generated Instance Port Map for inst_6
inst_6: inst_6_e
;
# End of Generated Instance Port Map for inst_6
# Generated Instance Port Map for inst_7
inst_7: inst_7_e
;
# End of Generated Instance Port Map for inst_7
# Generated Instance Port Map for inst_8
inst_8: inst_8_e
;
# End of Generated Instance Port Map for inst_8
# Generated Instance Port Map for inst_9
inst_9: inst_9_e
;
# End of Generated Instance Port Map for inst_9
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
entity logical3 is
end entity;
architecture test of logical3 is
signal v : bit_vector(1 to 3);
begin
process is
begin
v <= "110";
wait for 1 ns;
assert and v = '0';
assert nand v = '1';
assert or v = '1';
assert nor v = '0';
assert xor v = '0';
assert xnor v = '1';
v <= "111";
wait for 1 ns;
assert and v = '1';
assert nand v = '0';
assert or v = '1';
assert nor v = '0';
assert xor v = '1';
assert xnor v = '0';
wait;
end process;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity flexible_lvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
use_extra_ddio_register: string := "YES";
use_extra_pll_clk: string := "NO";
buffer_implementation: string := "RAM";
registered_data_align_input: string := "OFF";
use_external_pll: string := "OFF";
registered_output: string := "ON";
add_latency : string := "YES";
REGISTER_WIDTH : vl_notype;
LATENCY : vl_notype;
NUM_OF_SYNC_STAGES: vl_notype
);
port(
rx_in : in vl_logic_vector;
rx_fastclk : in vl_logic;
rx_slowclk : in vl_logic;
rx_syncclk : in vl_logic;
pll_areset : in vl_logic;
rx_data_align : in vl_logic_vector;
rx_cda_reset : in vl_logic_vector;
rx_locked : in vl_logic;
rx_out : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of use_extra_ddio_register : constant is 1;
attribute mti_svvh_generic_type of use_extra_pll_clk : constant is 1;
attribute mti_svvh_generic_type of buffer_implementation : constant is 1;
attribute mti_svvh_generic_type of registered_data_align_input : constant is 1;
attribute mti_svvh_generic_type of use_external_pll : constant is 1;
attribute mti_svvh_generic_type of registered_output : constant is 1;
attribute mti_svvh_generic_type of add_latency : constant is 1;
attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3;
attribute mti_svvh_generic_type of LATENCY : constant is 3;
attribute mti_svvh_generic_type of NUM_OF_SYNC_STAGES : constant is 3;
end flexible_lvds_rx;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
jUspyP0iAzXCKRkWWALogs7DK0stlsk8Ac9AtlcQkNLb+v4KJXyzKMaA1G3HKNGySfJikCFIiQGN
72J2MmtuHQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cKqUYaFMNmCnFie+T9Bg/PWl0G/iI0Wwvxi8yg1uvhU+lULQwvsZobF3b5H3RVvcM1TvVo0mPQ6k
kvfjHChtR9Rm1NpzK/TRK2cpT/+XraxaAt13AHt4v2Li7Q1TiFtsxvE6WBJbw8xzFPgX5R8zoI9Z
xQThHyQ9Y0HDSp1JiVY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rFOHHUOUrlJWwbymLPd0dCS2AYpSybSEh5ZJJbT2A45w3gZSOvWrHDhtyqbVqlsstgmvEppRS7Od
QNC5LyNk3kmW1uaE7GY2uSy02V9O8r5GVpsXmVkckbPU6l3hNdHiq87O/M3FndWS3dRZKC2A9DNv
bxz63dYttgfvXc5MPhWWemkmYn4ub4EIx/qAGLM9aFdqsmVcpqD+z3B2/7FaJ04Qz60yVohM/5tS
jIFb71LWEqo1l7vk1zCjSPSV0BZUoqJCLSUriAztHm8yRLgBWaPhdvKrVL2jTnL8VzXHno7XlT2u
8DJTujTqNn3NgU8XdwkEfXWwJloZpkBe/g4FYw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
UXdq/o460lUpiPxpmyXCPPGC8od551Yv5DkCjILx/FsUVVTBP4kjFbMPaO60DdqvjuuG4tbMEfjp
2/SkkKnaMW8T2/bbQ8ucMuk5+tE7e8o3ToGwREI/EcKPPr+MdcsfhulzsMujxgkbDbEzoyjXfX50
GxjOvKXRGfrs9Ld82oo=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qemEWucBj3cySwkGtLMneG+WUTUsSnlBhS2UqRJnnbzkZPsIe5912fGNcd+Nuti2S0HrMJucuzBg
zebkZVhwJr98XAXk9E/oT3Nikt/5/G48yTzIJ1KWyz7lHLQAMY5r9Ue3kKojXrs4FG3eiB8y3tqJ
6m+4D0meMUujO/nNAXC3tHlCuRO8ceR9RAOCygQ2wythHpck6/MLVuFD+G6ruOGnDicsOf9eZMCt
HHOdeHmjhn4k/2RRwCGfdChmxzvczso/a5DXM4ixnJQJqy0OGo0toyQcqZBnI3h+wvQYrg94uDIy
dSHACaAVhozF4EfVFXpDLBYFmP1PxyStVPkjEg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 41760)
`protect data_block
Kf9ZRzDZT6viViR4dEheu/wX8omfwPjaHPglDOTgrX0IjhnSMMLFR+RpZ2NpzSI/d9iR/Zv85gK6
ItIIhUnEZxRYx8CeZVm3cjr8eGLJ+smUM0B5ZSY6GapxuPzJSpfEGvEtVhN7MNCVC85Sv3HOq6i1
3ypkZdwwfYzkLyb2MfOBlXR1KBnh4IqlQqVnPwzSIZmoJVQ+rPTidlJ7BvNMWJ4n6CHaQUUXQvyc
LmD43brsfpcNp9XSAndIjOzp7M7qG+AvNr2No7CNwJRfy0vEdvCxN44G9YowETIPYvGm6liDcqSX
dGEVJOG3w3V0DOxwGOpbKN9Mm4yJe6XDHbWWFgLuoqiwNRx7U67ErgZ/1OCPSqw3HDRNtW1yF+Ys
PzIA8IprXSKW/2frACS7vwkxmh+hkvV7Q3isu3Hhl95OeQJAQM1tVZZBw++iyvexg0ObDVxX7nbU
ywOdKAa4IxXk29e54bguzD52E66i9wHAwaD4Eln9ALgsEgicKvTT/RIoFygMAMeLRehykpK8mDJJ
9qidCrLWO2zqFZkP9SA70GbCptMO5el7AMIlggHOpuCcBO1R/tuNNxUKTsReieG0XKwsTGx1hi3c
sKfat9F6fn2p2VTv2E4m1dBPHq23v2z0nrm5kS8tU4PMMlKCaa0RaL5urbO0+pIGmoMlo9Znt17f
Jef6rn2YfMIeENutlYJdijesXgyfkgaCTZEOqxjS2nqFJ0I1sqbsyLNCj6Agk2EXpEzMsYptH+qZ
VIDTM7yEfjAQHmQTMmyQa/uTg0xtDiC72OoJC5Jer/FZXmI3sic9tlV/wQMGI2yI+OYNtSAT2u6h
Wex4MECHCgkfQjNpn8kWipImxBULHHqgG3S5v8i73Evg/zXFDDPXPNKMWBhs5a0drFs6sUrRefzS
HAjl78O7sS7y9KeV6tFEoK87kQhLkphBr959+0aMcb2SPZug+ztW1JYp2w+fw1CM/bVyezQVsGjA
Z0EGf9zpnp3xW2Y2l1+3PRsYpTKdD/xW4IjpTf1/0vJrgJ66KfsmWtEgFi1qHGSTW2f1iyEwTMKL
KnWplQzewgL/fcZb+zrfjiZ/FH/YVFKMroZKwY5dG2NpG80nCTUIVEdIu9qE4Hh2ZWUDo8F7F57z
dNl2RhsvJMTieypsbHKy9bA6h+cOMVpy58B9GA4MC0TTaL2BO6B8xD5q+HwziJEoYpjEMvLZMpVg
pgByHopr7TKwuSxcGwPUttA4PGLnzS3E8SLlX7xttCmEMqrym6ydIQpSe0CWcuKt9rJl8TT5s93L
jA8sf9xYhBNHJu84jk11Dqqjd2I+oQaAiV3o6gkCYEDogcS23VwZ8rEXq7Roo5TXoXAcjBrKFZUN
UDlyEuP7xalfKRJLJ2liWRzXCwsaNOkeZCAz9qCEZjn6cJHCAtM6nihRUyDuylxy/w/Epbzi082k
G1m7QohnMJ4yOhKf+xkPHP+7lXiJ3dkIJPYrRIh8EpJf5UDhnxhw0vR4kai2L0qsRHzax+rWf6Tg
p7a6lNhkP5rBTWzOBnaYB50J34FePZ4ky5zPfx/4lyBmWLUxyXwpsOu/jF/Dc9X/qks9xz1S3JOI
6RTO/KQvRiQjNC/hFoVNsonuoX9JZ/PyB3ae9TU2X6SRIIiEF2IK0MPcQmuC/Ch7SVgHoeJ2ij6L
z0Ws3rLwz3mQXTjBnwSwgkrULKEIyjD0qrrTCtu9dKvltm48SfSJKcgGCaug0HaWr3F/hM1EH1Da
MfA80xmpm2iZYd+yDSFyf0BBrXbRWV0nU95TR0GytV2y84pTAVOj5G2qfiZIWdOfPnjm2Ei7Emt+
QtZB1RvGnosiGh78aG840TkXJ3Dx2hynYaGSE+4jrjO78VGXuN0QkfpP2kk03TQ/k2MhbgxVfA6b
wYDBxgBisAllhiHFh2imQ2i0Ggzm2BD8f2mxY1uZlS4tifA85KlOwRRF+1FqRPonomPCIetPp3Uf
podYZ6fn2MZvoDkcjD+pq6Z+sySkr3S+JBMN9icPW5LYvHIdCvcnQyGoozvsvzzCwthzkvoDrxBT
JuNCsTI1ZySOJTY8JM1hPyj0vXexG79+44pduYsdFLk6K6ujepihcSC3PHQdcq+J1RNPI+PAYI5u
hQb8qdzWL58FRYxlIfhMq61QXsV8T8ayT2iQzvz0cAR4HO+CJp+BILtXL9Pg12kRQMNGYhPvzsI6
tve/NlYFaSzoy37IOmQhQp7s39MQMv++w4M28t4M0eqwP7zW2Xgvij2uHAMWmGj3Agq3iQt+Q3PB
ZvbAvpxbQ7+GLXy4Ow92PCpWj6AgKrz0QN1rKH8bFwKtQr8ExE39DQV3etUn8b1Mq+XU1lOCZsBE
kuGclbjjqlkB+yw5xHK1Xk2kkuH3FINAlDmLDY02PZI7cVGBHxGe+uUJxqIuaHz7eWDzO7q153t/
vDfaWp2BT+ddUAboNCTRl+s8wXEGKknUrnCermH06ne4iWFaczgOHGq6OMV1l2ekuhmFjsnzHY4v
oXJ1G0RnPTbTuHhSyftB7B0IB4gybRx4ZFOY+21gfCjbhFAXA93PFLIX/ie+AcY/O47sYjYTSlnK
eK3Yw0MUGprWwxxlG0CxlMHubzIIbskXfAElsevXZsI/yaNB16J1UaKYjXUyOJVRvAgq4CulOfZR
ACm3TERU44iRol3ZWX1m6uWSufWNHjXeLO/LZeU3KsQ0v4GTGkADupBwTNF2suIkBpJAPq7YDigj
uQuQiRrhQz/H8ErtfBXXJlS6b1rxQVcIYPjPmq6ZBC4IdffV+mu0lLjAnYHAUnuBWMUHLrjLcbwV
36PnBtkORt+jufB+ppQftOyAvTMKEb82sY8HneUOITs7tx9NjqJa5P1h9lVR/z5YVaiCi0XoVfHY
FKq4qz6o/eoCwb8WPBwNtfOVRi4tNqNuGVCtNlbkbLMzDymP/Eho+aUoumrrfhCzfHg+jLbORDL3
ev/xcmD2/31c3cGSBXjpNP6lA3xHPocAFuR0tELAcUFJPwdebiK/VOLRLkNRh2l0jU267ksu39xk
jyaDXjMtTqQ+02Bk28jOKWVKYwEdonbSclOOGQxNO6skIafDZMyJFGuJzU2q2vhUtN/T98P+Ljj7
Oh38r9qxs7yqEj4kCh4b11TruqNeKjma0k1QKeGYIQiloqYSfwqbptIyCmxoXkCK55d0EyJuo5X8
Cicu+jlL9wIyzrgmP8H3zncK5VVxM+drDiZWqDfj6+q5O9JzjsShEXt7n+yjT5dH8sSgMUg08lwi
32oubJfwLbIa8jdU4RxEQn9SWqINcDI7C8TnbcOqo1fKRbEEpo80yAFdJ5kq/VP3QlFH0ZUz3e67
SNCo1+8bFLvu8Wr1XPbUZxiyrZnEDaHBq6VeJS8wpjuI4VAgwxPUPxkVZnNSbL57wKZJww8OAsuw
r6cPPSQpMpqcRPMQCBB8mes5tH768r1Vap/xouh6dmIL0wFJjVXBYepQB7OlGU4ICUubYpLcPfep
4A9FhaO6xNA0VYf+NuQxzh8UqkkbB1joCFgdiBwL5m9Kvk6N1BpJe3Y+90ULjAxcZYHgmwPS8m9Y
kAVyLx9iCHuoYPof8OWn/he4vUt2SdWXAVVtka4+33oPuKjH97RCBvXWF29AGjMteTh9ACN6fbjX
JqJ/yWZ0JlXuaW7TNuTKJ1L+5ZtQI8XCWFfSW36dvozNnKu2seq4NCTwdtgzbNhztaigZwudlUxu
kdHkqdrtqRNC/EMJptpH1peqLkRv3/rKyocbUAE8oRw+vCpq+PJ2zkq3ugMLwQty+m2ER50MTeYl
X1t01viw/P/KsCQFvA3QQuSUKFxAQqRXjCRX+i3wdbm3LjSWWEn44b/jGFpdSM1wKUBRiasGYj7i
t4vTuTj1uwdGFKyX7feADu562Ry0/yi82okbQN/lyXwbR5R4PyiEAPTDgdfisZ3vI+wytQWbNxP5
zabOutk8FaT2dTC4q+DEFsPsmX40M/iT3oeojN2IhwDnoi9c95ZALthRuj6uKq4uNoDRJ6TypjM7
fQhJwHCJOfZJpqdvHsZC3x9DRHNwvo0gB9U/X2nmNC3ueWEEexxdV2uK0yZS9J3eeRrS84T5AdV4
lv+c11hKVvNI/ldU5m2CgFBrBrXNjXNQTCw65c3GaYhQK70pJiBcz9fmjxuilsG26h4G42A77PHX
XShRX3ThVKxOvesA6bVuAHoJwCGJGKOwwHcTSWnc9AkLPgA6KgXTv39inL9lE3ermdf0TrKKgaMI
9RAwGc4yOMxFYfRsgVyzWTFqnYcAys8/F8FXjmnwdGvWPtGN5ZnxSMx0hrWb8nbHgXTzzkaSAhsl
pyc9eQGdAcZj6fON+YH+qFSmjyL2VxM5kJ5xlnNWYd2QFCwSg4+KTh7ZkawdDydKiTz8SlBQIMWk
2xcuzNytijRBIZSXAY6Wn2mnsFDSvfAfyEWEzrpx+idt4GX+c3LRiTmx0U2eu6daKU957geTxQ/Z
zgLWhOiC00Qnx6CJ6Hp4KZEcmSqwXXk1PPaCNYCvynMwz+wrg0fJ4cKxH+4NZ5uAxXQBhNEQKnXE
F9FkSOJ77GdNkfWltlrkn70w533GcyWc2eIx4yj2p5Gt8y7lvufQVVYwPJ/1Kq+Iq5kwr7/GJ4Zj
SeK8Bhuu7oCsRGd6P2GB01ynI3eYqF8+A4nyAKYcyWBnrRplHPQHsxlHewM4XlK5kOEaan4HWq63
GXrbrMKoZBysYjiNmJs5pB06SZpaAxilodylEA7nvIgfGYLyy5l+oe68dJE99TjIxcyBaX6/vmFH
DMJ3tFQV3SZ3cR363cZexaRBzM7SnfaFH9Dl7wUy5hALSrfUZ3y+XIjEEcDJVGW5OO3viVOpcgbD
U0ftRH2UpCN69IlocWCQGGzHS7FHnrftR8942VfGgKUgb95YaqpU9Yt8GGFe39bH5wMvcYHR//6z
DMp0cgEfpJtrwl1lWx5KrBQseoqyM5PP/L8fXfAVsWroDzEFpYgNKcT61hmCu8oHItHxlLLnAHfp
dhAefnaxIWz2L3gACi+jt3V1XaWKbhXSmmwCEX870Haa4Qx6LXdIM3RO54l/EZP2NHHyqWubktee
ERooD755VKJilpjtvGBwUzmuiV/htbFNl3MyuTllGPYlNoNlE7UasaNccYeBu3axPq84Hb/dBCDa
kRjD/pi1euYDovNxKKPB/nNrEELZhmm2Je92W7Q3CtzWauK5ig7BzItXJu6Tq9bNtdQ9chQyZF4M
zHOlsISlaWIbl962in7y7fUDvIelPauTHxpa0FvnoSuBzqZLHk/6uF3ryYdbZQ7YUW6rStt19nV5
fX5phrb26+tF/oBlsEqPBgGiACswFpOJUjXwRQ09mSUqUDLImLtN03PEuHPt8e+ftEzkR9ktS4ex
glAaoQueMtRY0ga756NV4ju/ttlBEr9cTsexCcEbyj04bpBfKkqlEkuAcjNjm/7+Xa34SK1G0EIP
oT3P3wzbw7F79a0M0hv9cBes1VMdfZmeLHoacbw+46Ci8Jza+rzEzsVGFDK7B9LEUGPkAOcRd0Hl
L4qrqHtelbg1P688CkLof/cMhqfUw2amcl3KZ9Lc0S0O7tPvNpxBG1oFdO9qmDbjXYwZFycWKLZz
2HA1r86kGqiIRiVP9nIso5keXEQo77tsLLYx0KM0bJAUTmwLiuQUFJkhyA5y0MDNldtn5Ot4qe30
gkZtF13Kh3MIimx7iZRWGRKuRqYJGf9VkTPprMBE/aERI/S+lyLi7E2JBh1wF7o3e5U9bD/ryKFF
vKg66jL7Uv84e/dmeGJSQt+ItA0EfUelz0E/lA7YCsduZyRg1ltCMQr2N1daHctkz1Gx7grHP1iw
PpR00qtBAw5sf2ApTNQy7SmiN7CyqxjGntjxSslesBkn6Tgao19RFvNAfd3OFUWC26D+0X4VQL2r
saW1aG3dkTymrPfQYH+NhsL8MoTZW//P465tjCRO1F1Tm4DqZbiF8W0PXkW7VcnGzHllgNXxClA4
y/OOF24/+abYS3HtMFRrsoaLnTwPHFcW2205S8JwNVhLnbUwh82tHwRUiBWCr0nGGrufO2s8dzda
Y0bXeOIe9gnGeGto/D0BXdIXrhLeXFmJEUHlAcP1lXbcDM/Kq+Ggr13VORPnr8byMWOG12WnJ48C
qgpNAc79iXCzVJSWGo+cx7EmnEV4tWrKeqVUNgX0KXZusGZHmucptEpsb9hEWMjklIHTMBYF72B9
90nrF1114clphYlYfxluztKts0Di7A4KSSFM14jqV7Lg/FR0lIUCrDjnt2Jew9o4w2ZaMbp4ej4N
HBvWhi05fGDFOHqMYkiIiOvI9TNRo0DUrr7nHVzSAr4N1WDD0EEF+6ZCIeGXn1s6yeqYUEnypo6y
ROoLvedTT+rI9NuMgz+JI+uZZx6jdfLvJ+qbPM0VktBkUoCng3X2PzqEkQbmWGZHY/N94PlBjer1
XA1fEjmqVmEF7GFPhRbpCsHKVzvlGyq53VbUitcov5takpHPkCUjVl/dhUo+dtY6dM0UjkLd4YU8
50RSYSZwGzxyYr2fZP7Xnq9tVkdWFQMcZ229LmYAMSoGCQahKxxy9sSHCtop0UKAUFBAOAl0RhOc
qwSGFqT/EmroySXTH9Dwp6FqJFC5LGnGkBqKysnAihpUfhJz5phJ6WYLhNgWomE/na7klcL4w+9r
8YH47VOm6hH7kNzmJ9OG69ip6KRORcPeM3KScuFfE2p48yisYCS4R3OmheWAMqranc9SFA5frgiD
pxUwXW8Uj1GJXELJ0xv/A1WUq+rM9BRxfs59WJ6BFNrA8lNesnU860lO6wZt9K6nYjO/YcFZ0MPD
Ut7CJUHE7JRyoJHu6cdHNPs2KdlHlXQauDWMmXkO3pP1PsDzpngNpDLmJAuYv+Kue1fKwLCIyFvu
PeFihsoDpJQgVWOlg7BiiUA33HCqGQfv0zb58kfGpvYrdHNCncvGtNLpq+Lf84uSPasu7Oz9FiJG
SYcew575LFF30p6T0XleK/TG6EMwyEV7zwczDc2hHlJxfRvTM9XmWJst0YoJBAELMm35wgMAtWqT
Uh17X6em2G3UKV7LN8OjqOjpvshACVAJIFMYiHEp3x8COSYgrNHuXTWcwg5welKCMjdbUG69N5Ev
bKcPgqGEh0KCwMA+Wij5RnumvIfGKKffevKuc+OVCD/IxWINkaO3+YvKeSDkEhgd4rVLjNFmEgAY
8Nr9ChJYYAzyFjMo4MOpb0HX4jxYDQgUukuIR7x8DpvVuZhOrMEYp/PzOtGoHE1bVVabp6znHAwg
MTbAbfW3gatOAZbuJqG0KbRKxyS3SiNz/ok9fw80TAFjwFYagrngfTq202tV/CVzw4xHg8+QzG1P
meKnUP9IwtXTXwn3OEk2tmDQOnwTqoMVEmvr/wgWUjEHH267gpoVcviDQfvWFcVqOL2geeFCpkpk
2FGdW0YC09ASPAVm3kS3rWc4r18eBnA5q9Ku/tzQxSVwudyhf/fElbPMF3kX0KIdTWHdfwjzH+1A
heFf78JiSNuQt308VldVSu8ryLgyE5x4aMw6vxg9r9kj/tx44E3OwpER25jzkUSoFjo65OLGkeV8
WFP+BG/S3DdymvND0iphtRvp3zSHLapy8+Sjrl2EfMhKw4TKEkW2wUn73Yw659eSMGcNx9zvKNkG
9KBQqI8HPeHNViydedrqXHxv4Ly6j7AJmdxl/w2asalnwRDERNJ304ojmseznTw6D4MloDg4lqvT
B28ts/qEZJCnYfNI1Pekl5fuU3werqHWnyfwCU8dKT6b7sEkRnJgoQKHVlkyX9H1UrZvV7SLWP55
jFzeYsHfTZXbKJX7P9fOBbnKXdeVwDC7uJrH+MgcewJoaXAlkUSaqJ4yJFfg47xKcCWHepQE44yc
oT+CpgtTAkZckX5pWcbQ1uP0FXh4x+PMPwf9b/ffQRrkr2irO9oTc+YO1jEXdGqp+3PCcO13fIKx
BUjfE1IOaRsszinqQzyIVvqCohp7XYYgY1i5bJT86kupampH2XgU8yutKDw6CKmIbOQtWraGbstL
1Rg+t9XhQ/uT2N3Uynb7Vpj+VpXLYms2net1IBdblPwG65RYU/n0XmdcBDesl12tH0NSjvXynWyh
E7TvjAohDR04yOej/8/C6lSiYdhd7qvh8cf4YcotIOkGHBLSRry4pYFGLKeSEK4UdgqDMK2ReotR
07LpRWzczJsNdCiGgMnyuTNnDPv8Ly7JaB6nW1HyaNVJrZx2LGGqwgDC/vXMMbOoqSPgO5JVSb0R
YiHRGmAkGNr/rQsOp7sHgX/CN/oBpH/gAQimURlekz8DEu4nz+Tu3Q7zb1ZyZuoiVrWx+GKPW+2A
ezN7teXnmvHfuLAYsQjH9aqAPojfuFpehdufO74Lqiev/oB5S2JyReKx2IvLF0AiNINRWSycfMxM
zjNGLCk4DJA+qVCJC2qZeRblRIQNyMcgvh6qP6SYJykzvFR3q29dATTmWQSbm8YNdeMvcnpr4y4Z
f77anQKfc8ek3B1H6hZUlTsVJhP8iFgRtvSCvcA1W9qbBDQoqK99nEhSDBs68UxMuUA/kRsJcrVH
CACh/OdZhJDWDnahb61e74kH8iZw04wo6AmILXqvFQHrAVmpDR1Zx3kOKJ5YJI4bydYxavwoxq55
9cjV1oXsjTfPmebkkAAvzCF8q50LPmzGd69vnpWjQ4HrZm05S5QP9vVifcdjxfdlD9WfVXSgpIGf
qrpw+OKACQogitSZbvKM2iCxZ3nBhCtb1ZSAWU5dFOfg+OcEhQDidDOl0y5bCnqQF2H2+RR4zvvJ
5WgVVVaD0IIbeV5XW2TjtWOFZekm5rSesA48WPR5145tazsOr5b8MD+h2wcxwGG80OH1DJ+W1o7h
N0aRVZU3I3x7sYtOTl0FqEj9aKm1Jx9ZSbF4p39FXY5xTmGpOkIzbJav1cNUl/BQJFmwDxQ+RMKS
svPp3Y+sBJ09CCi5NH0qieShMLq2aToznmrx0W4NIw0HsP94b7caeWoC6kWHWe9lsaJ3rKfyNWjX
+Uc8H0Asb3x8sxxxyxd506xnxJxN9vV3iSIhQsmI+iJBfHenJFzh8KzQU9Lh9iYcSf/zxeXpPG83
fdK++IOjiIk/Iq4OlNNh+2hvBsmT/13+Q/M9qQbY/d6gnKGSbNjL+++RtH4AZFrc/PYykUzlaCbP
yhheYAxeQNn+g5aD3l0teVC3DgSbZKZC9B6wkuGI7umIQbLbb2nAkZZbLjVHNyVf+r93aggUuX6p
Fb3P5TIYpouh1nmtJ/JmFe+eEwEIp+oiOU+FboDg+9CiXwM8l1wErqQ3YjuXRXza0JqtaW2tZnri
dqrCOlxhdAhLQR+1iLE50NDrpWQz6vKyebOLTqiWMGQNhu7Nt5ZvDwzWU/LIjWEzaW+ZIPA9e2lz
nZM1y1588S1n+3CEk/7mKl95BdocUiLmh9kqsy+oJtsH6WlnOoo/uduIXN3iDPmqeHwN8TRxYHh+
GH8CSIJc94dCxpBhIG6EUkxxqDGRYy8kHh+P7SmuiJYMzmYJlXPPtD10e2uADEajQlykXAwi9mCr
aDzfgYA5cdQ3zA4ADdcKsJ4AIZa2zAHDlAK6e9fSujxyJAHqDmCV21ManYAw8XV9c0ORrzKguNXI
5gYaKEXIji0cq5SAbUFIg8ORIc1ORoRjRKGRdNMQw5JQ2OtY52u76BgX5/U5rn0M8jF6QX57jzS1
K1c7r42Wn9nBU0FvS0f7w7oNCNYJCHOR+CPohYR4l543MDbh+7dmEtcEBdnJRLTo1hOfZM3QouBH
MKRIlrJPIYM2Wd6/Mk6tWa0EFaliAFaq7/1k9XezSTPZ7sO8/koSwuO0+ndtOncEGpCS/S5R3fd4
KYNYDi9eUXQQgvWVdVwBDbt5jGtxU3FV1jzJrzraI4BVO9Rhwq1AAQOYWp9uS47+fEHlPFWud4L/
f7ec6G2h8BfBNzc6yhcUBUoANzQhMe5w5KWutWxS2fzZTom5Y3bl5zYWEh6dDR6f3KTira/QJFti
A9dy/SK3YfEuqYtjMTg20+aNwC67sfWmKxqTHsLRNdNbILuM8Xa68WjUXZIMaDTJwlfxaVVQB9Ye
Lbu8NzcaTyzrk3fbuPKVieXq7RtshBtgiKcwtBBKEmdQK+/p+uMvHPS1sWzCqOaMWRW6eReKI9h8
Iu8qRWgHUtMFHs23hHWl+UPcdx6i3609JBjObERMMNMRkz0iTzbLJ7ShurGkFZCoXfXkX2+YjKk1
joKqCEAjC8+6Iqpf3UIpeJXmNAv9l9HwsJZQo1halkJw4sLoPNNkv0wjJB2/2pXeYlnwYHj//tP1
W/REQ3ao92GXbKkGb7vMq10WT3D+HRhywWGBmPbvIGv14+cr99/FuuwWJ9YxTLG1AA0q9pLNtnoz
WjSdS5b1Sw0RUcVWvBbufniAMpisdjRZZrCF6L5W67QFFJ9S1riuY3ChHztqjkvoq6cNcme0feVW
ybddQHJ0uENl51LCERa0Rl4940WnF6vcavcXVnfmxuVdcpzlV8nn8pIVdrgMY6A9Enx8wW75Wl1K
iKkZLn3s7HpoJ4rn4vAhnGRMlRnrnWP76oo/RTMahcN46vDzmiyq/GwEgjZW2oLns08yXQCT7UxL
AHaN8S2nGcAWT/ObrcqOMNA1CjUOBniD85/VLirQ5vOKEULVZmUuwM1dNuXKT2jmnZO4T0zggiCT
yEoG73ZIQpbjhuflKDdqOjGrXC9e1FRRRe+oqJF/07WBPnowlXnaXcst1XCxZWyJqA51CbfX9zwH
rKnlWMwY2p7fPOGMLkZFSxTId4PtLjko8lyVgwln0EcI95qJmqwp2pvJ0aFCYxQXch+MjvHx+vBf
c6j+2ZOvLs8eoanEZOgsbsXbwncE7tEyRLQVMghQVHhLcCrbykSDe5499YQjq3EBKLpawuZMarxU
B9R00t4uIcomqKLppqGvxAEsWBPCPWLyut2pl9O2Ajk7mdFpcfQfEYl4tIbnOvsH2Qa/9WnsdFPY
VE3zz+56DW2v3TEwvkuYWqkSUoG7xFsqAgUf1wLHBF3n8RwKEXNV8n4P60QR6dMB4N1fyBkA9KD4
LuGF4vmKT/f83TlmxWKTY6ervSBjO4rBC5wlpoNMpFeTJ5o/HY5tiG0EvPqygilxlm516LZnzIcA
8b4f8x1OfHWCWBE5Ht5ekUP07bpX8uz39wDNVsAq6PfwjdU4zf0X4DPMlTm+oCJuMroOYzZErL+O
Cw7ENUBpUst2Ng3eNCBKjowof7d+u6zSAG1lvuJdS+3bD6Hr+eSmCr2F6U5Wlhx4DQWXz4RAiFXR
bC8DFC7gDMQTQe4xtzbkYX51MwJo0ZYyq5pK+/sXki/3oI6x3XOizcZw+7kmrMZcQiwq/PjNBKde
mD/R48km1taPOcgo2DQ1tMoJpQxRxTuJ5cPVFHI3sMdUUDsS5Z/iQfgC1S+P1qBxKkCaKwwtVBDw
7Q2nnxmdMv/t6xPXHgE2htCAi8Yl5Sc35l26w97qaStGX+3hODlXyeYu1glzzPsCBEQmjPiW8RxH
TXZd1Fo4NRD6HmKA7Yha/h/5epUkOLoW8207AROYx1GatJmSiDONtGCSOsngbkidI6q0/mLOa+mc
jj6xMMqj9XNNz1vc2ihJq27/xw6zvjZcSUuF6HqwlmJs93XazTdkYd92H3UtWjbkcN0w+OD/ctrS
68Vx76p+tZfQNzxKdxtTykDdAnlsflFCBRN6XIqLZAENiuP+4WXYfIDX2N3LgmDS1yy4gIHif1EA
ibXPPyuiaeZBHQhmdXvl2XRoLyorUGKKa5RTsV1Kps0Z029p/ZYPu8NMPF3Tlq1q88GjjL9IMvSr
VZmYGkmAosv6op/k3tRr82ls1zA0XbjFO9yLTZyD1SD4p99zVNh/g029wrbPILo88Re0wp8XZhXk
gY/wtXD0dPE09k6paOz2KyZ9ifdbuNb+6pdrvQzh/qI6s/l+sIiWhDTM65gqwG4zfqU2zmhm9Nb/
Xizjd0TJ/6lVFf8d3Gzg6qpjpA2tZdElwF0GMcDB4DRKzNEaxcSnkFPgGYL4+d13PeCVU0Lk/k7z
Gh7ZxbwmGPVkmLDiwK12pUjIWZyi7XULVJnEAIoscMpuIB+ET3XZ0gtok1Gvr8EBdHkUypPw5LI0
BKXe9Pec2i78UdtEX0ofipbelDuv1UlWHZwWlIQtrwaKAGSzUEzCwQWcKdV8aBeYK3lSseZ1qS0i
Bodmy03+YINytpsLwwxuWwSkDZU7J8j5r/dwsPy+vk3oACZCTcM/rm/aqshtsORfwkWNRC7RpPwm
dAHXOb4nwlfQU9ltfHHo1Dy7gDygKk+Mqy8OYDb0ku4qUjftypJL7qG3nIJ/NkrqnIo3QLUxYIFA
54fp2TUVVHBoQfe63s300FE3Q4nxayrhKn4tLq+s7Og7fi1P9n59wpDpuvyasViRQ8HWZVKI4Cik
2nQYWFzJcOWJ4h1YeVVXwcoB0B+Bwi4YNs+S3nIBfMWZgHboc7OC0FfvB1sGDTuKkOZWelxD4hms
Uw7X1vKgaS9cJwP7xE2mhcHSNrL7kOWWu0HWLEVWSk+emONoN8P7z+I064pUawhQjfl0yzs9TDgv
NARRNjx0RqF84q5sfa+/jkdCL5S5dzHXI7QoHjZb/FpHtwIF2tmTdAMMEB037FCiWwEVA/NRp1PT
ZfJbHlvSEAolMExJ1bwEYe3185HcRDn5MQiKfDa6Z1fq3dt55U0TBok7Tq/XR6wpJ65MaTVtSB7f
GZhxJLf8niKUlUmv4gmKJ32L2r+IiNS5QoWAq0GuRgyC4AcpAnhV3dBsjyGihxBJsLzmpE3fiaDz
7A5pka6DHzs8B+Ly5gqzLHdVEMe3kvCZaLiSApqSBhHRN4A7I9ziMd0HbNP8yd9HIwyx1Gk0wBlr
DEqj8/XYPB+FfVr/RDZBr0alTOi7eykt7ErYq2fAiTzqhf1kK1MKiVc1xDGBdS1VjCy4HFVLyePL
561CjHlUdaKNRQPK6EhrDxcC9FVfqNAMNzGsgVsDDODOwephPrRzsgHTYz6wCA9p4WvE0wvxMmfD
P0zb0tJvE9LJnX6j2Uuum8Sq1fFENaxl8IPnTs4RA/tIqYnQAfY+FIFblniV2f4/GTTzgYUm9yef
JvaXIMprRzStqelYIOpdBZ042viuP5T9gXj3jPuYPxor6Qw58pV2frujdCEVecgaveYh3j/8lMPp
TQE56kMjogkyR5RJ1q/u+bhvPJKR65LnaX3vnAizessI+noG9SVOQKVICf7M6gKGmzmYw5AuCVqb
m1GQVxXs+AOeMnBH0tW/OBR2pAMbfAxjaF1n1AbRd+IdhboEfCkLsXvHrxdlV2XTTrZoI3s5ioeK
koy8uU848vT4EKHF8Y+OHAnhB1r4odlDDVX1zFPHUEg4hX2hr8hKwRAvufoGcZrlV7L1CbwwbEn3
D5nbxeOhSYx874Z1XTBo5sAi23FWYMAJn4Hp4tw8a/tDC2Z88DrdzgHcsfqTQtNxgUZt+VDJ7daz
baBzFMGU8+RNGVs8fOlnaJ7oyc7Kb3OlsCA0S9KVeJCDLHSvhlrOYwilYRA2P0ZvqIPav4oSWShp
WdxChr/oCjPDmX23eYU05C+qGsdQQjRJ26KhmfQt8KyTfM8v6sm2ickMen5XPrdE6kQxAqDDxFOs
BMjIFtOYzJyPZzt6T0vjRBz4SemQha3CltjPjJgj+geqosS40PpeVQqqq7SwObU2pNA8ZD5Yi+tD
B3rtau8ihBi1drSP9PHS5jf4IZq1a2D1IUZaug4zF0pC7CDyAExyy6CcoizpDT5j5nTacGo1M3qd
OREUeyb/ZqUZBMpRPQmLKUincVFJKn/bwPzoQDLe06OeZik3ua9lekAee8McCWj0vuHXk05eJPsN
8Ys5PT3dz7+hnsASebT1071gNiUwC/UkEaacJ230bg5ZnbdkxrXPfQwgApDHWEmV1NOpIE+Tl3g0
BPzuyIE/uabB/GMC3gC3Rh3IPrcXAI0BJrm5AdN9pA+U9Z3THGKNECrUzzxCAPubOhsIVjbX0VLS
DUu5+4CA7hg2Y/6r8R68uMt7+JlXSfHSqYs56qZ4RhonexwEkmJVAbQjzpUed8YeGHSGL7qbGiZP
gz/Azy8II6mbYJ4aIO/7g1zZaPeOgzeoA7A26DuEdbjFtVePwriTA/VeIi6D1nxirctei7OZu9yR
df/8nClNIdNvLiuybg28VI16Yyapf3iQA2jh+bgstkCq0nqiF29Y5IUrKQSw/aRuFDDrXeV5jjQ3
UDRTIBaIBu+/0k8x5Pd3+X8XizqGa8wyZMiKetlcNVbbI/ka5c27S/bnNqY3dlp8etSymFJ0r2yr
eekW/ekDyKfYPtqDGa5hKc5RBGGFs4pYgF4PIoPwUifu84C9NqRBaF7N8QgYLT6KDyeNW0f1bUQf
h7i4QMdrYTqRwA7rrz1Zo2TBZloCbCSG3UksFiX7LrEizC2XTRQjNzQWFCSgUWb1fRebGD4dZHxD
PYMhZSDyWU7upma81aSyKSmQYPS0mmfLNOsdaEkvPo3MRo4DHH0kS4lPbAGl2aVoSzWjoMv/jwtr
CReqLGuRGv0XUsbxjk8UH7R1tzGAipJsEUlnVEq0Q2iE5elM77Xkt8K6VKG6gJwNO7BOASbnvZ6d
WZ7+4lNfcmFmKLQkxk2n9MC8X5cUrI8WXhBs4JHIz3aHqdPyf6zRTR/9Hwtl/6JYAPLVK92KFdCQ
iRBWOcJBpWpMvZDE/YrqWRZcdIA+GDm654CTpIU8XH+X24rc9tNCN9s4HMhZbhsiZtgze+zCx+M1
kidj84cRPCHae+K58b61w5rvzf/AjEz7zaCRUACnPKVrTEZeKWgv/UYtnWe4xH+GCWx+Qzyush7/
skAINIvsetqwvr0X/uhz4qBbjNunhADPzZBnzufbq2RXuwq6f3BkrS56WeFQWXfeXAN4yVejqmPB
cAGbOXRSvEmIJtYhdHyRn3S16lAaUXa2KS/xWNT9dF3Gg2dA17ZYefyWmKbAZU8tDp1Jr+8MaYnz
hc+3p3XPuuDpUVVGsP4pKPtYxZ/c0SFBxCXvTxxu9NLpCZOqztMFBpVzkJKbQHkMKt6zKQaEQzZn
SEvmDgTFBpzPK+Xo8G0bujr8R/2v4mJom7JkspfgzPdejf+tXVio7+XuI1WVHuIo4knEoo5wl1pf
9KctYuehNlJ+IOFJo8/LTqejN5O35aADUzyh7z4hWiEMBHq6ocXIgWPuEUEaRz88779lCTbm5UyL
vN53lfVJR+SEPYdillMGKY4Lc2ueBUlIXWpO8QlZ82zj5a//7Nw9PGtBaQc64+wHd+gJHMxyi9vH
d8E8xxauldOQwDZT6/yQbuH4fSSaAIm2fACv58LSuLgj2UewFKb3/1LXLdgxRqAuot6b4G2/bV5W
m8T1fQJJnQ7rokdAGvshpIKht2pSUG0BiZRrgFJXJAoh0rCUIp4Y6S0J2kCLaIdy/lmTqyn9TeZ9
AyQqY9uuZj6sCbhsCAhQg1wHmQ7NV5T8GRxKDJH4ub/Mz2Zvbj0+0wkQDwG4+uG/6xbrCF/E48jV
4GaR/XwzjcrQRwIFdW4f3EM0Ucx6l40U7q4m7UBUtjgfm+Ccm4f1ORRjgrljLbOvc6KXky8GiouR
DfiHiUqtrht5uh8nqrLHt/Y5j+ApMFz5YgC/rgTq+KwV46xR6hZ9Y8KFN+hxl2UDlootAbcV8718
abOCQxu3sTgZVGo66pgHL+bf0Svi2lpxAYgFtTvi90prl6jGmu08abe7uPChdIA1x7zMhyBjQQ4b
IY2Wr9rzPorv55ZrnxIvgA+y09P4B2ly8V59HuIA3Nymee+p+mbwlMc/c5ysNYmutHqNWg1YojVQ
W+2y01hc9m4QR5Z8wvz6VbveEKPwPn/hWhKgtqpZxzjDOqT15/BUtBxo68yn5PkwFAk7+v6IAg2j
VnkNVTQwyPn02pTJOAHF+doLQV44QP4IRjTSb3wla8KbSTCItfPzPebD7xmq8eV1/he5NEFppkJi
+5r0I6TE5i+fzG2mtp0yEacqt3lC0opKq8Ca7M5fF2LI9m3QWmsnSWJxVPgYE4mAF/66LwOv7dvN
V+Y2qc9/m3YQZFLZ5stYHG6xTr/29sV0r6S7/knm0I7Hgg980h3m4hGeQpnWa75jIwuTVxfH4Mg4
uINWT0p74dbi6icR1rPzHLPguX6wyD1npHxAj3LzrQCgTIwfyLM6GkY8AyplSN3Am5XKZ2FfAuX/
1+46qLE8olW3u+Wesi4zhZgRJhpWJfXI6oebxLaEMHrzbSkm4/AB04yQrSvb7/oeeSsgQNmkUBmx
BwfewdkwEFTI7ntOPp/whzEPdDIIn06H1ESzGZDKjlBHNirKh3YF39gl5NViXP86lLiUb0qDdoyL
slrEn8ElRgkNGq9mdzJ8VXe2sNTGwaydzj+snwCdOHcbF80J/exj0Zp0h3U1Kb60XCa1ksx+B8oZ
H6PaIRjeCRA81z/VzvlaZxv8DUKKHI18u/TA+Ina6zn0pDAHjUj2Aw9tcGKOMOY7Gzj9Ri0w0kE+
Y/UPxZ1PdEaqzNZEtwEk0X4AOsPNx36fVgNzytmuqRV7yJHNuOU0qCm+isp56fMSgHT6+DgXmtKc
Zz+2Dbb0cprk7e1KPnQhdRnlWPVqq8FnPLbVrsZl727aOZfv+1lqAaOHquvDGN+L2aIg2ZzqKifx
30AUlnrMigWAYR2dbwOmqKxjPiuU/Mtvh9PaWSbpKHHlaymfL9LuwbabXRjiSTcrKgDrVXSnCH19
RJCw4MIaVy2fMUh9bOFyuLPDuyNbJjv85ZUc0nqeVZftbg0nIotRq1N72M2iEfcbRSL+2kdCVbbO
RQTa1W3MVP9ocWKV8cG9a7nr1fZI3tt2Sl7QikdvpHhmLwhD3ayIPVOYhnXyasMFA1PMHddu1kxT
kKJX3wdlOnOt622KTBvTDNy6VpT/iTKCkjg5/muB/iLdE9XGHGSSCLjE1mkzpYLw90vEvQ/Hk0I9
y+y4Z7DRI64rOd5Q0EJLyFv5nvBJ8JsS1ZApE8c2rZbVcDfPWs5K1UkovqoYhcVcIZcr0VHCp0nz
fbAfrQXc3WwoU8msB03s0Wjxdfa5N20aJfLanbBC6iwDfqaeYQ6HFmH52L4yC4T/lfOLYqLeqV/G
BMVsXvcp4fVKhB/hdKDjmwr/nU80MSHiJYE+JkNImwyM3Cl9GpEmAcSTku0uFMx4QkWVAjeR5YdC
oioOqzwDFyUKlJsWUo8cys96/N+stPqgZPOEf2wtNTyqDEieWcUE1GjTz4Kd8T9/RE340qJAGMqb
z+r5ahowY2eY8RQrHpF9z7Z80dsg4Eg/WMTRcfccY/UlIvp09w3iBueKC2w7Y5C81NQL6Y6B6vck
29bh+Z/9EkYZ33BdP4z+XYqtqPZRTEzZi87hT1JQL17Yw41Lr/r0T/MIyc6ibeEkSselxWRb2d9M
HymYuTyEirCiuwV266OkBVUPgP0tspesOL6BFsva8B39KolL0Inp/Kw46OX4Hs2prWy2Kj1arYe7
an9h0daxWAPhX0KxBWrMT0uxXrn9aS/PDT6JUMPRepnhmZRrQBrZF03TzL8R6phhDZqiCToxcQda
qgTlNkMGbpdPoV9l02i76AlDoY8EFFt+ovpJXXwLO46u6Wq6zBoZvb3Os9xVEqnL20IKigyCgzGv
7Rws4MFrcEuwQjqx3KiDCNS3YsO1IXjIA4GDk2JDPN9s6TTIgwCAggQ//ItzkPHVf3tniYsGxPLn
kvhGaiR3yyePMGlUSszDuwi7EXeS0Jvw4YhsnvgOPAdqHKQtvthpn3RCBTzM4tOHgWxWmWdOLE7N
7lGHHXiM0T95l7rU0RhHiccvXXHzX2nMW6UGqmpbLKWjSLTLENt9vYOxUzqJezgVbx1sUWRKKot1
93XP86blUoxL3Nkps1SEYbZqZwrsWDsOwbv0R3I1Zbb4oQVJn8NItDJHUGuehGtHr0760W2hjL2u
VK8gY+YOv6SdJ1fKcOYO6Atl7K092CvSJ5jZeEI7NxlSNDp4q26Gdxeg27vZRhQ2121HwmJY5tzi
iAnPEkroCZbmMGXnGn3UemYYPPdQm1g6Sji2qmUYRxA6aepBm+s2azOGWXoJBbp4+QjmlUu3QLmq
HZ0QXkmp/PQQvetaS8a193inKMiHE8OdzRCUGQfL5h8XbSN7z/ruSZqxRz8GcBhGUTNksoTPunr3
O5EK3HkVFVgc5e/h71ZWwtnEwKn8Z8u+z/sFl9xIDwivN6iRxospbpZWoTAODFUymP019s4HcLvT
wl+UTUb58o0R+zcM7q7PxAIYxVEvQNnUAooem+VrWrylnRyjetaNSVg1ETxcujA262qXoXpMHNfS
76D0LvP/DYr8EDGFCKioaKygpj+TtWtn6xbSvKsxBjRnt7U8DL2RP+cWKjPbAG/eGyKZuSrCnRWP
J5osjDYDEhdItKQ9n6n0wBtx47VSfl9DdopBv2/1dikpa4hYT1cvoRjSPCf+7W5pSmxe+i6m8hAR
e5ykC6jSCrbdPocs9a+u0nCGNxYxc+B6Qf4wSLlCOmaanfBxPQmPgmDiDFPpPpI97Ul8tV4phkz2
Ejyh4cc/Q42OYEPTmngdIYeEYKPtFFplyGXB69epmoFyasf/UE15IjsF9wdDFuKZs0Nbmv/mco1u
LF1eqkC5Va1XZrykhkKqaOL6tnLV5lJcvqsB68ngUVDkSmZ4xs0KHZNeitnoLGpICs2NzNDpay8y
VuMg8QKgEtd0Q0T0l7Hu141Rhr7O+AwYdjYPhZsR/m9cM4Sdhd5B7nNbcW/nlA4srxd/EvUgfiQ0
CybZrqlj5+T5nInkzNzTcxzheupw6ItWlkQD7Uf50wG9wJA74HWGUGhxYv5R6262C21wY3Lf8sqU
L4xQ7oUJbeMGLp/XTCZIodhpVftS8J0eGv6O/icSKZmPrHRAQfF562mXuHS+WQnw5knfDA56NCKn
OMl+Dxsz6QHXypNTZrtwt0gq3UizBWVGtFf6MN11KrS8G9K9gGYmuAPGe8yshR0kEPCkkMXBPwIC
1SLLZei/yvmOZHwFCSmaqwwzRaCuKfNYPJcmmWrX6+miRGvQBdpuc4jyD428Jz1OuI6BDHd2PXLF
eV7N+yHAvo+t4fHQPuOa/3K9q82hfvSc7X7n/Utnrh2BRJo19v+YrPoZCPPCSNcBxRWBtaVTbs8+
oAwZ6XxA6SwIM1T8amdXeeofwFzmTkjAJyegwFMTMyY5r9tam4/bEvLZMlLKEPn4YRI+YFBbBQ1o
uJOhL/ItqBqerVc+kHFPZQ1vIrWj1duyJE4lzbbZCPkatXG89SVWI7ZX45aYrz4puyNZ9tV3LiO1
OqVvOHdciggksf2qxk/YJ5FCWZQgOhZenpOm5MYRNcRiiRd/Nx7NozcPw4t/89BaB9UK+2MNcYa6
FtaHOfyRqHjqU7FXoldSlIak6PLTxrKNPlmNLj4ePgZkVV7mv1qhrnyaVZiUR4tPPIWIXq8REPJp
G4NhHvqkzqXbBHvaVfgawyvU4ftLS0Y+/eUOamVbUzalNysqnszQvopboUzJileAYVQMLcvO3zIV
pmt5mreD7upkiEKP08ikVzLFdWKO2kyQ2P+kzR03jUnnpSocHH3JYQoJCa5VFBos7pr6GfZYdXAw
cmrSowiW47i95R0KbVONTpXo3xoO8bMD7xJn9hx89jmsblWxveEsUwxtd360of2wKwFvMEoldR5T
GVFk6p2PqWGb9Ni06lWjFd1iAsWO7jiE9t9zWEQeknmEA3BbCIh+oUsbiNINyEF7QINppHVw6VOt
9Cuqc8Iq/BcdhUqvaVeWhGX4FdFWuVuipo4jeyHgfW7/Q+v56IGCWAID7A2Fc358lqMVQe83Jpsb
igIYe1k+dYDmp912UkBx3ACYX7WQ8on1aRomrFCrbhbjDEyuD3khv1tBVTx9mpjg62Xm1vP8HPio
//G9ipX1oItfysjlS5kG8QTf3/rcV/OvlnEqCJ166x9IHR+eoBNmPxGorj/qdYnncRfww3veDIdt
GTuQepsVEvN9Ac5T30hqKtMJr4TM30B9Y+r+gjEgjjMiR80duIlBcZHP/ZRMGwUhghEEq79Z1wda
kPIxhut4LSXWcdqxUogHLgQJ9u+iB/1r1ZEzT7BE+v/wJXBzdW+BgZR9RtJoTvNLIFv3hUtU92yj
q+hHFt8rRVogQxBDlB9oYczNdTHJQO6+/M2gtyl/xDBbSdVOjxNX8KR3jd1Kn1v2g2Nj0pwcwM9D
CHje32u8rDQx2JnS76z6qf4uJJfRBpiu/LG90WnbNPPqkhWqiFr57iMeOe6l3R6aN6D+9Tk9kOFF
7YP3YVzDMXDV9llhcvqRpnL4CjLNNTJ/AKH9QjP/xpD8Mc/IdMsux42mZu1Tc4tseyP0n+0NEByY
DxyEoNbP4cX/pzkkYC2QIRm2JeuG9S8ivxGS9ukcgL/ujqH03qdaKNbkKJM5ABJAUwHxMJHuUXMV
0ZaxXQkPouLKPjfrh9DVxCSLIMelJMEAgw9O4T8mgaHKAfsD+NCSdpkaTJwmXF0y33fHCyZNhM/G
OO8ID7zWcbya6H8TBAJxksMjiUSYqV9Wl24pyZZdCPSGeDVm6rRUQdQ6qJKIXbHLvePX7vfaXHID
x/ZSXOp/4mFGAxe5ZXxLusdOXe6ydoZ1MWyN6qlg0Hqpj5enREaFRsHSyJJoBFwkQ3SUw5XYmJNF
9j3tVXhNbWnFR+Z4csuhuboeBU1PXYyMOMBxK3o4LTMzZNDPfSE6U+F/lc/iqbRjmzZZX43pgvxP
f3sPDTeu+Lhju02V8BT69G7Ad7tH2Afwh8pMO84AOB/Wzj5Nin2j4LsfNCF5+nE3oqo5/ODCI8lf
PrDIS3SuNOnkHuUhwvjOwKZdG4BhC3n40mG0DIFFxGp/ImVCwLGxUBqgjTlcIsSB9Tu2sSH1cZRL
+3/vixF4dsx+YHFAcQvnQGGR1bN+1MGzToYfqPJiyurQmCg6h0yuAuu8wcfyLZrn5hb2IrFlF+d2
CueoBFE+w3Rgo3wdOrWtw69dJCUfLimdyKsOs+shAMtaR3NnlB5GNhxTCtMPPZ7jnLf/nKlDJqfs
9L1Mqtd7wOeS2sgJOWbamhUHTT17fViXtppgXbwlTgRROV8fboq8FXpoRAnP3+4gHablmZMvQYZB
mDYNHus5ajf/cxAA3P3iElSx8iabq4nJb0bFRpWmTpTg9Ot1KvtLqmDjH8C9pobBdCvnYOgV/T1X
qQ6WQ4nkXKtBm8L5UdVE5xqrnIab5+t8q4OjF0m7twGSRCi9Q4og1vrNp9hWW/AZel25EQ25hmhE
w8t4SfbAQUmAhhL1q1E9Gb0hMO82NJd7PrXRst7ZSfy/b9HhA8vlWc59cCnE+m3k5xthJvGDYaQH
mTh3b0jicWlCPRcIZIQXufe6cYbtADa7i3y63RL/l8ot77L/Hao/Mui+oqu8rbSoiovAdXsNsuAy
B0eOsM9iAv+qKwC+GH2hcjHgoFKDI5AGtns/sfDlhPB29yHWJVxY+lH+MatTh9NlVvicATsvO1AB
ZkZaHJsBwLnuvOX5FEJqXZkcs739uY03731MeJVQMYVNWcafdc4XTG7jIjb/lRxrbWuQr3EqRqbK
w6rm2iAKfJ88a7/qvQfdYwmdC1T+WKWC3tBVvW3lgBVX0F6s2HY7Y5nROw6KSIgU7kZbfR+z6SYo
57SKzqdI2lxukk4owAijuU3TELUujvNKabYfBsqRrx5FOjssF5S7K/jrgogzLic7Gxtj+rM+9PWs
wWcOE/qA6Mb2hSYW2gy/57Mc41/yxXIol5MMml1mSArPVA+EKFkFYrOEMYULukMOV1oFRo+O/JjY
les2x9g3HLrSJJoYZ5ee2RKaqtGgQPHjE/6x65fXvj082U4tMt0WYjdNTFO/9+8KqPghQCdvfFP/
ml22tMWEjeC7D0R7q9du6JEt1cGWdkQy5euIvyA0t3iRIwSF6vt67u+ttL68w0mBWAqLa7OGqOBW
XTeGr36ePsk85p6tggkI+HaAGi47Q9P96p5CqDOoP0ayBnU994XrtLjnjP1XphQAE050427rmhXG
yDvRGDx8HOn8/h+KrrkStgeYT5G5kPhz2I1SbaKPIK5hprbGpUjSE51nGdSsNemVPsTVoagxkrLO
zcvsK2Ut48ju2wQixnVxjkZKxYJZ/ziIn/ioCiI/YrPlDoz3DKAWdH7+DQP0nbcpha/MP4/mhoYS
r7zxC6yfXVtxYoDJzvCoChNY4OdgQq0fuPj93t3P+vjyogT3USp5pWeiWYNEyqgY0OwTJWe0bnHm
QDbiZSWPcOhL02xDo62v7C1p1lRoFCqEQFVRem7V/0pNaM+J5p3WoP6uloIlTlGALVLH+6Cevs5b
4Q7MNGn1qp4y48qp9+/Rc5xZv0+dxYmzQbMZ5aV59R+Vu/GXDU4VxuXNIYs29U3I9FCPBWoCpCSc
Ws+jfTpGR/IlrkVwtH9Kcz5/CEVztYiU65qAsOknLOZcwphmaOfAQq1wT1vAAzdaLapYK3sBsqDk
F6GGrWN+zGqckhne8M/YVAz4zGpH/FUpzqck4sh1WNMNs6eAsX31Undsr5pjfta5ORYUustNxtoQ
EVok97pyvl13cl0x03smMxqY7k2Pz/gLVqhM17SbnM61ocFS1m32VP3b37YukXm3QiqM3XmNVd9i
f9y3XE7f4sONvdkvjysSv3R6UXr/vf6TLnOSGMIw9RknmEnFvWX2S9j/A882qOlGtXa6xTUB8yhQ
w+oFKO7fxoWznw/mYSKMO1IPJsAYza78s4kABfyrZ4HAcRg8GYD0T39Yf34kBZcd2UtzYWNP4U7f
maco8KCiXoUzgUZGLIa1FV3KzsHaOy6/pEssFxn8CCZGf34WneQ5gqCTD07FUVgAtjudJdUAEwCB
VoxpIQNc0buwxF9IVdxeGU3aVPBWc2X+4dQT1lY3kbpjLH2FLqHn7oC12K2aYJCaQJdP8ZbrE5yx
UgydxgfGLf/HCZi0msYsBvnRBRw9jx2NCLw4iSs/d6bAP25zGwUOtw6nVKru8q2vI/6QMHxaMy1l
j0xItRAAHzu+kcmzhTOg63mw/EnMDURrUPpaiO7gFeG9IsRcZWaRUfQTJtgw54Mj78zEfJSfz/9s
cEnEhVD0GsiAlKD6ObFxHg6kfwjCzy1cY0ipmBdLT8j1092ePsQ62WYce4a+lQ01oMhwBrZ3o4Vq
qDPLWpQ41w+8og9Ve0oYgo2M5iii/EcUVF303IbNreOK2dUEgqQECMuIQrAHhipwfoPx4aY/n1ML
UDFo+DEetD9Rh+EOEIoMSk8HLKmVEoY4YWEMV+Zw00TfJSQe3WGtjf5OObNvGscdPWEiUGkiB0J3
doKp0fMKINycHd/KTQF0hOAcM5VbUrdv/gaEeBHuBBh5rO/saliIYthGoFAlr1EYGNq1tZYoay8D
Ry8jghQh6ZM9/v6IZwvWkFwU/9V0ejbuoObjHjRkeyq0Wj0/qM5AjgPQbeJZ3aLcW6GPWLJrrBTz
OstbLoh4VlxZsjC0BCosqH65PPEmzTGf2Uad7EuDgCrhcehB9v5NR6SSRzuLM/W1TdpAntxluT+l
3suqizNJ1TRNUBI3wTrIUnb0fTM830c9wOj6xVWNdaZYPPtjv+oSUj9YZs1o5Sf9H3otR8nlWFRR
eKz5T4m+BkCuf2Uam/sq6iMgh8bCw42u5dmUICaj7UyRKfP/r7W5NdwrPA4ew1RqOV0rLhNyEpr3
4FNF+1is2vOqP+MAHPVPBEm7EFTHNy08T6Tp6xCifEqhbw27g3tfmZ3JDK03zHzDqAY/oOtQF4G2
pXSxeanAhkEB6aUEXjPiPux/53RBfC8Xzxb03kCD3flITragfo/r/l40f6K5l85Q9D5kGUG5MRnJ
5hnR9uQo4skwnifUD3B8+9aRHfROIQ336ypcQiyn7bH6CtlO8bTzo194M/TZB1vJ/kgHpnjzcYm/
hcoPGtzlDvezWNLucnZcR2ZzDIP6cyMrdIZxm5o3mn4Q/5M8du8jyu0wBIJFsHD1tRmCGQ8hiOj8
ovoymdSLlC3xe8ZKcxMxHl0rokcDYUC0+FhhDZm8epUuGQT3Y7QOLIqt6z4njdJYqELkiACw15Mh
J93/I4ML/1blGqDRQduKiMwE6OwVx2Up0WLYq9vHz5l6fi110sofpRPDVE9xEvBcHcHdzV9+RHjz
OtZw930yOArEsBFSMToLRbkmdlAfGwbkkbgM6Iu4ubLIW98sEVDMblJNzjhbAjGy0gxpSUHxNL4K
fmGfc/phpkOuRVPRfpw1jftb9/KRga6KQrPyinsKPLv5zm3u9YYyTq3xnusxQeUDy8lOcBvi9SaJ
xRfoc0V7c/uVQgiqbHpMa8iwbuNg0XrXivcKfELr4ONap/D8h0LOMLuVpi18m38gZkttCxmb269m
N+hXYQL+b7r/qm6vrBNZW3PTo0F/+XVuu6oUarAhnRgd4HBhIkQMTmKgwN+CflIPJSxMb32kbAMy
K3yQNH8TuGEkdU7m8v3R01jtYFxxSCJhpcNsLB7s0W2gvaulxVF8xyMdVVu37ni+In4ngcKfKq+H
Mv8RY5uwrQ980e1Hi94lhf1NUZbo3mPoXBqLyNUUCADs6cTvGB0H2yjSYIXcDZTgh6Ng+RPKQ6Dv
zq/S39TIoOIzFhDUf3x0qI8MlCZMY0qQZPQHHcwoAbp6kXKX6ZSYpwXr02u3RYkUeNWnoC9Sszl8
gsrusESlyO8YgghFStHdbsEHlObQ+cxtaDXHInillXg1Aao0uwfnpeZrHC6Tc9jN/9Lqj9EwJGs2
aPMr+9mBKPM1f68tfjgQMiYS0i8RrlXRavq0oHEm9NqWfc6Sk7uVKoN8PRBT3jtzlMmQ1hOuw3QS
Jb1bpCDzg6VvTht1+2GUx/KyR5onlKA9ohmUM/JobbS8golQMEew0Lzkc44GhsYVB77VgSi1V5Fo
+AkZUAQJC/PECLsr4eDTun8GUKuPiDsbrMZH57yM5cfmlaNnJe0OzofsOcWCfD+L7lJNdlKRdBf6
Bzs0+A618teK2B8tf5/A5kwDC8et86JeNHca4iZnGJEYPyXVdcoo3ftabm8jGF3aH40bgknWB+bX
b+4NDGnWKhMXhfJAMH41X+NtgFVu2I4TEJOyrZu5FMERGY9ToTpNeQLtzC2dC5uu8sj4E8dIztOq
14//2UlSx/s5HY17S2+QZjDb0n4x04rOr6yGZix2V8or9qlBENwnQ/vCI54sfrQxu4JwAlKsdX7Q
h8pRziPb+CBfCcTxjQsMqQPpDfZncZneIwlypirD3BAmwXKTaYVfXLDW/Eq7FNMM/Mm9Z2RC7TbN
mtpDB/IkTlQzN/VzPPVu8V8RQFlrCZr3hmOcLJRF+RBCevgNTZGyiWB4UHv0PUZ2tT3s3kUjQxt+
BL0Amyl2wbYdTgmtzEo3URGaIqtg+olkh9uJ4hE+rtHVqv9GbcznhU9KZtxuzG0Rb/VPp4h8dLr1
x2l0BurZ4YTwdeG0zpp+Muk+FkOOVV3OKIOPgpzokhDb5C4ExLEVekGU+XXADWmMSK/5+rD2I9DO
Xx9UOJHkmZIEAHURhtuhFmjlCnF07UtSqPSbvGENPO79SiM/ptPPB1uafIDyzivB6vCwrv3AqoB0
uHpd70xfrM24wOnxjkvRWwDO1KftbJx9ehIwOmTQGzhggTtNCP3ao40Dg28kFJoBaPOTJ2PLLpvd
8KuwLUZRliuGRLXynvuq7YlpCNoKrSgoWVBzFqnTr2hnlV1qS00HLwyxL25xFN25NQKLSgDCPFy8
F4j5TyZkKX0NjDOFd1WVxskjG2IzzUap0Sncq7Irdzg/A8BPJ6AJi21uXAGSrE+oVC00zoZRY1Wl
k7vzO91JPGOfNPim9qI9vL7kwzZKm7VRZYiqEcIDe1ihdOoP8jVz9ekYBaTdvh2ynEgvIUuyUcdn
0hUnoXovd7DmKLwHxdE6uxIJS2thFDiSTZrL7+8Bl7xVqIP5ybqYqz1A40Fl/J8woy228gog9Vmb
NLx5xD4dVrdx1p5I5paCCZcIw/sfnoWhM0MwiibGswI96sEI3M6SwTLZ8RZUbDL9UEv5Rd5Rfmlh
hRvtbAbn9ZMG+6StjQXtfyH0ZsfNsjW9TSV6D+AbdGqUZj3cdZr24PaQ+OWFEnyQDRCTTDo4s9lE
byUnpLHAyeuMoPIXbobxf3zZBhg5ZLL3OVHq/4RODAH9xgSNTI5wWgSY/YMZohBVJCr/7gVdu17X
ihYYCdbfOTeb8mqpSDuGwfR4g9JSswb4Ag0q9FLaF4kIwx7F2MwFCBXS2dk4lvUfdoUdth6Jw1EN
k7G6szx5o5l7O3sg1P8FOYF/JtwmTh8rWlydjYtAdzqRwB2aWihgOdu9iU0vJp9pFNBxR7PgZZVP
hRr72yS38Ukn6ghZRySUCt1pCSWcmpnIN5rIWgFRA+YV8M5lxDSY3dp2m7BNG8pTRL57v3WtZReq
hJfp9NOJsEhE8uEFU0tR4A0DN1cpLRsNkhtToC3IbHVGWY4LW3465rTBCwxXUWYB1xMCS57k+1CE
1UKEiTizdnfJIA6ZqmZTA45YaPe2hyCtddPvDRQlmyN9aJDloTQkCtlsbmDizxbdv97MJMJKSbEj
eHUsBK5ZOOJiq6XrUV9Csnk+E5zqbYDxvRvPj06mdwqHwifaxeyZdb/7elegWLuDdBjp4UsZ2EEJ
uyQ3ilHE8ygUO28Mb5Xm5uq3tkpGWJvYKHXC5nxZYPg0ro3+0rX79c67DOXWkvFzXw14GLbVR+9z
cCngcrESYO1AKVFXP0ggUz4PirNDWZ1Oi4uqRXy2nCGOtkZrW/uELSDmxVa2aFSe3MBEC6S/xCxB
b4gZo9HtEYRSzoLvORwTrDNeFoBmTvBM+D+EsKAk5/3sUAyc9h2sEShMu80ByrVap+pos+dC/PKr
ZTEp/ini0NGFA+SqDtMqVrnrZ5sgqmR1LxZsAWwseJUg/MwfkEOoF5Scq5RBtLYfDlJ0HE+dQ7f5
Xv02Nwl9cQ3Xh9fXM5G0yQYwBCEsLFTtF/hqsH9V4mnumoPlqmKuXiAH8HrB2K5PTrR7G51YkajB
dgzUzQc6YQYgPr/4tAqczt2f0KXhJBvw6Zv363C3d2GZAvPAsgYlJDEi9lJMVkSLcjxfVNheB564
WWheC/WPS9bRaktakpI7odUuz80MM7DL4YFPMoBVohABdmYSPATOZrNiq4dnZpKeGoA1cPShWQ8c
UG0WM3cZYH0TmCoZUISg+5jXKPaNvATdDR7tqdCAxCapWVZlRi92uh2QgR4FQ8BkTL4zP0+U/g5g
ELRWNk3+2neEaz2bGJs9sBLuu3fPRF3i1PU+QR5XYy1nUCla9y8fsf+BGM/oZZEXoHB2YYRV0daz
8vgFYG7ukJmwnaG9q/eOBITgFCPVPe1/rdNqmfvQ3ivz0K9oMY/HryQnf5N0YQY6jPnuiPb/VA48
lFHuyqPPiYdMYYTarVB1w5Hki1kIeZWH0Ap9aExTPtPnITg3X8Ptz5kRRH0/uby4Z/H0e8darEej
FML4kEvinl4YzwvtkmOWwDu8v8npRONNEga/nb4aeLZ2H7PQ/EnRv5tijR+MmptoYoG3zucSd/69
ALU1JIlBlteMPh5Oj5GT3ckG4TEhZMF1lpbPCyHw1cHYd1GAIFnJBQoDKLWS5TJQ1otmJO6Og03Q
ZIEBQHz6aYuNanWK24EnXyG2dxfUYUz8PFpWZQ+l9tq9uquYVLj5x0JgPc7ukWKdSg4IeIN3w7vC
V4qPvDygGhJORuuol5wsmtgdjkxEZPEzhW+DVvWMwUmrQQx1w65zeyse2emnS991B0Iee4JPTdut
VjiQNdQ8LGNvmkiZ1GlTXcTswpmEPNBqx4dhxzK8ONSV+vcbDI3vGay34Uo+spRbVkm3JyZd1ox1
iRdi+akJtw6pi+ZO/WQ7hXYN8wAd+uTJ8dFhL4P+zlFtt/slM4N1/4akdIXhK5iJjBA4tEOZ4T3B
poZbFcMeSLKtwR5siTF1VOA6Rd5flwbUaDcJgy0e0Y/pD9efAkBwlIe83heMkyicV4nD9jeserv7
DpIineowyucyNjpghXJBEB6mexCGKihz4xwFnQKRhnRDoh1BBvQ5eYEhEO9gwFcAMqMOM2cPAPBV
b3Yb3oTlpX8gznOOZSY0bRTSJiGiJwCEvm5frnQ712YdOJTejCWCZwYJa7AevjdREJnK85T4xbdm
8xkwBQqvUuSEGr3mExv9cC/NaUjNp7CxbWidemkoptJqhYxxSAEA/Kb8cB2F34t3EMMCuCd9mLVc
zXmS30LXOmghkDiJTHK3c+ekscwQF43EtqkVHSAPQgtIGe0JEWM9J0q/Zi8xHMwp0l192/QsfxVX
22QIH5G6+yLY1BsmHiqrUUVeWIv22V8r9fQ0jUFb36TNF0joKzE6eodtIQlvxpsH9egN7E8FScCv
mZk0kegBeHbInuSUhA9OrSRkQWqjrjU1q/MsNMmouPF0tftTDXGzKQqt5SElegZbbDRvFGuHXU+C
AxYxu3BYH5mRppn/6ZWaOcaPXsoTsjvE4GDYkx6OoMo5F4b06sW3/+DD0Xuv4XOGSnTHFzX3TZcc
AT1cMwspropb5l70iNI/zHKQ0MnfOsMPNWCntAJNxQVUR1V6BxWYNeEpEweoEGo7GTsiH2aoj98t
85xjU8lDUjjULVztNRa4l1G1p5Uu1aIK1k9Hgz12p3d8FDFxswgwmFoShPFUbfUwb7fYnBdyG4uD
aFQI4O8JxeqWl7b+NJeh6Go1XC2Vj6XaSrHIf2ut+PMQKzdTIx4TumWnQtWc1+9R7mmKjDdTDRmw
ff81ACWboi8maIEbHfLhJDp+1Ihyb63WAteJrq8w6XbmTq/KpPK6CuRIbCxOFeE+ftTBAZgjEWAh
RPhgbTOYxXopgTgRHN3YNULPzWSrzFm8gReQ9IszX5K0nckSdtrJPm8rJyrCpltQ9Gev2sNzgFaR
SZn57Ty1F6jtOTeZMY1wj+qIbuvaBDzyX+9iCO7QfdeUuzyyk6eWR82tv+9QiCO/mdof3t3uwjve
W7zyeqDQcoLAoNesFNs3Dxx654pXQ4SQKI4jdNG+EU9aN9yB0ejOrrqvzNrrGCX3spz8o/U5uq1p
GdbuW5NL+f1yZrTXZG2S/KeObeGGGGiXj08q1HHDIerRQxgdLFADqReULBlfXo6YEwx+eHvoFY2H
NF9I+ZJymaRZ7DpXSxB8NsYtlXKr22Hre4aNZjsZm95RivYfvV/kevRzwEU00lSPwEHIuieKAeCk
9h0zCyPaQkN5FvXPQ92RSXdPi8psjRpMm+1cn0Ak6GDG2hsGw3M8vQkoS5xkVrgdToOTkJlmbrlo
5MmJcF17rzSSxhK3D2mBVH2sk3ACnybcTsBupPbtYap4/5LIBprPeBSUCzej1+VIPfyaruYATW5i
P508bcjivycntxLpVK3MpwvDPea81X24HJSH9HB2Oc+T/hLaRfzo2UcDZ9AeH3wRs80f8JLPv3LN
QCzJJE5QUNpS98tN4oRZycIHfNnUjG547eSuXaOJ6kpk6YoVcld9TLCmrXR+3HGgzXj4oWX6jDmu
wWotaoYelcdufZLwOfulIoh7/pDl2X+Rmf7MWeTN6AzrTyp8joqG7444hepa2dfFz9pDTvSn153Q
JNz1LnrjWo7m0B5CgcgUWASMBu7x/SG79WpPs6ERGZV3nnHBba1onrW33LT+vTQDcsUS3uiw9Qjp
k52V0H3XCtLF2BlFXEnbdgseIbUQd8jMP+fgkOFr2GEQZJ63qFUIYmuz0HfZvoNJ712puHth5qAi
SBSpPOmG75dXv1dQOpuNv4zIWwmNF4UC3oe7GnyFrLEwrRZRE/iZyUGgkqbBjymIxW1TKoLvhba2
UTkjMfhzuJ3HVTalYYa0NpmvwsQ3V1TiuKvESQ94t/biUa9JWlKJezXxeFKDs9fSzDqkKGbpQPEl
SdHWVL4aHzK4ylQZek/EVU/lVJCsyxwuia7pNw5VMJIFaUOlNdYd8G2OiAp/NbVZkynfqIEgA1W0
g0SO2pzNH9TMQSpn0a1DlV72DCLvoM5DHmfhShqizSbL+T0MgCM/9wj6nTfdDWFwoGYx36dYYBSU
dyQTSurHmEBxBlEwIAmLN3qTIApozHKbG4Wi3Cdvn76GcIBxe1gdJ3GMVs2HyR44IAlsv+vXVRRa
47BMgATjaTvH/9P7p0EU7tNIIXWuNkiqWtLAu/FUgqJh2ENNWeakviOnT/Vbh5tpLN32h8DlNaCw
jQU4wjJvFoQkgkUVjrST14Lco76ir8lONeROoSGuJO44mjQ2n4HpUUS5yge064qU23FDS7855jZY
g19eMfhcni3O1ExBeKpdTEeQfaHx7leG5VcUcCCOqs4+e4szmsNxVBFsVcqvq0jiv/A+ZffLLCIS
qR6NWBxi1F1uEHWpqCrI5ffuuKA/qMz6GoBzXNDisl/DnT0afMgsP+U46EHgZV13EGKM6GIIKBwE
hZyW8f23ZmbXYfLgnqJt8gBlB9BCQqgJ+/AJkY3H0BTusjheeF81D1NjVACicNeMtb6GGkf8Bgwc
Yk0LLzOm754FNrprLaee6OPRBMf5nB5fiyodahm2cb/rHOhkL81yS3Fyzqktxfw9zkqz+D9ze1js
xX6VVbtTlFHrzgBhPU/X2MYkacWSEJZodVi+oYVne47/4Jav5O5Hw/QqbZaY+e4qUhOmxS1B2ImA
yqkcAjX6muEcfYVmrbE+Ry8WqpaLqixmONW6OuKqaMD62e6xbDRapR3llNzUgI59hk0NuKDYK/2L
prZfCzR2OVRXYN5mZhrrRBiIqqnZCgmyPk8nqlvNFMuVbQvPoTqV7XuyCE/ZOV+Npk6BYnCI//Hz
XP+AihKAeYvuVv6MhC+XH3QbWdJLziQNkqsnBJWu1+I8MGg4tv/AUqGgN7wGIovXh6vhLOtRqdmX
rbq2TUTQUALy6YL10uqa0IwMp1UiiztnRrDLixOomPpbFVpwJhvl4lCEI5IFYssBBYmNBc5TMZ1k
Q7UJpQv4w/npec0QTSl8GFnDa4ReUzbY53lCalk8YSTJQap7K936J9JDkdZWKdgCDSNi9ioQXgWs
JnvinaAT8vdiIFeNtl5wP9I5L6yGZY98MAQVmf+6SOWSCnXrr3hOUCOuYaHhEFjLNaTpJsjizt/H
WNnbvtgssz/R+rVetAODsCx/6+IkXxUS2hyKuQJPNMpa1iTKOnp2ITHA8FvITg9lzN1lmYX33h/D
tYxzx/xL+wreruC9nSO0g8mQ7+Me78G8HX5M9h2KU7PfrVVRwBqpexpPmNpJJ0vE2/pKR1lOPMu/
LLMBph5X0sOhXR5n3wUj3r/wEf4eekCE2Eyef41vy/Dcs5eYzuBdvlYhCq0SuugPbYn/1ZQkjqji
EFEfUsJToelhTlqGEj/PC+ZeOpFfHDgqjIvGjRwr0ajq8LEX2xcZaeRQNo2WznSGlPB+oU16V6A5
wMaOrbEjOTBGQy3qpCRcX88iim4TOH+sdGKNauw4mHejtMOgUElmAsAuYCJ9q09sXACb62+YoCLU
gMlVWGIxbGlgeswS7IcfKQswQAYh/+vuceS+qPFBNxH34ZhLUnJ1qmrX/cN/FYzyuudX8Vo1eTkR
3M3+7CCcbrC2UQJ8VpC7DENntnwuGqykNZGV41u64WXzn6mw3MFyrahA9pVIOvouZ47fIDcqmEAm
rrD2JAtkXHzhmwGuueUowaTZA5HeD9xWypjorPA23RXPFV9N49gYj5iT/1f//syVbrwWLdl/t+kH
ArpNwXv27n+tguITRzVjJY7G+CRW8ABBrgORxXPVZQU3pr8CoYcBQgZK/1quePZHKeirjaIQE/V4
aCsZPCPIpdvCRTdQScenItM7csRbtJD/rSLtQFed8QucMCnMnIQjzjzy/iAfeEYLyMl5CUelDWdB
JOv0VaAgUGdkUKCErHjyQP7jOrIfSc7UKnzACmN7wzKuNkqKplI0T1gzkNiN7Qx2Pr3OOg0q2X6B
LlB2b69Zy9DRe/aMIUTEOSCgjH6su//Rv7bcAuSWwPX8b/1QABO8DQiVassLbOGFZJbh4rkTTwYi
xz0i6KfQjgKVU2IuCNAqQbzb9XK9pblKHmbrrrfKLHdaTeorL/LBoJWFugVTg+WM3tWAlLmHOQ9q
MOJQWbOfyhZCJBC36ZiZ8508UWv/YZj+cr/PhDKXiJQ04A2jm2q8smpkO17e9imPruocoKqY02lQ
0lZsmLk79kfepMScnClfbznr2CgBdSJbHI2qPg5UXvchNNdmE3Vnaw7vPOREIG0IUiN+fDKMC7rL
lMN8XtxgLWUZaajH/UMImnvHDOPFeCzWidTwWqr7WwDisnDvnfwmjyhsn+PpOih0QAzfkwhcwA9k
QEYwWO98A+WOP0KmBMY7yqHa6iiiouXp+TrHlzGDF6JhDGKk5DzsdqrrroeF8zOLLkXmZbcK3G8d
oiDOSwL6Ds9Cc8wb2RI939OwFep+7dyA33ApF0gLHrnl47JyVgvAEyEvjd8xlkcEXgtO6dllL/CJ
hGiTJ3Pkuii7X5BJOSiI51kAbYX5wcS4QZ/ImBQm3MhPr00LIwxCHaYSAjNKvR5dHkXQCGlxuDfj
hN20/bk2LU4W1+AeuAon2EH20sKlR7zXfmugr3rZxxEgx8/oh/nplZUhYosG4WRD9eOkmM2yWrM+
wNBs7U2sKCayX8cHQi9kNStFZB5WsQNKfuNnzEYaqOfLaa/rPD1P0ewmTG1jDIqv/T7q+jTt8G1n
AP22u94nTLs9gjXXoL89676SufKP6RiBcZty4LznUtgL7eovlyKa9UUEnR6qRIhUoefpZyWyoihA
iVFe0StLejtUpvS4vzEP6C012EONNEztAquiLsRpYwftz2g9m2u9+9LBKrCv1YeLy/zz2PzMUbMF
eoezsFyN5XylaQPfE8vyFMNgwcbt9W3TMFn4l71FRm+6p1W0Yjd9nedNAwWpdkpZLUMshseHrSiI
OhJKPy9zIh5qBDYgRCob2ZXW+kHufDGkx4NTANEhhUviwtox2hKtoomjE1LY4d5DuDzeC7+lwVBj
TPjQ63b0yPE3cPv7I0nZ2og+2OihTMJVyEGsUqE1OWeZH1wTZPvG3Gp17E5PsDRL/p5pDwRUojti
umNHfHxR8r3Qq2khW8lJmpwIk76/Tqlwk88Bi8LSPT3OG7OjQn03rvQ7K4/QfFhe/IRTHtovg02x
VIWfsJEvn2HaIUSYQhdrqPLtSBAQ/+AuFQ5/r8+QnYnR5I7ZNlckgU62mHsciJ5Qy0anRHXW5FOj
Pwx/YDCSY2kWJlFEcjLEDU2/aurlME8imghJiATg6syXEoTwyTQuNeDg58SJNHpy+v16czjTnqvn
mvWH2S1HH+XDOAa+6QM9lRYr8OO4nHYC44+oZMq0CCRRctN4aFu/jRLbe4JZuemxoDXXXgPr1pGi
nyOv1MLM6/W3zL52Fnaf79nIEU+lVn8DnC03BJTTzsacXITc+CJWozq1Uu8bqD+PQwYLbkYFNWbK
UlEE4hOhMYfIrnFbJutixh7FYa1ijlmklH3dw83JfN86Kn+DguStHzFTiseKH7FRTZ3y4Tbp7TY6
CInYMTceGJ3nLDGMjCw3L+dBIIwztfmP08W6+L6xDGJYgpnvnhv5HRt29w4GSbxxxPuILuJdGznq
JQmQerxxa3XALc9J3oGHK/fwIfGMOD+fkASAMPV9YqlKOn/y7qmPAHZjeDTVRy6MZq1k8YfX+GN/
X7WJw/C25vdQvOPpRT/aaFRKS3Ic/m5qv45T2ubbtqzWMxmpEs4zNVpi56qi4Js7W3H/ooPcYDtl
uKAAdxgC+aTMZH/9ZqLwmWk/qRnvvfivVRvUeLsDaCuH8q+GAp2iFRMG5+Z88NeF0dWqIuSRRfLD
tmmYmBvBBG4Bn9msTiz7JbePJbAxOOgBk6BbLdAMFmyJSUeVux63rdYUTqJi7Z8xz7B1FcW/mQtz
YTXm7ZicTsO7Z93KAIrCHrm6uly32vp45luGvQaK2k3adc74nAOUm4AAZ17dNMmJTaCdu7VetHlL
+XIAwm54c4qyPrWEiecSOt0Wiz9SXoi0pYvqYOxj8D6x2u8uKb7TES8pmai4WMLsru+2ENhmRWi2
Z+WnptsvKSKvFckcPbFOOFtPsGwx8Umbm8pGWC0+pt7PDa1V9e2w76acXwu9m4qaUa7P/uqC2LOQ
ZpkFQe96FW3P1neCiJhRJqKspdtN0Lhl2019MM23ibL7dgy6XpIo3OwyXxjRmHv85kiXj+rljzpS
i2LZ+jiJBd0V981PbjU2Qg3Mkg7qgJrNRq+Bnt7CeRFKmLQMZ0DozZcbymoAth2Zpdnf/FwcySMW
jZssnieAkS1jZ7eueceHcWVVuVTrUpwpQg16p65CQ6DiyLTHNDYhQxymwty2RRwXPhXXbEA8Aj/z
d/rt3yovN0I1SMozEMLvci/9pxVS12/fBhUlLmg9xvdUNBikvuYvYioRpdUtna8MAFp0HOCk9Ax1
7B2RLaxMOrrZeO/fw3rPK0TtEo/Uok/drq5CdJgZCy1Z3oQYAHTXvd/HpvQZNFOlnkvpGhzALdtF
ds+hEeqEV0U08k+haW9ARjY7a17/HzlO2/ISRdTDLuaPxmBEWdxKPktFz/49VaOtBLiKR4Y1JHDZ
WMd8Bklmd1CKDglNwHWnbXGNrI/iaQ29PIlbenzTJjDOJFlEb2RgvrqyiAl/6n7OzMhe4O55X/S2
Ls8O0PBnliPg38ZpT16xKYbv2MfZNWQqETew5lJmqDhNnULNRHFrv4IQ73r6avbyRKqlKkwkFPX/
1IgzLGh/qwFgnQTShWC/Dl4xrtpF1/tahh86tGoNJ7R2mAJ0Bv+ld6B9naQsNvNGfoOdq3c9DaMa
kUNTjkwEE7/gkBnyuQ16f0ycUVkwORd/ztekFDIpwWx7KRWwGWXF7xd6viMGU/afEplYj15YaqB9
LTiY6oZ07aPKohxUwJ+l8Hf8GCBfk/VzSeSqsdtgW9U75tUtRQhw9zdyxtISbuw0i0YQo9ZFS6N/
acAlnMMLBU7vq8pfhVPuQSl976/BQ+FZmwO7OV0Cpu8Pa0oWORaq5a8ZkfCT2CPuWa7IgTl8uay0
HP1UBzw8B4KLPB51ll3XP4iIulVLX4tGn5mEOpmjUWHCI1HBJy4OrK1iMTWXRSVwXAs3hGO7p8Mc
0s6keKRznMuUIgUVEWEiimvbLtzszfZ7PfGhQYtztfcUosqX2pywg9MYqRYPPaKYokj9k7nHPHPF
KI33F8XtmAexCZaziGyWsdm8ejCGnHY8xs/gdcfxfdYy42bXhsPMdbV7OWha7SaLifFc3lp4gYAK
hAiERJLSVaWCm5aTbJoKscGb1nmiU4qRvjZhMmet99d+SAhjBF84uBxhdvCRGuPTw73L7cFNTp8c
1gywdsmWUcsUXi3P9xvbs7J+5zZS97bw31mzxPiZnVs2tVfr5RiYU7AESAEVdM3uG5i/i62glpTv
XV/UgumoR8M8Z6xNYIefULMyjthIWwIsJqgaApVbj/u3UhrFjuAJ2pkjkqtG6s27aluwMzh0dRgc
1qUY2X6S1C+OAPiEDehkJWmMQyiioquG3CoiKNJCiw8oxgKS6oW/qbmuUyfjkWfvw1GMXZ7g1yP+
rqDBTpIZtaXdtI61mZkIhN6eWGCTPf2NKnCmYnFVZAn1oZoWjHsQRsrxgoaWau5dWF/HrqMsZKTA
jctCpmnJVq0JB17D0Ewp7FHRhoyiMeChVwW7cZWeRwUYIm0FsrUJ0oFClxpTKkp5e2OmPWNXKRSD
dR9IoP9Ev/1bhr7gt/llkS6HLcJogYoliULNPb30rjVNkg/+kMUpmvo6pMvzhZKIT92/KLMZC5kM
9He+lOnJuBS6C48EhG5X8TvN39vQ0ybVNroxi62MgIPvasJmlZKtoz7y1uVE0HXeIlFKaeTyRkYb
ZAw3BiixUPCkOTU4M49dSlQiasqoDApfWrY1MRHHeCRPmbYC73lwOm3fYOuWzSgLVNSnVQcMt8ev
i6l8/EF4+vgKluwGl0ZUJ/cejo4q57kS31MLTk2h3+PC82dEJ8C+SBed2iNeAy4uvu8MqSIGoYrA
WYb0AEotgx34/KqHt5Msl3c526K17EQHqwMT+nJ4GcgNkeE0E1Xep0dU/4mdoiLlC3GXnS8VV0Sa
381HyYlnu8f70v2NhXdVFQBiF8M4lDu33kK54BJA6IgmfcimdGhSHo6dqJ27zgzZxJcFR1JWou18
spo5yzgU0nnbYwMyaiAu0+zhNAWfwEl9B+MxeSWXsNgp8laWv9210ffoQq8x07x4ujxZUltc8gLc
/V6J2o4i7+wo+5X7ktfHipLBAFbGZ8nHxPX/kMASz6dBn/9exzxN03Q71qOfQ2l7HmzVkPjnBFeK
0uMAPK5xug35ojP9Mi3ZDJUhb+8U9eS8EcQrB0YSA/aNsi2MfMHucv4NjJnAWxBhURgw2wrgUH56
NKDSSrV6VR0oO9R4ookY9KoBOP7aWudd+IL/EG8jc14m04cyS32Y64t4F40VKNLw9+Uu9jgzCDPP
OxcsmZ8ATjN54U8/apfb2tzl7EmDKZv65FABcLOtXHhu/Dq3p0yh86lU770DKdh3nrrH4Zx0U2Xp
brF/nR09t/MD/TpFcMTA8+6DJZDXHp4IpTBTTLfInzmwCglDlZKuPlLJKCbx1s5eCnZRDbsH+OoW
ZvBQFtyIB+r10w2USpy78GI1B6eUV7cHFKNf5h48bpZoeqJefkoI9FI8uE1BkbjLZaxT2VgKtWTF
KYvl6om03AKKejjE58Z07rNnVqvRejkQxBgLV98U/mGy+QtHiC0wCkSBmPpP3bfTrWljDv67C/7B
v8JgIYeYC8Nz+20k9j1TI7RBFRew7toulmZPQFJk2V6Jq33w6+5IcvGg3oAHdqGbV3Q9arl+2eto
sCbEW43iVfVjsKeQoDu9MotfyZSiT7VaQuriTjSHeDnkaNjRATtGVzLcLpeUGPUCdf6fAm2Nw/Oe
dNWlTSSkOOF6B73RIvro2oIGaVNw9PN2mHFgcDzN6jzKu+cRQfIa/rhTmfLlT4TUK8I5oLYppho0
DdyEPJtOW/lV9Y+OJlvT1/9NhiQHvsbKuXUWB3Iye05GmnRYwP+aGiN6adXVkxGdQLdvlloHOyaq
qQBC9JoxprFPFFz43zcgajpEIH0bM7jbQ5/yG96goaWfK3pMNZld/H8+aYfvWuTYyR2HGMug6N6v
FEYGIBd6DX5CkEWLOMdtrcH7Oc3yuiWbYTnx7NtPz+gzwA6hnG+sgzfbzfTRz+E0+4NFBOIGyNvc
OMrEedIFFAZt7QJF4P2f0kNrYVME1cza3gqDotEKJyNsOMJLMep7dZwhZAXKTRnrK9wQFm0Bv5xw
ogZU6xC41rHthBzuY1MIpKdgT3fR2Hrks0qm3l8rLceLazN8PcumZRHLAB2u8Kz9RWk/UfH2HabL
XI0NSqfJWcUJ3wkB5eSeiaKBTIPJzaSiyE2HKEDoW+ew50hAcseWeFEwRLwyG+AC2uoA/YvmID8f
jfGQImRrb26ilg5s33yRdkD1rDj4hPOFsGGC7xQiTOHFxlqUck3af4FUbs7do1Bp6Vbm96LOfjM/
+2imAxLcTsQVLVS682u1WNLD1xtvaGk6b7FIAxfjc4P3IDM5huJVon8H4kO1bG5Kd5+qQyO4miyD
qTVyTpxlnFOIJIN61qlVuHI12lBgo/ISL15SWn4azgBzIIpSq9/RW/0GVJ1yeHHsWhn7dopjsQ/f
tu39YfQ7R1FzVFgBaWoQxPgTQc9A/qc8L1IQVaLp9XFdcTwF455V1XAe4i5fjqXq0wAoVI2LqV+a
GnwhV3FbyBZ1R6LSK2QePzNYnsismGeNMjiUzS1cc5D9jvz1MStVRddkaKbKqhP6KNX4e69Qk5Ko
cljSONyew1uNXHbb+tfKjsf4281PA2DjXiw8/Xctj6rkrMGKW3W2YKzxaW8wLQUdt/Bak2zjjdIz
HAfrTwLpzzN/VRNbMlHU0tT88D57KMwipXiOXKgBx6MFwrTZXUHX626alJZcltBDpN2oHMsK1SIy
xUNbugBjb3sGdxvIrkPlfzfghwKmJIzQADyEGo7t+Rh3UHBlVM1eFZujS5tw4rcPsOMnWoyf1E9+
X+STQeEum71s2DeJt+LzpCX6lvI1GsrfYuwXGIkUagYugsbJLscaLVzvFbwM8N2pF3GPWDig1uFT
duPaKSvKkcmmho5ii/2aPGRAB+mFxdGWb1R7V5U+A94lz/aF4WUFaJ33I5YKHfmaCoVHpTzaXk+Y
NLVG77X0/f8/M4R7cZCgfnJiAXa4DLgwwe0gPnsiOExZ7Rqzwoy9v5/6T0Mphqm9yUzp5y9k6b5/
NVDQLTiCmSJGtB7HrOP78rlDePf1SVp48bdVBKRuOKjQ1npTq3Pm4Riz2/0YHSAMbZLkWkXUm+zt
HKOkvMo1Qu545JbZR4tNHf133iiz8KYOEwALu4EwJQ9RxbonyB2LkuwXFK1eRH5m2tRSsOfbgTzS
ZLAR6JlZT1jm8ppzPhI11/FkJc+gAA/VBLlPzAkHRTnKMbZEZOAyTVC653nTBn31vawtGK8Qx4qZ
15ZNibVSmgsxLkvRiRgC6oOWKOSVNl9y00JFyaCNCEbo+kFf/A6Gqh2h3nV4A60BxB5oxFPmNSvF
13pDOJFoJcCZ1PQdJFZJl4yBPSy+QyzD/lU6CabJmO7wXaIsroBUsitKGPowvBVDzhTj/yOCItIg
99re8bBbhPZnzg/iBjQcIuSvCMUM3grAHtYuMANIEl0fwlmFa9EglDvypgR9oK75BSR+zOp+mC9t
7P6/xsEuLXhYeI8m/eLMA3WZw5JNzPd0OYkAwv1YQbsWPnc1SSxnq3s0UnAtkuVAWoIxQrNVf4In
tsVml10O6A07uR/egYOOsssRnKRGifqJcnjiassCD7VuJj0Q+RLv+s0m8ajrVtov6SKlQ3PXkSi3
2IrKldVgklQEIi/ngOzIyLiAK8vXvCO5MLRahBRdg4HU/gFmadwabdFvrkfgC4OVUGSpjCFxBcl1
A11XfzlU7LNAeafkrYqy0jrAClkU9rv2m41C0bB09LD5ImntBEVWjJFiGMjea0/sgKY0sIQfT0Mz
7ATwidLpwkDCRSLn50jifxuRUiIA+Cx41SBjVU3ClOM9J9Ko3IBSo48qfQbqyBng4OKciOh4lvXR
8fEgHa+kc24HB3a9AP/LHA/2qi72lThWO/ymmUfdD6IJd1ptrfp/gYMlq6KRulNRgIKJ6RU2Ugq5
xpgEliohCZkjw9i8Rwml29QNHIFjT6AwFPSIbslbq8da+UlMSwvlgsBivOQ5C6mN7Y1OC5rkuGm6
8wB01NM77BQJpOOHN8aFoM9oMkNWNv/vMf2wXDY0fHmIu0i1GnoT8hfW6ZHFJ+u6UdAYDJVzX49I
IfjC8u1RHzd9kTUm+bwo0xcbwNe/IOGgoC2F8uSgPi5VQoYIHNNE/ev8pDUtmWj4KoI+sC6FyNEb
vAOn/U19JuObQrjP3e2nNXe50T0QUad7U0EF+bk4ZWllVcGDvSeK47tu/UuBY2pv3jRDfZu5wNUu
3ej55hloN036jLs7FN5vpI0emzOJZZnsEe6fZGzIQl59fsrWLI+ZH6NdgmtbOsVrm2jlIiPJmKcc
rCKja/5A8raEF+OpVSclGCYs5sxjNdSGsfR6QVsRwIBeXAv7a200254Wsj9VTcjqGdAsPIVxu60z
XpWWsGLFyxXCTjVZW89v5Qgcd2H7BlYUHYqTwUdnPpd2QgkMQ9DYTvkCbhW4FuECKqPoM/ML3PSi
UBxi0km3+Es2r+tmBXBmah26DBfmo7mce9Ez3vv4pDcFmTH/bjMzjwKLBU1geM9D60QIFfYw29Om
n1me/muvKmnxRPKRsvkcnfym5cK9EK6TNnNqxgOiAdzJXbAG2IiBJ9Y8Di3T+D6Ls0AsEnD/FtiN
89FrjGiIUsrLfboK7n3xTsRQKBF6SzgJZGDW+MMEeHjGeWQ3NL8bPZ49rNdmpkivTDfNpyuMaXBO
6uJviUtwePk0W/1fzG9hbXCkajRkdul/wfQmm86ClQOBzXqLOz5+GEaoPMITOOUG1tTBk5IseHOk
4dl28iYybndFPaOeH4ol8xurRBVP+43D/p/lLjaDlPD0GlFOKROT+EXwpjN6oLXvM6zX+ZnYVawo
j4KQuVhcm6bRZR3HYVAu7h04PZRaAfoincB6lf5p30O35dNc4ZoLbO5ZDS9A+4rGJvTqwcckz1CZ
y6yZDSaquZExESnF4cbgYZON6Izw83ogCuAL1zAG2GNKHkRZpc4iRrpJjFxomvwtfyi3vLB74EH9
PtTSDECKu3H0mwwyRKeNOIxm7zf4LLIrxQY/8FNwFF9uIJ/xRCEFukDK+y2nCPOTLZ3OBF5rv3TY
DxyaR9wSn0Uo2GJ9VDlCe6ixm15KB9BbKU+PhEmxMxheSpRlwoe9kGdMnF9+00nvp181E6j8cXrL
6u4Bb157XtvUpTiyqNtVOEiDyAFvgmnbu9Y+InAL3A32JsKg9jGgwFwbdbTBTsKBNfN4P41y2UZ+
G4jpyGxa/vCbmZEn67M+zX5zlzivZfCGwfcoe8TAcYw+VVWjQgnf1ZN7dpCvmUWQc7GOpZH8ZeSq
HvwcKfpaYFGcrlKYNP6WoSLMFS+OTh5bBTGGcYfNiNrJHt2LRklsCNoSsoaeAmHvZE3QH8qkTkko
5z8O4cIL+m42ElnPLfVKvFYbyz2PIug8dQs3UoZru/P14jdWOaqYqXj+R1NWUbQh+LcckoCF2aOT
qPuzxI7ZOb5ZIqX9jIOTegeQ40VtNf71CnmzQyFq+uLZcpx74ZGH9dbrYLioYnXjUFQmYp59KPdM
qNvCwKC0zBQGlqFmxUL/4iISA9c9JRa7Z6h9bXvlqI5Gl7mMm6+CENHrRoGc1CJSe4i7oIyhNPnn
B3WTuCZbbjxvUPa4DfWR3EKtjdM4BrQrl1GrMp61+XPf563R8hHP26dpXy0UZ2W0du2WDHDqoAjT
D2GhjQT+oRCRrgXf1KwSxR+KcUkPjiOt3os4Lnz24nhs8JmgCIFmaVvpRBL9QmgfdlZ3ycWRTOzH
RlofEjpvyc8ZF2b2SYdDU9qUG/YB5h3/nXrhcOu4nOiBOTAwdGtr/auAf8SmCX0eHsukSOwvt81E
YCtF1vBmcMT5m5kh4SYOlzMljjWVHmB9/heLKcHMzfRhLupv7z0kyTPrCvQMZ5PX4M4pHuSHaEOj
I+a3HleSmSU5d2AKxtK5o0ePWZGBFeXp6LM/S/JEylUXxouLFx4nnEWB5+TsF6QEKVKVtXKx4tKW
owQxYJ+gGIYBD8RTYvifUpylCwWFkIS56MauYUXPj9GfqQw01NyV3nY07KRBwN1cTqab4upgtjlp
abzTdawFhh/y3xKsCVN55Yv+K1inbd6K+xOaAPyEQiJyV8WIZxqWLIQwD+F9cZMuR7SD4KPin8tA
ffu8DdS65FLlM1uwG5g9AXAjdabfrlK1kkztIRPlGv9d5JbyM6IsOLYG8UkajeNYZlWtHwxiur3K
aamqS0Y/yEPWJiLPCZ/3CXWbg47ys6xiJQQFlrWHJ/4wtDmD1YnhvkM+1oDt+mTOF/68rpB81hW6
6BvWBBC0RGCBWk8Zz+0epCd21gKESzz+XcZMWz2blE3+0OX8qNRuhXg+S1xXp3CVGgZhUuRQAs0K
K3QTyeeiJFuKdsXcM5fNCK2bT1XNQ/Vf6ItejHerpEteZsKV6nXejb5DWmN1we2IxU+10TNA478R
kxAVV2AGCgWF5rgfT3h2M+OAomHRX/PgUQYR/q7rwFhpPcZ7t9d2EGjhX3ivQNzyve1+6ENpwBZW
bI4c69UyN5T+bYZUiEUnpQ0ygYs+SvGXWt83shNSPISrSbHWsrGQLzvCJe4mTtP0bcEiLgbTVhwC
2+KJdqQtVn0LpJ79m67DwIWpby3ZUpuUtQHjeoU5Z5W1wDlfJm4JW11vN8/3F50Zv7tkVX3m3NJu
822i1Lb3AppZmMYfoDoG62/5sLhOzNVQHSKnR8AH+f5DMSoDPF1HYcV3S5aFBq90HZLoEiHDE63L
UZ7v/4GCSXYgTiWhKHJr7s3pDt3cBjvrCNB49k9QCkwC87KMmj7eGIh7gRBi52J4aNANHktmsWvI
5t40k4bGQOb8bMXlIuv06k9IDizX3pF0FkLIttNExx4c6u7IRiXO7OYbwF2mUOnxwXdLs5IkCjGB
CjPMZgUh/M2LeRatQlAhtDqWn+kO2dafB/wEWVk9A9YZG2GYcaF030Bh3IpFlXAqcGI0Yca7UZDR
h/9gqhF4s+0lF0b/Hk6mn02qIuhA5iLH5GVSkwKQT5Dsu2C0bkKTVL+VHYBPb7/zjthMpUOqT5pu
c2zm/cWpFPae8uaw7dz0eC+pnwDA1L4dCNN88seEznrHjP0aRv3bhtPn62j7nWHRRv6hZOuH3a0Y
Sky2ifxb8c/q8NYZ7m1WxdutlOy96h/QPTpywC11T0d8FO4zp73gcrbIUNsivMV57Zgz0BxKuZ7g
9yApOygIARfUUwdgYY2cLKJtL5ZCQ0idjZ5Psbf4XXGAyKmgEncRNZ38PzLFr7hKJpoRpt/4Ji4J
iy1F4uKnpbta3s84+8scr89YOWKYbfhs2dv1yVAA5mXlDXvLH7gh9FFmGvpq5Wlh8PWDkMSZjxAn
yCytlW3fyA4Is6UzqcC9ZGCdNZUN8dKrpy1InEBv9jafAY6p55V8zKFQyCLAQdAx02EgKvKAVAzT
Uw0Yy2g9GoDEw0MDCQJJ6lAMRQfg1nB7xacXmpq2R/pDyGAKaYZsHjJPlXbv5zKtVtXmO5WUFgLl
C07pG0M0D11di4KzNCh+f2rIWZ46E9jOQyzMMwcFHOeeuXlxfFb9rS/FMmK0wRLuA4GPEVbdBuvj
CbKGa85X2LHVUvArmOGsvBIz9Y1SI5bwse2aJdj8ZW757SXAsb57c7V1fnMlTZPFVKRvDzO5+4Rt
F2Lyd+cVLqFkwIBv+BBlqtqEzhWE6E5VbyVv97qjbia6xpumUicL2ZwKNdnHE23lXfRiHP2lhqg3
P2grC3FDjtIYFFl3yOdSGMY8g+9G1fF6PCzsBa1F45HIykz47iFUb/rsIZSBQcPzv44+N4rF75eJ
3XQtMy20CrxTd0e+ZN9TImRp/qiJ4ZNJtxySS9OG6cyctK/3HrTPImzMTl7uQ0t2GAmh+aDEjH0u
sTp8kqFwojh66nqYM8LfjE+H7Tuf6952jvsMKKEUCJxaKF3iCSyQmyQfpUm4gwEZOcwRQuKYlcGo
it3zAK8LaGDKrjiC2DOXD3st63OSUNV6+FOqnC9q7RbbKRQ5z1B75eie+Xu9NgCAOoMTnLcvBNaC
eER6qFu4LSFBTpPff5aCPN9qAqJvEBqQ4BeHm9sDlc2J9pJrUbbuuBJ3VpkLWkQHtks/lwoodFwv
kx/LyITYeIUgcXF4em3X9WDh0vNHgifcxUxBMkgJ4isteoAHW3hrEzGJKtMsy6DNOgDm022CSb5J
kcExeNhx2zWadba4zKRWW5+IEEkOXPoBAdkYnXnFtKvkjC6k1s1dpin94zFJJ7CFLkGpTCuSlffA
rOQYwKBtfzt+CHCoGSP5KkHAFWT0DZQjCZV/sJSC6BDbmLhfuR/0GGMKT5p8WCxphQp9Dfxajp9X
Wt7PUkUM/mJHn2Su+tvUuEEUCS3mAV203i9WGQneGOPehFpryvWQPg7Sx1/NHFb1aXXL8LA2g3TX
xFn8WppJAgKxFFo3KpTiOViDzVftr8rd6aOUnhEMiN6Lcf+/sjkDmXlWPpAEK5RrRrzRMxkVpvXD
Vw/H0eZP5Vkg9C89AdpCmMIoZsH6ETHICOVmAJhzEyygnxsj88+OdBIx3uRa2Gqh6mBx85nhEYaV
MNm7DucVs15cVgWKyhW2kYBOT4NaFK1EZN2Lc6kcKuhf0OeS+EjWxfs2Ra0g8PfEb4VxWlNKjttk
XrVlGGmA/6EXdRG0aXSJe5XPlqnStQEPO0R+45G9Gp2SbWQF/fnQP/Lb9wz/vBU08tghsS50Mdn2
DB2nMeHAY4XSdHK9/vkYxVlhCWRrj+LnUUmzsnKAUvtWw6kppuznmMUm6ocTt7LorwtV9/NMDcmh
R+6GkexZ10apZkXmWrY84fislnLQfKTsD/CSp4OXLXf23OLUD409tBZQ22q+3vWb0AvWysS6iu88
q5ppICV5VjClMNTq4Wnb7Ixi0ADd4VOyyZaMC4CdWSMlj2IDUhulQfRvjKvsi2zv5PA/zB63LUok
E0WEOqCyIGBFE2QrVyxmJEfJwxp1St8Sr8iRNQsKq7/SC8lQZSNGGIf4WOpPff52mmiaFY8qn8CB
oWV70wPHgBwVCJeykGO3BWjUl/Hoa7VkzeQKMAfqAp1yuUXhDAIp8raytQJi4HD5hz4yrUVz7KzU
5IEsvrFDyF3/vlILte8J2zbe6rEdIQJecKq4YQbznGP52BkBDLzzoxEqifY9zLZr051bA6USmPJ+
0XYDMWoSCjZGJGHvK9Sx2gI25NIpEDbrwg3OlAwv+e8N9lsJDffMNwLAEegITPqI8yIq6tgF0+Hh
3fE82brZ1BF1lLOun1s3xMnmysnPHB3gK1DnOeZ/bX301H1NGjNrosCyPjy7gyumkIEJECqhFREb
664g/wPinOU1ZmFsS0ihaTpfy1HYWdcLsP3tzZgLiX//Rt+qHqlZlgflBpHOrEu7cwbfzhaezEAM
9IEnAuX5/nndI65tAsEmpGdHaCf5yJr2cjzAews0V3ul9H4iMZKbpX1h8x2IVH0Ys/NypLJpiYy7
f+wfrxfCOKiaJudLq4JdOEb1CvLey3Z2PNtQmfMJ3sUayHcnWWNF6ypqEHm2s73gmZ83rVxoVjLI
4otcgZs1ZJREEs0glrJ2uYSrEmETml2UXnCVYL9qvr3STBHoeWR8RgxFBIF21XMg9URjtDMZThZ9
iw88N3kkBQSfNm8Y8VHsBoxTTD3wuIoWTAdY1yvWfRvibgLryETn8WirvwTDdGswnw4W+w4eTvoP
gT4Ej/vyXe680TWdOJgz7+gs8Ec46WQzi59ry5QfXzmrC78tMHaO/XeT/LPTPvXHYu6WNzHGeFAG
ZG5vWmr+LcExnAgHWdtMtaCy2qoOVPVTRKei1wMCFo/tYeCxEd6IlFWSAcS25TVmrM2pAb+CAQ8d
cv8EPGozqPk+8RW0ECy2I/WssIXIMtCC9lU/m/jkHcAHKJNBLD8UobE3QCezTAjTtWdGhP8ShDnv
r8+xtEdaVTDw9E6QHpOXedDC5R+PdJdQSuRNiMAnA1vgt5NC/Uc5Bbl0W8OvSfIMSfQwe148bpKg
j7KCUE6mrs2A6xlUPvLP+RO467i5FQpMNIt/j/13wCOGcYxqG9cPTu4wolbJIgtoMxaYV/a5+FyI
UpO+PxnpRzmY5yg6iKqWWAP1lDY7OXc6JIvyRwuNQAjfUiTsmaWTYU3RQ/KXFepU+lcGXWhiklvD
MEhcCdst9Eh94KLez1uiVXzP8RAZiRRsGlqirdGBIEQl9fqs9ukDI06GIwQpuAcd/l1ACWkj5U4z
gctdYMDpx8WttoPDOqaFGQDnK0yYs0ce7zWrZUChGxyFAwbukDOOi9yv2T1iyaF6iBmWtCJS+8gb
HFYTpLnyRa/eYcQ/2iEsJ5xIP+idbh/HrxZhXACD9o6O1cuGuBBVP39ie2Hr2vE2Jjx/v2ydIhpU
s8rwKrstI47p2cWchUvlJ/iwrniSUuCKMhAch68zOS84L6nDT/N60sX79085hjkP8F7jonUiooSb
A+Vpk7lIYBi3E8+GbgpMMqw4MbBs0hSPPuVezrvfghd7Pj/P22u3CxFqV+2nkLW5PgJLzjWoCIzD
77vWtvfNy6xs+W0G8Hs+73nGW9LuZJvXCc94jjGnSYT/KM1hhYvNBEs+EeySe3rmu3s+pH3wui44
Ro1y5DK03vjv0+AFp/sVZkn27RCwIhdj+DPYC2fKLgSDfZEMi4/oxI34GNLLCaVgYZMunTXSBikP
/rOC5jhLU+LA8fOzKBv0v4fNsElYU9hSFt9rRBuGtc36VAnYurMQvOOKiC4x8HMV6mqx+DQlprjp
zFeb+Wbbw+QidrV6dWjRxL7GsooWCD+kqXaWZqpNvm8rdUfqdSRXGZCgXn+/K+nQ6uwH366Bwk9y
jae5XYH5N+LXbj+SZQvkg81/7HG3NKjyCcRzyJutrvFz9jqr4jU2vJzYPpzT40QNJtWiyZNIgZZA
acsrBdPhgXzkYRUSM4mQGEyvXhcep/uVNKJZYO1t0zp20DLi4XtBYHGj2uF2h/BSCYQsyO/7xsp9
wLxOZHr9/JSlalWxH+sfsz6VJt4bF1mnWU+UbDt4Hc5XjNDZTKtQoWLeGXOBYI/A36VWwT/T/HeP
ptCPy9+S8zknNA0y16o098V5zMp9kv/XhcB4AlWEvjdunRnJIXn10zv/Yj3tKOCV358UfN0jMG3I
VvP7X5nGCimgVF969i9pz1eu/C61w7dLiqM0iCdhvS0OkE7GS2V982ogkGr5j64cdD9xQ7MyACUq
8YVkNCVkOTJsPxnwSvqKF0a4zCkXx+kNchJnipmazpGKfV4kdtn9X7rVSMOzdzCVhU9D91kRYHn9
0Qr6T3J/VKAD1sTHAzX3w3UmWkbZe+kSmxw4FcFzlAySpSUDpXHeA0hZFRUo2OU2ezHzVrjH9yhw
4TBEAxOqv1FEQi7s8ap4AdjleeU+vI0hlltqn9IbZItHh7ma/54Isb7Cqj7I1+DQo9aYVUUgHdvB
ZNMVClrbAMVQje/AIY7iwK6sWfLa/wzue/ttiYnyxOXB0Mk3C4ECR6TkWxLfbp9p6869w+c0ZJ6G
ZJ7FuEka4OfCMlF7SaWeG3K+TnT18x8rGdL35ocov5l6qRjroTmIa3ANcsAuwQC3+A7FbviWQGCI
g2hKwoexyLfTkGxshhdrYLiKCQCjkQBy9T/95HOvvcb2tkdiZZoXqkA+u+gSiXcJcjTuWHs2f4WD
IRG7BZNdPf7se0qU0C+Azq3iJYSupLmhnsH8bo7hWjuRkN1EL6FtM6SGZ1w72BDp53k1J+92AULK
SexBC2mxubE3G5B8SlcbMync4YW+8U7EaVi6j5maMR88EpkYo9qbhv4LcedUFN8BHvYMAjEMENc7
wVFN7PyIP62FPfCBeXqDFCCeLDYWBmELVMCGJazlBW5iktX6xgs4KZ7b5lI2GtSkDLvzzvpRp/Cb
LgEQHn2ASP7vb/Ssv6dnYl0RbiXpxG2cCLIfxsssj3TevZ2OcCez85KdZlbc7JoaLl7+W+si6cXl
bnfur22f9swYzwOeg6MOqXgVWY1ydXyuH0mCBql/rYMXdyLQUk/xepXEKtn+vvsWKdpIKm+RB3hW
AZyrtNiwn0otjQKNK33GXumkGWH5y6uQg9rXTYPIwf4AS2jMCPamfPSv/2OKTc5pQIz4l3i3FK7+
/N9syzX2E5XOSsZGnqsmI7bNC8Gvk9E3GfpzB1dOoG9F1Xocii10lB5ADmLE6+0sY+/vXzLDJSOe
bCMphI4pwfQIYfvUys+XWtiLQSVDxN/5uw30TeHGyQj+4QgNKzGqRxEjXMQJBkNjbcynZbcSKYq8
8P7l2mMUv1qXwd1jCd6CzSrqDrHt5qcH+ZYbt8QCJyxddgbAOgfrtNnb0+WCCKBtNCUmrTAa+XiK
8ZTjR6wPH/rhRfcU6ww4wStpkej1+ws1u5rhAv9YVFw5TICosdRDJC5SndE/F14biEQkcd8F17vq
hxqju2x9fEZSiVMF6ybcUGCMK1+u3ssdRQFZAowq8o8MQrm7o8c+HmFXmDsPA5AiyTnvKAQQZigc
C12mvF3qLiKxGAV1cbOvtTO/8yk0LAgn4jA84Ktf0CwrojMSQFaPF77Dc6QyAyadhs2iM2ZcezpO
DWKpFKpAtcl43rq8YSL2jfQSfo+nIHWQ6v/k9+75rXtVPs4I3y6TolsvBdq66BXfDbAELWCOC8PA
T7FCVp7B1/0TEgLALb3dyVdqlz3ZnyjVVl5Zpxuoe7oaNsrRFQKihhZqbOXMtkrEzQFXdkNESekL
oTc6bSXVa786IV4eOW7n6u90+yHXQ6vjkZn3Ni62Dzh1M+Wgb6ODV/tCxcX7/jOFopo8NU6PFbQJ
hlZoxu37y4pMrdDprCGf0097FlNcVjtoHQyJ+P4OkPccOt1q/g+UsezE4WaCiolhjzJJhPvG0rqy
UYpaflL2r1RS+Pu1q+xqtHuFHEwS786oUuOfn8R6SsO4AhGcTptEY2sLSarm67n7JMSiaEeE+iU2
vdNlv/tomb57gRDSRYmAmbFIzOMNDZDHDN8WrG4BwlpzWvNEVMSAjvBBbJfbVstXSJohrHFLfuNt
S7fc1T/cp5dNzSX9IcqFjiIhkz9OiMbvQyqfHlmBSvHt6FKfES2YQKYFCLAlcqf52xMBDD1+wF9o
fsdX3RLvtCrocs66mqRqxr3OlKsPWKiuMlG9iyrHoupkakNnES44ZuKzVv3ilw1cmt3bjDqXlczr
uEbBOScaSa9QNPJLDsJbY9j23BhqcWmFXCTfEI+DGInGO3A1YRY1x7YCgQjNX8HeVfmhrflKyjJo
IyAIbi6d/YpHysqAp4QkHdta8/Q87/vzSjKbp/q/zH1PhCtv5UCd119XCSQ4+S1MlYBRGh2L7Oay
FA5VY7Z8pgvwojHdKSd1SVzmUBnhQcQxyos1TYsfcA84RZk1Abb2QXMhIzQnbuKF8mZXJsWmD1al
796xUoXuvzbZCoLMerTY9mHQA7r5pvZYjPivvEUiotTVO48nuFtTols6pAD++hBdjRnepsdhh7+r
w0vVOzt4ABltwdoYgbMYBcOGQHiC51Kyj3YflyHb1MAocD38x5kSYrGxpDEcsf5Y6DVJffgr6kW5
gRd4TNqNbMlU+4a51mF7NukjmJPI4Ds3vquxY8ZsPs26Dh1iShevW0ZNGvXmgW4+WImKGM4/lzdR
1ebWA8pcdh0FfTOAz77mCrPY9E29EOKuM278APdkZRdQiDtomis+tDgqmi7Q+JA4gsTGoxfOAyXL
tEFJoZ768W48q9H0K88YBEHY7U5mh/rs5MaADSjlHxZFouxzbYK1UivNdcCm5PJ7lmPWVeibq4gu
aXp2qJS5G2c87nu5wkHqW6jXZgvvrXfBy2Q4eFFql+S+HacdV+T4NLeGYPDoWiGnI48LPPssim4c
orx2GftqYVUrNnSscjZXSK8bD4KnkYg5btIucxNKPhaJaaGon8L5FkeiuROxLnwCRipkaZZmdunZ
XJ24KyLsNTcuPvhggI+m6B3u3rIScocSDbvp0udv1lG5aij1RGwIaq6Jj0aNmxbE32vx+wsrulwV
TxFsqPbBWB8AOK57t+RYcEMawa/AGMvU6xxWyz5HKPAlucXd+YbFyozY/I+muSNcrdrl3JWnyoVi
O0s007bO6wP4XdaXlUxx8/A2BDjAUYnwNnX9lSz9dR8RXHUtaaOidjk1YIGF8bsB2M7IVpT44aaD
YQBTpR3mjQRFouQ9NVuoZyOWz/P1QNbIYJAee4p1EqeyMWnxQzAMHjxCOLBHz5p58YEP0mHB4HEh
1i0XPPAzefjFzEHRbkrTTv/X3b9PWC/4p5xzPL4kXSJBqMcQ7coPeAytX/c4blj2Mbs/oUykRqz+
hPC/pdRra7z8Vc2en1ydhxe4w5aj/gDlduY1+pcA3XayvSxJYxi3q1W52k7PhEFOXpQiKLIUlhLZ
wLBYCdYq+Z+qYmAT9iXN2HHREL2G2PJiDxhKGx0p6lpYuIzsW9RwfN9nZRoYjOwFXoz/0zk78r90
/t23psK2c61ixUUYNvp6sDSbGsHbnTz61DNKI++Q36Zuwd3IU8xD+siicrQOstt9nSSkAVSVkoJj
Qek6jCNI6un7hDykhTm+7nOab5CSqmZxd7ZexWMp+6JYku2LR+2bQ7nHofIMyX3G+UViEHvhCglg
VT5kmVh93eDpbaZ/2SUCAFqVJKPxYuxnGIR+q71Zeh9LmMggIR/MzLmyi71XYue5oexQg+/kzaYX
tpNnOrgeFJnNHG0xUWN3ChWBKYIBzIcSxTXgAb7LPe/a0L2EqXzuskb+gYPdnbGTPGYsolDhyN2b
WS2dqG/3LRML42sNlaUlhO66ETASA5EOyY6TtlDOFXAb/W9pZ2301wB4oacdHYk537PX5JiU6n4d
+WRWbFzG89gyhk8jkWX+pJQEJf/5MJr8NkgEMaMEc21bfLJj4E5KCTWFwE7nEa6ifjQauAaXiHh+
5lJG95R2ggdNfMjaiBMC35ayMiBGW1KMYy6lefvPl3txoYu/W6f+EdySpJZectOfJvXIwm0AY6Y7
MO+13ZEC+V0kY641wYlW1DgX9t6kr0eJCigHR4NiX/D7BGtosyx/rLg2SKY+eHzYUpTD4Lm4e14Y
oipGkW6Z2Qlqr3gBtx3BFOVvNSHx0jv5uu056CUBK99cgEVhJVmqimaGj4w6YM7XYYn2TdRVWRnu
VqCJnswi4/vLv46H1cZqtziSSn5a7tuIl+n69rlITXGBXjQaDCty1A085hTTX7QOU899gU/0IevE
6YQWtEW6G2Xx4SEIa9Kd8YlsEL5SA0IyzezXDuHWEZcMylHthtZwFRYS2+nxzBpCpkEbE/DoEb+x
R6Ch6lsRGQp+dqqgxf7odbGdW7C/nStzMT5fpKGCpHHGpam7i9h49qTE6lAALh8OIK/gcQTkS0RQ
ccDEyYG4Cmq8RZAC1sNxPLltpg8CIgdtW4PUr6+VRmqeLEup/Jg4J2m+KmeDSG8HhVvgi3ltl/HE
z4mILjP+0YjckkVq5DslB6OJmru40xMwbG7DFk9diX3DfU0DKfw80qFgakp3GPp/EnXgzBFaTQy7
pk3tzmUFP/cDD5h7Srv8Q8D7IsyQ94ldyznXzTfFw9SIx39paIiZcfPK0o+GN+RIJZWomIftzcXo
kooD6mRoG18u/9LA6yHyoHHLU7uLN/BBkl1URxEEXnINWEVXSoR9K1o7CcFTe7+rlLBJfr/ilqE9
bwAH3Brih1oUug7jp1+MZuUl1znFvbAxEdo6o+jsg5Gqyz6JRZ6MzVmJjzPmobJfurUiFDsXuQym
3C/FiJ5vtjHwOPMqWiH+2hmpiCnKjrKbw+IovBAPxCnXXz1lCl8d9O/mPIO46564fCBXRiTEskLA
K7amY6iAFQkUaNO0fnTlEPrbc/jl7rGHBkyvm+fywC1VNzW6P5ZoHPvRASeFL3M/V5xSLkqtGTPa
4s6o6VRd2Kbajt/Jui9WEwn6IqXQPGp+TAtqQ8jus34Nk6+ynuIZoq/kkc/cVE6UVGCRIOIC/MX5
E1BiC0G4mAHIj/Gm8H4bd+zsjV16Uofs7hIJcbz8RnsBd2HQtv+pMzP7EteApMlnqOO0sazSklGA
5L0Lcfo+MrRyyonDyMYWKzhotAcPjfLY20VILgCLlH+yXUMgSqwQ8xUgrdlWQS68FzcrX5GwYHJD
AcCUbUU3xHOA2iIgNq9G6S9XVcSKxGKqVbj8V8pKTVlI6mOyduXJ8ZOPw3f8pTq/nHf/SD/vjKK/
w6hgTKGVxm7eM/+6lmtDlsu2FXXWQWN8ITyDlpYzSMpDYQ3HsaT3ihcbFBZK0T0NP0h9NDH6jOkb
/rLAS0wIYhKR8fSJHJcLzUi3CBIDlmrax9sVW81kEj2qqvYmTQQ26VyGBxtJ5tjNraJLv/fNxH7g
QBHjHeJ2D3jPP0kqFKjmQm5F9mmCO9IT8rMzduFVzjE1nAxjG8gP0FFHn1syM+4C5i+4NmSurbmQ
w55sVWIH+vizx5ufI7AjZw47FNkfwy4xXoM0JNs5bD5TFpIJJr0gc+WBn/ChcPlEqb2AoFHKB42k
AmS1atTSbD5zodSutIk2kTrUKQpOjsHVut59OQLDg6doqCfOD2A9cJO9twksQWEq9AOTvKU+EWSy
mtCEQ5qfbfaKT7s7dduaMzzPnJQSRvtC2h0nKWuLYgRGYykY6HaBlj2BsCdtgdshK2H7q3Sch5f7
5gOjKc8IDVeve6PfzAuq68lKNgnpOnBcH3Wc+6zmAK8ufiHo0HSp7OXcNRHHpXo3MG7EnAF+i1dz
HllJp26QK0i+Hsgre/3FIYZaTjXUo5E//1svf79YrZ+JxFo7VqNb9tUaTYZQrRYXBbekzhqN6qkl
fe72t8fJOXObJ5cY29FzAtGF1rBDbjq/4wNRXxXmFK1DFzE6Za5cRfQcPgeBMDaL0YzyxfTBJ+WZ
KjV0ZmSdYI3dlwiJa2twcktriZRbmvsW48SYrHrYBleJfUvrSQq8Ba1o5yP4Sbp06wHi2lm0jbaJ
6UJilp6zKjP9aoyPT4tQiI7FcGDUWPa3Tjbd0RSe1A8XbFTGapzkjaALH2mNDRwOyFbdiDQXq0ZH
UvPmzlbjGXlTiSVf4gwNstc+joAKTd/rhCbtTSVXrk1qdLWKFHhewzFX5zNwyl+m8VQLD2DPe5YM
t0MUlSRsca1DNHTihXEQraZDgz5XXgIVVIG0QVnAUxN7iB83mA50PTjf8oP9G+V5sqQ6WCAwESxo
4/AKSAvXOH9mqB2o3SxXEZE5rPxG9m5zmqw+QzqXP+hcZap9VzFBVQieCi7qlR8yHMU/ov0+aFOz
vlQ3D9nlK8sWFk2VwzkbfQW/i+juJXbiUj6V8XPjOK3NAr+SDLSWuL90RuTqKXw3Lzk2JwXY08q7
1FZLXlnk6jdccIAKaX//9/gH/T9wSRZt9extME8Rrd/7w/LjqkjLjrhbFp2ApxzhMMpY0aLtwaQd
SqvGdApg+/NziuH5AoW0xXGKssaf07/p74Wjt9x0OHWyZsFWd8EaNpxRFmWxd6W//3KVXiBnMZvS
XZjJvk0LRJtjphwTS/mkbWtdLUuVYyyFZsNj4tS7MX6aM0rohWirmchuQtF3tutJDtAC9gN8vCfS
0CjFG1mIDE9KvPFU8SoXWJbFPcU0GhDhdI1C/ofiPgavayeDiEiLf1/XW0Cfa2RZIIzSIH74w238
m8I+xTWZD0gGQLZGuh8Fqx/DL5rs7+yGKxvh3LgSYs3B4JX++ui+4QN5KtJXl6Fh71I02B0ba0K0
+flnr9pJoceP+wAfYVFbtBGOugguFn6I8nwODNq8n+Pb0gDn852kOYm3j4yGAdPMFvwKHzsr6PU4
UX05c9ta8yvelmUs1bOHGbP2P31xcYkZwA3aVGt7vmO8we6GaCxUv/obKWGuAkMc0mX9jAuvFjfb
hyXr83uu2xaR6cG+PXasp8bfqV9QmFTowWD8Pao5uT+U2Gwcyu+AnvJ0yoCJprJpGgz23tcvb+F0
Ca9B2ySc/x0fMPLx4XBpyx9ukZuGWiS1e884ZobXvvPpGtO+k+Q03Bz0NIl66cdBJvEhLPYaMHIk
JjWl0S+HjtD8MrAwc9HW+eCmVPZ7eLuxE1r/AwpVEIM29gYPWnBHJQDXBD3yCdJwmqTAST52q500
9XVmEljpg+RECm7Yr2p4LP2zYCihQFqO0iN1njVOjjyiYmZPtMFptIqIMMyGnmNvUf4KElp4lNlW
2aAdyD4HJ6hOfJohBzStqyXaDIt8velbesdJSf15mCJe+HlG/53xJRbtpOOuqYCP4mK48Fa6KJsp
JXeSlT119vkE8CWT9qIGqV33yUdL+WxMByZa32dYKfscwF60AcWkwLRMFcHgvzO5kNAF1nhHdzYr
FdZA7UtKP6IDQ/tVq3+AeKbvJyspmsLoIRAnAmfnk8wjIRs4YBi9uXK3+9dkaraM7unpvlo4BaST
B41j9x4BEPDcviSHEQiYcn7WpCjWPePjZobIgZZktA64fSyvOSKXrZj2zP3lkYnjBZjPLsKphcA4
+pf/eYb/ent5YuI3ipuN0XkhXTm0snBgbjBdlK4jljR0v2BkvkT5UFTYTZkccJCEQJwnx94tXZvT
TmRRR1k34af1xqDNqYHlbl0oBIgathRLEB5crIqKFDJLVe1urpf3gj5EK7TTOyAp/OIUiAqlJn9E
sFFXv5fCCMbpBvtGXpTYwiE2lJZJjQaRyZxXzlFu+sqYEEAiC+3rL34pt7KjZQLRcb4hl8ZMXGfK
3Zggjh/kkkK7tnZSm/VWurpYcqaQP/MAXtGrQ2QoZL6MIKqwZ7Hb2GQgWYmTMmi1kWbioS0d8iLX
Pz0tkixBhZb9RWVjmLRB8hYo1uSSgm3hPZMfUIAupaaR84qcNaIpws8k9P4DSCbZpoNAfkGsZjUH
ETgrrBuE0xEB+2CvBQ06TSS9EuPE1tF41DbNlXnagDsm7gfucLP3YbOgs3K14NoiIx0G7QMq3rNr
ydgV4l8YYendIAat5HSb4Th1BZsTx6pE5XIRfVtuG8uBckY8C45QpNc2ram7rKjkP8MsllwmRjzL
rJOk2blPgKZVpCT1KJ541gpdw9nkRxCReU3GOaR7Ae4Vq9cFZP1zz3R8/EG3mRhPTxGUEgGjUHG6
Nf7fVjzb1y9Nx3rgIwdA8Q1DT5mA05ECqHgWRTpVBU4kPbXt/Sogd+8joztjVBniqbwuccJhEy0s
1NFuVdZ98CLcDW+IaELl/t+mEN9g2ZpJH6Qxf1VWMh1LjNep+yprfhnCR9bFxhq8tRvjmrhZXW0T
9cFPfzarmfbmsseORWb/h/WquNQaDQf8fSVVjmc4kZn1OPiusj+wdEwlLPSFH5mVZFXEfK5oWcRS
PN6CqCQYRylz4QgIPQrTsSGhDljEeapgBSkk29b6szkP/NUu/mstXUpKBB2UKf31CJ2i83NXpfDe
TcjLmylFX3dFWGcumd+cD8ab2wHJxbu/qEsQJ4xqelEvPXobnHXuzgrD4Zq9SQPMnXNVLV2D0MfT
RpEZQqQxXfvE3BXawE6Xk78pTcOgNtDTUuitBU9MqmgKY3ypmNiV9AKhkJ3r6P9WGP+qghJ67eHh
qJLpsRohn1PCkFr95OfHx9w0ZyLFs30OPy6F2xUEGMfOncq59YovAUOGA6XJmshdiz0BuSrS7P2T
iFNEZIJDFHEH/PoBTGcJX+IwLEsGC6gDZjWtdJhKemJK19R/GPsvNe1ummp8p75W6FNfHPp6mwSv
v4Gf5wmEWan7zn14eRiiBiu9+WcQkdyArGOtLdiLBeE7jjStLDi5M7SQ9+zIvij2doQCGeArM2b7
Ucgq2ZyrVShTK2f8pN1IspJ1pFDYtRn5aWqGaogJEv4YQvV+V6kv2R6vS8PEZ4RxH5op6p4e449M
nCDpWXc40gdeEWVYcr10XMtf7ZwMW+xxq+SbE8oU6SDb99R481m9O94c4JzjT4FYwEzDM2TwLuy/
+uuHyrCn7xZDbGOJW36gX7p3DjdTEx6y/Yw5r0CE7IOO7168WcKgqO+l/RV0LLlBACQbWzQ2ZdoV
ZwXJwvGOFZ+EYasNCfs0sJX/DXe3bbz8J6mww3D0bj/iSiqyacqYFHzYr4ck16x9bxPjCiSudkWw
ESeLp2h9jHnyhILD8r8uyQZG3yhK+eECj9O3UnztkUXYjCkaxLIjmObNBWV+dfKyrrXTxO5pg2XJ
cNAdxVFwRQlStrM3Ic6LmE39AnrN+/dpqAknQUNnnKsYQAlU
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
jUspyP0iAzXCKRkWWALogs7DK0stlsk8Ac9AtlcQkNLb+v4KJXyzKMaA1G3HKNGySfJikCFIiQGN
72J2MmtuHQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cKqUYaFMNmCnFie+T9Bg/PWl0G/iI0Wwvxi8yg1uvhU+lULQwvsZobF3b5H3RVvcM1TvVo0mPQ6k
kvfjHChtR9Rm1NpzK/TRK2cpT/+XraxaAt13AHt4v2Li7Q1TiFtsxvE6WBJbw8xzFPgX5R8zoI9Z
xQThHyQ9Y0HDSp1JiVY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rFOHHUOUrlJWwbymLPd0dCS2AYpSybSEh5ZJJbT2A45w3gZSOvWrHDhtyqbVqlsstgmvEppRS7Od
QNC5LyNk3kmW1uaE7GY2uSy02V9O8r5GVpsXmVkckbPU6l3hNdHiq87O/M3FndWS3dRZKC2A9DNv
bxz63dYttgfvXc5MPhWWemkmYn4ub4EIx/qAGLM9aFdqsmVcpqD+z3B2/7FaJ04Qz60yVohM/5tS
jIFb71LWEqo1l7vk1zCjSPSV0BZUoqJCLSUriAztHm8yRLgBWaPhdvKrVL2jTnL8VzXHno7XlT2u
8DJTujTqNn3NgU8XdwkEfXWwJloZpkBe/g4FYw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
UXdq/o460lUpiPxpmyXCPPGC8od551Yv5DkCjILx/FsUVVTBP4kjFbMPaO60DdqvjuuG4tbMEfjp
2/SkkKnaMW8T2/bbQ8ucMuk5+tE7e8o3ToGwREI/EcKPPr+MdcsfhulzsMujxgkbDbEzoyjXfX50
GxjOvKXRGfrs9Ld82oo=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qemEWucBj3cySwkGtLMneG+WUTUsSnlBhS2UqRJnnbzkZPsIe5912fGNcd+Nuti2S0HrMJucuzBg
zebkZVhwJr98XAXk9E/oT3Nikt/5/G48yTzIJ1KWyz7lHLQAMY5r9Ue3kKojXrs4FG3eiB8y3tqJ
6m+4D0meMUujO/nNAXC3tHlCuRO8ceR9RAOCygQ2wythHpck6/MLVuFD+G6ruOGnDicsOf9eZMCt
HHOdeHmjhn4k/2RRwCGfdChmxzvczso/a5DXM4ixnJQJqy0OGo0toyQcqZBnI3h+wvQYrg94uDIy
dSHACaAVhozF4EfVFXpDLBYFmP1PxyStVPkjEg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 41760)
`protect data_block
Kf9ZRzDZT6viViR4dEheu/wX8omfwPjaHPglDOTgrX0IjhnSMMLFR+RpZ2NpzSI/d9iR/Zv85gK6
ItIIhUnEZxRYx8CeZVm3cjr8eGLJ+smUM0B5ZSY6GapxuPzJSpfEGvEtVhN7MNCVC85Sv3HOq6i1
3ypkZdwwfYzkLyb2MfOBlXR1KBnh4IqlQqVnPwzSIZmoJVQ+rPTidlJ7BvNMWJ4n6CHaQUUXQvyc
LmD43brsfpcNp9XSAndIjOzp7M7qG+AvNr2No7CNwJRfy0vEdvCxN44G9YowETIPYvGm6liDcqSX
dGEVJOG3w3V0DOxwGOpbKN9Mm4yJe6XDHbWWFgLuoqiwNRx7U67ErgZ/1OCPSqw3HDRNtW1yF+Ys
PzIA8IprXSKW/2frACS7vwkxmh+hkvV7Q3isu3Hhl95OeQJAQM1tVZZBw++iyvexg0ObDVxX7nbU
ywOdKAa4IxXk29e54bguzD52E66i9wHAwaD4Eln9ALgsEgicKvTT/RIoFygMAMeLRehykpK8mDJJ
9qidCrLWO2zqFZkP9SA70GbCptMO5el7AMIlggHOpuCcBO1R/tuNNxUKTsReieG0XKwsTGx1hi3c
sKfat9F6fn2p2VTv2E4m1dBPHq23v2z0nrm5kS8tU4PMMlKCaa0RaL5urbO0+pIGmoMlo9Znt17f
Jef6rn2YfMIeENutlYJdijesXgyfkgaCTZEOqxjS2nqFJ0I1sqbsyLNCj6Agk2EXpEzMsYptH+qZ
VIDTM7yEfjAQHmQTMmyQa/uTg0xtDiC72OoJC5Jer/FZXmI3sic9tlV/wQMGI2yI+OYNtSAT2u6h
Wex4MECHCgkfQjNpn8kWipImxBULHHqgG3S5v8i73Evg/zXFDDPXPNKMWBhs5a0drFs6sUrRefzS
HAjl78O7sS7y9KeV6tFEoK87kQhLkphBr959+0aMcb2SPZug+ztW1JYp2w+fw1CM/bVyezQVsGjA
Z0EGf9zpnp3xW2Y2l1+3PRsYpTKdD/xW4IjpTf1/0vJrgJ66KfsmWtEgFi1qHGSTW2f1iyEwTMKL
KnWplQzewgL/fcZb+zrfjiZ/FH/YVFKMroZKwY5dG2NpG80nCTUIVEdIu9qE4Hh2ZWUDo8F7F57z
dNl2RhsvJMTieypsbHKy9bA6h+cOMVpy58B9GA4MC0TTaL2BO6B8xD5q+HwziJEoYpjEMvLZMpVg
pgByHopr7TKwuSxcGwPUttA4PGLnzS3E8SLlX7xttCmEMqrym6ydIQpSe0CWcuKt9rJl8TT5s93L
jA8sf9xYhBNHJu84jk11Dqqjd2I+oQaAiV3o6gkCYEDogcS23VwZ8rEXq7Roo5TXoXAcjBrKFZUN
UDlyEuP7xalfKRJLJ2liWRzXCwsaNOkeZCAz9qCEZjn6cJHCAtM6nihRUyDuylxy/w/Epbzi082k
G1m7QohnMJ4yOhKf+xkPHP+7lXiJ3dkIJPYrRIh8EpJf5UDhnxhw0vR4kai2L0qsRHzax+rWf6Tg
p7a6lNhkP5rBTWzOBnaYB50J34FePZ4ky5zPfx/4lyBmWLUxyXwpsOu/jF/Dc9X/qks9xz1S3JOI
6RTO/KQvRiQjNC/hFoVNsonuoX9JZ/PyB3ae9TU2X6SRIIiEF2IK0MPcQmuC/Ch7SVgHoeJ2ij6L
z0Ws3rLwz3mQXTjBnwSwgkrULKEIyjD0qrrTCtu9dKvltm48SfSJKcgGCaug0HaWr3F/hM1EH1Da
MfA80xmpm2iZYd+yDSFyf0BBrXbRWV0nU95TR0GytV2y84pTAVOj5G2qfiZIWdOfPnjm2Ei7Emt+
QtZB1RvGnosiGh78aG840TkXJ3Dx2hynYaGSE+4jrjO78VGXuN0QkfpP2kk03TQ/k2MhbgxVfA6b
wYDBxgBisAllhiHFh2imQ2i0Ggzm2BD8f2mxY1uZlS4tifA85KlOwRRF+1FqRPonomPCIetPp3Uf
podYZ6fn2MZvoDkcjD+pq6Z+sySkr3S+JBMN9icPW5LYvHIdCvcnQyGoozvsvzzCwthzkvoDrxBT
JuNCsTI1ZySOJTY8JM1hPyj0vXexG79+44pduYsdFLk6K6ujepihcSC3PHQdcq+J1RNPI+PAYI5u
hQb8qdzWL58FRYxlIfhMq61QXsV8T8ayT2iQzvz0cAR4HO+CJp+BILtXL9Pg12kRQMNGYhPvzsI6
tve/NlYFaSzoy37IOmQhQp7s39MQMv++w4M28t4M0eqwP7zW2Xgvij2uHAMWmGj3Agq3iQt+Q3PB
ZvbAvpxbQ7+GLXy4Ow92PCpWj6AgKrz0QN1rKH8bFwKtQr8ExE39DQV3etUn8b1Mq+XU1lOCZsBE
kuGclbjjqlkB+yw5xHK1Xk2kkuH3FINAlDmLDY02PZI7cVGBHxGe+uUJxqIuaHz7eWDzO7q153t/
vDfaWp2BT+ddUAboNCTRl+s8wXEGKknUrnCermH06ne4iWFaczgOHGq6OMV1l2ekuhmFjsnzHY4v
oXJ1G0RnPTbTuHhSyftB7B0IB4gybRx4ZFOY+21gfCjbhFAXA93PFLIX/ie+AcY/O47sYjYTSlnK
eK3Yw0MUGprWwxxlG0CxlMHubzIIbskXfAElsevXZsI/yaNB16J1UaKYjXUyOJVRvAgq4CulOfZR
ACm3TERU44iRol3ZWX1m6uWSufWNHjXeLO/LZeU3KsQ0v4GTGkADupBwTNF2suIkBpJAPq7YDigj
uQuQiRrhQz/H8ErtfBXXJlS6b1rxQVcIYPjPmq6ZBC4IdffV+mu0lLjAnYHAUnuBWMUHLrjLcbwV
36PnBtkORt+jufB+ppQftOyAvTMKEb82sY8HneUOITs7tx9NjqJa5P1h9lVR/z5YVaiCi0XoVfHY
FKq4qz6o/eoCwb8WPBwNtfOVRi4tNqNuGVCtNlbkbLMzDymP/Eho+aUoumrrfhCzfHg+jLbORDL3
ev/xcmD2/31c3cGSBXjpNP6lA3xHPocAFuR0tELAcUFJPwdebiK/VOLRLkNRh2l0jU267ksu39xk
jyaDXjMtTqQ+02Bk28jOKWVKYwEdonbSclOOGQxNO6skIafDZMyJFGuJzU2q2vhUtN/T98P+Ljj7
Oh38r9qxs7yqEj4kCh4b11TruqNeKjma0k1QKeGYIQiloqYSfwqbptIyCmxoXkCK55d0EyJuo5X8
Cicu+jlL9wIyzrgmP8H3zncK5VVxM+drDiZWqDfj6+q5O9JzjsShEXt7n+yjT5dH8sSgMUg08lwi
32oubJfwLbIa8jdU4RxEQn9SWqINcDI7C8TnbcOqo1fKRbEEpo80yAFdJ5kq/VP3QlFH0ZUz3e67
SNCo1+8bFLvu8Wr1XPbUZxiyrZnEDaHBq6VeJS8wpjuI4VAgwxPUPxkVZnNSbL57wKZJww8OAsuw
r6cPPSQpMpqcRPMQCBB8mes5tH768r1Vap/xouh6dmIL0wFJjVXBYepQB7OlGU4ICUubYpLcPfep
4A9FhaO6xNA0VYf+NuQxzh8UqkkbB1joCFgdiBwL5m9Kvk6N1BpJe3Y+90ULjAxcZYHgmwPS8m9Y
kAVyLx9iCHuoYPof8OWn/he4vUt2SdWXAVVtka4+33oPuKjH97RCBvXWF29AGjMteTh9ACN6fbjX
JqJ/yWZ0JlXuaW7TNuTKJ1L+5ZtQI8XCWFfSW36dvozNnKu2seq4NCTwdtgzbNhztaigZwudlUxu
kdHkqdrtqRNC/EMJptpH1peqLkRv3/rKyocbUAE8oRw+vCpq+PJ2zkq3ugMLwQty+m2ER50MTeYl
X1t01viw/P/KsCQFvA3QQuSUKFxAQqRXjCRX+i3wdbm3LjSWWEn44b/jGFpdSM1wKUBRiasGYj7i
t4vTuTj1uwdGFKyX7feADu562Ry0/yi82okbQN/lyXwbR5R4PyiEAPTDgdfisZ3vI+wytQWbNxP5
zabOutk8FaT2dTC4q+DEFsPsmX40M/iT3oeojN2IhwDnoi9c95ZALthRuj6uKq4uNoDRJ6TypjM7
fQhJwHCJOfZJpqdvHsZC3x9DRHNwvo0gB9U/X2nmNC3ueWEEexxdV2uK0yZS9J3eeRrS84T5AdV4
lv+c11hKVvNI/ldU5m2CgFBrBrXNjXNQTCw65c3GaYhQK70pJiBcz9fmjxuilsG26h4G42A77PHX
XShRX3ThVKxOvesA6bVuAHoJwCGJGKOwwHcTSWnc9AkLPgA6KgXTv39inL9lE3ermdf0TrKKgaMI
9RAwGc4yOMxFYfRsgVyzWTFqnYcAys8/F8FXjmnwdGvWPtGN5ZnxSMx0hrWb8nbHgXTzzkaSAhsl
pyc9eQGdAcZj6fON+YH+qFSmjyL2VxM5kJ5xlnNWYd2QFCwSg4+KTh7ZkawdDydKiTz8SlBQIMWk
2xcuzNytijRBIZSXAY6Wn2mnsFDSvfAfyEWEzrpx+idt4GX+c3LRiTmx0U2eu6daKU957geTxQ/Z
zgLWhOiC00Qnx6CJ6Hp4KZEcmSqwXXk1PPaCNYCvynMwz+wrg0fJ4cKxH+4NZ5uAxXQBhNEQKnXE
F9FkSOJ77GdNkfWltlrkn70w533GcyWc2eIx4yj2p5Gt8y7lvufQVVYwPJ/1Kq+Iq5kwr7/GJ4Zj
SeK8Bhuu7oCsRGd6P2GB01ynI3eYqF8+A4nyAKYcyWBnrRplHPQHsxlHewM4XlK5kOEaan4HWq63
GXrbrMKoZBysYjiNmJs5pB06SZpaAxilodylEA7nvIgfGYLyy5l+oe68dJE99TjIxcyBaX6/vmFH
DMJ3tFQV3SZ3cR363cZexaRBzM7SnfaFH9Dl7wUy5hALSrfUZ3y+XIjEEcDJVGW5OO3viVOpcgbD
U0ftRH2UpCN69IlocWCQGGzHS7FHnrftR8942VfGgKUgb95YaqpU9Yt8GGFe39bH5wMvcYHR//6z
DMp0cgEfpJtrwl1lWx5KrBQseoqyM5PP/L8fXfAVsWroDzEFpYgNKcT61hmCu8oHItHxlLLnAHfp
dhAefnaxIWz2L3gACi+jt3V1XaWKbhXSmmwCEX870Haa4Qx6LXdIM3RO54l/EZP2NHHyqWubktee
ERooD755VKJilpjtvGBwUzmuiV/htbFNl3MyuTllGPYlNoNlE7UasaNccYeBu3axPq84Hb/dBCDa
kRjD/pi1euYDovNxKKPB/nNrEELZhmm2Je92W7Q3CtzWauK5ig7BzItXJu6Tq9bNtdQ9chQyZF4M
zHOlsISlaWIbl962in7y7fUDvIelPauTHxpa0FvnoSuBzqZLHk/6uF3ryYdbZQ7YUW6rStt19nV5
fX5phrb26+tF/oBlsEqPBgGiACswFpOJUjXwRQ09mSUqUDLImLtN03PEuHPt8e+ftEzkR9ktS4ex
glAaoQueMtRY0ga756NV4ju/ttlBEr9cTsexCcEbyj04bpBfKkqlEkuAcjNjm/7+Xa34SK1G0EIP
oT3P3wzbw7F79a0M0hv9cBes1VMdfZmeLHoacbw+46Ci8Jza+rzEzsVGFDK7B9LEUGPkAOcRd0Hl
L4qrqHtelbg1P688CkLof/cMhqfUw2amcl3KZ9Lc0S0O7tPvNpxBG1oFdO9qmDbjXYwZFycWKLZz
2HA1r86kGqiIRiVP9nIso5keXEQo77tsLLYx0KM0bJAUTmwLiuQUFJkhyA5y0MDNldtn5Ot4qe30
gkZtF13Kh3MIimx7iZRWGRKuRqYJGf9VkTPprMBE/aERI/S+lyLi7E2JBh1wF7o3e5U9bD/ryKFF
vKg66jL7Uv84e/dmeGJSQt+ItA0EfUelz0E/lA7YCsduZyRg1ltCMQr2N1daHctkz1Gx7grHP1iw
PpR00qtBAw5sf2ApTNQy7SmiN7CyqxjGntjxSslesBkn6Tgao19RFvNAfd3OFUWC26D+0X4VQL2r
saW1aG3dkTymrPfQYH+NhsL8MoTZW//P465tjCRO1F1Tm4DqZbiF8W0PXkW7VcnGzHllgNXxClA4
y/OOF24/+abYS3HtMFRrsoaLnTwPHFcW2205S8JwNVhLnbUwh82tHwRUiBWCr0nGGrufO2s8dzda
Y0bXeOIe9gnGeGto/D0BXdIXrhLeXFmJEUHlAcP1lXbcDM/Kq+Ggr13VORPnr8byMWOG12WnJ48C
qgpNAc79iXCzVJSWGo+cx7EmnEV4tWrKeqVUNgX0KXZusGZHmucptEpsb9hEWMjklIHTMBYF72B9
90nrF1114clphYlYfxluztKts0Di7A4KSSFM14jqV7Lg/FR0lIUCrDjnt2Jew9o4w2ZaMbp4ej4N
HBvWhi05fGDFOHqMYkiIiOvI9TNRo0DUrr7nHVzSAr4N1WDD0EEF+6ZCIeGXn1s6yeqYUEnypo6y
ROoLvedTT+rI9NuMgz+JI+uZZx6jdfLvJ+qbPM0VktBkUoCng3X2PzqEkQbmWGZHY/N94PlBjer1
XA1fEjmqVmEF7GFPhRbpCsHKVzvlGyq53VbUitcov5takpHPkCUjVl/dhUo+dtY6dM0UjkLd4YU8
50RSYSZwGzxyYr2fZP7Xnq9tVkdWFQMcZ229LmYAMSoGCQahKxxy9sSHCtop0UKAUFBAOAl0RhOc
qwSGFqT/EmroySXTH9Dwp6FqJFC5LGnGkBqKysnAihpUfhJz5phJ6WYLhNgWomE/na7klcL4w+9r
8YH47VOm6hH7kNzmJ9OG69ip6KRORcPeM3KScuFfE2p48yisYCS4R3OmheWAMqranc9SFA5frgiD
pxUwXW8Uj1GJXELJ0xv/A1WUq+rM9BRxfs59WJ6BFNrA8lNesnU860lO6wZt9K6nYjO/YcFZ0MPD
Ut7CJUHE7JRyoJHu6cdHNPs2KdlHlXQauDWMmXkO3pP1PsDzpngNpDLmJAuYv+Kue1fKwLCIyFvu
PeFihsoDpJQgVWOlg7BiiUA33HCqGQfv0zb58kfGpvYrdHNCncvGtNLpq+Lf84uSPasu7Oz9FiJG
SYcew575LFF30p6T0XleK/TG6EMwyEV7zwczDc2hHlJxfRvTM9XmWJst0YoJBAELMm35wgMAtWqT
Uh17X6em2G3UKV7LN8OjqOjpvshACVAJIFMYiHEp3x8COSYgrNHuXTWcwg5welKCMjdbUG69N5Ev
bKcPgqGEh0KCwMA+Wij5RnumvIfGKKffevKuc+OVCD/IxWINkaO3+YvKeSDkEhgd4rVLjNFmEgAY
8Nr9ChJYYAzyFjMo4MOpb0HX4jxYDQgUukuIR7x8DpvVuZhOrMEYp/PzOtGoHE1bVVabp6znHAwg
MTbAbfW3gatOAZbuJqG0KbRKxyS3SiNz/ok9fw80TAFjwFYagrngfTq202tV/CVzw4xHg8+QzG1P
meKnUP9IwtXTXwn3OEk2tmDQOnwTqoMVEmvr/wgWUjEHH267gpoVcviDQfvWFcVqOL2geeFCpkpk
2FGdW0YC09ASPAVm3kS3rWc4r18eBnA5q9Ku/tzQxSVwudyhf/fElbPMF3kX0KIdTWHdfwjzH+1A
heFf78JiSNuQt308VldVSu8ryLgyE5x4aMw6vxg9r9kj/tx44E3OwpER25jzkUSoFjo65OLGkeV8
WFP+BG/S3DdymvND0iphtRvp3zSHLapy8+Sjrl2EfMhKw4TKEkW2wUn73Yw659eSMGcNx9zvKNkG
9KBQqI8HPeHNViydedrqXHxv4Ly6j7AJmdxl/w2asalnwRDERNJ304ojmseznTw6D4MloDg4lqvT
B28ts/qEZJCnYfNI1Pekl5fuU3werqHWnyfwCU8dKT6b7sEkRnJgoQKHVlkyX9H1UrZvV7SLWP55
jFzeYsHfTZXbKJX7P9fOBbnKXdeVwDC7uJrH+MgcewJoaXAlkUSaqJ4yJFfg47xKcCWHepQE44yc
oT+CpgtTAkZckX5pWcbQ1uP0FXh4x+PMPwf9b/ffQRrkr2irO9oTc+YO1jEXdGqp+3PCcO13fIKx
BUjfE1IOaRsszinqQzyIVvqCohp7XYYgY1i5bJT86kupampH2XgU8yutKDw6CKmIbOQtWraGbstL
1Rg+t9XhQ/uT2N3Uynb7Vpj+VpXLYms2net1IBdblPwG65RYU/n0XmdcBDesl12tH0NSjvXynWyh
E7TvjAohDR04yOej/8/C6lSiYdhd7qvh8cf4YcotIOkGHBLSRry4pYFGLKeSEK4UdgqDMK2ReotR
07LpRWzczJsNdCiGgMnyuTNnDPv8Ly7JaB6nW1HyaNVJrZx2LGGqwgDC/vXMMbOoqSPgO5JVSb0R
YiHRGmAkGNr/rQsOp7sHgX/CN/oBpH/gAQimURlekz8DEu4nz+Tu3Q7zb1ZyZuoiVrWx+GKPW+2A
ezN7teXnmvHfuLAYsQjH9aqAPojfuFpehdufO74Lqiev/oB5S2JyReKx2IvLF0AiNINRWSycfMxM
zjNGLCk4DJA+qVCJC2qZeRblRIQNyMcgvh6qP6SYJykzvFR3q29dATTmWQSbm8YNdeMvcnpr4y4Z
f77anQKfc8ek3B1H6hZUlTsVJhP8iFgRtvSCvcA1W9qbBDQoqK99nEhSDBs68UxMuUA/kRsJcrVH
CACh/OdZhJDWDnahb61e74kH8iZw04wo6AmILXqvFQHrAVmpDR1Zx3kOKJ5YJI4bydYxavwoxq55
9cjV1oXsjTfPmebkkAAvzCF8q50LPmzGd69vnpWjQ4HrZm05S5QP9vVifcdjxfdlD9WfVXSgpIGf
qrpw+OKACQogitSZbvKM2iCxZ3nBhCtb1ZSAWU5dFOfg+OcEhQDidDOl0y5bCnqQF2H2+RR4zvvJ
5WgVVVaD0IIbeV5XW2TjtWOFZekm5rSesA48WPR5145tazsOr5b8MD+h2wcxwGG80OH1DJ+W1o7h
N0aRVZU3I3x7sYtOTl0FqEj9aKm1Jx9ZSbF4p39FXY5xTmGpOkIzbJav1cNUl/BQJFmwDxQ+RMKS
svPp3Y+sBJ09CCi5NH0qieShMLq2aToznmrx0W4NIw0HsP94b7caeWoC6kWHWe9lsaJ3rKfyNWjX
+Uc8H0Asb3x8sxxxyxd506xnxJxN9vV3iSIhQsmI+iJBfHenJFzh8KzQU9Lh9iYcSf/zxeXpPG83
fdK++IOjiIk/Iq4OlNNh+2hvBsmT/13+Q/M9qQbY/d6gnKGSbNjL+++RtH4AZFrc/PYykUzlaCbP
yhheYAxeQNn+g5aD3l0teVC3DgSbZKZC9B6wkuGI7umIQbLbb2nAkZZbLjVHNyVf+r93aggUuX6p
Fb3P5TIYpouh1nmtJ/JmFe+eEwEIp+oiOU+FboDg+9CiXwM8l1wErqQ3YjuXRXza0JqtaW2tZnri
dqrCOlxhdAhLQR+1iLE50NDrpWQz6vKyebOLTqiWMGQNhu7Nt5ZvDwzWU/LIjWEzaW+ZIPA9e2lz
nZM1y1588S1n+3CEk/7mKl95BdocUiLmh9kqsy+oJtsH6WlnOoo/uduIXN3iDPmqeHwN8TRxYHh+
GH8CSIJc94dCxpBhIG6EUkxxqDGRYy8kHh+P7SmuiJYMzmYJlXPPtD10e2uADEajQlykXAwi9mCr
aDzfgYA5cdQ3zA4ADdcKsJ4AIZa2zAHDlAK6e9fSujxyJAHqDmCV21ManYAw8XV9c0ORrzKguNXI
5gYaKEXIji0cq5SAbUFIg8ORIc1ORoRjRKGRdNMQw5JQ2OtY52u76BgX5/U5rn0M8jF6QX57jzS1
K1c7r42Wn9nBU0FvS0f7w7oNCNYJCHOR+CPohYR4l543MDbh+7dmEtcEBdnJRLTo1hOfZM3QouBH
MKRIlrJPIYM2Wd6/Mk6tWa0EFaliAFaq7/1k9XezSTPZ7sO8/koSwuO0+ndtOncEGpCS/S5R3fd4
KYNYDi9eUXQQgvWVdVwBDbt5jGtxU3FV1jzJrzraI4BVO9Rhwq1AAQOYWp9uS47+fEHlPFWud4L/
f7ec6G2h8BfBNzc6yhcUBUoANzQhMe5w5KWutWxS2fzZTom5Y3bl5zYWEh6dDR6f3KTira/QJFti
A9dy/SK3YfEuqYtjMTg20+aNwC67sfWmKxqTHsLRNdNbILuM8Xa68WjUXZIMaDTJwlfxaVVQB9Ye
Lbu8NzcaTyzrk3fbuPKVieXq7RtshBtgiKcwtBBKEmdQK+/p+uMvHPS1sWzCqOaMWRW6eReKI9h8
Iu8qRWgHUtMFHs23hHWl+UPcdx6i3609JBjObERMMNMRkz0iTzbLJ7ShurGkFZCoXfXkX2+YjKk1
joKqCEAjC8+6Iqpf3UIpeJXmNAv9l9HwsJZQo1halkJw4sLoPNNkv0wjJB2/2pXeYlnwYHj//tP1
W/REQ3ao92GXbKkGb7vMq10WT3D+HRhywWGBmPbvIGv14+cr99/FuuwWJ9YxTLG1AA0q9pLNtnoz
WjSdS5b1Sw0RUcVWvBbufniAMpisdjRZZrCF6L5W67QFFJ9S1riuY3ChHztqjkvoq6cNcme0feVW
ybddQHJ0uENl51LCERa0Rl4940WnF6vcavcXVnfmxuVdcpzlV8nn8pIVdrgMY6A9Enx8wW75Wl1K
iKkZLn3s7HpoJ4rn4vAhnGRMlRnrnWP76oo/RTMahcN46vDzmiyq/GwEgjZW2oLns08yXQCT7UxL
AHaN8S2nGcAWT/ObrcqOMNA1CjUOBniD85/VLirQ5vOKEULVZmUuwM1dNuXKT2jmnZO4T0zggiCT
yEoG73ZIQpbjhuflKDdqOjGrXC9e1FRRRe+oqJF/07WBPnowlXnaXcst1XCxZWyJqA51CbfX9zwH
rKnlWMwY2p7fPOGMLkZFSxTId4PtLjko8lyVgwln0EcI95qJmqwp2pvJ0aFCYxQXch+MjvHx+vBf
c6j+2ZOvLs8eoanEZOgsbsXbwncE7tEyRLQVMghQVHhLcCrbykSDe5499YQjq3EBKLpawuZMarxU
B9R00t4uIcomqKLppqGvxAEsWBPCPWLyut2pl9O2Ajk7mdFpcfQfEYl4tIbnOvsH2Qa/9WnsdFPY
VE3zz+56DW2v3TEwvkuYWqkSUoG7xFsqAgUf1wLHBF3n8RwKEXNV8n4P60QR6dMB4N1fyBkA9KD4
LuGF4vmKT/f83TlmxWKTY6ervSBjO4rBC5wlpoNMpFeTJ5o/HY5tiG0EvPqygilxlm516LZnzIcA
8b4f8x1OfHWCWBE5Ht5ekUP07bpX8uz39wDNVsAq6PfwjdU4zf0X4DPMlTm+oCJuMroOYzZErL+O
Cw7ENUBpUst2Ng3eNCBKjowof7d+u6zSAG1lvuJdS+3bD6Hr+eSmCr2F6U5Wlhx4DQWXz4RAiFXR
bC8DFC7gDMQTQe4xtzbkYX51MwJo0ZYyq5pK+/sXki/3oI6x3XOizcZw+7kmrMZcQiwq/PjNBKde
mD/R48km1taPOcgo2DQ1tMoJpQxRxTuJ5cPVFHI3sMdUUDsS5Z/iQfgC1S+P1qBxKkCaKwwtVBDw
7Q2nnxmdMv/t6xPXHgE2htCAi8Yl5Sc35l26w97qaStGX+3hODlXyeYu1glzzPsCBEQmjPiW8RxH
TXZd1Fo4NRD6HmKA7Yha/h/5epUkOLoW8207AROYx1GatJmSiDONtGCSOsngbkidI6q0/mLOa+mc
jj6xMMqj9XNNz1vc2ihJq27/xw6zvjZcSUuF6HqwlmJs93XazTdkYd92H3UtWjbkcN0w+OD/ctrS
68Vx76p+tZfQNzxKdxtTykDdAnlsflFCBRN6XIqLZAENiuP+4WXYfIDX2N3LgmDS1yy4gIHif1EA
ibXPPyuiaeZBHQhmdXvl2XRoLyorUGKKa5RTsV1Kps0Z029p/ZYPu8NMPF3Tlq1q88GjjL9IMvSr
VZmYGkmAosv6op/k3tRr82ls1zA0XbjFO9yLTZyD1SD4p99zVNh/g029wrbPILo88Re0wp8XZhXk
gY/wtXD0dPE09k6paOz2KyZ9ifdbuNb+6pdrvQzh/qI6s/l+sIiWhDTM65gqwG4zfqU2zmhm9Nb/
Xizjd0TJ/6lVFf8d3Gzg6qpjpA2tZdElwF0GMcDB4DRKzNEaxcSnkFPgGYL4+d13PeCVU0Lk/k7z
Gh7ZxbwmGPVkmLDiwK12pUjIWZyi7XULVJnEAIoscMpuIB+ET3XZ0gtok1Gvr8EBdHkUypPw5LI0
BKXe9Pec2i78UdtEX0ofipbelDuv1UlWHZwWlIQtrwaKAGSzUEzCwQWcKdV8aBeYK3lSseZ1qS0i
Bodmy03+YINytpsLwwxuWwSkDZU7J8j5r/dwsPy+vk3oACZCTcM/rm/aqshtsORfwkWNRC7RpPwm
dAHXOb4nwlfQU9ltfHHo1Dy7gDygKk+Mqy8OYDb0ku4qUjftypJL7qG3nIJ/NkrqnIo3QLUxYIFA
54fp2TUVVHBoQfe63s300FE3Q4nxayrhKn4tLq+s7Og7fi1P9n59wpDpuvyasViRQ8HWZVKI4Cik
2nQYWFzJcOWJ4h1YeVVXwcoB0B+Bwi4YNs+S3nIBfMWZgHboc7OC0FfvB1sGDTuKkOZWelxD4hms
Uw7X1vKgaS9cJwP7xE2mhcHSNrL7kOWWu0HWLEVWSk+emONoN8P7z+I064pUawhQjfl0yzs9TDgv
NARRNjx0RqF84q5sfa+/jkdCL5S5dzHXI7QoHjZb/FpHtwIF2tmTdAMMEB037FCiWwEVA/NRp1PT
ZfJbHlvSEAolMExJ1bwEYe3185HcRDn5MQiKfDa6Z1fq3dt55U0TBok7Tq/XR6wpJ65MaTVtSB7f
GZhxJLf8niKUlUmv4gmKJ32L2r+IiNS5QoWAq0GuRgyC4AcpAnhV3dBsjyGihxBJsLzmpE3fiaDz
7A5pka6DHzs8B+Ly5gqzLHdVEMe3kvCZaLiSApqSBhHRN4A7I9ziMd0HbNP8yd9HIwyx1Gk0wBlr
DEqj8/XYPB+FfVr/RDZBr0alTOi7eykt7ErYq2fAiTzqhf1kK1MKiVc1xDGBdS1VjCy4HFVLyePL
561CjHlUdaKNRQPK6EhrDxcC9FVfqNAMNzGsgVsDDODOwephPrRzsgHTYz6wCA9p4WvE0wvxMmfD
P0zb0tJvE9LJnX6j2Uuum8Sq1fFENaxl8IPnTs4RA/tIqYnQAfY+FIFblniV2f4/GTTzgYUm9yef
JvaXIMprRzStqelYIOpdBZ042viuP5T9gXj3jPuYPxor6Qw58pV2frujdCEVecgaveYh3j/8lMPp
TQE56kMjogkyR5RJ1q/u+bhvPJKR65LnaX3vnAizessI+noG9SVOQKVICf7M6gKGmzmYw5AuCVqb
m1GQVxXs+AOeMnBH0tW/OBR2pAMbfAxjaF1n1AbRd+IdhboEfCkLsXvHrxdlV2XTTrZoI3s5ioeK
koy8uU848vT4EKHF8Y+OHAnhB1r4odlDDVX1zFPHUEg4hX2hr8hKwRAvufoGcZrlV7L1CbwwbEn3
D5nbxeOhSYx874Z1XTBo5sAi23FWYMAJn4Hp4tw8a/tDC2Z88DrdzgHcsfqTQtNxgUZt+VDJ7daz
baBzFMGU8+RNGVs8fOlnaJ7oyc7Kb3OlsCA0S9KVeJCDLHSvhlrOYwilYRA2P0ZvqIPav4oSWShp
WdxChr/oCjPDmX23eYU05C+qGsdQQjRJ26KhmfQt8KyTfM8v6sm2ickMen5XPrdE6kQxAqDDxFOs
BMjIFtOYzJyPZzt6T0vjRBz4SemQha3CltjPjJgj+geqosS40PpeVQqqq7SwObU2pNA8ZD5Yi+tD
B3rtau8ihBi1drSP9PHS5jf4IZq1a2D1IUZaug4zF0pC7CDyAExyy6CcoizpDT5j5nTacGo1M3qd
OREUeyb/ZqUZBMpRPQmLKUincVFJKn/bwPzoQDLe06OeZik3ua9lekAee8McCWj0vuHXk05eJPsN
8Ys5PT3dz7+hnsASebT1071gNiUwC/UkEaacJ230bg5ZnbdkxrXPfQwgApDHWEmV1NOpIE+Tl3g0
BPzuyIE/uabB/GMC3gC3Rh3IPrcXAI0BJrm5AdN9pA+U9Z3THGKNECrUzzxCAPubOhsIVjbX0VLS
DUu5+4CA7hg2Y/6r8R68uMt7+JlXSfHSqYs56qZ4RhonexwEkmJVAbQjzpUed8YeGHSGL7qbGiZP
gz/Azy8II6mbYJ4aIO/7g1zZaPeOgzeoA7A26DuEdbjFtVePwriTA/VeIi6D1nxirctei7OZu9yR
df/8nClNIdNvLiuybg28VI16Yyapf3iQA2jh+bgstkCq0nqiF29Y5IUrKQSw/aRuFDDrXeV5jjQ3
UDRTIBaIBu+/0k8x5Pd3+X8XizqGa8wyZMiKetlcNVbbI/ka5c27S/bnNqY3dlp8etSymFJ0r2yr
eekW/ekDyKfYPtqDGa5hKc5RBGGFs4pYgF4PIoPwUifu84C9NqRBaF7N8QgYLT6KDyeNW0f1bUQf
h7i4QMdrYTqRwA7rrz1Zo2TBZloCbCSG3UksFiX7LrEizC2XTRQjNzQWFCSgUWb1fRebGD4dZHxD
PYMhZSDyWU7upma81aSyKSmQYPS0mmfLNOsdaEkvPo3MRo4DHH0kS4lPbAGl2aVoSzWjoMv/jwtr
CReqLGuRGv0XUsbxjk8UH7R1tzGAipJsEUlnVEq0Q2iE5elM77Xkt8K6VKG6gJwNO7BOASbnvZ6d
WZ7+4lNfcmFmKLQkxk2n9MC8X5cUrI8WXhBs4JHIz3aHqdPyf6zRTR/9Hwtl/6JYAPLVK92KFdCQ
iRBWOcJBpWpMvZDE/YrqWRZcdIA+GDm654CTpIU8XH+X24rc9tNCN9s4HMhZbhsiZtgze+zCx+M1
kidj84cRPCHae+K58b61w5rvzf/AjEz7zaCRUACnPKVrTEZeKWgv/UYtnWe4xH+GCWx+Qzyush7/
skAINIvsetqwvr0X/uhz4qBbjNunhADPzZBnzufbq2RXuwq6f3BkrS56WeFQWXfeXAN4yVejqmPB
cAGbOXRSvEmIJtYhdHyRn3S16lAaUXa2KS/xWNT9dF3Gg2dA17ZYefyWmKbAZU8tDp1Jr+8MaYnz
hc+3p3XPuuDpUVVGsP4pKPtYxZ/c0SFBxCXvTxxu9NLpCZOqztMFBpVzkJKbQHkMKt6zKQaEQzZn
SEvmDgTFBpzPK+Xo8G0bujr8R/2v4mJom7JkspfgzPdejf+tXVio7+XuI1WVHuIo4knEoo5wl1pf
9KctYuehNlJ+IOFJo8/LTqejN5O35aADUzyh7z4hWiEMBHq6ocXIgWPuEUEaRz88779lCTbm5UyL
vN53lfVJR+SEPYdillMGKY4Lc2ueBUlIXWpO8QlZ82zj5a//7Nw9PGtBaQc64+wHd+gJHMxyi9vH
d8E8xxauldOQwDZT6/yQbuH4fSSaAIm2fACv58LSuLgj2UewFKb3/1LXLdgxRqAuot6b4G2/bV5W
m8T1fQJJnQ7rokdAGvshpIKht2pSUG0BiZRrgFJXJAoh0rCUIp4Y6S0J2kCLaIdy/lmTqyn9TeZ9
AyQqY9uuZj6sCbhsCAhQg1wHmQ7NV5T8GRxKDJH4ub/Mz2Zvbj0+0wkQDwG4+uG/6xbrCF/E48jV
4GaR/XwzjcrQRwIFdW4f3EM0Ucx6l40U7q4m7UBUtjgfm+Ccm4f1ORRjgrljLbOvc6KXky8GiouR
DfiHiUqtrht5uh8nqrLHt/Y5j+ApMFz5YgC/rgTq+KwV46xR6hZ9Y8KFN+hxl2UDlootAbcV8718
abOCQxu3sTgZVGo66pgHL+bf0Svi2lpxAYgFtTvi90prl6jGmu08abe7uPChdIA1x7zMhyBjQQ4b
IY2Wr9rzPorv55ZrnxIvgA+y09P4B2ly8V59HuIA3Nymee+p+mbwlMc/c5ysNYmutHqNWg1YojVQ
W+2y01hc9m4QR5Z8wvz6VbveEKPwPn/hWhKgtqpZxzjDOqT15/BUtBxo68yn5PkwFAk7+v6IAg2j
VnkNVTQwyPn02pTJOAHF+doLQV44QP4IRjTSb3wla8KbSTCItfPzPebD7xmq8eV1/he5NEFppkJi
+5r0I6TE5i+fzG2mtp0yEacqt3lC0opKq8Ca7M5fF2LI9m3QWmsnSWJxVPgYE4mAF/66LwOv7dvN
V+Y2qc9/m3YQZFLZ5stYHG6xTr/29sV0r6S7/knm0I7Hgg980h3m4hGeQpnWa75jIwuTVxfH4Mg4
uINWT0p74dbi6icR1rPzHLPguX6wyD1npHxAj3LzrQCgTIwfyLM6GkY8AyplSN3Am5XKZ2FfAuX/
1+46qLE8olW3u+Wesi4zhZgRJhpWJfXI6oebxLaEMHrzbSkm4/AB04yQrSvb7/oeeSsgQNmkUBmx
BwfewdkwEFTI7ntOPp/whzEPdDIIn06H1ESzGZDKjlBHNirKh3YF39gl5NViXP86lLiUb0qDdoyL
slrEn8ElRgkNGq9mdzJ8VXe2sNTGwaydzj+snwCdOHcbF80J/exj0Zp0h3U1Kb60XCa1ksx+B8oZ
H6PaIRjeCRA81z/VzvlaZxv8DUKKHI18u/TA+Ina6zn0pDAHjUj2Aw9tcGKOMOY7Gzj9Ri0w0kE+
Y/UPxZ1PdEaqzNZEtwEk0X4AOsPNx36fVgNzytmuqRV7yJHNuOU0qCm+isp56fMSgHT6+DgXmtKc
Zz+2Dbb0cprk7e1KPnQhdRnlWPVqq8FnPLbVrsZl727aOZfv+1lqAaOHquvDGN+L2aIg2ZzqKifx
30AUlnrMigWAYR2dbwOmqKxjPiuU/Mtvh9PaWSbpKHHlaymfL9LuwbabXRjiSTcrKgDrVXSnCH19
RJCw4MIaVy2fMUh9bOFyuLPDuyNbJjv85ZUc0nqeVZftbg0nIotRq1N72M2iEfcbRSL+2kdCVbbO
RQTa1W3MVP9ocWKV8cG9a7nr1fZI3tt2Sl7QikdvpHhmLwhD3ayIPVOYhnXyasMFA1PMHddu1kxT
kKJX3wdlOnOt622KTBvTDNy6VpT/iTKCkjg5/muB/iLdE9XGHGSSCLjE1mkzpYLw90vEvQ/Hk0I9
y+y4Z7DRI64rOd5Q0EJLyFv5nvBJ8JsS1ZApE8c2rZbVcDfPWs5K1UkovqoYhcVcIZcr0VHCp0nz
fbAfrQXc3WwoU8msB03s0Wjxdfa5N20aJfLanbBC6iwDfqaeYQ6HFmH52L4yC4T/lfOLYqLeqV/G
BMVsXvcp4fVKhB/hdKDjmwr/nU80MSHiJYE+JkNImwyM3Cl9GpEmAcSTku0uFMx4QkWVAjeR5YdC
oioOqzwDFyUKlJsWUo8cys96/N+stPqgZPOEf2wtNTyqDEieWcUE1GjTz4Kd8T9/RE340qJAGMqb
z+r5ahowY2eY8RQrHpF9z7Z80dsg4Eg/WMTRcfccY/UlIvp09w3iBueKC2w7Y5C81NQL6Y6B6vck
29bh+Z/9EkYZ33BdP4z+XYqtqPZRTEzZi87hT1JQL17Yw41Lr/r0T/MIyc6ibeEkSselxWRb2d9M
HymYuTyEirCiuwV266OkBVUPgP0tspesOL6BFsva8B39KolL0Inp/Kw46OX4Hs2prWy2Kj1arYe7
an9h0daxWAPhX0KxBWrMT0uxXrn9aS/PDT6JUMPRepnhmZRrQBrZF03TzL8R6phhDZqiCToxcQda
qgTlNkMGbpdPoV9l02i76AlDoY8EFFt+ovpJXXwLO46u6Wq6zBoZvb3Os9xVEqnL20IKigyCgzGv
7Rws4MFrcEuwQjqx3KiDCNS3YsO1IXjIA4GDk2JDPN9s6TTIgwCAggQ//ItzkPHVf3tniYsGxPLn
kvhGaiR3yyePMGlUSszDuwi7EXeS0Jvw4YhsnvgOPAdqHKQtvthpn3RCBTzM4tOHgWxWmWdOLE7N
7lGHHXiM0T95l7rU0RhHiccvXXHzX2nMW6UGqmpbLKWjSLTLENt9vYOxUzqJezgVbx1sUWRKKot1
93XP86blUoxL3Nkps1SEYbZqZwrsWDsOwbv0R3I1Zbb4oQVJn8NItDJHUGuehGtHr0760W2hjL2u
VK8gY+YOv6SdJ1fKcOYO6Atl7K092CvSJ5jZeEI7NxlSNDp4q26Gdxeg27vZRhQ2121HwmJY5tzi
iAnPEkroCZbmMGXnGn3UemYYPPdQm1g6Sji2qmUYRxA6aepBm+s2azOGWXoJBbp4+QjmlUu3QLmq
HZ0QXkmp/PQQvetaS8a193inKMiHE8OdzRCUGQfL5h8XbSN7z/ruSZqxRz8GcBhGUTNksoTPunr3
O5EK3HkVFVgc5e/h71ZWwtnEwKn8Z8u+z/sFl9xIDwivN6iRxospbpZWoTAODFUymP019s4HcLvT
wl+UTUb58o0R+zcM7q7PxAIYxVEvQNnUAooem+VrWrylnRyjetaNSVg1ETxcujA262qXoXpMHNfS
76D0LvP/DYr8EDGFCKioaKygpj+TtWtn6xbSvKsxBjRnt7U8DL2RP+cWKjPbAG/eGyKZuSrCnRWP
J5osjDYDEhdItKQ9n6n0wBtx47VSfl9DdopBv2/1dikpa4hYT1cvoRjSPCf+7W5pSmxe+i6m8hAR
e5ykC6jSCrbdPocs9a+u0nCGNxYxc+B6Qf4wSLlCOmaanfBxPQmPgmDiDFPpPpI97Ul8tV4phkz2
Ejyh4cc/Q42OYEPTmngdIYeEYKPtFFplyGXB69epmoFyasf/UE15IjsF9wdDFuKZs0Nbmv/mco1u
LF1eqkC5Va1XZrykhkKqaOL6tnLV5lJcvqsB68ngUVDkSmZ4xs0KHZNeitnoLGpICs2NzNDpay8y
VuMg8QKgEtd0Q0T0l7Hu141Rhr7O+AwYdjYPhZsR/m9cM4Sdhd5B7nNbcW/nlA4srxd/EvUgfiQ0
CybZrqlj5+T5nInkzNzTcxzheupw6ItWlkQD7Uf50wG9wJA74HWGUGhxYv5R6262C21wY3Lf8sqU
L4xQ7oUJbeMGLp/XTCZIodhpVftS8J0eGv6O/icSKZmPrHRAQfF562mXuHS+WQnw5knfDA56NCKn
OMl+Dxsz6QHXypNTZrtwt0gq3UizBWVGtFf6MN11KrS8G9K9gGYmuAPGe8yshR0kEPCkkMXBPwIC
1SLLZei/yvmOZHwFCSmaqwwzRaCuKfNYPJcmmWrX6+miRGvQBdpuc4jyD428Jz1OuI6BDHd2PXLF
eV7N+yHAvo+t4fHQPuOa/3K9q82hfvSc7X7n/Utnrh2BRJo19v+YrPoZCPPCSNcBxRWBtaVTbs8+
oAwZ6XxA6SwIM1T8amdXeeofwFzmTkjAJyegwFMTMyY5r9tam4/bEvLZMlLKEPn4YRI+YFBbBQ1o
uJOhL/ItqBqerVc+kHFPZQ1vIrWj1duyJE4lzbbZCPkatXG89SVWI7ZX45aYrz4puyNZ9tV3LiO1
OqVvOHdciggksf2qxk/YJ5FCWZQgOhZenpOm5MYRNcRiiRd/Nx7NozcPw4t/89BaB9UK+2MNcYa6
FtaHOfyRqHjqU7FXoldSlIak6PLTxrKNPlmNLj4ePgZkVV7mv1qhrnyaVZiUR4tPPIWIXq8REPJp
G4NhHvqkzqXbBHvaVfgawyvU4ftLS0Y+/eUOamVbUzalNysqnszQvopboUzJileAYVQMLcvO3zIV
pmt5mreD7upkiEKP08ikVzLFdWKO2kyQ2P+kzR03jUnnpSocHH3JYQoJCa5VFBos7pr6GfZYdXAw
cmrSowiW47i95R0KbVONTpXo3xoO8bMD7xJn9hx89jmsblWxveEsUwxtd360of2wKwFvMEoldR5T
GVFk6p2PqWGb9Ni06lWjFd1iAsWO7jiE9t9zWEQeknmEA3BbCIh+oUsbiNINyEF7QINppHVw6VOt
9Cuqc8Iq/BcdhUqvaVeWhGX4FdFWuVuipo4jeyHgfW7/Q+v56IGCWAID7A2Fc358lqMVQe83Jpsb
igIYe1k+dYDmp912UkBx3ACYX7WQ8on1aRomrFCrbhbjDEyuD3khv1tBVTx9mpjg62Xm1vP8HPio
//G9ipX1oItfysjlS5kG8QTf3/rcV/OvlnEqCJ166x9IHR+eoBNmPxGorj/qdYnncRfww3veDIdt
GTuQepsVEvN9Ac5T30hqKtMJr4TM30B9Y+r+gjEgjjMiR80duIlBcZHP/ZRMGwUhghEEq79Z1wda
kPIxhut4LSXWcdqxUogHLgQJ9u+iB/1r1ZEzT7BE+v/wJXBzdW+BgZR9RtJoTvNLIFv3hUtU92yj
q+hHFt8rRVogQxBDlB9oYczNdTHJQO6+/M2gtyl/xDBbSdVOjxNX8KR3jd1Kn1v2g2Nj0pwcwM9D
CHje32u8rDQx2JnS76z6qf4uJJfRBpiu/LG90WnbNPPqkhWqiFr57iMeOe6l3R6aN6D+9Tk9kOFF
7YP3YVzDMXDV9llhcvqRpnL4CjLNNTJ/AKH9QjP/xpD8Mc/IdMsux42mZu1Tc4tseyP0n+0NEByY
DxyEoNbP4cX/pzkkYC2QIRm2JeuG9S8ivxGS9ukcgL/ujqH03qdaKNbkKJM5ABJAUwHxMJHuUXMV
0ZaxXQkPouLKPjfrh9DVxCSLIMelJMEAgw9O4T8mgaHKAfsD+NCSdpkaTJwmXF0y33fHCyZNhM/G
OO8ID7zWcbya6H8TBAJxksMjiUSYqV9Wl24pyZZdCPSGeDVm6rRUQdQ6qJKIXbHLvePX7vfaXHID
x/ZSXOp/4mFGAxe5ZXxLusdOXe6ydoZ1MWyN6qlg0Hqpj5enREaFRsHSyJJoBFwkQ3SUw5XYmJNF
9j3tVXhNbWnFR+Z4csuhuboeBU1PXYyMOMBxK3o4LTMzZNDPfSE6U+F/lc/iqbRjmzZZX43pgvxP
f3sPDTeu+Lhju02V8BT69G7Ad7tH2Afwh8pMO84AOB/Wzj5Nin2j4LsfNCF5+nE3oqo5/ODCI8lf
PrDIS3SuNOnkHuUhwvjOwKZdG4BhC3n40mG0DIFFxGp/ImVCwLGxUBqgjTlcIsSB9Tu2sSH1cZRL
+3/vixF4dsx+YHFAcQvnQGGR1bN+1MGzToYfqPJiyurQmCg6h0yuAuu8wcfyLZrn5hb2IrFlF+d2
CueoBFE+w3Rgo3wdOrWtw69dJCUfLimdyKsOs+shAMtaR3NnlB5GNhxTCtMPPZ7jnLf/nKlDJqfs
9L1Mqtd7wOeS2sgJOWbamhUHTT17fViXtppgXbwlTgRROV8fboq8FXpoRAnP3+4gHablmZMvQYZB
mDYNHus5ajf/cxAA3P3iElSx8iabq4nJb0bFRpWmTpTg9Ot1KvtLqmDjH8C9pobBdCvnYOgV/T1X
qQ6WQ4nkXKtBm8L5UdVE5xqrnIab5+t8q4OjF0m7twGSRCi9Q4og1vrNp9hWW/AZel25EQ25hmhE
w8t4SfbAQUmAhhL1q1E9Gb0hMO82NJd7PrXRst7ZSfy/b9HhA8vlWc59cCnE+m3k5xthJvGDYaQH
mTh3b0jicWlCPRcIZIQXufe6cYbtADa7i3y63RL/l8ot77L/Hao/Mui+oqu8rbSoiovAdXsNsuAy
B0eOsM9iAv+qKwC+GH2hcjHgoFKDI5AGtns/sfDlhPB29yHWJVxY+lH+MatTh9NlVvicATsvO1AB
ZkZaHJsBwLnuvOX5FEJqXZkcs739uY03731MeJVQMYVNWcafdc4XTG7jIjb/lRxrbWuQr3EqRqbK
w6rm2iAKfJ88a7/qvQfdYwmdC1T+WKWC3tBVvW3lgBVX0F6s2HY7Y5nROw6KSIgU7kZbfR+z6SYo
57SKzqdI2lxukk4owAijuU3TELUujvNKabYfBsqRrx5FOjssF5S7K/jrgogzLic7Gxtj+rM+9PWs
wWcOE/qA6Mb2hSYW2gy/57Mc41/yxXIol5MMml1mSArPVA+EKFkFYrOEMYULukMOV1oFRo+O/JjY
les2x9g3HLrSJJoYZ5ee2RKaqtGgQPHjE/6x65fXvj082U4tMt0WYjdNTFO/9+8KqPghQCdvfFP/
ml22tMWEjeC7D0R7q9du6JEt1cGWdkQy5euIvyA0t3iRIwSF6vt67u+ttL68w0mBWAqLa7OGqOBW
XTeGr36ePsk85p6tggkI+HaAGi47Q9P96p5CqDOoP0ayBnU994XrtLjnjP1XphQAE050427rmhXG
yDvRGDx8HOn8/h+KrrkStgeYT5G5kPhz2I1SbaKPIK5hprbGpUjSE51nGdSsNemVPsTVoagxkrLO
zcvsK2Ut48ju2wQixnVxjkZKxYJZ/ziIn/ioCiI/YrPlDoz3DKAWdH7+DQP0nbcpha/MP4/mhoYS
r7zxC6yfXVtxYoDJzvCoChNY4OdgQq0fuPj93t3P+vjyogT3USp5pWeiWYNEyqgY0OwTJWe0bnHm
QDbiZSWPcOhL02xDo62v7C1p1lRoFCqEQFVRem7V/0pNaM+J5p3WoP6uloIlTlGALVLH+6Cevs5b
4Q7MNGn1qp4y48qp9+/Rc5xZv0+dxYmzQbMZ5aV59R+Vu/GXDU4VxuXNIYs29U3I9FCPBWoCpCSc
Ws+jfTpGR/IlrkVwtH9Kcz5/CEVztYiU65qAsOknLOZcwphmaOfAQq1wT1vAAzdaLapYK3sBsqDk
F6GGrWN+zGqckhne8M/YVAz4zGpH/FUpzqck4sh1WNMNs6eAsX31Undsr5pjfta5ORYUustNxtoQ
EVok97pyvl13cl0x03smMxqY7k2Pz/gLVqhM17SbnM61ocFS1m32VP3b37YukXm3QiqM3XmNVd9i
f9y3XE7f4sONvdkvjysSv3R6UXr/vf6TLnOSGMIw9RknmEnFvWX2S9j/A882qOlGtXa6xTUB8yhQ
w+oFKO7fxoWznw/mYSKMO1IPJsAYza78s4kABfyrZ4HAcRg8GYD0T39Yf34kBZcd2UtzYWNP4U7f
maco8KCiXoUzgUZGLIa1FV3KzsHaOy6/pEssFxn8CCZGf34WneQ5gqCTD07FUVgAtjudJdUAEwCB
VoxpIQNc0buwxF9IVdxeGU3aVPBWc2X+4dQT1lY3kbpjLH2FLqHn7oC12K2aYJCaQJdP8ZbrE5yx
UgydxgfGLf/HCZi0msYsBvnRBRw9jx2NCLw4iSs/d6bAP25zGwUOtw6nVKru8q2vI/6QMHxaMy1l
j0xItRAAHzu+kcmzhTOg63mw/EnMDURrUPpaiO7gFeG9IsRcZWaRUfQTJtgw54Mj78zEfJSfz/9s
cEnEhVD0GsiAlKD6ObFxHg6kfwjCzy1cY0ipmBdLT8j1092ePsQ62WYce4a+lQ01oMhwBrZ3o4Vq
qDPLWpQ41w+8og9Ve0oYgo2M5iii/EcUVF303IbNreOK2dUEgqQECMuIQrAHhipwfoPx4aY/n1ML
UDFo+DEetD9Rh+EOEIoMSk8HLKmVEoY4YWEMV+Zw00TfJSQe3WGtjf5OObNvGscdPWEiUGkiB0J3
doKp0fMKINycHd/KTQF0hOAcM5VbUrdv/gaEeBHuBBh5rO/saliIYthGoFAlr1EYGNq1tZYoay8D
Ry8jghQh6ZM9/v6IZwvWkFwU/9V0ejbuoObjHjRkeyq0Wj0/qM5AjgPQbeJZ3aLcW6GPWLJrrBTz
OstbLoh4VlxZsjC0BCosqH65PPEmzTGf2Uad7EuDgCrhcehB9v5NR6SSRzuLM/W1TdpAntxluT+l
3suqizNJ1TRNUBI3wTrIUnb0fTM830c9wOj6xVWNdaZYPPtjv+oSUj9YZs1o5Sf9H3otR8nlWFRR
eKz5T4m+BkCuf2Uam/sq6iMgh8bCw42u5dmUICaj7UyRKfP/r7W5NdwrPA4ew1RqOV0rLhNyEpr3
4FNF+1is2vOqP+MAHPVPBEm7EFTHNy08T6Tp6xCifEqhbw27g3tfmZ3JDK03zHzDqAY/oOtQF4G2
pXSxeanAhkEB6aUEXjPiPux/53RBfC8Xzxb03kCD3flITragfo/r/l40f6K5l85Q9D5kGUG5MRnJ
5hnR9uQo4skwnifUD3B8+9aRHfROIQ336ypcQiyn7bH6CtlO8bTzo194M/TZB1vJ/kgHpnjzcYm/
hcoPGtzlDvezWNLucnZcR2ZzDIP6cyMrdIZxm5o3mn4Q/5M8du8jyu0wBIJFsHD1tRmCGQ8hiOj8
ovoymdSLlC3xe8ZKcxMxHl0rokcDYUC0+FhhDZm8epUuGQT3Y7QOLIqt6z4njdJYqELkiACw15Mh
J93/I4ML/1blGqDRQduKiMwE6OwVx2Up0WLYq9vHz5l6fi110sofpRPDVE9xEvBcHcHdzV9+RHjz
OtZw930yOArEsBFSMToLRbkmdlAfGwbkkbgM6Iu4ubLIW98sEVDMblJNzjhbAjGy0gxpSUHxNL4K
fmGfc/phpkOuRVPRfpw1jftb9/KRga6KQrPyinsKPLv5zm3u9YYyTq3xnusxQeUDy8lOcBvi9SaJ
xRfoc0V7c/uVQgiqbHpMa8iwbuNg0XrXivcKfELr4ONap/D8h0LOMLuVpi18m38gZkttCxmb269m
N+hXYQL+b7r/qm6vrBNZW3PTo0F/+XVuu6oUarAhnRgd4HBhIkQMTmKgwN+CflIPJSxMb32kbAMy
K3yQNH8TuGEkdU7m8v3R01jtYFxxSCJhpcNsLB7s0W2gvaulxVF8xyMdVVu37ni+In4ngcKfKq+H
Mv8RY5uwrQ980e1Hi94lhf1NUZbo3mPoXBqLyNUUCADs6cTvGB0H2yjSYIXcDZTgh6Ng+RPKQ6Dv
zq/S39TIoOIzFhDUf3x0qI8MlCZMY0qQZPQHHcwoAbp6kXKX6ZSYpwXr02u3RYkUeNWnoC9Sszl8
gsrusESlyO8YgghFStHdbsEHlObQ+cxtaDXHInillXg1Aao0uwfnpeZrHC6Tc9jN/9Lqj9EwJGs2
aPMr+9mBKPM1f68tfjgQMiYS0i8RrlXRavq0oHEm9NqWfc6Sk7uVKoN8PRBT3jtzlMmQ1hOuw3QS
Jb1bpCDzg6VvTht1+2GUx/KyR5onlKA9ohmUM/JobbS8golQMEew0Lzkc44GhsYVB77VgSi1V5Fo
+AkZUAQJC/PECLsr4eDTun8GUKuPiDsbrMZH57yM5cfmlaNnJe0OzofsOcWCfD+L7lJNdlKRdBf6
Bzs0+A618teK2B8tf5/A5kwDC8et86JeNHca4iZnGJEYPyXVdcoo3ftabm8jGF3aH40bgknWB+bX
b+4NDGnWKhMXhfJAMH41X+NtgFVu2I4TEJOyrZu5FMERGY9ToTpNeQLtzC2dC5uu8sj4E8dIztOq
14//2UlSx/s5HY17S2+QZjDb0n4x04rOr6yGZix2V8or9qlBENwnQ/vCI54sfrQxu4JwAlKsdX7Q
h8pRziPb+CBfCcTxjQsMqQPpDfZncZneIwlypirD3BAmwXKTaYVfXLDW/Eq7FNMM/Mm9Z2RC7TbN
mtpDB/IkTlQzN/VzPPVu8V8RQFlrCZr3hmOcLJRF+RBCevgNTZGyiWB4UHv0PUZ2tT3s3kUjQxt+
BL0Amyl2wbYdTgmtzEo3URGaIqtg+olkh9uJ4hE+rtHVqv9GbcznhU9KZtxuzG0Rb/VPp4h8dLr1
x2l0BurZ4YTwdeG0zpp+Muk+FkOOVV3OKIOPgpzokhDb5C4ExLEVekGU+XXADWmMSK/5+rD2I9DO
Xx9UOJHkmZIEAHURhtuhFmjlCnF07UtSqPSbvGENPO79SiM/ptPPB1uafIDyzivB6vCwrv3AqoB0
uHpd70xfrM24wOnxjkvRWwDO1KftbJx9ehIwOmTQGzhggTtNCP3ao40Dg28kFJoBaPOTJ2PLLpvd
8KuwLUZRliuGRLXynvuq7YlpCNoKrSgoWVBzFqnTr2hnlV1qS00HLwyxL25xFN25NQKLSgDCPFy8
F4j5TyZkKX0NjDOFd1WVxskjG2IzzUap0Sncq7Irdzg/A8BPJ6AJi21uXAGSrE+oVC00zoZRY1Wl
k7vzO91JPGOfNPim9qI9vL7kwzZKm7VRZYiqEcIDe1ihdOoP8jVz9ekYBaTdvh2ynEgvIUuyUcdn
0hUnoXovd7DmKLwHxdE6uxIJS2thFDiSTZrL7+8Bl7xVqIP5ybqYqz1A40Fl/J8woy228gog9Vmb
NLx5xD4dVrdx1p5I5paCCZcIw/sfnoWhM0MwiibGswI96sEI3M6SwTLZ8RZUbDL9UEv5Rd5Rfmlh
hRvtbAbn9ZMG+6StjQXtfyH0ZsfNsjW9TSV6D+AbdGqUZj3cdZr24PaQ+OWFEnyQDRCTTDo4s9lE
byUnpLHAyeuMoPIXbobxf3zZBhg5ZLL3OVHq/4RODAH9xgSNTI5wWgSY/YMZohBVJCr/7gVdu17X
ihYYCdbfOTeb8mqpSDuGwfR4g9JSswb4Ag0q9FLaF4kIwx7F2MwFCBXS2dk4lvUfdoUdth6Jw1EN
k7G6szx5o5l7O3sg1P8FOYF/JtwmTh8rWlydjYtAdzqRwB2aWihgOdu9iU0vJp9pFNBxR7PgZZVP
hRr72yS38Ukn6ghZRySUCt1pCSWcmpnIN5rIWgFRA+YV8M5lxDSY3dp2m7BNG8pTRL57v3WtZReq
hJfp9NOJsEhE8uEFU0tR4A0DN1cpLRsNkhtToC3IbHVGWY4LW3465rTBCwxXUWYB1xMCS57k+1CE
1UKEiTizdnfJIA6ZqmZTA45YaPe2hyCtddPvDRQlmyN9aJDloTQkCtlsbmDizxbdv97MJMJKSbEj
eHUsBK5ZOOJiq6XrUV9Csnk+E5zqbYDxvRvPj06mdwqHwifaxeyZdb/7elegWLuDdBjp4UsZ2EEJ
uyQ3ilHE8ygUO28Mb5Xm5uq3tkpGWJvYKHXC5nxZYPg0ro3+0rX79c67DOXWkvFzXw14GLbVR+9z
cCngcrESYO1AKVFXP0ggUz4PirNDWZ1Oi4uqRXy2nCGOtkZrW/uELSDmxVa2aFSe3MBEC6S/xCxB
b4gZo9HtEYRSzoLvORwTrDNeFoBmTvBM+D+EsKAk5/3sUAyc9h2sEShMu80ByrVap+pos+dC/PKr
ZTEp/ini0NGFA+SqDtMqVrnrZ5sgqmR1LxZsAWwseJUg/MwfkEOoF5Scq5RBtLYfDlJ0HE+dQ7f5
Xv02Nwl9cQ3Xh9fXM5G0yQYwBCEsLFTtF/hqsH9V4mnumoPlqmKuXiAH8HrB2K5PTrR7G51YkajB
dgzUzQc6YQYgPr/4tAqczt2f0KXhJBvw6Zv363C3d2GZAvPAsgYlJDEi9lJMVkSLcjxfVNheB564
WWheC/WPS9bRaktakpI7odUuz80MM7DL4YFPMoBVohABdmYSPATOZrNiq4dnZpKeGoA1cPShWQ8c
UG0WM3cZYH0TmCoZUISg+5jXKPaNvATdDR7tqdCAxCapWVZlRi92uh2QgR4FQ8BkTL4zP0+U/g5g
ELRWNk3+2neEaz2bGJs9sBLuu3fPRF3i1PU+QR5XYy1nUCla9y8fsf+BGM/oZZEXoHB2YYRV0daz
8vgFYG7ukJmwnaG9q/eOBITgFCPVPe1/rdNqmfvQ3ivz0K9oMY/HryQnf5N0YQY6jPnuiPb/VA48
lFHuyqPPiYdMYYTarVB1w5Hki1kIeZWH0Ap9aExTPtPnITg3X8Ptz5kRRH0/uby4Z/H0e8darEej
FML4kEvinl4YzwvtkmOWwDu8v8npRONNEga/nb4aeLZ2H7PQ/EnRv5tijR+MmptoYoG3zucSd/69
ALU1JIlBlteMPh5Oj5GT3ckG4TEhZMF1lpbPCyHw1cHYd1GAIFnJBQoDKLWS5TJQ1otmJO6Og03Q
ZIEBQHz6aYuNanWK24EnXyG2dxfUYUz8PFpWZQ+l9tq9uquYVLj5x0JgPc7ukWKdSg4IeIN3w7vC
V4qPvDygGhJORuuol5wsmtgdjkxEZPEzhW+DVvWMwUmrQQx1w65zeyse2emnS991B0Iee4JPTdut
VjiQNdQ8LGNvmkiZ1GlTXcTswpmEPNBqx4dhxzK8ONSV+vcbDI3vGay34Uo+spRbVkm3JyZd1ox1
iRdi+akJtw6pi+ZO/WQ7hXYN8wAd+uTJ8dFhL4P+zlFtt/slM4N1/4akdIXhK5iJjBA4tEOZ4T3B
poZbFcMeSLKtwR5siTF1VOA6Rd5flwbUaDcJgy0e0Y/pD9efAkBwlIe83heMkyicV4nD9jeserv7
DpIineowyucyNjpghXJBEB6mexCGKihz4xwFnQKRhnRDoh1BBvQ5eYEhEO9gwFcAMqMOM2cPAPBV
b3Yb3oTlpX8gznOOZSY0bRTSJiGiJwCEvm5frnQ712YdOJTejCWCZwYJa7AevjdREJnK85T4xbdm
8xkwBQqvUuSEGr3mExv9cC/NaUjNp7CxbWidemkoptJqhYxxSAEA/Kb8cB2F34t3EMMCuCd9mLVc
zXmS30LXOmghkDiJTHK3c+ekscwQF43EtqkVHSAPQgtIGe0JEWM9J0q/Zi8xHMwp0l192/QsfxVX
22QIH5G6+yLY1BsmHiqrUUVeWIv22V8r9fQ0jUFb36TNF0joKzE6eodtIQlvxpsH9egN7E8FScCv
mZk0kegBeHbInuSUhA9OrSRkQWqjrjU1q/MsNMmouPF0tftTDXGzKQqt5SElegZbbDRvFGuHXU+C
AxYxu3BYH5mRppn/6ZWaOcaPXsoTsjvE4GDYkx6OoMo5F4b06sW3/+DD0Xuv4XOGSnTHFzX3TZcc
AT1cMwspropb5l70iNI/zHKQ0MnfOsMPNWCntAJNxQVUR1V6BxWYNeEpEweoEGo7GTsiH2aoj98t
85xjU8lDUjjULVztNRa4l1G1p5Uu1aIK1k9Hgz12p3d8FDFxswgwmFoShPFUbfUwb7fYnBdyG4uD
aFQI4O8JxeqWl7b+NJeh6Go1XC2Vj6XaSrHIf2ut+PMQKzdTIx4TumWnQtWc1+9R7mmKjDdTDRmw
ff81ACWboi8maIEbHfLhJDp+1Ihyb63WAteJrq8w6XbmTq/KpPK6CuRIbCxOFeE+ftTBAZgjEWAh
RPhgbTOYxXopgTgRHN3YNULPzWSrzFm8gReQ9IszX5K0nckSdtrJPm8rJyrCpltQ9Gev2sNzgFaR
SZn57Ty1F6jtOTeZMY1wj+qIbuvaBDzyX+9iCO7QfdeUuzyyk6eWR82tv+9QiCO/mdof3t3uwjve
W7zyeqDQcoLAoNesFNs3Dxx654pXQ4SQKI4jdNG+EU9aN9yB0ejOrrqvzNrrGCX3spz8o/U5uq1p
GdbuW5NL+f1yZrTXZG2S/KeObeGGGGiXj08q1HHDIerRQxgdLFADqReULBlfXo6YEwx+eHvoFY2H
NF9I+ZJymaRZ7DpXSxB8NsYtlXKr22Hre4aNZjsZm95RivYfvV/kevRzwEU00lSPwEHIuieKAeCk
9h0zCyPaQkN5FvXPQ92RSXdPi8psjRpMm+1cn0Ak6GDG2hsGw3M8vQkoS5xkVrgdToOTkJlmbrlo
5MmJcF17rzSSxhK3D2mBVH2sk3ACnybcTsBupPbtYap4/5LIBprPeBSUCzej1+VIPfyaruYATW5i
P508bcjivycntxLpVK3MpwvDPea81X24HJSH9HB2Oc+T/hLaRfzo2UcDZ9AeH3wRs80f8JLPv3LN
QCzJJE5QUNpS98tN4oRZycIHfNnUjG547eSuXaOJ6kpk6YoVcld9TLCmrXR+3HGgzXj4oWX6jDmu
wWotaoYelcdufZLwOfulIoh7/pDl2X+Rmf7MWeTN6AzrTyp8joqG7444hepa2dfFz9pDTvSn153Q
JNz1LnrjWo7m0B5CgcgUWASMBu7x/SG79WpPs6ERGZV3nnHBba1onrW33LT+vTQDcsUS3uiw9Qjp
k52V0H3XCtLF2BlFXEnbdgseIbUQd8jMP+fgkOFr2GEQZJ63qFUIYmuz0HfZvoNJ712puHth5qAi
SBSpPOmG75dXv1dQOpuNv4zIWwmNF4UC3oe7GnyFrLEwrRZRE/iZyUGgkqbBjymIxW1TKoLvhba2
UTkjMfhzuJ3HVTalYYa0NpmvwsQ3V1TiuKvESQ94t/biUa9JWlKJezXxeFKDs9fSzDqkKGbpQPEl
SdHWVL4aHzK4ylQZek/EVU/lVJCsyxwuia7pNw5VMJIFaUOlNdYd8G2OiAp/NbVZkynfqIEgA1W0
g0SO2pzNH9TMQSpn0a1DlV72DCLvoM5DHmfhShqizSbL+T0MgCM/9wj6nTfdDWFwoGYx36dYYBSU
dyQTSurHmEBxBlEwIAmLN3qTIApozHKbG4Wi3Cdvn76GcIBxe1gdJ3GMVs2HyR44IAlsv+vXVRRa
47BMgATjaTvH/9P7p0EU7tNIIXWuNkiqWtLAu/FUgqJh2ENNWeakviOnT/Vbh5tpLN32h8DlNaCw
jQU4wjJvFoQkgkUVjrST14Lco76ir8lONeROoSGuJO44mjQ2n4HpUUS5yge064qU23FDS7855jZY
g19eMfhcni3O1ExBeKpdTEeQfaHx7leG5VcUcCCOqs4+e4szmsNxVBFsVcqvq0jiv/A+ZffLLCIS
qR6NWBxi1F1uEHWpqCrI5ffuuKA/qMz6GoBzXNDisl/DnT0afMgsP+U46EHgZV13EGKM6GIIKBwE
hZyW8f23ZmbXYfLgnqJt8gBlB9BCQqgJ+/AJkY3H0BTusjheeF81D1NjVACicNeMtb6GGkf8Bgwc
Yk0LLzOm754FNrprLaee6OPRBMf5nB5fiyodahm2cb/rHOhkL81yS3Fyzqktxfw9zkqz+D9ze1js
xX6VVbtTlFHrzgBhPU/X2MYkacWSEJZodVi+oYVne47/4Jav5O5Hw/QqbZaY+e4qUhOmxS1B2ImA
yqkcAjX6muEcfYVmrbE+Ry8WqpaLqixmONW6OuKqaMD62e6xbDRapR3llNzUgI59hk0NuKDYK/2L
prZfCzR2OVRXYN5mZhrrRBiIqqnZCgmyPk8nqlvNFMuVbQvPoTqV7XuyCE/ZOV+Npk6BYnCI//Hz
XP+AihKAeYvuVv6MhC+XH3QbWdJLziQNkqsnBJWu1+I8MGg4tv/AUqGgN7wGIovXh6vhLOtRqdmX
rbq2TUTQUALy6YL10uqa0IwMp1UiiztnRrDLixOomPpbFVpwJhvl4lCEI5IFYssBBYmNBc5TMZ1k
Q7UJpQv4w/npec0QTSl8GFnDa4ReUzbY53lCalk8YSTJQap7K936J9JDkdZWKdgCDSNi9ioQXgWs
JnvinaAT8vdiIFeNtl5wP9I5L6yGZY98MAQVmf+6SOWSCnXrr3hOUCOuYaHhEFjLNaTpJsjizt/H
WNnbvtgssz/R+rVetAODsCx/6+IkXxUS2hyKuQJPNMpa1iTKOnp2ITHA8FvITg9lzN1lmYX33h/D
tYxzx/xL+wreruC9nSO0g8mQ7+Me78G8HX5M9h2KU7PfrVVRwBqpexpPmNpJJ0vE2/pKR1lOPMu/
LLMBph5X0sOhXR5n3wUj3r/wEf4eekCE2Eyef41vy/Dcs5eYzuBdvlYhCq0SuugPbYn/1ZQkjqji
EFEfUsJToelhTlqGEj/PC+ZeOpFfHDgqjIvGjRwr0ajq8LEX2xcZaeRQNo2WznSGlPB+oU16V6A5
wMaOrbEjOTBGQy3qpCRcX88iim4TOH+sdGKNauw4mHejtMOgUElmAsAuYCJ9q09sXACb62+YoCLU
gMlVWGIxbGlgeswS7IcfKQswQAYh/+vuceS+qPFBNxH34ZhLUnJ1qmrX/cN/FYzyuudX8Vo1eTkR
3M3+7CCcbrC2UQJ8VpC7DENntnwuGqykNZGV41u64WXzn6mw3MFyrahA9pVIOvouZ47fIDcqmEAm
rrD2JAtkXHzhmwGuueUowaTZA5HeD9xWypjorPA23RXPFV9N49gYj5iT/1f//syVbrwWLdl/t+kH
ArpNwXv27n+tguITRzVjJY7G+CRW8ABBrgORxXPVZQU3pr8CoYcBQgZK/1quePZHKeirjaIQE/V4
aCsZPCPIpdvCRTdQScenItM7csRbtJD/rSLtQFed8QucMCnMnIQjzjzy/iAfeEYLyMl5CUelDWdB
JOv0VaAgUGdkUKCErHjyQP7jOrIfSc7UKnzACmN7wzKuNkqKplI0T1gzkNiN7Qx2Pr3OOg0q2X6B
LlB2b69Zy9DRe/aMIUTEOSCgjH6su//Rv7bcAuSWwPX8b/1QABO8DQiVassLbOGFZJbh4rkTTwYi
xz0i6KfQjgKVU2IuCNAqQbzb9XK9pblKHmbrrrfKLHdaTeorL/LBoJWFugVTg+WM3tWAlLmHOQ9q
MOJQWbOfyhZCJBC36ZiZ8508UWv/YZj+cr/PhDKXiJQ04A2jm2q8smpkO17e9imPruocoKqY02lQ
0lZsmLk79kfepMScnClfbznr2CgBdSJbHI2qPg5UXvchNNdmE3Vnaw7vPOREIG0IUiN+fDKMC7rL
lMN8XtxgLWUZaajH/UMImnvHDOPFeCzWidTwWqr7WwDisnDvnfwmjyhsn+PpOih0QAzfkwhcwA9k
QEYwWO98A+WOP0KmBMY7yqHa6iiiouXp+TrHlzGDF6JhDGKk5DzsdqrrroeF8zOLLkXmZbcK3G8d
oiDOSwL6Ds9Cc8wb2RI939OwFep+7dyA33ApF0gLHrnl47JyVgvAEyEvjd8xlkcEXgtO6dllL/CJ
hGiTJ3Pkuii7X5BJOSiI51kAbYX5wcS4QZ/ImBQm3MhPr00LIwxCHaYSAjNKvR5dHkXQCGlxuDfj
hN20/bk2LU4W1+AeuAon2EH20sKlR7zXfmugr3rZxxEgx8/oh/nplZUhYosG4WRD9eOkmM2yWrM+
wNBs7U2sKCayX8cHQi9kNStFZB5WsQNKfuNnzEYaqOfLaa/rPD1P0ewmTG1jDIqv/T7q+jTt8G1n
AP22u94nTLs9gjXXoL89676SufKP6RiBcZty4LznUtgL7eovlyKa9UUEnR6qRIhUoefpZyWyoihA
iVFe0StLejtUpvS4vzEP6C012EONNEztAquiLsRpYwftz2g9m2u9+9LBKrCv1YeLy/zz2PzMUbMF
eoezsFyN5XylaQPfE8vyFMNgwcbt9W3TMFn4l71FRm+6p1W0Yjd9nedNAwWpdkpZLUMshseHrSiI
OhJKPy9zIh5qBDYgRCob2ZXW+kHufDGkx4NTANEhhUviwtox2hKtoomjE1LY4d5DuDzeC7+lwVBj
TPjQ63b0yPE3cPv7I0nZ2og+2OihTMJVyEGsUqE1OWeZH1wTZPvG3Gp17E5PsDRL/p5pDwRUojti
umNHfHxR8r3Qq2khW8lJmpwIk76/Tqlwk88Bi8LSPT3OG7OjQn03rvQ7K4/QfFhe/IRTHtovg02x
VIWfsJEvn2HaIUSYQhdrqPLtSBAQ/+AuFQ5/r8+QnYnR5I7ZNlckgU62mHsciJ5Qy0anRHXW5FOj
Pwx/YDCSY2kWJlFEcjLEDU2/aurlME8imghJiATg6syXEoTwyTQuNeDg58SJNHpy+v16czjTnqvn
mvWH2S1HH+XDOAa+6QM9lRYr8OO4nHYC44+oZMq0CCRRctN4aFu/jRLbe4JZuemxoDXXXgPr1pGi
nyOv1MLM6/W3zL52Fnaf79nIEU+lVn8DnC03BJTTzsacXITc+CJWozq1Uu8bqD+PQwYLbkYFNWbK
UlEE4hOhMYfIrnFbJutixh7FYa1ijlmklH3dw83JfN86Kn+DguStHzFTiseKH7FRTZ3y4Tbp7TY6
CInYMTceGJ3nLDGMjCw3L+dBIIwztfmP08W6+L6xDGJYgpnvnhv5HRt29w4GSbxxxPuILuJdGznq
JQmQerxxa3XALc9J3oGHK/fwIfGMOD+fkASAMPV9YqlKOn/y7qmPAHZjeDTVRy6MZq1k8YfX+GN/
X7WJw/C25vdQvOPpRT/aaFRKS3Ic/m5qv45T2ubbtqzWMxmpEs4zNVpi56qi4Js7W3H/ooPcYDtl
uKAAdxgC+aTMZH/9ZqLwmWk/qRnvvfivVRvUeLsDaCuH8q+GAp2iFRMG5+Z88NeF0dWqIuSRRfLD
tmmYmBvBBG4Bn9msTiz7JbePJbAxOOgBk6BbLdAMFmyJSUeVux63rdYUTqJi7Z8xz7B1FcW/mQtz
YTXm7ZicTsO7Z93KAIrCHrm6uly32vp45luGvQaK2k3adc74nAOUm4AAZ17dNMmJTaCdu7VetHlL
+XIAwm54c4qyPrWEiecSOt0Wiz9SXoi0pYvqYOxj8D6x2u8uKb7TES8pmai4WMLsru+2ENhmRWi2
Z+WnptsvKSKvFckcPbFOOFtPsGwx8Umbm8pGWC0+pt7PDa1V9e2w76acXwu9m4qaUa7P/uqC2LOQ
ZpkFQe96FW3P1neCiJhRJqKspdtN0Lhl2019MM23ibL7dgy6XpIo3OwyXxjRmHv85kiXj+rljzpS
i2LZ+jiJBd0V981PbjU2Qg3Mkg7qgJrNRq+Bnt7CeRFKmLQMZ0DozZcbymoAth2Zpdnf/FwcySMW
jZssnieAkS1jZ7eueceHcWVVuVTrUpwpQg16p65CQ6DiyLTHNDYhQxymwty2RRwXPhXXbEA8Aj/z
d/rt3yovN0I1SMozEMLvci/9pxVS12/fBhUlLmg9xvdUNBikvuYvYioRpdUtna8MAFp0HOCk9Ax1
7B2RLaxMOrrZeO/fw3rPK0TtEo/Uok/drq5CdJgZCy1Z3oQYAHTXvd/HpvQZNFOlnkvpGhzALdtF
ds+hEeqEV0U08k+haW9ARjY7a17/HzlO2/ISRdTDLuaPxmBEWdxKPktFz/49VaOtBLiKR4Y1JHDZ
WMd8Bklmd1CKDglNwHWnbXGNrI/iaQ29PIlbenzTJjDOJFlEb2RgvrqyiAl/6n7OzMhe4O55X/S2
Ls8O0PBnliPg38ZpT16xKYbv2MfZNWQqETew5lJmqDhNnULNRHFrv4IQ73r6avbyRKqlKkwkFPX/
1IgzLGh/qwFgnQTShWC/Dl4xrtpF1/tahh86tGoNJ7R2mAJ0Bv+ld6B9naQsNvNGfoOdq3c9DaMa
kUNTjkwEE7/gkBnyuQ16f0ycUVkwORd/ztekFDIpwWx7KRWwGWXF7xd6viMGU/afEplYj15YaqB9
LTiY6oZ07aPKohxUwJ+l8Hf8GCBfk/VzSeSqsdtgW9U75tUtRQhw9zdyxtISbuw0i0YQo9ZFS6N/
acAlnMMLBU7vq8pfhVPuQSl976/BQ+FZmwO7OV0Cpu8Pa0oWORaq5a8ZkfCT2CPuWa7IgTl8uay0
HP1UBzw8B4KLPB51ll3XP4iIulVLX4tGn5mEOpmjUWHCI1HBJy4OrK1iMTWXRSVwXAs3hGO7p8Mc
0s6keKRznMuUIgUVEWEiimvbLtzszfZ7PfGhQYtztfcUosqX2pywg9MYqRYPPaKYokj9k7nHPHPF
KI33F8XtmAexCZaziGyWsdm8ejCGnHY8xs/gdcfxfdYy42bXhsPMdbV7OWha7SaLifFc3lp4gYAK
hAiERJLSVaWCm5aTbJoKscGb1nmiU4qRvjZhMmet99d+SAhjBF84uBxhdvCRGuPTw73L7cFNTp8c
1gywdsmWUcsUXi3P9xvbs7J+5zZS97bw31mzxPiZnVs2tVfr5RiYU7AESAEVdM3uG5i/i62glpTv
XV/UgumoR8M8Z6xNYIefULMyjthIWwIsJqgaApVbj/u3UhrFjuAJ2pkjkqtG6s27aluwMzh0dRgc
1qUY2X6S1C+OAPiEDehkJWmMQyiioquG3CoiKNJCiw8oxgKS6oW/qbmuUyfjkWfvw1GMXZ7g1yP+
rqDBTpIZtaXdtI61mZkIhN6eWGCTPf2NKnCmYnFVZAn1oZoWjHsQRsrxgoaWau5dWF/HrqMsZKTA
jctCpmnJVq0JB17D0Ewp7FHRhoyiMeChVwW7cZWeRwUYIm0FsrUJ0oFClxpTKkp5e2OmPWNXKRSD
dR9IoP9Ev/1bhr7gt/llkS6HLcJogYoliULNPb30rjVNkg/+kMUpmvo6pMvzhZKIT92/KLMZC5kM
9He+lOnJuBS6C48EhG5X8TvN39vQ0ybVNroxi62MgIPvasJmlZKtoz7y1uVE0HXeIlFKaeTyRkYb
ZAw3BiixUPCkOTU4M49dSlQiasqoDApfWrY1MRHHeCRPmbYC73lwOm3fYOuWzSgLVNSnVQcMt8ev
i6l8/EF4+vgKluwGl0ZUJ/cejo4q57kS31MLTk2h3+PC82dEJ8C+SBed2iNeAy4uvu8MqSIGoYrA
WYb0AEotgx34/KqHt5Msl3c526K17EQHqwMT+nJ4GcgNkeE0E1Xep0dU/4mdoiLlC3GXnS8VV0Sa
381HyYlnu8f70v2NhXdVFQBiF8M4lDu33kK54BJA6IgmfcimdGhSHo6dqJ27zgzZxJcFR1JWou18
spo5yzgU0nnbYwMyaiAu0+zhNAWfwEl9B+MxeSWXsNgp8laWv9210ffoQq8x07x4ujxZUltc8gLc
/V6J2o4i7+wo+5X7ktfHipLBAFbGZ8nHxPX/kMASz6dBn/9exzxN03Q71qOfQ2l7HmzVkPjnBFeK
0uMAPK5xug35ojP9Mi3ZDJUhb+8U9eS8EcQrB0YSA/aNsi2MfMHucv4NjJnAWxBhURgw2wrgUH56
NKDSSrV6VR0oO9R4ookY9KoBOP7aWudd+IL/EG8jc14m04cyS32Y64t4F40VKNLw9+Uu9jgzCDPP
OxcsmZ8ATjN54U8/apfb2tzl7EmDKZv65FABcLOtXHhu/Dq3p0yh86lU770DKdh3nrrH4Zx0U2Xp
brF/nR09t/MD/TpFcMTA8+6DJZDXHp4IpTBTTLfInzmwCglDlZKuPlLJKCbx1s5eCnZRDbsH+OoW
ZvBQFtyIB+r10w2USpy78GI1B6eUV7cHFKNf5h48bpZoeqJefkoI9FI8uE1BkbjLZaxT2VgKtWTF
KYvl6om03AKKejjE58Z07rNnVqvRejkQxBgLV98U/mGy+QtHiC0wCkSBmPpP3bfTrWljDv67C/7B
v8JgIYeYC8Nz+20k9j1TI7RBFRew7toulmZPQFJk2V6Jq33w6+5IcvGg3oAHdqGbV3Q9arl+2eto
sCbEW43iVfVjsKeQoDu9MotfyZSiT7VaQuriTjSHeDnkaNjRATtGVzLcLpeUGPUCdf6fAm2Nw/Oe
dNWlTSSkOOF6B73RIvro2oIGaVNw9PN2mHFgcDzN6jzKu+cRQfIa/rhTmfLlT4TUK8I5oLYppho0
DdyEPJtOW/lV9Y+OJlvT1/9NhiQHvsbKuXUWB3Iye05GmnRYwP+aGiN6adXVkxGdQLdvlloHOyaq
qQBC9JoxprFPFFz43zcgajpEIH0bM7jbQ5/yG96goaWfK3pMNZld/H8+aYfvWuTYyR2HGMug6N6v
FEYGIBd6DX5CkEWLOMdtrcH7Oc3yuiWbYTnx7NtPz+gzwA6hnG+sgzfbzfTRz+E0+4NFBOIGyNvc
OMrEedIFFAZt7QJF4P2f0kNrYVME1cza3gqDotEKJyNsOMJLMep7dZwhZAXKTRnrK9wQFm0Bv5xw
ogZU6xC41rHthBzuY1MIpKdgT3fR2Hrks0qm3l8rLceLazN8PcumZRHLAB2u8Kz9RWk/UfH2HabL
XI0NSqfJWcUJ3wkB5eSeiaKBTIPJzaSiyE2HKEDoW+ew50hAcseWeFEwRLwyG+AC2uoA/YvmID8f
jfGQImRrb26ilg5s33yRdkD1rDj4hPOFsGGC7xQiTOHFxlqUck3af4FUbs7do1Bp6Vbm96LOfjM/
+2imAxLcTsQVLVS682u1WNLD1xtvaGk6b7FIAxfjc4P3IDM5huJVon8H4kO1bG5Kd5+qQyO4miyD
qTVyTpxlnFOIJIN61qlVuHI12lBgo/ISL15SWn4azgBzIIpSq9/RW/0GVJ1yeHHsWhn7dopjsQ/f
tu39YfQ7R1FzVFgBaWoQxPgTQc9A/qc8L1IQVaLp9XFdcTwF455V1XAe4i5fjqXq0wAoVI2LqV+a
GnwhV3FbyBZ1R6LSK2QePzNYnsismGeNMjiUzS1cc5D9jvz1MStVRddkaKbKqhP6KNX4e69Qk5Ko
cljSONyew1uNXHbb+tfKjsf4281PA2DjXiw8/Xctj6rkrMGKW3W2YKzxaW8wLQUdt/Bak2zjjdIz
HAfrTwLpzzN/VRNbMlHU0tT88D57KMwipXiOXKgBx6MFwrTZXUHX626alJZcltBDpN2oHMsK1SIy
xUNbugBjb3sGdxvIrkPlfzfghwKmJIzQADyEGo7t+Rh3UHBlVM1eFZujS5tw4rcPsOMnWoyf1E9+
X+STQeEum71s2DeJt+LzpCX6lvI1GsrfYuwXGIkUagYugsbJLscaLVzvFbwM8N2pF3GPWDig1uFT
duPaKSvKkcmmho5ii/2aPGRAB+mFxdGWb1R7V5U+A94lz/aF4WUFaJ33I5YKHfmaCoVHpTzaXk+Y
NLVG77X0/f8/M4R7cZCgfnJiAXa4DLgwwe0gPnsiOExZ7Rqzwoy9v5/6T0Mphqm9yUzp5y9k6b5/
NVDQLTiCmSJGtB7HrOP78rlDePf1SVp48bdVBKRuOKjQ1npTq3Pm4Riz2/0YHSAMbZLkWkXUm+zt
HKOkvMo1Qu545JbZR4tNHf133iiz8KYOEwALu4EwJQ9RxbonyB2LkuwXFK1eRH5m2tRSsOfbgTzS
ZLAR6JlZT1jm8ppzPhI11/FkJc+gAA/VBLlPzAkHRTnKMbZEZOAyTVC653nTBn31vawtGK8Qx4qZ
15ZNibVSmgsxLkvRiRgC6oOWKOSVNl9y00JFyaCNCEbo+kFf/A6Gqh2h3nV4A60BxB5oxFPmNSvF
13pDOJFoJcCZ1PQdJFZJl4yBPSy+QyzD/lU6CabJmO7wXaIsroBUsitKGPowvBVDzhTj/yOCItIg
99re8bBbhPZnzg/iBjQcIuSvCMUM3grAHtYuMANIEl0fwlmFa9EglDvypgR9oK75BSR+zOp+mC9t
7P6/xsEuLXhYeI8m/eLMA3WZw5JNzPd0OYkAwv1YQbsWPnc1SSxnq3s0UnAtkuVAWoIxQrNVf4In
tsVml10O6A07uR/egYOOsssRnKRGifqJcnjiassCD7VuJj0Q+RLv+s0m8ajrVtov6SKlQ3PXkSi3
2IrKldVgklQEIi/ngOzIyLiAK8vXvCO5MLRahBRdg4HU/gFmadwabdFvrkfgC4OVUGSpjCFxBcl1
A11XfzlU7LNAeafkrYqy0jrAClkU9rv2m41C0bB09LD5ImntBEVWjJFiGMjea0/sgKY0sIQfT0Mz
7ATwidLpwkDCRSLn50jifxuRUiIA+Cx41SBjVU3ClOM9J9Ko3IBSo48qfQbqyBng4OKciOh4lvXR
8fEgHa+kc24HB3a9AP/LHA/2qi72lThWO/ymmUfdD6IJd1ptrfp/gYMlq6KRulNRgIKJ6RU2Ugq5
xpgEliohCZkjw9i8Rwml29QNHIFjT6AwFPSIbslbq8da+UlMSwvlgsBivOQ5C6mN7Y1OC5rkuGm6
8wB01NM77BQJpOOHN8aFoM9oMkNWNv/vMf2wXDY0fHmIu0i1GnoT8hfW6ZHFJ+u6UdAYDJVzX49I
IfjC8u1RHzd9kTUm+bwo0xcbwNe/IOGgoC2F8uSgPi5VQoYIHNNE/ev8pDUtmWj4KoI+sC6FyNEb
vAOn/U19JuObQrjP3e2nNXe50T0QUad7U0EF+bk4ZWllVcGDvSeK47tu/UuBY2pv3jRDfZu5wNUu
3ej55hloN036jLs7FN5vpI0emzOJZZnsEe6fZGzIQl59fsrWLI+ZH6NdgmtbOsVrm2jlIiPJmKcc
rCKja/5A8raEF+OpVSclGCYs5sxjNdSGsfR6QVsRwIBeXAv7a200254Wsj9VTcjqGdAsPIVxu60z
XpWWsGLFyxXCTjVZW89v5Qgcd2H7BlYUHYqTwUdnPpd2QgkMQ9DYTvkCbhW4FuECKqPoM/ML3PSi
UBxi0km3+Es2r+tmBXBmah26DBfmo7mce9Ez3vv4pDcFmTH/bjMzjwKLBU1geM9D60QIFfYw29Om
n1me/muvKmnxRPKRsvkcnfym5cK9EK6TNnNqxgOiAdzJXbAG2IiBJ9Y8Di3T+D6Ls0AsEnD/FtiN
89FrjGiIUsrLfboK7n3xTsRQKBF6SzgJZGDW+MMEeHjGeWQ3NL8bPZ49rNdmpkivTDfNpyuMaXBO
6uJviUtwePk0W/1fzG9hbXCkajRkdul/wfQmm86ClQOBzXqLOz5+GEaoPMITOOUG1tTBk5IseHOk
4dl28iYybndFPaOeH4ol8xurRBVP+43D/p/lLjaDlPD0GlFOKROT+EXwpjN6oLXvM6zX+ZnYVawo
j4KQuVhcm6bRZR3HYVAu7h04PZRaAfoincB6lf5p30O35dNc4ZoLbO5ZDS9A+4rGJvTqwcckz1CZ
y6yZDSaquZExESnF4cbgYZON6Izw83ogCuAL1zAG2GNKHkRZpc4iRrpJjFxomvwtfyi3vLB74EH9
PtTSDECKu3H0mwwyRKeNOIxm7zf4LLIrxQY/8FNwFF9uIJ/xRCEFukDK+y2nCPOTLZ3OBF5rv3TY
DxyaR9wSn0Uo2GJ9VDlCe6ixm15KB9BbKU+PhEmxMxheSpRlwoe9kGdMnF9+00nvp181E6j8cXrL
6u4Bb157XtvUpTiyqNtVOEiDyAFvgmnbu9Y+InAL3A32JsKg9jGgwFwbdbTBTsKBNfN4P41y2UZ+
G4jpyGxa/vCbmZEn67M+zX5zlzivZfCGwfcoe8TAcYw+VVWjQgnf1ZN7dpCvmUWQc7GOpZH8ZeSq
HvwcKfpaYFGcrlKYNP6WoSLMFS+OTh5bBTGGcYfNiNrJHt2LRklsCNoSsoaeAmHvZE3QH8qkTkko
5z8O4cIL+m42ElnPLfVKvFYbyz2PIug8dQs3UoZru/P14jdWOaqYqXj+R1NWUbQh+LcckoCF2aOT
qPuzxI7ZOb5ZIqX9jIOTegeQ40VtNf71CnmzQyFq+uLZcpx74ZGH9dbrYLioYnXjUFQmYp59KPdM
qNvCwKC0zBQGlqFmxUL/4iISA9c9JRa7Z6h9bXvlqI5Gl7mMm6+CENHrRoGc1CJSe4i7oIyhNPnn
B3WTuCZbbjxvUPa4DfWR3EKtjdM4BrQrl1GrMp61+XPf563R8hHP26dpXy0UZ2W0du2WDHDqoAjT
D2GhjQT+oRCRrgXf1KwSxR+KcUkPjiOt3os4Lnz24nhs8JmgCIFmaVvpRBL9QmgfdlZ3ycWRTOzH
RlofEjpvyc8ZF2b2SYdDU9qUG/YB5h3/nXrhcOu4nOiBOTAwdGtr/auAf8SmCX0eHsukSOwvt81E
YCtF1vBmcMT5m5kh4SYOlzMljjWVHmB9/heLKcHMzfRhLupv7z0kyTPrCvQMZ5PX4M4pHuSHaEOj
I+a3HleSmSU5d2AKxtK5o0ePWZGBFeXp6LM/S/JEylUXxouLFx4nnEWB5+TsF6QEKVKVtXKx4tKW
owQxYJ+gGIYBD8RTYvifUpylCwWFkIS56MauYUXPj9GfqQw01NyV3nY07KRBwN1cTqab4upgtjlp
abzTdawFhh/y3xKsCVN55Yv+K1inbd6K+xOaAPyEQiJyV8WIZxqWLIQwD+F9cZMuR7SD4KPin8tA
ffu8DdS65FLlM1uwG5g9AXAjdabfrlK1kkztIRPlGv9d5JbyM6IsOLYG8UkajeNYZlWtHwxiur3K
aamqS0Y/yEPWJiLPCZ/3CXWbg47ys6xiJQQFlrWHJ/4wtDmD1YnhvkM+1oDt+mTOF/68rpB81hW6
6BvWBBC0RGCBWk8Zz+0epCd21gKESzz+XcZMWz2blE3+0OX8qNRuhXg+S1xXp3CVGgZhUuRQAs0K
K3QTyeeiJFuKdsXcM5fNCK2bT1XNQ/Vf6ItejHerpEteZsKV6nXejb5DWmN1we2IxU+10TNA478R
kxAVV2AGCgWF5rgfT3h2M+OAomHRX/PgUQYR/q7rwFhpPcZ7t9d2EGjhX3ivQNzyve1+6ENpwBZW
bI4c69UyN5T+bYZUiEUnpQ0ygYs+SvGXWt83shNSPISrSbHWsrGQLzvCJe4mTtP0bcEiLgbTVhwC
2+KJdqQtVn0LpJ79m67DwIWpby3ZUpuUtQHjeoU5Z5W1wDlfJm4JW11vN8/3F50Zv7tkVX3m3NJu
822i1Lb3AppZmMYfoDoG62/5sLhOzNVQHSKnR8AH+f5DMSoDPF1HYcV3S5aFBq90HZLoEiHDE63L
UZ7v/4GCSXYgTiWhKHJr7s3pDt3cBjvrCNB49k9QCkwC87KMmj7eGIh7gRBi52J4aNANHktmsWvI
5t40k4bGQOb8bMXlIuv06k9IDizX3pF0FkLIttNExx4c6u7IRiXO7OYbwF2mUOnxwXdLs5IkCjGB
CjPMZgUh/M2LeRatQlAhtDqWn+kO2dafB/wEWVk9A9YZG2GYcaF030Bh3IpFlXAqcGI0Yca7UZDR
h/9gqhF4s+0lF0b/Hk6mn02qIuhA5iLH5GVSkwKQT5Dsu2C0bkKTVL+VHYBPb7/zjthMpUOqT5pu
c2zm/cWpFPae8uaw7dz0eC+pnwDA1L4dCNN88seEznrHjP0aRv3bhtPn62j7nWHRRv6hZOuH3a0Y
Sky2ifxb8c/q8NYZ7m1WxdutlOy96h/QPTpywC11T0d8FO4zp73gcrbIUNsivMV57Zgz0BxKuZ7g
9yApOygIARfUUwdgYY2cLKJtL5ZCQ0idjZ5Psbf4XXGAyKmgEncRNZ38PzLFr7hKJpoRpt/4Ji4J
iy1F4uKnpbta3s84+8scr89YOWKYbfhs2dv1yVAA5mXlDXvLH7gh9FFmGvpq5Wlh8PWDkMSZjxAn
yCytlW3fyA4Is6UzqcC9ZGCdNZUN8dKrpy1InEBv9jafAY6p55V8zKFQyCLAQdAx02EgKvKAVAzT
Uw0Yy2g9GoDEw0MDCQJJ6lAMRQfg1nB7xacXmpq2R/pDyGAKaYZsHjJPlXbv5zKtVtXmO5WUFgLl
C07pG0M0D11di4KzNCh+f2rIWZ46E9jOQyzMMwcFHOeeuXlxfFb9rS/FMmK0wRLuA4GPEVbdBuvj
CbKGa85X2LHVUvArmOGsvBIz9Y1SI5bwse2aJdj8ZW757SXAsb57c7V1fnMlTZPFVKRvDzO5+4Rt
F2Lyd+cVLqFkwIBv+BBlqtqEzhWE6E5VbyVv97qjbia6xpumUicL2ZwKNdnHE23lXfRiHP2lhqg3
P2grC3FDjtIYFFl3yOdSGMY8g+9G1fF6PCzsBa1F45HIykz47iFUb/rsIZSBQcPzv44+N4rF75eJ
3XQtMy20CrxTd0e+ZN9TImRp/qiJ4ZNJtxySS9OG6cyctK/3HrTPImzMTl7uQ0t2GAmh+aDEjH0u
sTp8kqFwojh66nqYM8LfjE+H7Tuf6952jvsMKKEUCJxaKF3iCSyQmyQfpUm4gwEZOcwRQuKYlcGo
it3zAK8LaGDKrjiC2DOXD3st63OSUNV6+FOqnC9q7RbbKRQ5z1B75eie+Xu9NgCAOoMTnLcvBNaC
eER6qFu4LSFBTpPff5aCPN9qAqJvEBqQ4BeHm9sDlc2J9pJrUbbuuBJ3VpkLWkQHtks/lwoodFwv
kx/LyITYeIUgcXF4em3X9WDh0vNHgifcxUxBMkgJ4isteoAHW3hrEzGJKtMsy6DNOgDm022CSb5J
kcExeNhx2zWadba4zKRWW5+IEEkOXPoBAdkYnXnFtKvkjC6k1s1dpin94zFJJ7CFLkGpTCuSlffA
rOQYwKBtfzt+CHCoGSP5KkHAFWT0DZQjCZV/sJSC6BDbmLhfuR/0GGMKT5p8WCxphQp9Dfxajp9X
Wt7PUkUM/mJHn2Su+tvUuEEUCS3mAV203i9WGQneGOPehFpryvWQPg7Sx1/NHFb1aXXL8LA2g3TX
xFn8WppJAgKxFFo3KpTiOViDzVftr8rd6aOUnhEMiN6Lcf+/sjkDmXlWPpAEK5RrRrzRMxkVpvXD
Vw/H0eZP5Vkg9C89AdpCmMIoZsH6ETHICOVmAJhzEyygnxsj88+OdBIx3uRa2Gqh6mBx85nhEYaV
MNm7DucVs15cVgWKyhW2kYBOT4NaFK1EZN2Lc6kcKuhf0OeS+EjWxfs2Ra0g8PfEb4VxWlNKjttk
XrVlGGmA/6EXdRG0aXSJe5XPlqnStQEPO0R+45G9Gp2SbWQF/fnQP/Lb9wz/vBU08tghsS50Mdn2
DB2nMeHAY4XSdHK9/vkYxVlhCWRrj+LnUUmzsnKAUvtWw6kppuznmMUm6ocTt7LorwtV9/NMDcmh
R+6GkexZ10apZkXmWrY84fislnLQfKTsD/CSp4OXLXf23OLUD409tBZQ22q+3vWb0AvWysS6iu88
q5ppICV5VjClMNTq4Wnb7Ixi0ADd4VOyyZaMC4CdWSMlj2IDUhulQfRvjKvsi2zv5PA/zB63LUok
E0WEOqCyIGBFE2QrVyxmJEfJwxp1St8Sr8iRNQsKq7/SC8lQZSNGGIf4WOpPff52mmiaFY8qn8CB
oWV70wPHgBwVCJeykGO3BWjUl/Hoa7VkzeQKMAfqAp1yuUXhDAIp8raytQJi4HD5hz4yrUVz7KzU
5IEsvrFDyF3/vlILte8J2zbe6rEdIQJecKq4YQbznGP52BkBDLzzoxEqifY9zLZr051bA6USmPJ+
0XYDMWoSCjZGJGHvK9Sx2gI25NIpEDbrwg3OlAwv+e8N9lsJDffMNwLAEegITPqI8yIq6tgF0+Hh
3fE82brZ1BF1lLOun1s3xMnmysnPHB3gK1DnOeZ/bX301H1NGjNrosCyPjy7gyumkIEJECqhFREb
664g/wPinOU1ZmFsS0ihaTpfy1HYWdcLsP3tzZgLiX//Rt+qHqlZlgflBpHOrEu7cwbfzhaezEAM
9IEnAuX5/nndI65tAsEmpGdHaCf5yJr2cjzAews0V3ul9H4iMZKbpX1h8x2IVH0Ys/NypLJpiYy7
f+wfrxfCOKiaJudLq4JdOEb1CvLey3Z2PNtQmfMJ3sUayHcnWWNF6ypqEHm2s73gmZ83rVxoVjLI
4otcgZs1ZJREEs0glrJ2uYSrEmETml2UXnCVYL9qvr3STBHoeWR8RgxFBIF21XMg9URjtDMZThZ9
iw88N3kkBQSfNm8Y8VHsBoxTTD3wuIoWTAdY1yvWfRvibgLryETn8WirvwTDdGswnw4W+w4eTvoP
gT4Ej/vyXe680TWdOJgz7+gs8Ec46WQzi59ry5QfXzmrC78tMHaO/XeT/LPTPvXHYu6WNzHGeFAG
ZG5vWmr+LcExnAgHWdtMtaCy2qoOVPVTRKei1wMCFo/tYeCxEd6IlFWSAcS25TVmrM2pAb+CAQ8d
cv8EPGozqPk+8RW0ECy2I/WssIXIMtCC9lU/m/jkHcAHKJNBLD8UobE3QCezTAjTtWdGhP8ShDnv
r8+xtEdaVTDw9E6QHpOXedDC5R+PdJdQSuRNiMAnA1vgt5NC/Uc5Bbl0W8OvSfIMSfQwe148bpKg
j7KCUE6mrs2A6xlUPvLP+RO467i5FQpMNIt/j/13wCOGcYxqG9cPTu4wolbJIgtoMxaYV/a5+FyI
UpO+PxnpRzmY5yg6iKqWWAP1lDY7OXc6JIvyRwuNQAjfUiTsmaWTYU3RQ/KXFepU+lcGXWhiklvD
MEhcCdst9Eh94KLez1uiVXzP8RAZiRRsGlqirdGBIEQl9fqs9ukDI06GIwQpuAcd/l1ACWkj5U4z
gctdYMDpx8WttoPDOqaFGQDnK0yYs0ce7zWrZUChGxyFAwbukDOOi9yv2T1iyaF6iBmWtCJS+8gb
HFYTpLnyRa/eYcQ/2iEsJ5xIP+idbh/HrxZhXACD9o6O1cuGuBBVP39ie2Hr2vE2Jjx/v2ydIhpU
s8rwKrstI47p2cWchUvlJ/iwrniSUuCKMhAch68zOS84L6nDT/N60sX79085hjkP8F7jonUiooSb
A+Vpk7lIYBi3E8+GbgpMMqw4MbBs0hSPPuVezrvfghd7Pj/P22u3CxFqV+2nkLW5PgJLzjWoCIzD
77vWtvfNy6xs+W0G8Hs+73nGW9LuZJvXCc94jjGnSYT/KM1hhYvNBEs+EeySe3rmu3s+pH3wui44
Ro1y5DK03vjv0+AFp/sVZkn27RCwIhdj+DPYC2fKLgSDfZEMi4/oxI34GNLLCaVgYZMunTXSBikP
/rOC5jhLU+LA8fOzKBv0v4fNsElYU9hSFt9rRBuGtc36VAnYurMQvOOKiC4x8HMV6mqx+DQlprjp
zFeb+Wbbw+QidrV6dWjRxL7GsooWCD+kqXaWZqpNvm8rdUfqdSRXGZCgXn+/K+nQ6uwH366Bwk9y
jae5XYH5N+LXbj+SZQvkg81/7HG3NKjyCcRzyJutrvFz9jqr4jU2vJzYPpzT40QNJtWiyZNIgZZA
acsrBdPhgXzkYRUSM4mQGEyvXhcep/uVNKJZYO1t0zp20DLi4XtBYHGj2uF2h/BSCYQsyO/7xsp9
wLxOZHr9/JSlalWxH+sfsz6VJt4bF1mnWU+UbDt4Hc5XjNDZTKtQoWLeGXOBYI/A36VWwT/T/HeP
ptCPy9+S8zknNA0y16o098V5zMp9kv/XhcB4AlWEvjdunRnJIXn10zv/Yj3tKOCV358UfN0jMG3I
VvP7X5nGCimgVF969i9pz1eu/C61w7dLiqM0iCdhvS0OkE7GS2V982ogkGr5j64cdD9xQ7MyACUq
8YVkNCVkOTJsPxnwSvqKF0a4zCkXx+kNchJnipmazpGKfV4kdtn9X7rVSMOzdzCVhU9D91kRYHn9
0Qr6T3J/VKAD1sTHAzX3w3UmWkbZe+kSmxw4FcFzlAySpSUDpXHeA0hZFRUo2OU2ezHzVrjH9yhw
4TBEAxOqv1FEQi7s8ap4AdjleeU+vI0hlltqn9IbZItHh7ma/54Isb7Cqj7I1+DQo9aYVUUgHdvB
ZNMVClrbAMVQje/AIY7iwK6sWfLa/wzue/ttiYnyxOXB0Mk3C4ECR6TkWxLfbp9p6869w+c0ZJ6G
ZJ7FuEka4OfCMlF7SaWeG3K+TnT18x8rGdL35ocov5l6qRjroTmIa3ANcsAuwQC3+A7FbviWQGCI
g2hKwoexyLfTkGxshhdrYLiKCQCjkQBy9T/95HOvvcb2tkdiZZoXqkA+u+gSiXcJcjTuWHs2f4WD
IRG7BZNdPf7se0qU0C+Azq3iJYSupLmhnsH8bo7hWjuRkN1EL6FtM6SGZ1w72BDp53k1J+92AULK
SexBC2mxubE3G5B8SlcbMync4YW+8U7EaVi6j5maMR88EpkYo9qbhv4LcedUFN8BHvYMAjEMENc7
wVFN7PyIP62FPfCBeXqDFCCeLDYWBmELVMCGJazlBW5iktX6xgs4KZ7b5lI2GtSkDLvzzvpRp/Cb
LgEQHn2ASP7vb/Ssv6dnYl0RbiXpxG2cCLIfxsssj3TevZ2OcCez85KdZlbc7JoaLl7+W+si6cXl
bnfur22f9swYzwOeg6MOqXgVWY1ydXyuH0mCBql/rYMXdyLQUk/xepXEKtn+vvsWKdpIKm+RB3hW
AZyrtNiwn0otjQKNK33GXumkGWH5y6uQg9rXTYPIwf4AS2jMCPamfPSv/2OKTc5pQIz4l3i3FK7+
/N9syzX2E5XOSsZGnqsmI7bNC8Gvk9E3GfpzB1dOoG9F1Xocii10lB5ADmLE6+0sY+/vXzLDJSOe
bCMphI4pwfQIYfvUys+XWtiLQSVDxN/5uw30TeHGyQj+4QgNKzGqRxEjXMQJBkNjbcynZbcSKYq8
8P7l2mMUv1qXwd1jCd6CzSrqDrHt5qcH+ZYbt8QCJyxddgbAOgfrtNnb0+WCCKBtNCUmrTAa+XiK
8ZTjR6wPH/rhRfcU6ww4wStpkej1+ws1u5rhAv9YVFw5TICosdRDJC5SndE/F14biEQkcd8F17vq
hxqju2x9fEZSiVMF6ybcUGCMK1+u3ssdRQFZAowq8o8MQrm7o8c+HmFXmDsPA5AiyTnvKAQQZigc
C12mvF3qLiKxGAV1cbOvtTO/8yk0LAgn4jA84Ktf0CwrojMSQFaPF77Dc6QyAyadhs2iM2ZcezpO
DWKpFKpAtcl43rq8YSL2jfQSfo+nIHWQ6v/k9+75rXtVPs4I3y6TolsvBdq66BXfDbAELWCOC8PA
T7FCVp7B1/0TEgLALb3dyVdqlz3ZnyjVVl5Zpxuoe7oaNsrRFQKihhZqbOXMtkrEzQFXdkNESekL
oTc6bSXVa786IV4eOW7n6u90+yHXQ6vjkZn3Ni62Dzh1M+Wgb6ODV/tCxcX7/jOFopo8NU6PFbQJ
hlZoxu37y4pMrdDprCGf0097FlNcVjtoHQyJ+P4OkPccOt1q/g+UsezE4WaCiolhjzJJhPvG0rqy
UYpaflL2r1RS+Pu1q+xqtHuFHEwS786oUuOfn8R6SsO4AhGcTptEY2sLSarm67n7JMSiaEeE+iU2
vdNlv/tomb57gRDSRYmAmbFIzOMNDZDHDN8WrG4BwlpzWvNEVMSAjvBBbJfbVstXSJohrHFLfuNt
S7fc1T/cp5dNzSX9IcqFjiIhkz9OiMbvQyqfHlmBSvHt6FKfES2YQKYFCLAlcqf52xMBDD1+wF9o
fsdX3RLvtCrocs66mqRqxr3OlKsPWKiuMlG9iyrHoupkakNnES44ZuKzVv3ilw1cmt3bjDqXlczr
uEbBOScaSa9QNPJLDsJbY9j23BhqcWmFXCTfEI+DGInGO3A1YRY1x7YCgQjNX8HeVfmhrflKyjJo
IyAIbi6d/YpHysqAp4QkHdta8/Q87/vzSjKbp/q/zH1PhCtv5UCd119XCSQ4+S1MlYBRGh2L7Oay
FA5VY7Z8pgvwojHdKSd1SVzmUBnhQcQxyos1TYsfcA84RZk1Abb2QXMhIzQnbuKF8mZXJsWmD1al
796xUoXuvzbZCoLMerTY9mHQA7r5pvZYjPivvEUiotTVO48nuFtTols6pAD++hBdjRnepsdhh7+r
w0vVOzt4ABltwdoYgbMYBcOGQHiC51Kyj3YflyHb1MAocD38x5kSYrGxpDEcsf5Y6DVJffgr6kW5
gRd4TNqNbMlU+4a51mF7NukjmJPI4Ds3vquxY8ZsPs26Dh1iShevW0ZNGvXmgW4+WImKGM4/lzdR
1ebWA8pcdh0FfTOAz77mCrPY9E29EOKuM278APdkZRdQiDtomis+tDgqmi7Q+JA4gsTGoxfOAyXL
tEFJoZ768W48q9H0K88YBEHY7U5mh/rs5MaADSjlHxZFouxzbYK1UivNdcCm5PJ7lmPWVeibq4gu
aXp2qJS5G2c87nu5wkHqW6jXZgvvrXfBy2Q4eFFql+S+HacdV+T4NLeGYPDoWiGnI48LPPssim4c
orx2GftqYVUrNnSscjZXSK8bD4KnkYg5btIucxNKPhaJaaGon8L5FkeiuROxLnwCRipkaZZmdunZ
XJ24KyLsNTcuPvhggI+m6B3u3rIScocSDbvp0udv1lG5aij1RGwIaq6Jj0aNmxbE32vx+wsrulwV
TxFsqPbBWB8AOK57t+RYcEMawa/AGMvU6xxWyz5HKPAlucXd+YbFyozY/I+muSNcrdrl3JWnyoVi
O0s007bO6wP4XdaXlUxx8/A2BDjAUYnwNnX9lSz9dR8RXHUtaaOidjk1YIGF8bsB2M7IVpT44aaD
YQBTpR3mjQRFouQ9NVuoZyOWz/P1QNbIYJAee4p1EqeyMWnxQzAMHjxCOLBHz5p58YEP0mHB4HEh
1i0XPPAzefjFzEHRbkrTTv/X3b9PWC/4p5xzPL4kXSJBqMcQ7coPeAytX/c4blj2Mbs/oUykRqz+
hPC/pdRra7z8Vc2en1ydhxe4w5aj/gDlduY1+pcA3XayvSxJYxi3q1W52k7PhEFOXpQiKLIUlhLZ
wLBYCdYq+Z+qYmAT9iXN2HHREL2G2PJiDxhKGx0p6lpYuIzsW9RwfN9nZRoYjOwFXoz/0zk78r90
/t23psK2c61ixUUYNvp6sDSbGsHbnTz61DNKI++Q36Zuwd3IU8xD+siicrQOstt9nSSkAVSVkoJj
Qek6jCNI6un7hDykhTm+7nOab5CSqmZxd7ZexWMp+6JYku2LR+2bQ7nHofIMyX3G+UViEHvhCglg
VT5kmVh93eDpbaZ/2SUCAFqVJKPxYuxnGIR+q71Zeh9LmMggIR/MzLmyi71XYue5oexQg+/kzaYX
tpNnOrgeFJnNHG0xUWN3ChWBKYIBzIcSxTXgAb7LPe/a0L2EqXzuskb+gYPdnbGTPGYsolDhyN2b
WS2dqG/3LRML42sNlaUlhO66ETASA5EOyY6TtlDOFXAb/W9pZ2301wB4oacdHYk537PX5JiU6n4d
+WRWbFzG89gyhk8jkWX+pJQEJf/5MJr8NkgEMaMEc21bfLJj4E5KCTWFwE7nEa6ifjQauAaXiHh+
5lJG95R2ggdNfMjaiBMC35ayMiBGW1KMYy6lefvPl3txoYu/W6f+EdySpJZectOfJvXIwm0AY6Y7
MO+13ZEC+V0kY641wYlW1DgX9t6kr0eJCigHR4NiX/D7BGtosyx/rLg2SKY+eHzYUpTD4Lm4e14Y
oipGkW6Z2Qlqr3gBtx3BFOVvNSHx0jv5uu056CUBK99cgEVhJVmqimaGj4w6YM7XYYn2TdRVWRnu
VqCJnswi4/vLv46H1cZqtziSSn5a7tuIl+n69rlITXGBXjQaDCty1A085hTTX7QOU899gU/0IevE
6YQWtEW6G2Xx4SEIa9Kd8YlsEL5SA0IyzezXDuHWEZcMylHthtZwFRYS2+nxzBpCpkEbE/DoEb+x
R6Ch6lsRGQp+dqqgxf7odbGdW7C/nStzMT5fpKGCpHHGpam7i9h49qTE6lAALh8OIK/gcQTkS0RQ
ccDEyYG4Cmq8RZAC1sNxPLltpg8CIgdtW4PUr6+VRmqeLEup/Jg4J2m+KmeDSG8HhVvgi3ltl/HE
z4mILjP+0YjckkVq5DslB6OJmru40xMwbG7DFk9diX3DfU0DKfw80qFgakp3GPp/EnXgzBFaTQy7
pk3tzmUFP/cDD5h7Srv8Q8D7IsyQ94ldyznXzTfFw9SIx39paIiZcfPK0o+GN+RIJZWomIftzcXo
kooD6mRoG18u/9LA6yHyoHHLU7uLN/BBkl1URxEEXnINWEVXSoR9K1o7CcFTe7+rlLBJfr/ilqE9
bwAH3Brih1oUug7jp1+MZuUl1znFvbAxEdo6o+jsg5Gqyz6JRZ6MzVmJjzPmobJfurUiFDsXuQym
3C/FiJ5vtjHwOPMqWiH+2hmpiCnKjrKbw+IovBAPxCnXXz1lCl8d9O/mPIO46564fCBXRiTEskLA
K7amY6iAFQkUaNO0fnTlEPrbc/jl7rGHBkyvm+fywC1VNzW6P5ZoHPvRASeFL3M/V5xSLkqtGTPa
4s6o6VRd2Kbajt/Jui9WEwn6IqXQPGp+TAtqQ8jus34Nk6+ynuIZoq/kkc/cVE6UVGCRIOIC/MX5
E1BiC0G4mAHIj/Gm8H4bd+zsjV16Uofs7hIJcbz8RnsBd2HQtv+pMzP7EteApMlnqOO0sazSklGA
5L0Lcfo+MrRyyonDyMYWKzhotAcPjfLY20VILgCLlH+yXUMgSqwQ8xUgrdlWQS68FzcrX5GwYHJD
AcCUbUU3xHOA2iIgNq9G6S9XVcSKxGKqVbj8V8pKTVlI6mOyduXJ8ZOPw3f8pTq/nHf/SD/vjKK/
w6hgTKGVxm7eM/+6lmtDlsu2FXXWQWN8ITyDlpYzSMpDYQ3HsaT3ihcbFBZK0T0NP0h9NDH6jOkb
/rLAS0wIYhKR8fSJHJcLzUi3CBIDlmrax9sVW81kEj2qqvYmTQQ26VyGBxtJ5tjNraJLv/fNxH7g
QBHjHeJ2D3jPP0kqFKjmQm5F9mmCO9IT8rMzduFVzjE1nAxjG8gP0FFHn1syM+4C5i+4NmSurbmQ
w55sVWIH+vizx5ufI7AjZw47FNkfwy4xXoM0JNs5bD5TFpIJJr0gc+WBn/ChcPlEqb2AoFHKB42k
AmS1atTSbD5zodSutIk2kTrUKQpOjsHVut59OQLDg6doqCfOD2A9cJO9twksQWEq9AOTvKU+EWSy
mtCEQ5qfbfaKT7s7dduaMzzPnJQSRvtC2h0nKWuLYgRGYykY6HaBlj2BsCdtgdshK2H7q3Sch5f7
5gOjKc8IDVeve6PfzAuq68lKNgnpOnBcH3Wc+6zmAK8ufiHo0HSp7OXcNRHHpXo3MG7EnAF+i1dz
HllJp26QK0i+Hsgre/3FIYZaTjXUo5E//1svf79YrZ+JxFo7VqNb9tUaTYZQrRYXBbekzhqN6qkl
fe72t8fJOXObJ5cY29FzAtGF1rBDbjq/4wNRXxXmFK1DFzE6Za5cRfQcPgeBMDaL0YzyxfTBJ+WZ
KjV0ZmSdYI3dlwiJa2twcktriZRbmvsW48SYrHrYBleJfUvrSQq8Ba1o5yP4Sbp06wHi2lm0jbaJ
6UJilp6zKjP9aoyPT4tQiI7FcGDUWPa3Tjbd0RSe1A8XbFTGapzkjaALH2mNDRwOyFbdiDQXq0ZH
UvPmzlbjGXlTiSVf4gwNstc+joAKTd/rhCbtTSVXrk1qdLWKFHhewzFX5zNwyl+m8VQLD2DPe5YM
t0MUlSRsca1DNHTihXEQraZDgz5XXgIVVIG0QVnAUxN7iB83mA50PTjf8oP9G+V5sqQ6WCAwESxo
4/AKSAvXOH9mqB2o3SxXEZE5rPxG9m5zmqw+QzqXP+hcZap9VzFBVQieCi7qlR8yHMU/ov0+aFOz
vlQ3D9nlK8sWFk2VwzkbfQW/i+juJXbiUj6V8XPjOK3NAr+SDLSWuL90RuTqKXw3Lzk2JwXY08q7
1FZLXlnk6jdccIAKaX//9/gH/T9wSRZt9extME8Rrd/7w/LjqkjLjrhbFp2ApxzhMMpY0aLtwaQd
SqvGdApg+/NziuH5AoW0xXGKssaf07/p74Wjt9x0OHWyZsFWd8EaNpxRFmWxd6W//3KVXiBnMZvS
XZjJvk0LRJtjphwTS/mkbWtdLUuVYyyFZsNj4tS7MX6aM0rohWirmchuQtF3tutJDtAC9gN8vCfS
0CjFG1mIDE9KvPFU8SoXWJbFPcU0GhDhdI1C/ofiPgavayeDiEiLf1/XW0Cfa2RZIIzSIH74w238
m8I+xTWZD0gGQLZGuh8Fqx/DL5rs7+yGKxvh3LgSYs3B4JX++ui+4QN5KtJXl6Fh71I02B0ba0K0
+flnr9pJoceP+wAfYVFbtBGOugguFn6I8nwODNq8n+Pb0gDn852kOYm3j4yGAdPMFvwKHzsr6PU4
UX05c9ta8yvelmUs1bOHGbP2P31xcYkZwA3aVGt7vmO8we6GaCxUv/obKWGuAkMc0mX9jAuvFjfb
hyXr83uu2xaR6cG+PXasp8bfqV9QmFTowWD8Pao5uT+U2Gwcyu+AnvJ0yoCJprJpGgz23tcvb+F0
Ca9B2ySc/x0fMPLx4XBpyx9ukZuGWiS1e884ZobXvvPpGtO+k+Q03Bz0NIl66cdBJvEhLPYaMHIk
JjWl0S+HjtD8MrAwc9HW+eCmVPZ7eLuxE1r/AwpVEIM29gYPWnBHJQDXBD3yCdJwmqTAST52q500
9XVmEljpg+RECm7Yr2p4LP2zYCihQFqO0iN1njVOjjyiYmZPtMFptIqIMMyGnmNvUf4KElp4lNlW
2aAdyD4HJ6hOfJohBzStqyXaDIt8velbesdJSf15mCJe+HlG/53xJRbtpOOuqYCP4mK48Fa6KJsp
JXeSlT119vkE8CWT9qIGqV33yUdL+WxMByZa32dYKfscwF60AcWkwLRMFcHgvzO5kNAF1nhHdzYr
FdZA7UtKP6IDQ/tVq3+AeKbvJyspmsLoIRAnAmfnk8wjIRs4YBi9uXK3+9dkaraM7unpvlo4BaST
B41j9x4BEPDcviSHEQiYcn7WpCjWPePjZobIgZZktA64fSyvOSKXrZj2zP3lkYnjBZjPLsKphcA4
+pf/eYb/ent5YuI3ipuN0XkhXTm0snBgbjBdlK4jljR0v2BkvkT5UFTYTZkccJCEQJwnx94tXZvT
TmRRR1k34af1xqDNqYHlbl0oBIgathRLEB5crIqKFDJLVe1urpf3gj5EK7TTOyAp/OIUiAqlJn9E
sFFXv5fCCMbpBvtGXpTYwiE2lJZJjQaRyZxXzlFu+sqYEEAiC+3rL34pt7KjZQLRcb4hl8ZMXGfK
3Zggjh/kkkK7tnZSm/VWurpYcqaQP/MAXtGrQ2QoZL6MIKqwZ7Hb2GQgWYmTMmi1kWbioS0d8iLX
Pz0tkixBhZb9RWVjmLRB8hYo1uSSgm3hPZMfUIAupaaR84qcNaIpws8k9P4DSCbZpoNAfkGsZjUH
ETgrrBuE0xEB+2CvBQ06TSS9EuPE1tF41DbNlXnagDsm7gfucLP3YbOgs3K14NoiIx0G7QMq3rNr
ydgV4l8YYendIAat5HSb4Th1BZsTx6pE5XIRfVtuG8uBckY8C45QpNc2ram7rKjkP8MsllwmRjzL
rJOk2blPgKZVpCT1KJ541gpdw9nkRxCReU3GOaR7Ae4Vq9cFZP1zz3R8/EG3mRhPTxGUEgGjUHG6
Nf7fVjzb1y9Nx3rgIwdA8Q1DT5mA05ECqHgWRTpVBU4kPbXt/Sogd+8joztjVBniqbwuccJhEy0s
1NFuVdZ98CLcDW+IaELl/t+mEN9g2ZpJH6Qxf1VWMh1LjNep+yprfhnCR9bFxhq8tRvjmrhZXW0T
9cFPfzarmfbmsseORWb/h/WquNQaDQf8fSVVjmc4kZn1OPiusj+wdEwlLPSFH5mVZFXEfK5oWcRS
PN6CqCQYRylz4QgIPQrTsSGhDljEeapgBSkk29b6szkP/NUu/mstXUpKBB2UKf31CJ2i83NXpfDe
TcjLmylFX3dFWGcumd+cD8ab2wHJxbu/qEsQJ4xqelEvPXobnHXuzgrD4Zq9SQPMnXNVLV2D0MfT
RpEZQqQxXfvE3BXawE6Xk78pTcOgNtDTUuitBU9MqmgKY3ypmNiV9AKhkJ3r6P9WGP+qghJ67eHh
qJLpsRohn1PCkFr95OfHx9w0ZyLFs30OPy6F2xUEGMfOncq59YovAUOGA6XJmshdiz0BuSrS7P2T
iFNEZIJDFHEH/PoBTGcJX+IwLEsGC6gDZjWtdJhKemJK19R/GPsvNe1ummp8p75W6FNfHPp6mwSv
v4Gf5wmEWan7zn14eRiiBiu9+WcQkdyArGOtLdiLBeE7jjStLDi5M7SQ9+zIvij2doQCGeArM2b7
Ucgq2ZyrVShTK2f8pN1IspJ1pFDYtRn5aWqGaogJEv4YQvV+V6kv2R6vS8PEZ4RxH5op6p4e449M
nCDpWXc40gdeEWVYcr10XMtf7ZwMW+xxq+SbE8oU6SDb99R481m9O94c4JzjT4FYwEzDM2TwLuy/
+uuHyrCn7xZDbGOJW36gX7p3DjdTEx6y/Yw5r0CE7IOO7168WcKgqO+l/RV0LLlBACQbWzQ2ZdoV
ZwXJwvGOFZ+EYasNCfs0sJX/DXe3bbz8J6mww3D0bj/iSiqyacqYFHzYr4ck16x9bxPjCiSudkWw
ESeLp2h9jHnyhILD8r8uyQZG3yhK+eECj9O3UnztkUXYjCkaxLIjmObNBWV+dfKyrrXTxO5pg2XJ
cNAdxVFwRQlStrM3Ic6LmE39AnrN+/dpqAknQUNnnKsYQAlU
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
jUspyP0iAzXCKRkWWALogs7DK0stlsk8Ac9AtlcQkNLb+v4KJXyzKMaA1G3HKNGySfJikCFIiQGN
72J2MmtuHQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cKqUYaFMNmCnFie+T9Bg/PWl0G/iI0Wwvxi8yg1uvhU+lULQwvsZobF3b5H3RVvcM1TvVo0mPQ6k
kvfjHChtR9Rm1NpzK/TRK2cpT/+XraxaAt13AHt4v2Li7Q1TiFtsxvE6WBJbw8xzFPgX5R8zoI9Z
xQThHyQ9Y0HDSp1JiVY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rFOHHUOUrlJWwbymLPd0dCS2AYpSybSEh5ZJJbT2A45w3gZSOvWrHDhtyqbVqlsstgmvEppRS7Od
QNC5LyNk3kmW1uaE7GY2uSy02V9O8r5GVpsXmVkckbPU6l3hNdHiq87O/M3FndWS3dRZKC2A9DNv
bxz63dYttgfvXc5MPhWWemkmYn4ub4EIx/qAGLM9aFdqsmVcpqD+z3B2/7FaJ04Qz60yVohM/5tS
jIFb71LWEqo1l7vk1zCjSPSV0BZUoqJCLSUriAztHm8yRLgBWaPhdvKrVL2jTnL8VzXHno7XlT2u
8DJTujTqNn3NgU8XdwkEfXWwJloZpkBe/g4FYw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
UXdq/o460lUpiPxpmyXCPPGC8od551Yv5DkCjILx/FsUVVTBP4kjFbMPaO60DdqvjuuG4tbMEfjp
2/SkkKnaMW8T2/bbQ8ucMuk5+tE7e8o3ToGwREI/EcKPPr+MdcsfhulzsMujxgkbDbEzoyjXfX50
GxjOvKXRGfrs9Ld82oo=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qemEWucBj3cySwkGtLMneG+WUTUsSnlBhS2UqRJnnbzkZPsIe5912fGNcd+Nuti2S0HrMJucuzBg
zebkZVhwJr98XAXk9E/oT3Nikt/5/G48yTzIJ1KWyz7lHLQAMY5r9Ue3kKojXrs4FG3eiB8y3tqJ
6m+4D0meMUujO/nNAXC3tHlCuRO8ceR9RAOCygQ2wythHpck6/MLVuFD+G6ruOGnDicsOf9eZMCt
HHOdeHmjhn4k/2RRwCGfdChmxzvczso/a5DXM4ixnJQJqy0OGo0toyQcqZBnI3h+wvQYrg94uDIy
dSHACaAVhozF4EfVFXpDLBYFmP1PxyStVPkjEg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 41760)
`protect data_block
Kf9ZRzDZT6viViR4dEheu/wX8omfwPjaHPglDOTgrX0IjhnSMMLFR+RpZ2NpzSI/d9iR/Zv85gK6
ItIIhUnEZxRYx8CeZVm3cjr8eGLJ+smUM0B5ZSY6GapxuPzJSpfEGvEtVhN7MNCVC85Sv3HOq6i1
3ypkZdwwfYzkLyb2MfOBlXR1KBnh4IqlQqVnPwzSIZmoJVQ+rPTidlJ7BvNMWJ4n6CHaQUUXQvyc
LmD43brsfpcNp9XSAndIjOzp7M7qG+AvNr2No7CNwJRfy0vEdvCxN44G9YowETIPYvGm6liDcqSX
dGEVJOG3w3V0DOxwGOpbKN9Mm4yJe6XDHbWWFgLuoqiwNRx7U67ErgZ/1OCPSqw3HDRNtW1yF+Ys
PzIA8IprXSKW/2frACS7vwkxmh+hkvV7Q3isu3Hhl95OeQJAQM1tVZZBw++iyvexg0ObDVxX7nbU
ywOdKAa4IxXk29e54bguzD52E66i9wHAwaD4Eln9ALgsEgicKvTT/RIoFygMAMeLRehykpK8mDJJ
9qidCrLWO2zqFZkP9SA70GbCptMO5el7AMIlggHOpuCcBO1R/tuNNxUKTsReieG0XKwsTGx1hi3c
sKfat9F6fn2p2VTv2E4m1dBPHq23v2z0nrm5kS8tU4PMMlKCaa0RaL5urbO0+pIGmoMlo9Znt17f
Jef6rn2YfMIeENutlYJdijesXgyfkgaCTZEOqxjS2nqFJ0I1sqbsyLNCj6Agk2EXpEzMsYptH+qZ
VIDTM7yEfjAQHmQTMmyQa/uTg0xtDiC72OoJC5Jer/FZXmI3sic9tlV/wQMGI2yI+OYNtSAT2u6h
Wex4MECHCgkfQjNpn8kWipImxBULHHqgG3S5v8i73Evg/zXFDDPXPNKMWBhs5a0drFs6sUrRefzS
HAjl78O7sS7y9KeV6tFEoK87kQhLkphBr959+0aMcb2SPZug+ztW1JYp2w+fw1CM/bVyezQVsGjA
Z0EGf9zpnp3xW2Y2l1+3PRsYpTKdD/xW4IjpTf1/0vJrgJ66KfsmWtEgFi1qHGSTW2f1iyEwTMKL
KnWplQzewgL/fcZb+zrfjiZ/FH/YVFKMroZKwY5dG2NpG80nCTUIVEdIu9qE4Hh2ZWUDo8F7F57z
dNl2RhsvJMTieypsbHKy9bA6h+cOMVpy58B9GA4MC0TTaL2BO6B8xD5q+HwziJEoYpjEMvLZMpVg
pgByHopr7TKwuSxcGwPUttA4PGLnzS3E8SLlX7xttCmEMqrym6ydIQpSe0CWcuKt9rJl8TT5s93L
jA8sf9xYhBNHJu84jk11Dqqjd2I+oQaAiV3o6gkCYEDogcS23VwZ8rEXq7Roo5TXoXAcjBrKFZUN
UDlyEuP7xalfKRJLJ2liWRzXCwsaNOkeZCAz9qCEZjn6cJHCAtM6nihRUyDuylxy/w/Epbzi082k
G1m7QohnMJ4yOhKf+xkPHP+7lXiJ3dkIJPYrRIh8EpJf5UDhnxhw0vR4kai2L0qsRHzax+rWf6Tg
p7a6lNhkP5rBTWzOBnaYB50J34FePZ4ky5zPfx/4lyBmWLUxyXwpsOu/jF/Dc9X/qks9xz1S3JOI
6RTO/KQvRiQjNC/hFoVNsonuoX9JZ/PyB3ae9TU2X6SRIIiEF2IK0MPcQmuC/Ch7SVgHoeJ2ij6L
z0Ws3rLwz3mQXTjBnwSwgkrULKEIyjD0qrrTCtu9dKvltm48SfSJKcgGCaug0HaWr3F/hM1EH1Da
MfA80xmpm2iZYd+yDSFyf0BBrXbRWV0nU95TR0GytV2y84pTAVOj5G2qfiZIWdOfPnjm2Ei7Emt+
QtZB1RvGnosiGh78aG840TkXJ3Dx2hynYaGSE+4jrjO78VGXuN0QkfpP2kk03TQ/k2MhbgxVfA6b
wYDBxgBisAllhiHFh2imQ2i0Ggzm2BD8f2mxY1uZlS4tifA85KlOwRRF+1FqRPonomPCIetPp3Uf
podYZ6fn2MZvoDkcjD+pq6Z+sySkr3S+JBMN9icPW5LYvHIdCvcnQyGoozvsvzzCwthzkvoDrxBT
JuNCsTI1ZySOJTY8JM1hPyj0vXexG79+44pduYsdFLk6K6ujepihcSC3PHQdcq+J1RNPI+PAYI5u
hQb8qdzWL58FRYxlIfhMq61QXsV8T8ayT2iQzvz0cAR4HO+CJp+BILtXL9Pg12kRQMNGYhPvzsI6
tve/NlYFaSzoy37IOmQhQp7s39MQMv++w4M28t4M0eqwP7zW2Xgvij2uHAMWmGj3Agq3iQt+Q3PB
ZvbAvpxbQ7+GLXy4Ow92PCpWj6AgKrz0QN1rKH8bFwKtQr8ExE39DQV3etUn8b1Mq+XU1lOCZsBE
kuGclbjjqlkB+yw5xHK1Xk2kkuH3FINAlDmLDY02PZI7cVGBHxGe+uUJxqIuaHz7eWDzO7q153t/
vDfaWp2BT+ddUAboNCTRl+s8wXEGKknUrnCermH06ne4iWFaczgOHGq6OMV1l2ekuhmFjsnzHY4v
oXJ1G0RnPTbTuHhSyftB7B0IB4gybRx4ZFOY+21gfCjbhFAXA93PFLIX/ie+AcY/O47sYjYTSlnK
eK3Yw0MUGprWwxxlG0CxlMHubzIIbskXfAElsevXZsI/yaNB16J1UaKYjXUyOJVRvAgq4CulOfZR
ACm3TERU44iRol3ZWX1m6uWSufWNHjXeLO/LZeU3KsQ0v4GTGkADupBwTNF2suIkBpJAPq7YDigj
uQuQiRrhQz/H8ErtfBXXJlS6b1rxQVcIYPjPmq6ZBC4IdffV+mu0lLjAnYHAUnuBWMUHLrjLcbwV
36PnBtkORt+jufB+ppQftOyAvTMKEb82sY8HneUOITs7tx9NjqJa5P1h9lVR/z5YVaiCi0XoVfHY
FKq4qz6o/eoCwb8WPBwNtfOVRi4tNqNuGVCtNlbkbLMzDymP/Eho+aUoumrrfhCzfHg+jLbORDL3
ev/xcmD2/31c3cGSBXjpNP6lA3xHPocAFuR0tELAcUFJPwdebiK/VOLRLkNRh2l0jU267ksu39xk
jyaDXjMtTqQ+02Bk28jOKWVKYwEdonbSclOOGQxNO6skIafDZMyJFGuJzU2q2vhUtN/T98P+Ljj7
Oh38r9qxs7yqEj4kCh4b11TruqNeKjma0k1QKeGYIQiloqYSfwqbptIyCmxoXkCK55d0EyJuo5X8
Cicu+jlL9wIyzrgmP8H3zncK5VVxM+drDiZWqDfj6+q5O9JzjsShEXt7n+yjT5dH8sSgMUg08lwi
32oubJfwLbIa8jdU4RxEQn9SWqINcDI7C8TnbcOqo1fKRbEEpo80yAFdJ5kq/VP3QlFH0ZUz3e67
SNCo1+8bFLvu8Wr1XPbUZxiyrZnEDaHBq6VeJS8wpjuI4VAgwxPUPxkVZnNSbL57wKZJww8OAsuw
r6cPPSQpMpqcRPMQCBB8mes5tH768r1Vap/xouh6dmIL0wFJjVXBYepQB7OlGU4ICUubYpLcPfep
4A9FhaO6xNA0VYf+NuQxzh8UqkkbB1joCFgdiBwL5m9Kvk6N1BpJe3Y+90ULjAxcZYHgmwPS8m9Y
kAVyLx9iCHuoYPof8OWn/he4vUt2SdWXAVVtka4+33oPuKjH97RCBvXWF29AGjMteTh9ACN6fbjX
JqJ/yWZ0JlXuaW7TNuTKJ1L+5ZtQI8XCWFfSW36dvozNnKu2seq4NCTwdtgzbNhztaigZwudlUxu
kdHkqdrtqRNC/EMJptpH1peqLkRv3/rKyocbUAE8oRw+vCpq+PJ2zkq3ugMLwQty+m2ER50MTeYl
X1t01viw/P/KsCQFvA3QQuSUKFxAQqRXjCRX+i3wdbm3LjSWWEn44b/jGFpdSM1wKUBRiasGYj7i
t4vTuTj1uwdGFKyX7feADu562Ry0/yi82okbQN/lyXwbR5R4PyiEAPTDgdfisZ3vI+wytQWbNxP5
zabOutk8FaT2dTC4q+DEFsPsmX40M/iT3oeojN2IhwDnoi9c95ZALthRuj6uKq4uNoDRJ6TypjM7
fQhJwHCJOfZJpqdvHsZC3x9DRHNwvo0gB9U/X2nmNC3ueWEEexxdV2uK0yZS9J3eeRrS84T5AdV4
lv+c11hKVvNI/ldU5m2CgFBrBrXNjXNQTCw65c3GaYhQK70pJiBcz9fmjxuilsG26h4G42A77PHX
XShRX3ThVKxOvesA6bVuAHoJwCGJGKOwwHcTSWnc9AkLPgA6KgXTv39inL9lE3ermdf0TrKKgaMI
9RAwGc4yOMxFYfRsgVyzWTFqnYcAys8/F8FXjmnwdGvWPtGN5ZnxSMx0hrWb8nbHgXTzzkaSAhsl
pyc9eQGdAcZj6fON+YH+qFSmjyL2VxM5kJ5xlnNWYd2QFCwSg4+KTh7ZkawdDydKiTz8SlBQIMWk
2xcuzNytijRBIZSXAY6Wn2mnsFDSvfAfyEWEzrpx+idt4GX+c3LRiTmx0U2eu6daKU957geTxQ/Z
zgLWhOiC00Qnx6CJ6Hp4KZEcmSqwXXk1PPaCNYCvynMwz+wrg0fJ4cKxH+4NZ5uAxXQBhNEQKnXE
F9FkSOJ77GdNkfWltlrkn70w533GcyWc2eIx4yj2p5Gt8y7lvufQVVYwPJ/1Kq+Iq5kwr7/GJ4Zj
SeK8Bhuu7oCsRGd6P2GB01ynI3eYqF8+A4nyAKYcyWBnrRplHPQHsxlHewM4XlK5kOEaan4HWq63
GXrbrMKoZBysYjiNmJs5pB06SZpaAxilodylEA7nvIgfGYLyy5l+oe68dJE99TjIxcyBaX6/vmFH
DMJ3tFQV3SZ3cR363cZexaRBzM7SnfaFH9Dl7wUy5hALSrfUZ3y+XIjEEcDJVGW5OO3viVOpcgbD
U0ftRH2UpCN69IlocWCQGGzHS7FHnrftR8942VfGgKUgb95YaqpU9Yt8GGFe39bH5wMvcYHR//6z
DMp0cgEfpJtrwl1lWx5KrBQseoqyM5PP/L8fXfAVsWroDzEFpYgNKcT61hmCu8oHItHxlLLnAHfp
dhAefnaxIWz2L3gACi+jt3V1XaWKbhXSmmwCEX870Haa4Qx6LXdIM3RO54l/EZP2NHHyqWubktee
ERooD755VKJilpjtvGBwUzmuiV/htbFNl3MyuTllGPYlNoNlE7UasaNccYeBu3axPq84Hb/dBCDa
kRjD/pi1euYDovNxKKPB/nNrEELZhmm2Je92W7Q3CtzWauK5ig7BzItXJu6Tq9bNtdQ9chQyZF4M
zHOlsISlaWIbl962in7y7fUDvIelPauTHxpa0FvnoSuBzqZLHk/6uF3ryYdbZQ7YUW6rStt19nV5
fX5phrb26+tF/oBlsEqPBgGiACswFpOJUjXwRQ09mSUqUDLImLtN03PEuHPt8e+ftEzkR9ktS4ex
glAaoQueMtRY0ga756NV4ju/ttlBEr9cTsexCcEbyj04bpBfKkqlEkuAcjNjm/7+Xa34SK1G0EIP
oT3P3wzbw7F79a0M0hv9cBes1VMdfZmeLHoacbw+46Ci8Jza+rzEzsVGFDK7B9LEUGPkAOcRd0Hl
L4qrqHtelbg1P688CkLof/cMhqfUw2amcl3KZ9Lc0S0O7tPvNpxBG1oFdO9qmDbjXYwZFycWKLZz
2HA1r86kGqiIRiVP9nIso5keXEQo77tsLLYx0KM0bJAUTmwLiuQUFJkhyA5y0MDNldtn5Ot4qe30
gkZtF13Kh3MIimx7iZRWGRKuRqYJGf9VkTPprMBE/aERI/S+lyLi7E2JBh1wF7o3e5U9bD/ryKFF
vKg66jL7Uv84e/dmeGJSQt+ItA0EfUelz0E/lA7YCsduZyRg1ltCMQr2N1daHctkz1Gx7grHP1iw
PpR00qtBAw5sf2ApTNQy7SmiN7CyqxjGntjxSslesBkn6Tgao19RFvNAfd3OFUWC26D+0X4VQL2r
saW1aG3dkTymrPfQYH+NhsL8MoTZW//P465tjCRO1F1Tm4DqZbiF8W0PXkW7VcnGzHllgNXxClA4
y/OOF24/+abYS3HtMFRrsoaLnTwPHFcW2205S8JwNVhLnbUwh82tHwRUiBWCr0nGGrufO2s8dzda
Y0bXeOIe9gnGeGto/D0BXdIXrhLeXFmJEUHlAcP1lXbcDM/Kq+Ggr13VORPnr8byMWOG12WnJ48C
qgpNAc79iXCzVJSWGo+cx7EmnEV4tWrKeqVUNgX0KXZusGZHmucptEpsb9hEWMjklIHTMBYF72B9
90nrF1114clphYlYfxluztKts0Di7A4KSSFM14jqV7Lg/FR0lIUCrDjnt2Jew9o4w2ZaMbp4ej4N
HBvWhi05fGDFOHqMYkiIiOvI9TNRo0DUrr7nHVzSAr4N1WDD0EEF+6ZCIeGXn1s6yeqYUEnypo6y
ROoLvedTT+rI9NuMgz+JI+uZZx6jdfLvJ+qbPM0VktBkUoCng3X2PzqEkQbmWGZHY/N94PlBjer1
XA1fEjmqVmEF7GFPhRbpCsHKVzvlGyq53VbUitcov5takpHPkCUjVl/dhUo+dtY6dM0UjkLd4YU8
50RSYSZwGzxyYr2fZP7Xnq9tVkdWFQMcZ229LmYAMSoGCQahKxxy9sSHCtop0UKAUFBAOAl0RhOc
qwSGFqT/EmroySXTH9Dwp6FqJFC5LGnGkBqKysnAihpUfhJz5phJ6WYLhNgWomE/na7klcL4w+9r
8YH47VOm6hH7kNzmJ9OG69ip6KRORcPeM3KScuFfE2p48yisYCS4R3OmheWAMqranc9SFA5frgiD
pxUwXW8Uj1GJXELJ0xv/A1WUq+rM9BRxfs59WJ6BFNrA8lNesnU860lO6wZt9K6nYjO/YcFZ0MPD
Ut7CJUHE7JRyoJHu6cdHNPs2KdlHlXQauDWMmXkO3pP1PsDzpngNpDLmJAuYv+Kue1fKwLCIyFvu
PeFihsoDpJQgVWOlg7BiiUA33HCqGQfv0zb58kfGpvYrdHNCncvGtNLpq+Lf84uSPasu7Oz9FiJG
SYcew575LFF30p6T0XleK/TG6EMwyEV7zwczDc2hHlJxfRvTM9XmWJst0YoJBAELMm35wgMAtWqT
Uh17X6em2G3UKV7LN8OjqOjpvshACVAJIFMYiHEp3x8COSYgrNHuXTWcwg5welKCMjdbUG69N5Ev
bKcPgqGEh0KCwMA+Wij5RnumvIfGKKffevKuc+OVCD/IxWINkaO3+YvKeSDkEhgd4rVLjNFmEgAY
8Nr9ChJYYAzyFjMo4MOpb0HX4jxYDQgUukuIR7x8DpvVuZhOrMEYp/PzOtGoHE1bVVabp6znHAwg
MTbAbfW3gatOAZbuJqG0KbRKxyS3SiNz/ok9fw80TAFjwFYagrngfTq202tV/CVzw4xHg8+QzG1P
meKnUP9IwtXTXwn3OEk2tmDQOnwTqoMVEmvr/wgWUjEHH267gpoVcviDQfvWFcVqOL2geeFCpkpk
2FGdW0YC09ASPAVm3kS3rWc4r18eBnA5q9Ku/tzQxSVwudyhf/fElbPMF3kX0KIdTWHdfwjzH+1A
heFf78JiSNuQt308VldVSu8ryLgyE5x4aMw6vxg9r9kj/tx44E3OwpER25jzkUSoFjo65OLGkeV8
WFP+BG/S3DdymvND0iphtRvp3zSHLapy8+Sjrl2EfMhKw4TKEkW2wUn73Yw659eSMGcNx9zvKNkG
9KBQqI8HPeHNViydedrqXHxv4Ly6j7AJmdxl/w2asalnwRDERNJ304ojmseznTw6D4MloDg4lqvT
B28ts/qEZJCnYfNI1Pekl5fuU3werqHWnyfwCU8dKT6b7sEkRnJgoQKHVlkyX9H1UrZvV7SLWP55
jFzeYsHfTZXbKJX7P9fOBbnKXdeVwDC7uJrH+MgcewJoaXAlkUSaqJ4yJFfg47xKcCWHepQE44yc
oT+CpgtTAkZckX5pWcbQ1uP0FXh4x+PMPwf9b/ffQRrkr2irO9oTc+YO1jEXdGqp+3PCcO13fIKx
BUjfE1IOaRsszinqQzyIVvqCohp7XYYgY1i5bJT86kupampH2XgU8yutKDw6CKmIbOQtWraGbstL
1Rg+t9XhQ/uT2N3Uynb7Vpj+VpXLYms2net1IBdblPwG65RYU/n0XmdcBDesl12tH0NSjvXynWyh
E7TvjAohDR04yOej/8/C6lSiYdhd7qvh8cf4YcotIOkGHBLSRry4pYFGLKeSEK4UdgqDMK2ReotR
07LpRWzczJsNdCiGgMnyuTNnDPv8Ly7JaB6nW1HyaNVJrZx2LGGqwgDC/vXMMbOoqSPgO5JVSb0R
YiHRGmAkGNr/rQsOp7sHgX/CN/oBpH/gAQimURlekz8DEu4nz+Tu3Q7zb1ZyZuoiVrWx+GKPW+2A
ezN7teXnmvHfuLAYsQjH9aqAPojfuFpehdufO74Lqiev/oB5S2JyReKx2IvLF0AiNINRWSycfMxM
zjNGLCk4DJA+qVCJC2qZeRblRIQNyMcgvh6qP6SYJykzvFR3q29dATTmWQSbm8YNdeMvcnpr4y4Z
f77anQKfc8ek3B1H6hZUlTsVJhP8iFgRtvSCvcA1W9qbBDQoqK99nEhSDBs68UxMuUA/kRsJcrVH
CACh/OdZhJDWDnahb61e74kH8iZw04wo6AmILXqvFQHrAVmpDR1Zx3kOKJ5YJI4bydYxavwoxq55
9cjV1oXsjTfPmebkkAAvzCF8q50LPmzGd69vnpWjQ4HrZm05S5QP9vVifcdjxfdlD9WfVXSgpIGf
qrpw+OKACQogitSZbvKM2iCxZ3nBhCtb1ZSAWU5dFOfg+OcEhQDidDOl0y5bCnqQF2H2+RR4zvvJ
5WgVVVaD0IIbeV5XW2TjtWOFZekm5rSesA48WPR5145tazsOr5b8MD+h2wcxwGG80OH1DJ+W1o7h
N0aRVZU3I3x7sYtOTl0FqEj9aKm1Jx9ZSbF4p39FXY5xTmGpOkIzbJav1cNUl/BQJFmwDxQ+RMKS
svPp3Y+sBJ09CCi5NH0qieShMLq2aToznmrx0W4NIw0HsP94b7caeWoC6kWHWe9lsaJ3rKfyNWjX
+Uc8H0Asb3x8sxxxyxd506xnxJxN9vV3iSIhQsmI+iJBfHenJFzh8KzQU9Lh9iYcSf/zxeXpPG83
fdK++IOjiIk/Iq4OlNNh+2hvBsmT/13+Q/M9qQbY/d6gnKGSbNjL+++RtH4AZFrc/PYykUzlaCbP
yhheYAxeQNn+g5aD3l0teVC3DgSbZKZC9B6wkuGI7umIQbLbb2nAkZZbLjVHNyVf+r93aggUuX6p
Fb3P5TIYpouh1nmtJ/JmFe+eEwEIp+oiOU+FboDg+9CiXwM8l1wErqQ3YjuXRXza0JqtaW2tZnri
dqrCOlxhdAhLQR+1iLE50NDrpWQz6vKyebOLTqiWMGQNhu7Nt5ZvDwzWU/LIjWEzaW+ZIPA9e2lz
nZM1y1588S1n+3CEk/7mKl95BdocUiLmh9kqsy+oJtsH6WlnOoo/uduIXN3iDPmqeHwN8TRxYHh+
GH8CSIJc94dCxpBhIG6EUkxxqDGRYy8kHh+P7SmuiJYMzmYJlXPPtD10e2uADEajQlykXAwi9mCr
aDzfgYA5cdQ3zA4ADdcKsJ4AIZa2zAHDlAK6e9fSujxyJAHqDmCV21ManYAw8XV9c0ORrzKguNXI
5gYaKEXIji0cq5SAbUFIg8ORIc1ORoRjRKGRdNMQw5JQ2OtY52u76BgX5/U5rn0M8jF6QX57jzS1
K1c7r42Wn9nBU0FvS0f7w7oNCNYJCHOR+CPohYR4l543MDbh+7dmEtcEBdnJRLTo1hOfZM3QouBH
MKRIlrJPIYM2Wd6/Mk6tWa0EFaliAFaq7/1k9XezSTPZ7sO8/koSwuO0+ndtOncEGpCS/S5R3fd4
KYNYDi9eUXQQgvWVdVwBDbt5jGtxU3FV1jzJrzraI4BVO9Rhwq1AAQOYWp9uS47+fEHlPFWud4L/
f7ec6G2h8BfBNzc6yhcUBUoANzQhMe5w5KWutWxS2fzZTom5Y3bl5zYWEh6dDR6f3KTira/QJFti
A9dy/SK3YfEuqYtjMTg20+aNwC67sfWmKxqTHsLRNdNbILuM8Xa68WjUXZIMaDTJwlfxaVVQB9Ye
Lbu8NzcaTyzrk3fbuPKVieXq7RtshBtgiKcwtBBKEmdQK+/p+uMvHPS1sWzCqOaMWRW6eReKI9h8
Iu8qRWgHUtMFHs23hHWl+UPcdx6i3609JBjObERMMNMRkz0iTzbLJ7ShurGkFZCoXfXkX2+YjKk1
joKqCEAjC8+6Iqpf3UIpeJXmNAv9l9HwsJZQo1halkJw4sLoPNNkv0wjJB2/2pXeYlnwYHj//tP1
W/REQ3ao92GXbKkGb7vMq10WT3D+HRhywWGBmPbvIGv14+cr99/FuuwWJ9YxTLG1AA0q9pLNtnoz
WjSdS5b1Sw0RUcVWvBbufniAMpisdjRZZrCF6L5W67QFFJ9S1riuY3ChHztqjkvoq6cNcme0feVW
ybddQHJ0uENl51LCERa0Rl4940WnF6vcavcXVnfmxuVdcpzlV8nn8pIVdrgMY6A9Enx8wW75Wl1K
iKkZLn3s7HpoJ4rn4vAhnGRMlRnrnWP76oo/RTMahcN46vDzmiyq/GwEgjZW2oLns08yXQCT7UxL
AHaN8S2nGcAWT/ObrcqOMNA1CjUOBniD85/VLirQ5vOKEULVZmUuwM1dNuXKT2jmnZO4T0zggiCT
yEoG73ZIQpbjhuflKDdqOjGrXC9e1FRRRe+oqJF/07WBPnowlXnaXcst1XCxZWyJqA51CbfX9zwH
rKnlWMwY2p7fPOGMLkZFSxTId4PtLjko8lyVgwln0EcI95qJmqwp2pvJ0aFCYxQXch+MjvHx+vBf
c6j+2ZOvLs8eoanEZOgsbsXbwncE7tEyRLQVMghQVHhLcCrbykSDe5499YQjq3EBKLpawuZMarxU
B9R00t4uIcomqKLppqGvxAEsWBPCPWLyut2pl9O2Ajk7mdFpcfQfEYl4tIbnOvsH2Qa/9WnsdFPY
VE3zz+56DW2v3TEwvkuYWqkSUoG7xFsqAgUf1wLHBF3n8RwKEXNV8n4P60QR6dMB4N1fyBkA9KD4
LuGF4vmKT/f83TlmxWKTY6ervSBjO4rBC5wlpoNMpFeTJ5o/HY5tiG0EvPqygilxlm516LZnzIcA
8b4f8x1OfHWCWBE5Ht5ekUP07bpX8uz39wDNVsAq6PfwjdU4zf0X4DPMlTm+oCJuMroOYzZErL+O
Cw7ENUBpUst2Ng3eNCBKjowof7d+u6zSAG1lvuJdS+3bD6Hr+eSmCr2F6U5Wlhx4DQWXz4RAiFXR
bC8DFC7gDMQTQe4xtzbkYX51MwJo0ZYyq5pK+/sXki/3oI6x3XOizcZw+7kmrMZcQiwq/PjNBKde
mD/R48km1taPOcgo2DQ1tMoJpQxRxTuJ5cPVFHI3sMdUUDsS5Z/iQfgC1S+P1qBxKkCaKwwtVBDw
7Q2nnxmdMv/t6xPXHgE2htCAi8Yl5Sc35l26w97qaStGX+3hODlXyeYu1glzzPsCBEQmjPiW8RxH
TXZd1Fo4NRD6HmKA7Yha/h/5epUkOLoW8207AROYx1GatJmSiDONtGCSOsngbkidI6q0/mLOa+mc
jj6xMMqj9XNNz1vc2ihJq27/xw6zvjZcSUuF6HqwlmJs93XazTdkYd92H3UtWjbkcN0w+OD/ctrS
68Vx76p+tZfQNzxKdxtTykDdAnlsflFCBRN6XIqLZAENiuP+4WXYfIDX2N3LgmDS1yy4gIHif1EA
ibXPPyuiaeZBHQhmdXvl2XRoLyorUGKKa5RTsV1Kps0Z029p/ZYPu8NMPF3Tlq1q88GjjL9IMvSr
VZmYGkmAosv6op/k3tRr82ls1zA0XbjFO9yLTZyD1SD4p99zVNh/g029wrbPILo88Re0wp8XZhXk
gY/wtXD0dPE09k6paOz2KyZ9ifdbuNb+6pdrvQzh/qI6s/l+sIiWhDTM65gqwG4zfqU2zmhm9Nb/
Xizjd0TJ/6lVFf8d3Gzg6qpjpA2tZdElwF0GMcDB4DRKzNEaxcSnkFPgGYL4+d13PeCVU0Lk/k7z
Gh7ZxbwmGPVkmLDiwK12pUjIWZyi7XULVJnEAIoscMpuIB+ET3XZ0gtok1Gvr8EBdHkUypPw5LI0
BKXe9Pec2i78UdtEX0ofipbelDuv1UlWHZwWlIQtrwaKAGSzUEzCwQWcKdV8aBeYK3lSseZ1qS0i
Bodmy03+YINytpsLwwxuWwSkDZU7J8j5r/dwsPy+vk3oACZCTcM/rm/aqshtsORfwkWNRC7RpPwm
dAHXOb4nwlfQU9ltfHHo1Dy7gDygKk+Mqy8OYDb0ku4qUjftypJL7qG3nIJ/NkrqnIo3QLUxYIFA
54fp2TUVVHBoQfe63s300FE3Q4nxayrhKn4tLq+s7Og7fi1P9n59wpDpuvyasViRQ8HWZVKI4Cik
2nQYWFzJcOWJ4h1YeVVXwcoB0B+Bwi4YNs+S3nIBfMWZgHboc7OC0FfvB1sGDTuKkOZWelxD4hms
Uw7X1vKgaS9cJwP7xE2mhcHSNrL7kOWWu0HWLEVWSk+emONoN8P7z+I064pUawhQjfl0yzs9TDgv
NARRNjx0RqF84q5sfa+/jkdCL5S5dzHXI7QoHjZb/FpHtwIF2tmTdAMMEB037FCiWwEVA/NRp1PT
ZfJbHlvSEAolMExJ1bwEYe3185HcRDn5MQiKfDa6Z1fq3dt55U0TBok7Tq/XR6wpJ65MaTVtSB7f
GZhxJLf8niKUlUmv4gmKJ32L2r+IiNS5QoWAq0GuRgyC4AcpAnhV3dBsjyGihxBJsLzmpE3fiaDz
7A5pka6DHzs8B+Ly5gqzLHdVEMe3kvCZaLiSApqSBhHRN4A7I9ziMd0HbNP8yd9HIwyx1Gk0wBlr
DEqj8/XYPB+FfVr/RDZBr0alTOi7eykt7ErYq2fAiTzqhf1kK1MKiVc1xDGBdS1VjCy4HFVLyePL
561CjHlUdaKNRQPK6EhrDxcC9FVfqNAMNzGsgVsDDODOwephPrRzsgHTYz6wCA9p4WvE0wvxMmfD
P0zb0tJvE9LJnX6j2Uuum8Sq1fFENaxl8IPnTs4RA/tIqYnQAfY+FIFblniV2f4/GTTzgYUm9yef
JvaXIMprRzStqelYIOpdBZ042viuP5T9gXj3jPuYPxor6Qw58pV2frujdCEVecgaveYh3j/8lMPp
TQE56kMjogkyR5RJ1q/u+bhvPJKR65LnaX3vnAizessI+noG9SVOQKVICf7M6gKGmzmYw5AuCVqb
m1GQVxXs+AOeMnBH0tW/OBR2pAMbfAxjaF1n1AbRd+IdhboEfCkLsXvHrxdlV2XTTrZoI3s5ioeK
koy8uU848vT4EKHF8Y+OHAnhB1r4odlDDVX1zFPHUEg4hX2hr8hKwRAvufoGcZrlV7L1CbwwbEn3
D5nbxeOhSYx874Z1XTBo5sAi23FWYMAJn4Hp4tw8a/tDC2Z88DrdzgHcsfqTQtNxgUZt+VDJ7daz
baBzFMGU8+RNGVs8fOlnaJ7oyc7Kb3OlsCA0S9KVeJCDLHSvhlrOYwilYRA2P0ZvqIPav4oSWShp
WdxChr/oCjPDmX23eYU05C+qGsdQQjRJ26KhmfQt8KyTfM8v6sm2ickMen5XPrdE6kQxAqDDxFOs
BMjIFtOYzJyPZzt6T0vjRBz4SemQha3CltjPjJgj+geqosS40PpeVQqqq7SwObU2pNA8ZD5Yi+tD
B3rtau8ihBi1drSP9PHS5jf4IZq1a2D1IUZaug4zF0pC7CDyAExyy6CcoizpDT5j5nTacGo1M3qd
OREUeyb/ZqUZBMpRPQmLKUincVFJKn/bwPzoQDLe06OeZik3ua9lekAee8McCWj0vuHXk05eJPsN
8Ys5PT3dz7+hnsASebT1071gNiUwC/UkEaacJ230bg5ZnbdkxrXPfQwgApDHWEmV1NOpIE+Tl3g0
BPzuyIE/uabB/GMC3gC3Rh3IPrcXAI0BJrm5AdN9pA+U9Z3THGKNECrUzzxCAPubOhsIVjbX0VLS
DUu5+4CA7hg2Y/6r8R68uMt7+JlXSfHSqYs56qZ4RhonexwEkmJVAbQjzpUed8YeGHSGL7qbGiZP
gz/Azy8II6mbYJ4aIO/7g1zZaPeOgzeoA7A26DuEdbjFtVePwriTA/VeIi6D1nxirctei7OZu9yR
df/8nClNIdNvLiuybg28VI16Yyapf3iQA2jh+bgstkCq0nqiF29Y5IUrKQSw/aRuFDDrXeV5jjQ3
UDRTIBaIBu+/0k8x5Pd3+X8XizqGa8wyZMiKetlcNVbbI/ka5c27S/bnNqY3dlp8etSymFJ0r2yr
eekW/ekDyKfYPtqDGa5hKc5RBGGFs4pYgF4PIoPwUifu84C9NqRBaF7N8QgYLT6KDyeNW0f1bUQf
h7i4QMdrYTqRwA7rrz1Zo2TBZloCbCSG3UksFiX7LrEizC2XTRQjNzQWFCSgUWb1fRebGD4dZHxD
PYMhZSDyWU7upma81aSyKSmQYPS0mmfLNOsdaEkvPo3MRo4DHH0kS4lPbAGl2aVoSzWjoMv/jwtr
CReqLGuRGv0XUsbxjk8UH7R1tzGAipJsEUlnVEq0Q2iE5elM77Xkt8K6VKG6gJwNO7BOASbnvZ6d
WZ7+4lNfcmFmKLQkxk2n9MC8X5cUrI8WXhBs4JHIz3aHqdPyf6zRTR/9Hwtl/6JYAPLVK92KFdCQ
iRBWOcJBpWpMvZDE/YrqWRZcdIA+GDm654CTpIU8XH+X24rc9tNCN9s4HMhZbhsiZtgze+zCx+M1
kidj84cRPCHae+K58b61w5rvzf/AjEz7zaCRUACnPKVrTEZeKWgv/UYtnWe4xH+GCWx+Qzyush7/
skAINIvsetqwvr0X/uhz4qBbjNunhADPzZBnzufbq2RXuwq6f3BkrS56WeFQWXfeXAN4yVejqmPB
cAGbOXRSvEmIJtYhdHyRn3S16lAaUXa2KS/xWNT9dF3Gg2dA17ZYefyWmKbAZU8tDp1Jr+8MaYnz
hc+3p3XPuuDpUVVGsP4pKPtYxZ/c0SFBxCXvTxxu9NLpCZOqztMFBpVzkJKbQHkMKt6zKQaEQzZn
SEvmDgTFBpzPK+Xo8G0bujr8R/2v4mJom7JkspfgzPdejf+tXVio7+XuI1WVHuIo4knEoo5wl1pf
9KctYuehNlJ+IOFJo8/LTqejN5O35aADUzyh7z4hWiEMBHq6ocXIgWPuEUEaRz88779lCTbm5UyL
vN53lfVJR+SEPYdillMGKY4Lc2ueBUlIXWpO8QlZ82zj5a//7Nw9PGtBaQc64+wHd+gJHMxyi9vH
d8E8xxauldOQwDZT6/yQbuH4fSSaAIm2fACv58LSuLgj2UewFKb3/1LXLdgxRqAuot6b4G2/bV5W
m8T1fQJJnQ7rokdAGvshpIKht2pSUG0BiZRrgFJXJAoh0rCUIp4Y6S0J2kCLaIdy/lmTqyn9TeZ9
AyQqY9uuZj6sCbhsCAhQg1wHmQ7NV5T8GRxKDJH4ub/Mz2Zvbj0+0wkQDwG4+uG/6xbrCF/E48jV
4GaR/XwzjcrQRwIFdW4f3EM0Ucx6l40U7q4m7UBUtjgfm+Ccm4f1ORRjgrljLbOvc6KXky8GiouR
DfiHiUqtrht5uh8nqrLHt/Y5j+ApMFz5YgC/rgTq+KwV46xR6hZ9Y8KFN+hxl2UDlootAbcV8718
abOCQxu3sTgZVGo66pgHL+bf0Svi2lpxAYgFtTvi90prl6jGmu08abe7uPChdIA1x7zMhyBjQQ4b
IY2Wr9rzPorv55ZrnxIvgA+y09P4B2ly8V59HuIA3Nymee+p+mbwlMc/c5ysNYmutHqNWg1YojVQ
W+2y01hc9m4QR5Z8wvz6VbveEKPwPn/hWhKgtqpZxzjDOqT15/BUtBxo68yn5PkwFAk7+v6IAg2j
VnkNVTQwyPn02pTJOAHF+doLQV44QP4IRjTSb3wla8KbSTCItfPzPebD7xmq8eV1/he5NEFppkJi
+5r0I6TE5i+fzG2mtp0yEacqt3lC0opKq8Ca7M5fF2LI9m3QWmsnSWJxVPgYE4mAF/66LwOv7dvN
V+Y2qc9/m3YQZFLZ5stYHG6xTr/29sV0r6S7/knm0I7Hgg980h3m4hGeQpnWa75jIwuTVxfH4Mg4
uINWT0p74dbi6icR1rPzHLPguX6wyD1npHxAj3LzrQCgTIwfyLM6GkY8AyplSN3Am5XKZ2FfAuX/
1+46qLE8olW3u+Wesi4zhZgRJhpWJfXI6oebxLaEMHrzbSkm4/AB04yQrSvb7/oeeSsgQNmkUBmx
BwfewdkwEFTI7ntOPp/whzEPdDIIn06H1ESzGZDKjlBHNirKh3YF39gl5NViXP86lLiUb0qDdoyL
slrEn8ElRgkNGq9mdzJ8VXe2sNTGwaydzj+snwCdOHcbF80J/exj0Zp0h3U1Kb60XCa1ksx+B8oZ
H6PaIRjeCRA81z/VzvlaZxv8DUKKHI18u/TA+Ina6zn0pDAHjUj2Aw9tcGKOMOY7Gzj9Ri0w0kE+
Y/UPxZ1PdEaqzNZEtwEk0X4AOsPNx36fVgNzytmuqRV7yJHNuOU0qCm+isp56fMSgHT6+DgXmtKc
Zz+2Dbb0cprk7e1KPnQhdRnlWPVqq8FnPLbVrsZl727aOZfv+1lqAaOHquvDGN+L2aIg2ZzqKifx
30AUlnrMigWAYR2dbwOmqKxjPiuU/Mtvh9PaWSbpKHHlaymfL9LuwbabXRjiSTcrKgDrVXSnCH19
RJCw4MIaVy2fMUh9bOFyuLPDuyNbJjv85ZUc0nqeVZftbg0nIotRq1N72M2iEfcbRSL+2kdCVbbO
RQTa1W3MVP9ocWKV8cG9a7nr1fZI3tt2Sl7QikdvpHhmLwhD3ayIPVOYhnXyasMFA1PMHddu1kxT
kKJX3wdlOnOt622KTBvTDNy6VpT/iTKCkjg5/muB/iLdE9XGHGSSCLjE1mkzpYLw90vEvQ/Hk0I9
y+y4Z7DRI64rOd5Q0EJLyFv5nvBJ8JsS1ZApE8c2rZbVcDfPWs5K1UkovqoYhcVcIZcr0VHCp0nz
fbAfrQXc3WwoU8msB03s0Wjxdfa5N20aJfLanbBC6iwDfqaeYQ6HFmH52L4yC4T/lfOLYqLeqV/G
BMVsXvcp4fVKhB/hdKDjmwr/nU80MSHiJYE+JkNImwyM3Cl9GpEmAcSTku0uFMx4QkWVAjeR5YdC
oioOqzwDFyUKlJsWUo8cys96/N+stPqgZPOEf2wtNTyqDEieWcUE1GjTz4Kd8T9/RE340qJAGMqb
z+r5ahowY2eY8RQrHpF9z7Z80dsg4Eg/WMTRcfccY/UlIvp09w3iBueKC2w7Y5C81NQL6Y6B6vck
29bh+Z/9EkYZ33BdP4z+XYqtqPZRTEzZi87hT1JQL17Yw41Lr/r0T/MIyc6ibeEkSselxWRb2d9M
HymYuTyEirCiuwV266OkBVUPgP0tspesOL6BFsva8B39KolL0Inp/Kw46OX4Hs2prWy2Kj1arYe7
an9h0daxWAPhX0KxBWrMT0uxXrn9aS/PDT6JUMPRepnhmZRrQBrZF03TzL8R6phhDZqiCToxcQda
qgTlNkMGbpdPoV9l02i76AlDoY8EFFt+ovpJXXwLO46u6Wq6zBoZvb3Os9xVEqnL20IKigyCgzGv
7Rws4MFrcEuwQjqx3KiDCNS3YsO1IXjIA4GDk2JDPN9s6TTIgwCAggQ//ItzkPHVf3tniYsGxPLn
kvhGaiR3yyePMGlUSszDuwi7EXeS0Jvw4YhsnvgOPAdqHKQtvthpn3RCBTzM4tOHgWxWmWdOLE7N
7lGHHXiM0T95l7rU0RhHiccvXXHzX2nMW6UGqmpbLKWjSLTLENt9vYOxUzqJezgVbx1sUWRKKot1
93XP86blUoxL3Nkps1SEYbZqZwrsWDsOwbv0R3I1Zbb4oQVJn8NItDJHUGuehGtHr0760W2hjL2u
VK8gY+YOv6SdJ1fKcOYO6Atl7K092CvSJ5jZeEI7NxlSNDp4q26Gdxeg27vZRhQ2121HwmJY5tzi
iAnPEkroCZbmMGXnGn3UemYYPPdQm1g6Sji2qmUYRxA6aepBm+s2azOGWXoJBbp4+QjmlUu3QLmq
HZ0QXkmp/PQQvetaS8a193inKMiHE8OdzRCUGQfL5h8XbSN7z/ruSZqxRz8GcBhGUTNksoTPunr3
O5EK3HkVFVgc5e/h71ZWwtnEwKn8Z8u+z/sFl9xIDwivN6iRxospbpZWoTAODFUymP019s4HcLvT
wl+UTUb58o0R+zcM7q7PxAIYxVEvQNnUAooem+VrWrylnRyjetaNSVg1ETxcujA262qXoXpMHNfS
76D0LvP/DYr8EDGFCKioaKygpj+TtWtn6xbSvKsxBjRnt7U8DL2RP+cWKjPbAG/eGyKZuSrCnRWP
J5osjDYDEhdItKQ9n6n0wBtx47VSfl9DdopBv2/1dikpa4hYT1cvoRjSPCf+7W5pSmxe+i6m8hAR
e5ykC6jSCrbdPocs9a+u0nCGNxYxc+B6Qf4wSLlCOmaanfBxPQmPgmDiDFPpPpI97Ul8tV4phkz2
Ejyh4cc/Q42OYEPTmngdIYeEYKPtFFplyGXB69epmoFyasf/UE15IjsF9wdDFuKZs0Nbmv/mco1u
LF1eqkC5Va1XZrykhkKqaOL6tnLV5lJcvqsB68ngUVDkSmZ4xs0KHZNeitnoLGpICs2NzNDpay8y
VuMg8QKgEtd0Q0T0l7Hu141Rhr7O+AwYdjYPhZsR/m9cM4Sdhd5B7nNbcW/nlA4srxd/EvUgfiQ0
CybZrqlj5+T5nInkzNzTcxzheupw6ItWlkQD7Uf50wG9wJA74HWGUGhxYv5R6262C21wY3Lf8sqU
L4xQ7oUJbeMGLp/XTCZIodhpVftS8J0eGv6O/icSKZmPrHRAQfF562mXuHS+WQnw5knfDA56NCKn
OMl+Dxsz6QHXypNTZrtwt0gq3UizBWVGtFf6MN11KrS8G9K9gGYmuAPGe8yshR0kEPCkkMXBPwIC
1SLLZei/yvmOZHwFCSmaqwwzRaCuKfNYPJcmmWrX6+miRGvQBdpuc4jyD428Jz1OuI6BDHd2PXLF
eV7N+yHAvo+t4fHQPuOa/3K9q82hfvSc7X7n/Utnrh2BRJo19v+YrPoZCPPCSNcBxRWBtaVTbs8+
oAwZ6XxA6SwIM1T8amdXeeofwFzmTkjAJyegwFMTMyY5r9tam4/bEvLZMlLKEPn4YRI+YFBbBQ1o
uJOhL/ItqBqerVc+kHFPZQ1vIrWj1duyJE4lzbbZCPkatXG89SVWI7ZX45aYrz4puyNZ9tV3LiO1
OqVvOHdciggksf2qxk/YJ5FCWZQgOhZenpOm5MYRNcRiiRd/Nx7NozcPw4t/89BaB9UK+2MNcYa6
FtaHOfyRqHjqU7FXoldSlIak6PLTxrKNPlmNLj4ePgZkVV7mv1qhrnyaVZiUR4tPPIWIXq8REPJp
G4NhHvqkzqXbBHvaVfgawyvU4ftLS0Y+/eUOamVbUzalNysqnszQvopboUzJileAYVQMLcvO3zIV
pmt5mreD7upkiEKP08ikVzLFdWKO2kyQ2P+kzR03jUnnpSocHH3JYQoJCa5VFBos7pr6GfZYdXAw
cmrSowiW47i95R0KbVONTpXo3xoO8bMD7xJn9hx89jmsblWxveEsUwxtd360of2wKwFvMEoldR5T
GVFk6p2PqWGb9Ni06lWjFd1iAsWO7jiE9t9zWEQeknmEA3BbCIh+oUsbiNINyEF7QINppHVw6VOt
9Cuqc8Iq/BcdhUqvaVeWhGX4FdFWuVuipo4jeyHgfW7/Q+v56IGCWAID7A2Fc358lqMVQe83Jpsb
igIYe1k+dYDmp912UkBx3ACYX7WQ8on1aRomrFCrbhbjDEyuD3khv1tBVTx9mpjg62Xm1vP8HPio
//G9ipX1oItfysjlS5kG8QTf3/rcV/OvlnEqCJ166x9IHR+eoBNmPxGorj/qdYnncRfww3veDIdt
GTuQepsVEvN9Ac5T30hqKtMJr4TM30B9Y+r+gjEgjjMiR80duIlBcZHP/ZRMGwUhghEEq79Z1wda
kPIxhut4LSXWcdqxUogHLgQJ9u+iB/1r1ZEzT7BE+v/wJXBzdW+BgZR9RtJoTvNLIFv3hUtU92yj
q+hHFt8rRVogQxBDlB9oYczNdTHJQO6+/M2gtyl/xDBbSdVOjxNX8KR3jd1Kn1v2g2Nj0pwcwM9D
CHje32u8rDQx2JnS76z6qf4uJJfRBpiu/LG90WnbNPPqkhWqiFr57iMeOe6l3R6aN6D+9Tk9kOFF
7YP3YVzDMXDV9llhcvqRpnL4CjLNNTJ/AKH9QjP/xpD8Mc/IdMsux42mZu1Tc4tseyP0n+0NEByY
DxyEoNbP4cX/pzkkYC2QIRm2JeuG9S8ivxGS9ukcgL/ujqH03qdaKNbkKJM5ABJAUwHxMJHuUXMV
0ZaxXQkPouLKPjfrh9DVxCSLIMelJMEAgw9O4T8mgaHKAfsD+NCSdpkaTJwmXF0y33fHCyZNhM/G
OO8ID7zWcbya6H8TBAJxksMjiUSYqV9Wl24pyZZdCPSGeDVm6rRUQdQ6qJKIXbHLvePX7vfaXHID
x/ZSXOp/4mFGAxe5ZXxLusdOXe6ydoZ1MWyN6qlg0Hqpj5enREaFRsHSyJJoBFwkQ3SUw5XYmJNF
9j3tVXhNbWnFR+Z4csuhuboeBU1PXYyMOMBxK3o4LTMzZNDPfSE6U+F/lc/iqbRjmzZZX43pgvxP
f3sPDTeu+Lhju02V8BT69G7Ad7tH2Afwh8pMO84AOB/Wzj5Nin2j4LsfNCF5+nE3oqo5/ODCI8lf
PrDIS3SuNOnkHuUhwvjOwKZdG4BhC3n40mG0DIFFxGp/ImVCwLGxUBqgjTlcIsSB9Tu2sSH1cZRL
+3/vixF4dsx+YHFAcQvnQGGR1bN+1MGzToYfqPJiyurQmCg6h0yuAuu8wcfyLZrn5hb2IrFlF+d2
CueoBFE+w3Rgo3wdOrWtw69dJCUfLimdyKsOs+shAMtaR3NnlB5GNhxTCtMPPZ7jnLf/nKlDJqfs
9L1Mqtd7wOeS2sgJOWbamhUHTT17fViXtppgXbwlTgRROV8fboq8FXpoRAnP3+4gHablmZMvQYZB
mDYNHus5ajf/cxAA3P3iElSx8iabq4nJb0bFRpWmTpTg9Ot1KvtLqmDjH8C9pobBdCvnYOgV/T1X
qQ6WQ4nkXKtBm8L5UdVE5xqrnIab5+t8q4OjF0m7twGSRCi9Q4og1vrNp9hWW/AZel25EQ25hmhE
w8t4SfbAQUmAhhL1q1E9Gb0hMO82NJd7PrXRst7ZSfy/b9HhA8vlWc59cCnE+m3k5xthJvGDYaQH
mTh3b0jicWlCPRcIZIQXufe6cYbtADa7i3y63RL/l8ot77L/Hao/Mui+oqu8rbSoiovAdXsNsuAy
B0eOsM9iAv+qKwC+GH2hcjHgoFKDI5AGtns/sfDlhPB29yHWJVxY+lH+MatTh9NlVvicATsvO1AB
ZkZaHJsBwLnuvOX5FEJqXZkcs739uY03731MeJVQMYVNWcafdc4XTG7jIjb/lRxrbWuQr3EqRqbK
w6rm2iAKfJ88a7/qvQfdYwmdC1T+WKWC3tBVvW3lgBVX0F6s2HY7Y5nROw6KSIgU7kZbfR+z6SYo
57SKzqdI2lxukk4owAijuU3TELUujvNKabYfBsqRrx5FOjssF5S7K/jrgogzLic7Gxtj+rM+9PWs
wWcOE/qA6Mb2hSYW2gy/57Mc41/yxXIol5MMml1mSArPVA+EKFkFYrOEMYULukMOV1oFRo+O/JjY
les2x9g3HLrSJJoYZ5ee2RKaqtGgQPHjE/6x65fXvj082U4tMt0WYjdNTFO/9+8KqPghQCdvfFP/
ml22tMWEjeC7D0R7q9du6JEt1cGWdkQy5euIvyA0t3iRIwSF6vt67u+ttL68w0mBWAqLa7OGqOBW
XTeGr36ePsk85p6tggkI+HaAGi47Q9P96p5CqDOoP0ayBnU994XrtLjnjP1XphQAE050427rmhXG
yDvRGDx8HOn8/h+KrrkStgeYT5G5kPhz2I1SbaKPIK5hprbGpUjSE51nGdSsNemVPsTVoagxkrLO
zcvsK2Ut48ju2wQixnVxjkZKxYJZ/ziIn/ioCiI/YrPlDoz3DKAWdH7+DQP0nbcpha/MP4/mhoYS
r7zxC6yfXVtxYoDJzvCoChNY4OdgQq0fuPj93t3P+vjyogT3USp5pWeiWYNEyqgY0OwTJWe0bnHm
QDbiZSWPcOhL02xDo62v7C1p1lRoFCqEQFVRem7V/0pNaM+J5p3WoP6uloIlTlGALVLH+6Cevs5b
4Q7MNGn1qp4y48qp9+/Rc5xZv0+dxYmzQbMZ5aV59R+Vu/GXDU4VxuXNIYs29U3I9FCPBWoCpCSc
Ws+jfTpGR/IlrkVwtH9Kcz5/CEVztYiU65qAsOknLOZcwphmaOfAQq1wT1vAAzdaLapYK3sBsqDk
F6GGrWN+zGqckhne8M/YVAz4zGpH/FUpzqck4sh1WNMNs6eAsX31Undsr5pjfta5ORYUustNxtoQ
EVok97pyvl13cl0x03smMxqY7k2Pz/gLVqhM17SbnM61ocFS1m32VP3b37YukXm3QiqM3XmNVd9i
f9y3XE7f4sONvdkvjysSv3R6UXr/vf6TLnOSGMIw9RknmEnFvWX2S9j/A882qOlGtXa6xTUB8yhQ
w+oFKO7fxoWznw/mYSKMO1IPJsAYza78s4kABfyrZ4HAcRg8GYD0T39Yf34kBZcd2UtzYWNP4U7f
maco8KCiXoUzgUZGLIa1FV3KzsHaOy6/pEssFxn8CCZGf34WneQ5gqCTD07FUVgAtjudJdUAEwCB
VoxpIQNc0buwxF9IVdxeGU3aVPBWc2X+4dQT1lY3kbpjLH2FLqHn7oC12K2aYJCaQJdP8ZbrE5yx
UgydxgfGLf/HCZi0msYsBvnRBRw9jx2NCLw4iSs/d6bAP25zGwUOtw6nVKru8q2vI/6QMHxaMy1l
j0xItRAAHzu+kcmzhTOg63mw/EnMDURrUPpaiO7gFeG9IsRcZWaRUfQTJtgw54Mj78zEfJSfz/9s
cEnEhVD0GsiAlKD6ObFxHg6kfwjCzy1cY0ipmBdLT8j1092ePsQ62WYce4a+lQ01oMhwBrZ3o4Vq
qDPLWpQ41w+8og9Ve0oYgo2M5iii/EcUVF303IbNreOK2dUEgqQECMuIQrAHhipwfoPx4aY/n1ML
UDFo+DEetD9Rh+EOEIoMSk8HLKmVEoY4YWEMV+Zw00TfJSQe3WGtjf5OObNvGscdPWEiUGkiB0J3
doKp0fMKINycHd/KTQF0hOAcM5VbUrdv/gaEeBHuBBh5rO/saliIYthGoFAlr1EYGNq1tZYoay8D
Ry8jghQh6ZM9/v6IZwvWkFwU/9V0ejbuoObjHjRkeyq0Wj0/qM5AjgPQbeJZ3aLcW6GPWLJrrBTz
OstbLoh4VlxZsjC0BCosqH65PPEmzTGf2Uad7EuDgCrhcehB9v5NR6SSRzuLM/W1TdpAntxluT+l
3suqizNJ1TRNUBI3wTrIUnb0fTM830c9wOj6xVWNdaZYPPtjv+oSUj9YZs1o5Sf9H3otR8nlWFRR
eKz5T4m+BkCuf2Uam/sq6iMgh8bCw42u5dmUICaj7UyRKfP/r7W5NdwrPA4ew1RqOV0rLhNyEpr3
4FNF+1is2vOqP+MAHPVPBEm7EFTHNy08T6Tp6xCifEqhbw27g3tfmZ3JDK03zHzDqAY/oOtQF4G2
pXSxeanAhkEB6aUEXjPiPux/53RBfC8Xzxb03kCD3flITragfo/r/l40f6K5l85Q9D5kGUG5MRnJ
5hnR9uQo4skwnifUD3B8+9aRHfROIQ336ypcQiyn7bH6CtlO8bTzo194M/TZB1vJ/kgHpnjzcYm/
hcoPGtzlDvezWNLucnZcR2ZzDIP6cyMrdIZxm5o3mn4Q/5M8du8jyu0wBIJFsHD1tRmCGQ8hiOj8
ovoymdSLlC3xe8ZKcxMxHl0rokcDYUC0+FhhDZm8epUuGQT3Y7QOLIqt6z4njdJYqELkiACw15Mh
J93/I4ML/1blGqDRQduKiMwE6OwVx2Up0WLYq9vHz5l6fi110sofpRPDVE9xEvBcHcHdzV9+RHjz
OtZw930yOArEsBFSMToLRbkmdlAfGwbkkbgM6Iu4ubLIW98sEVDMblJNzjhbAjGy0gxpSUHxNL4K
fmGfc/phpkOuRVPRfpw1jftb9/KRga6KQrPyinsKPLv5zm3u9YYyTq3xnusxQeUDy8lOcBvi9SaJ
xRfoc0V7c/uVQgiqbHpMa8iwbuNg0XrXivcKfELr4ONap/D8h0LOMLuVpi18m38gZkttCxmb269m
N+hXYQL+b7r/qm6vrBNZW3PTo0F/+XVuu6oUarAhnRgd4HBhIkQMTmKgwN+CflIPJSxMb32kbAMy
K3yQNH8TuGEkdU7m8v3R01jtYFxxSCJhpcNsLB7s0W2gvaulxVF8xyMdVVu37ni+In4ngcKfKq+H
Mv8RY5uwrQ980e1Hi94lhf1NUZbo3mPoXBqLyNUUCADs6cTvGB0H2yjSYIXcDZTgh6Ng+RPKQ6Dv
zq/S39TIoOIzFhDUf3x0qI8MlCZMY0qQZPQHHcwoAbp6kXKX6ZSYpwXr02u3RYkUeNWnoC9Sszl8
gsrusESlyO8YgghFStHdbsEHlObQ+cxtaDXHInillXg1Aao0uwfnpeZrHC6Tc9jN/9Lqj9EwJGs2
aPMr+9mBKPM1f68tfjgQMiYS0i8RrlXRavq0oHEm9NqWfc6Sk7uVKoN8PRBT3jtzlMmQ1hOuw3QS
Jb1bpCDzg6VvTht1+2GUx/KyR5onlKA9ohmUM/JobbS8golQMEew0Lzkc44GhsYVB77VgSi1V5Fo
+AkZUAQJC/PECLsr4eDTun8GUKuPiDsbrMZH57yM5cfmlaNnJe0OzofsOcWCfD+L7lJNdlKRdBf6
Bzs0+A618teK2B8tf5/A5kwDC8et86JeNHca4iZnGJEYPyXVdcoo3ftabm8jGF3aH40bgknWB+bX
b+4NDGnWKhMXhfJAMH41X+NtgFVu2I4TEJOyrZu5FMERGY9ToTpNeQLtzC2dC5uu8sj4E8dIztOq
14//2UlSx/s5HY17S2+QZjDb0n4x04rOr6yGZix2V8or9qlBENwnQ/vCI54sfrQxu4JwAlKsdX7Q
h8pRziPb+CBfCcTxjQsMqQPpDfZncZneIwlypirD3BAmwXKTaYVfXLDW/Eq7FNMM/Mm9Z2RC7TbN
mtpDB/IkTlQzN/VzPPVu8V8RQFlrCZr3hmOcLJRF+RBCevgNTZGyiWB4UHv0PUZ2tT3s3kUjQxt+
BL0Amyl2wbYdTgmtzEo3URGaIqtg+olkh9uJ4hE+rtHVqv9GbcznhU9KZtxuzG0Rb/VPp4h8dLr1
x2l0BurZ4YTwdeG0zpp+Muk+FkOOVV3OKIOPgpzokhDb5C4ExLEVekGU+XXADWmMSK/5+rD2I9DO
Xx9UOJHkmZIEAHURhtuhFmjlCnF07UtSqPSbvGENPO79SiM/ptPPB1uafIDyzivB6vCwrv3AqoB0
uHpd70xfrM24wOnxjkvRWwDO1KftbJx9ehIwOmTQGzhggTtNCP3ao40Dg28kFJoBaPOTJ2PLLpvd
8KuwLUZRliuGRLXynvuq7YlpCNoKrSgoWVBzFqnTr2hnlV1qS00HLwyxL25xFN25NQKLSgDCPFy8
F4j5TyZkKX0NjDOFd1WVxskjG2IzzUap0Sncq7Irdzg/A8BPJ6AJi21uXAGSrE+oVC00zoZRY1Wl
k7vzO91JPGOfNPim9qI9vL7kwzZKm7VRZYiqEcIDe1ihdOoP8jVz9ekYBaTdvh2ynEgvIUuyUcdn
0hUnoXovd7DmKLwHxdE6uxIJS2thFDiSTZrL7+8Bl7xVqIP5ybqYqz1A40Fl/J8woy228gog9Vmb
NLx5xD4dVrdx1p5I5paCCZcIw/sfnoWhM0MwiibGswI96sEI3M6SwTLZ8RZUbDL9UEv5Rd5Rfmlh
hRvtbAbn9ZMG+6StjQXtfyH0ZsfNsjW9TSV6D+AbdGqUZj3cdZr24PaQ+OWFEnyQDRCTTDo4s9lE
byUnpLHAyeuMoPIXbobxf3zZBhg5ZLL3OVHq/4RODAH9xgSNTI5wWgSY/YMZohBVJCr/7gVdu17X
ihYYCdbfOTeb8mqpSDuGwfR4g9JSswb4Ag0q9FLaF4kIwx7F2MwFCBXS2dk4lvUfdoUdth6Jw1EN
k7G6szx5o5l7O3sg1P8FOYF/JtwmTh8rWlydjYtAdzqRwB2aWihgOdu9iU0vJp9pFNBxR7PgZZVP
hRr72yS38Ukn6ghZRySUCt1pCSWcmpnIN5rIWgFRA+YV8M5lxDSY3dp2m7BNG8pTRL57v3WtZReq
hJfp9NOJsEhE8uEFU0tR4A0DN1cpLRsNkhtToC3IbHVGWY4LW3465rTBCwxXUWYB1xMCS57k+1CE
1UKEiTizdnfJIA6ZqmZTA45YaPe2hyCtddPvDRQlmyN9aJDloTQkCtlsbmDizxbdv97MJMJKSbEj
eHUsBK5ZOOJiq6XrUV9Csnk+E5zqbYDxvRvPj06mdwqHwifaxeyZdb/7elegWLuDdBjp4UsZ2EEJ
uyQ3ilHE8ygUO28Mb5Xm5uq3tkpGWJvYKHXC5nxZYPg0ro3+0rX79c67DOXWkvFzXw14GLbVR+9z
cCngcrESYO1AKVFXP0ggUz4PirNDWZ1Oi4uqRXy2nCGOtkZrW/uELSDmxVa2aFSe3MBEC6S/xCxB
b4gZo9HtEYRSzoLvORwTrDNeFoBmTvBM+D+EsKAk5/3sUAyc9h2sEShMu80ByrVap+pos+dC/PKr
ZTEp/ini0NGFA+SqDtMqVrnrZ5sgqmR1LxZsAWwseJUg/MwfkEOoF5Scq5RBtLYfDlJ0HE+dQ7f5
Xv02Nwl9cQ3Xh9fXM5G0yQYwBCEsLFTtF/hqsH9V4mnumoPlqmKuXiAH8HrB2K5PTrR7G51YkajB
dgzUzQc6YQYgPr/4tAqczt2f0KXhJBvw6Zv363C3d2GZAvPAsgYlJDEi9lJMVkSLcjxfVNheB564
WWheC/WPS9bRaktakpI7odUuz80MM7DL4YFPMoBVohABdmYSPATOZrNiq4dnZpKeGoA1cPShWQ8c
UG0WM3cZYH0TmCoZUISg+5jXKPaNvATdDR7tqdCAxCapWVZlRi92uh2QgR4FQ8BkTL4zP0+U/g5g
ELRWNk3+2neEaz2bGJs9sBLuu3fPRF3i1PU+QR5XYy1nUCla9y8fsf+BGM/oZZEXoHB2YYRV0daz
8vgFYG7ukJmwnaG9q/eOBITgFCPVPe1/rdNqmfvQ3ivz0K9oMY/HryQnf5N0YQY6jPnuiPb/VA48
lFHuyqPPiYdMYYTarVB1w5Hki1kIeZWH0Ap9aExTPtPnITg3X8Ptz5kRRH0/uby4Z/H0e8darEej
FML4kEvinl4YzwvtkmOWwDu8v8npRONNEga/nb4aeLZ2H7PQ/EnRv5tijR+MmptoYoG3zucSd/69
ALU1JIlBlteMPh5Oj5GT3ckG4TEhZMF1lpbPCyHw1cHYd1GAIFnJBQoDKLWS5TJQ1otmJO6Og03Q
ZIEBQHz6aYuNanWK24EnXyG2dxfUYUz8PFpWZQ+l9tq9uquYVLj5x0JgPc7ukWKdSg4IeIN3w7vC
V4qPvDygGhJORuuol5wsmtgdjkxEZPEzhW+DVvWMwUmrQQx1w65zeyse2emnS991B0Iee4JPTdut
VjiQNdQ8LGNvmkiZ1GlTXcTswpmEPNBqx4dhxzK8ONSV+vcbDI3vGay34Uo+spRbVkm3JyZd1ox1
iRdi+akJtw6pi+ZO/WQ7hXYN8wAd+uTJ8dFhL4P+zlFtt/slM4N1/4akdIXhK5iJjBA4tEOZ4T3B
poZbFcMeSLKtwR5siTF1VOA6Rd5flwbUaDcJgy0e0Y/pD9efAkBwlIe83heMkyicV4nD9jeserv7
DpIineowyucyNjpghXJBEB6mexCGKihz4xwFnQKRhnRDoh1BBvQ5eYEhEO9gwFcAMqMOM2cPAPBV
b3Yb3oTlpX8gznOOZSY0bRTSJiGiJwCEvm5frnQ712YdOJTejCWCZwYJa7AevjdREJnK85T4xbdm
8xkwBQqvUuSEGr3mExv9cC/NaUjNp7CxbWidemkoptJqhYxxSAEA/Kb8cB2F34t3EMMCuCd9mLVc
zXmS30LXOmghkDiJTHK3c+ekscwQF43EtqkVHSAPQgtIGe0JEWM9J0q/Zi8xHMwp0l192/QsfxVX
22QIH5G6+yLY1BsmHiqrUUVeWIv22V8r9fQ0jUFb36TNF0joKzE6eodtIQlvxpsH9egN7E8FScCv
mZk0kegBeHbInuSUhA9OrSRkQWqjrjU1q/MsNMmouPF0tftTDXGzKQqt5SElegZbbDRvFGuHXU+C
AxYxu3BYH5mRppn/6ZWaOcaPXsoTsjvE4GDYkx6OoMo5F4b06sW3/+DD0Xuv4XOGSnTHFzX3TZcc
AT1cMwspropb5l70iNI/zHKQ0MnfOsMPNWCntAJNxQVUR1V6BxWYNeEpEweoEGo7GTsiH2aoj98t
85xjU8lDUjjULVztNRa4l1G1p5Uu1aIK1k9Hgz12p3d8FDFxswgwmFoShPFUbfUwb7fYnBdyG4uD
aFQI4O8JxeqWl7b+NJeh6Go1XC2Vj6XaSrHIf2ut+PMQKzdTIx4TumWnQtWc1+9R7mmKjDdTDRmw
ff81ACWboi8maIEbHfLhJDp+1Ihyb63WAteJrq8w6XbmTq/KpPK6CuRIbCxOFeE+ftTBAZgjEWAh
RPhgbTOYxXopgTgRHN3YNULPzWSrzFm8gReQ9IszX5K0nckSdtrJPm8rJyrCpltQ9Gev2sNzgFaR
SZn57Ty1F6jtOTeZMY1wj+qIbuvaBDzyX+9iCO7QfdeUuzyyk6eWR82tv+9QiCO/mdof3t3uwjve
W7zyeqDQcoLAoNesFNs3Dxx654pXQ4SQKI4jdNG+EU9aN9yB0ejOrrqvzNrrGCX3spz8o/U5uq1p
GdbuW5NL+f1yZrTXZG2S/KeObeGGGGiXj08q1HHDIerRQxgdLFADqReULBlfXo6YEwx+eHvoFY2H
NF9I+ZJymaRZ7DpXSxB8NsYtlXKr22Hre4aNZjsZm95RivYfvV/kevRzwEU00lSPwEHIuieKAeCk
9h0zCyPaQkN5FvXPQ92RSXdPi8psjRpMm+1cn0Ak6GDG2hsGw3M8vQkoS5xkVrgdToOTkJlmbrlo
5MmJcF17rzSSxhK3D2mBVH2sk3ACnybcTsBupPbtYap4/5LIBprPeBSUCzej1+VIPfyaruYATW5i
P508bcjivycntxLpVK3MpwvDPea81X24HJSH9HB2Oc+T/hLaRfzo2UcDZ9AeH3wRs80f8JLPv3LN
QCzJJE5QUNpS98tN4oRZycIHfNnUjG547eSuXaOJ6kpk6YoVcld9TLCmrXR+3HGgzXj4oWX6jDmu
wWotaoYelcdufZLwOfulIoh7/pDl2X+Rmf7MWeTN6AzrTyp8joqG7444hepa2dfFz9pDTvSn153Q
JNz1LnrjWo7m0B5CgcgUWASMBu7x/SG79WpPs6ERGZV3nnHBba1onrW33LT+vTQDcsUS3uiw9Qjp
k52V0H3XCtLF2BlFXEnbdgseIbUQd8jMP+fgkOFr2GEQZJ63qFUIYmuz0HfZvoNJ712puHth5qAi
SBSpPOmG75dXv1dQOpuNv4zIWwmNF4UC3oe7GnyFrLEwrRZRE/iZyUGgkqbBjymIxW1TKoLvhba2
UTkjMfhzuJ3HVTalYYa0NpmvwsQ3V1TiuKvESQ94t/biUa9JWlKJezXxeFKDs9fSzDqkKGbpQPEl
SdHWVL4aHzK4ylQZek/EVU/lVJCsyxwuia7pNw5VMJIFaUOlNdYd8G2OiAp/NbVZkynfqIEgA1W0
g0SO2pzNH9TMQSpn0a1DlV72DCLvoM5DHmfhShqizSbL+T0MgCM/9wj6nTfdDWFwoGYx36dYYBSU
dyQTSurHmEBxBlEwIAmLN3qTIApozHKbG4Wi3Cdvn76GcIBxe1gdJ3GMVs2HyR44IAlsv+vXVRRa
47BMgATjaTvH/9P7p0EU7tNIIXWuNkiqWtLAu/FUgqJh2ENNWeakviOnT/Vbh5tpLN32h8DlNaCw
jQU4wjJvFoQkgkUVjrST14Lco76ir8lONeROoSGuJO44mjQ2n4HpUUS5yge064qU23FDS7855jZY
g19eMfhcni3O1ExBeKpdTEeQfaHx7leG5VcUcCCOqs4+e4szmsNxVBFsVcqvq0jiv/A+ZffLLCIS
qR6NWBxi1F1uEHWpqCrI5ffuuKA/qMz6GoBzXNDisl/DnT0afMgsP+U46EHgZV13EGKM6GIIKBwE
hZyW8f23ZmbXYfLgnqJt8gBlB9BCQqgJ+/AJkY3H0BTusjheeF81D1NjVACicNeMtb6GGkf8Bgwc
Yk0LLzOm754FNrprLaee6OPRBMf5nB5fiyodahm2cb/rHOhkL81yS3Fyzqktxfw9zkqz+D9ze1js
xX6VVbtTlFHrzgBhPU/X2MYkacWSEJZodVi+oYVne47/4Jav5O5Hw/QqbZaY+e4qUhOmxS1B2ImA
yqkcAjX6muEcfYVmrbE+Ry8WqpaLqixmONW6OuKqaMD62e6xbDRapR3llNzUgI59hk0NuKDYK/2L
prZfCzR2OVRXYN5mZhrrRBiIqqnZCgmyPk8nqlvNFMuVbQvPoTqV7XuyCE/ZOV+Npk6BYnCI//Hz
XP+AihKAeYvuVv6MhC+XH3QbWdJLziQNkqsnBJWu1+I8MGg4tv/AUqGgN7wGIovXh6vhLOtRqdmX
rbq2TUTQUALy6YL10uqa0IwMp1UiiztnRrDLixOomPpbFVpwJhvl4lCEI5IFYssBBYmNBc5TMZ1k
Q7UJpQv4w/npec0QTSl8GFnDa4ReUzbY53lCalk8YSTJQap7K936J9JDkdZWKdgCDSNi9ioQXgWs
JnvinaAT8vdiIFeNtl5wP9I5L6yGZY98MAQVmf+6SOWSCnXrr3hOUCOuYaHhEFjLNaTpJsjizt/H
WNnbvtgssz/R+rVetAODsCx/6+IkXxUS2hyKuQJPNMpa1iTKOnp2ITHA8FvITg9lzN1lmYX33h/D
tYxzx/xL+wreruC9nSO0g8mQ7+Me78G8HX5M9h2KU7PfrVVRwBqpexpPmNpJJ0vE2/pKR1lOPMu/
LLMBph5X0sOhXR5n3wUj3r/wEf4eekCE2Eyef41vy/Dcs5eYzuBdvlYhCq0SuugPbYn/1ZQkjqji
EFEfUsJToelhTlqGEj/PC+ZeOpFfHDgqjIvGjRwr0ajq8LEX2xcZaeRQNo2WznSGlPB+oU16V6A5
wMaOrbEjOTBGQy3qpCRcX88iim4TOH+sdGKNauw4mHejtMOgUElmAsAuYCJ9q09sXACb62+YoCLU
gMlVWGIxbGlgeswS7IcfKQswQAYh/+vuceS+qPFBNxH34ZhLUnJ1qmrX/cN/FYzyuudX8Vo1eTkR
3M3+7CCcbrC2UQJ8VpC7DENntnwuGqykNZGV41u64WXzn6mw3MFyrahA9pVIOvouZ47fIDcqmEAm
rrD2JAtkXHzhmwGuueUowaTZA5HeD9xWypjorPA23RXPFV9N49gYj5iT/1f//syVbrwWLdl/t+kH
ArpNwXv27n+tguITRzVjJY7G+CRW8ABBrgORxXPVZQU3pr8CoYcBQgZK/1quePZHKeirjaIQE/V4
aCsZPCPIpdvCRTdQScenItM7csRbtJD/rSLtQFed8QucMCnMnIQjzjzy/iAfeEYLyMl5CUelDWdB
JOv0VaAgUGdkUKCErHjyQP7jOrIfSc7UKnzACmN7wzKuNkqKplI0T1gzkNiN7Qx2Pr3OOg0q2X6B
LlB2b69Zy9DRe/aMIUTEOSCgjH6su//Rv7bcAuSWwPX8b/1QABO8DQiVassLbOGFZJbh4rkTTwYi
xz0i6KfQjgKVU2IuCNAqQbzb9XK9pblKHmbrrrfKLHdaTeorL/LBoJWFugVTg+WM3tWAlLmHOQ9q
MOJQWbOfyhZCJBC36ZiZ8508UWv/YZj+cr/PhDKXiJQ04A2jm2q8smpkO17e9imPruocoKqY02lQ
0lZsmLk79kfepMScnClfbznr2CgBdSJbHI2qPg5UXvchNNdmE3Vnaw7vPOREIG0IUiN+fDKMC7rL
lMN8XtxgLWUZaajH/UMImnvHDOPFeCzWidTwWqr7WwDisnDvnfwmjyhsn+PpOih0QAzfkwhcwA9k
QEYwWO98A+WOP0KmBMY7yqHa6iiiouXp+TrHlzGDF6JhDGKk5DzsdqrrroeF8zOLLkXmZbcK3G8d
oiDOSwL6Ds9Cc8wb2RI939OwFep+7dyA33ApF0gLHrnl47JyVgvAEyEvjd8xlkcEXgtO6dllL/CJ
hGiTJ3Pkuii7X5BJOSiI51kAbYX5wcS4QZ/ImBQm3MhPr00LIwxCHaYSAjNKvR5dHkXQCGlxuDfj
hN20/bk2LU4W1+AeuAon2EH20sKlR7zXfmugr3rZxxEgx8/oh/nplZUhYosG4WRD9eOkmM2yWrM+
wNBs7U2sKCayX8cHQi9kNStFZB5WsQNKfuNnzEYaqOfLaa/rPD1P0ewmTG1jDIqv/T7q+jTt8G1n
AP22u94nTLs9gjXXoL89676SufKP6RiBcZty4LznUtgL7eovlyKa9UUEnR6qRIhUoefpZyWyoihA
iVFe0StLejtUpvS4vzEP6C012EONNEztAquiLsRpYwftz2g9m2u9+9LBKrCv1YeLy/zz2PzMUbMF
eoezsFyN5XylaQPfE8vyFMNgwcbt9W3TMFn4l71FRm+6p1W0Yjd9nedNAwWpdkpZLUMshseHrSiI
OhJKPy9zIh5qBDYgRCob2ZXW+kHufDGkx4NTANEhhUviwtox2hKtoomjE1LY4d5DuDzeC7+lwVBj
TPjQ63b0yPE3cPv7I0nZ2og+2OihTMJVyEGsUqE1OWeZH1wTZPvG3Gp17E5PsDRL/p5pDwRUojti
umNHfHxR8r3Qq2khW8lJmpwIk76/Tqlwk88Bi8LSPT3OG7OjQn03rvQ7K4/QfFhe/IRTHtovg02x
VIWfsJEvn2HaIUSYQhdrqPLtSBAQ/+AuFQ5/r8+QnYnR5I7ZNlckgU62mHsciJ5Qy0anRHXW5FOj
Pwx/YDCSY2kWJlFEcjLEDU2/aurlME8imghJiATg6syXEoTwyTQuNeDg58SJNHpy+v16czjTnqvn
mvWH2S1HH+XDOAa+6QM9lRYr8OO4nHYC44+oZMq0CCRRctN4aFu/jRLbe4JZuemxoDXXXgPr1pGi
nyOv1MLM6/W3zL52Fnaf79nIEU+lVn8DnC03BJTTzsacXITc+CJWozq1Uu8bqD+PQwYLbkYFNWbK
UlEE4hOhMYfIrnFbJutixh7FYa1ijlmklH3dw83JfN86Kn+DguStHzFTiseKH7FRTZ3y4Tbp7TY6
CInYMTceGJ3nLDGMjCw3L+dBIIwztfmP08W6+L6xDGJYgpnvnhv5HRt29w4GSbxxxPuILuJdGznq
JQmQerxxa3XALc9J3oGHK/fwIfGMOD+fkASAMPV9YqlKOn/y7qmPAHZjeDTVRy6MZq1k8YfX+GN/
X7WJw/C25vdQvOPpRT/aaFRKS3Ic/m5qv45T2ubbtqzWMxmpEs4zNVpi56qi4Js7W3H/ooPcYDtl
uKAAdxgC+aTMZH/9ZqLwmWk/qRnvvfivVRvUeLsDaCuH8q+GAp2iFRMG5+Z88NeF0dWqIuSRRfLD
tmmYmBvBBG4Bn9msTiz7JbePJbAxOOgBk6BbLdAMFmyJSUeVux63rdYUTqJi7Z8xz7B1FcW/mQtz
YTXm7ZicTsO7Z93KAIrCHrm6uly32vp45luGvQaK2k3adc74nAOUm4AAZ17dNMmJTaCdu7VetHlL
+XIAwm54c4qyPrWEiecSOt0Wiz9SXoi0pYvqYOxj8D6x2u8uKb7TES8pmai4WMLsru+2ENhmRWi2
Z+WnptsvKSKvFckcPbFOOFtPsGwx8Umbm8pGWC0+pt7PDa1V9e2w76acXwu9m4qaUa7P/uqC2LOQ
ZpkFQe96FW3P1neCiJhRJqKspdtN0Lhl2019MM23ibL7dgy6XpIo3OwyXxjRmHv85kiXj+rljzpS
i2LZ+jiJBd0V981PbjU2Qg3Mkg7qgJrNRq+Bnt7CeRFKmLQMZ0DozZcbymoAth2Zpdnf/FwcySMW
jZssnieAkS1jZ7eueceHcWVVuVTrUpwpQg16p65CQ6DiyLTHNDYhQxymwty2RRwXPhXXbEA8Aj/z
d/rt3yovN0I1SMozEMLvci/9pxVS12/fBhUlLmg9xvdUNBikvuYvYioRpdUtna8MAFp0HOCk9Ax1
7B2RLaxMOrrZeO/fw3rPK0TtEo/Uok/drq5CdJgZCy1Z3oQYAHTXvd/HpvQZNFOlnkvpGhzALdtF
ds+hEeqEV0U08k+haW9ARjY7a17/HzlO2/ISRdTDLuaPxmBEWdxKPktFz/49VaOtBLiKR4Y1JHDZ
WMd8Bklmd1CKDglNwHWnbXGNrI/iaQ29PIlbenzTJjDOJFlEb2RgvrqyiAl/6n7OzMhe4O55X/S2
Ls8O0PBnliPg38ZpT16xKYbv2MfZNWQqETew5lJmqDhNnULNRHFrv4IQ73r6avbyRKqlKkwkFPX/
1IgzLGh/qwFgnQTShWC/Dl4xrtpF1/tahh86tGoNJ7R2mAJ0Bv+ld6B9naQsNvNGfoOdq3c9DaMa
kUNTjkwEE7/gkBnyuQ16f0ycUVkwORd/ztekFDIpwWx7KRWwGWXF7xd6viMGU/afEplYj15YaqB9
LTiY6oZ07aPKohxUwJ+l8Hf8GCBfk/VzSeSqsdtgW9U75tUtRQhw9zdyxtISbuw0i0YQo9ZFS6N/
acAlnMMLBU7vq8pfhVPuQSl976/BQ+FZmwO7OV0Cpu8Pa0oWORaq5a8ZkfCT2CPuWa7IgTl8uay0
HP1UBzw8B4KLPB51ll3XP4iIulVLX4tGn5mEOpmjUWHCI1HBJy4OrK1iMTWXRSVwXAs3hGO7p8Mc
0s6keKRznMuUIgUVEWEiimvbLtzszfZ7PfGhQYtztfcUosqX2pywg9MYqRYPPaKYokj9k7nHPHPF
KI33F8XtmAexCZaziGyWsdm8ejCGnHY8xs/gdcfxfdYy42bXhsPMdbV7OWha7SaLifFc3lp4gYAK
hAiERJLSVaWCm5aTbJoKscGb1nmiU4qRvjZhMmet99d+SAhjBF84uBxhdvCRGuPTw73L7cFNTp8c
1gywdsmWUcsUXi3P9xvbs7J+5zZS97bw31mzxPiZnVs2tVfr5RiYU7AESAEVdM3uG5i/i62glpTv
XV/UgumoR8M8Z6xNYIefULMyjthIWwIsJqgaApVbj/u3UhrFjuAJ2pkjkqtG6s27aluwMzh0dRgc
1qUY2X6S1C+OAPiEDehkJWmMQyiioquG3CoiKNJCiw8oxgKS6oW/qbmuUyfjkWfvw1GMXZ7g1yP+
rqDBTpIZtaXdtI61mZkIhN6eWGCTPf2NKnCmYnFVZAn1oZoWjHsQRsrxgoaWau5dWF/HrqMsZKTA
jctCpmnJVq0JB17D0Ewp7FHRhoyiMeChVwW7cZWeRwUYIm0FsrUJ0oFClxpTKkp5e2OmPWNXKRSD
dR9IoP9Ev/1bhr7gt/llkS6HLcJogYoliULNPb30rjVNkg/+kMUpmvo6pMvzhZKIT92/KLMZC5kM
9He+lOnJuBS6C48EhG5X8TvN39vQ0ybVNroxi62MgIPvasJmlZKtoz7y1uVE0HXeIlFKaeTyRkYb
ZAw3BiixUPCkOTU4M49dSlQiasqoDApfWrY1MRHHeCRPmbYC73lwOm3fYOuWzSgLVNSnVQcMt8ev
i6l8/EF4+vgKluwGl0ZUJ/cejo4q57kS31MLTk2h3+PC82dEJ8C+SBed2iNeAy4uvu8MqSIGoYrA
WYb0AEotgx34/KqHt5Msl3c526K17EQHqwMT+nJ4GcgNkeE0E1Xep0dU/4mdoiLlC3GXnS8VV0Sa
381HyYlnu8f70v2NhXdVFQBiF8M4lDu33kK54BJA6IgmfcimdGhSHo6dqJ27zgzZxJcFR1JWou18
spo5yzgU0nnbYwMyaiAu0+zhNAWfwEl9B+MxeSWXsNgp8laWv9210ffoQq8x07x4ujxZUltc8gLc
/V6J2o4i7+wo+5X7ktfHipLBAFbGZ8nHxPX/kMASz6dBn/9exzxN03Q71qOfQ2l7HmzVkPjnBFeK
0uMAPK5xug35ojP9Mi3ZDJUhb+8U9eS8EcQrB0YSA/aNsi2MfMHucv4NjJnAWxBhURgw2wrgUH56
NKDSSrV6VR0oO9R4ookY9KoBOP7aWudd+IL/EG8jc14m04cyS32Y64t4F40VKNLw9+Uu9jgzCDPP
OxcsmZ8ATjN54U8/apfb2tzl7EmDKZv65FABcLOtXHhu/Dq3p0yh86lU770DKdh3nrrH4Zx0U2Xp
brF/nR09t/MD/TpFcMTA8+6DJZDXHp4IpTBTTLfInzmwCglDlZKuPlLJKCbx1s5eCnZRDbsH+OoW
ZvBQFtyIB+r10w2USpy78GI1B6eUV7cHFKNf5h48bpZoeqJefkoI9FI8uE1BkbjLZaxT2VgKtWTF
KYvl6om03AKKejjE58Z07rNnVqvRejkQxBgLV98U/mGy+QtHiC0wCkSBmPpP3bfTrWljDv67C/7B
v8JgIYeYC8Nz+20k9j1TI7RBFRew7toulmZPQFJk2V6Jq33w6+5IcvGg3oAHdqGbV3Q9arl+2eto
sCbEW43iVfVjsKeQoDu9MotfyZSiT7VaQuriTjSHeDnkaNjRATtGVzLcLpeUGPUCdf6fAm2Nw/Oe
dNWlTSSkOOF6B73RIvro2oIGaVNw9PN2mHFgcDzN6jzKu+cRQfIa/rhTmfLlT4TUK8I5oLYppho0
DdyEPJtOW/lV9Y+OJlvT1/9NhiQHvsbKuXUWB3Iye05GmnRYwP+aGiN6adXVkxGdQLdvlloHOyaq
qQBC9JoxprFPFFz43zcgajpEIH0bM7jbQ5/yG96goaWfK3pMNZld/H8+aYfvWuTYyR2HGMug6N6v
FEYGIBd6DX5CkEWLOMdtrcH7Oc3yuiWbYTnx7NtPz+gzwA6hnG+sgzfbzfTRz+E0+4NFBOIGyNvc
OMrEedIFFAZt7QJF4P2f0kNrYVME1cza3gqDotEKJyNsOMJLMep7dZwhZAXKTRnrK9wQFm0Bv5xw
ogZU6xC41rHthBzuY1MIpKdgT3fR2Hrks0qm3l8rLceLazN8PcumZRHLAB2u8Kz9RWk/UfH2HabL
XI0NSqfJWcUJ3wkB5eSeiaKBTIPJzaSiyE2HKEDoW+ew50hAcseWeFEwRLwyG+AC2uoA/YvmID8f
jfGQImRrb26ilg5s33yRdkD1rDj4hPOFsGGC7xQiTOHFxlqUck3af4FUbs7do1Bp6Vbm96LOfjM/
+2imAxLcTsQVLVS682u1WNLD1xtvaGk6b7FIAxfjc4P3IDM5huJVon8H4kO1bG5Kd5+qQyO4miyD
qTVyTpxlnFOIJIN61qlVuHI12lBgo/ISL15SWn4azgBzIIpSq9/RW/0GVJ1yeHHsWhn7dopjsQ/f
tu39YfQ7R1FzVFgBaWoQxPgTQc9A/qc8L1IQVaLp9XFdcTwF455V1XAe4i5fjqXq0wAoVI2LqV+a
GnwhV3FbyBZ1R6LSK2QePzNYnsismGeNMjiUzS1cc5D9jvz1MStVRddkaKbKqhP6KNX4e69Qk5Ko
cljSONyew1uNXHbb+tfKjsf4281PA2DjXiw8/Xctj6rkrMGKW3W2YKzxaW8wLQUdt/Bak2zjjdIz
HAfrTwLpzzN/VRNbMlHU0tT88D57KMwipXiOXKgBx6MFwrTZXUHX626alJZcltBDpN2oHMsK1SIy
xUNbugBjb3sGdxvIrkPlfzfghwKmJIzQADyEGo7t+Rh3UHBlVM1eFZujS5tw4rcPsOMnWoyf1E9+
X+STQeEum71s2DeJt+LzpCX6lvI1GsrfYuwXGIkUagYugsbJLscaLVzvFbwM8N2pF3GPWDig1uFT
duPaKSvKkcmmho5ii/2aPGRAB+mFxdGWb1R7V5U+A94lz/aF4WUFaJ33I5YKHfmaCoVHpTzaXk+Y
NLVG77X0/f8/M4R7cZCgfnJiAXa4DLgwwe0gPnsiOExZ7Rqzwoy9v5/6T0Mphqm9yUzp5y9k6b5/
NVDQLTiCmSJGtB7HrOP78rlDePf1SVp48bdVBKRuOKjQ1npTq3Pm4Riz2/0YHSAMbZLkWkXUm+zt
HKOkvMo1Qu545JbZR4tNHf133iiz8KYOEwALu4EwJQ9RxbonyB2LkuwXFK1eRH5m2tRSsOfbgTzS
ZLAR6JlZT1jm8ppzPhI11/FkJc+gAA/VBLlPzAkHRTnKMbZEZOAyTVC653nTBn31vawtGK8Qx4qZ
15ZNibVSmgsxLkvRiRgC6oOWKOSVNl9y00JFyaCNCEbo+kFf/A6Gqh2h3nV4A60BxB5oxFPmNSvF
13pDOJFoJcCZ1PQdJFZJl4yBPSy+QyzD/lU6CabJmO7wXaIsroBUsitKGPowvBVDzhTj/yOCItIg
99re8bBbhPZnzg/iBjQcIuSvCMUM3grAHtYuMANIEl0fwlmFa9EglDvypgR9oK75BSR+zOp+mC9t
7P6/xsEuLXhYeI8m/eLMA3WZw5JNzPd0OYkAwv1YQbsWPnc1SSxnq3s0UnAtkuVAWoIxQrNVf4In
tsVml10O6A07uR/egYOOsssRnKRGifqJcnjiassCD7VuJj0Q+RLv+s0m8ajrVtov6SKlQ3PXkSi3
2IrKldVgklQEIi/ngOzIyLiAK8vXvCO5MLRahBRdg4HU/gFmadwabdFvrkfgC4OVUGSpjCFxBcl1
A11XfzlU7LNAeafkrYqy0jrAClkU9rv2m41C0bB09LD5ImntBEVWjJFiGMjea0/sgKY0sIQfT0Mz
7ATwidLpwkDCRSLn50jifxuRUiIA+Cx41SBjVU3ClOM9J9Ko3IBSo48qfQbqyBng4OKciOh4lvXR
8fEgHa+kc24HB3a9AP/LHA/2qi72lThWO/ymmUfdD6IJd1ptrfp/gYMlq6KRulNRgIKJ6RU2Ugq5
xpgEliohCZkjw9i8Rwml29QNHIFjT6AwFPSIbslbq8da+UlMSwvlgsBivOQ5C6mN7Y1OC5rkuGm6
8wB01NM77BQJpOOHN8aFoM9oMkNWNv/vMf2wXDY0fHmIu0i1GnoT8hfW6ZHFJ+u6UdAYDJVzX49I
IfjC8u1RHzd9kTUm+bwo0xcbwNe/IOGgoC2F8uSgPi5VQoYIHNNE/ev8pDUtmWj4KoI+sC6FyNEb
vAOn/U19JuObQrjP3e2nNXe50T0QUad7U0EF+bk4ZWllVcGDvSeK47tu/UuBY2pv3jRDfZu5wNUu
3ej55hloN036jLs7FN5vpI0emzOJZZnsEe6fZGzIQl59fsrWLI+ZH6NdgmtbOsVrm2jlIiPJmKcc
rCKja/5A8raEF+OpVSclGCYs5sxjNdSGsfR6QVsRwIBeXAv7a200254Wsj9VTcjqGdAsPIVxu60z
XpWWsGLFyxXCTjVZW89v5Qgcd2H7BlYUHYqTwUdnPpd2QgkMQ9DYTvkCbhW4FuECKqPoM/ML3PSi
UBxi0km3+Es2r+tmBXBmah26DBfmo7mce9Ez3vv4pDcFmTH/bjMzjwKLBU1geM9D60QIFfYw29Om
n1me/muvKmnxRPKRsvkcnfym5cK9EK6TNnNqxgOiAdzJXbAG2IiBJ9Y8Di3T+D6Ls0AsEnD/FtiN
89FrjGiIUsrLfboK7n3xTsRQKBF6SzgJZGDW+MMEeHjGeWQ3NL8bPZ49rNdmpkivTDfNpyuMaXBO
6uJviUtwePk0W/1fzG9hbXCkajRkdul/wfQmm86ClQOBzXqLOz5+GEaoPMITOOUG1tTBk5IseHOk
4dl28iYybndFPaOeH4ol8xurRBVP+43D/p/lLjaDlPD0GlFOKROT+EXwpjN6oLXvM6zX+ZnYVawo
j4KQuVhcm6bRZR3HYVAu7h04PZRaAfoincB6lf5p30O35dNc4ZoLbO5ZDS9A+4rGJvTqwcckz1CZ
y6yZDSaquZExESnF4cbgYZON6Izw83ogCuAL1zAG2GNKHkRZpc4iRrpJjFxomvwtfyi3vLB74EH9
PtTSDECKu3H0mwwyRKeNOIxm7zf4LLIrxQY/8FNwFF9uIJ/xRCEFukDK+y2nCPOTLZ3OBF5rv3TY
DxyaR9wSn0Uo2GJ9VDlCe6ixm15KB9BbKU+PhEmxMxheSpRlwoe9kGdMnF9+00nvp181E6j8cXrL
6u4Bb157XtvUpTiyqNtVOEiDyAFvgmnbu9Y+InAL3A32JsKg9jGgwFwbdbTBTsKBNfN4P41y2UZ+
G4jpyGxa/vCbmZEn67M+zX5zlzivZfCGwfcoe8TAcYw+VVWjQgnf1ZN7dpCvmUWQc7GOpZH8ZeSq
HvwcKfpaYFGcrlKYNP6WoSLMFS+OTh5bBTGGcYfNiNrJHt2LRklsCNoSsoaeAmHvZE3QH8qkTkko
5z8O4cIL+m42ElnPLfVKvFYbyz2PIug8dQs3UoZru/P14jdWOaqYqXj+R1NWUbQh+LcckoCF2aOT
qPuzxI7ZOb5ZIqX9jIOTegeQ40VtNf71CnmzQyFq+uLZcpx74ZGH9dbrYLioYnXjUFQmYp59KPdM
qNvCwKC0zBQGlqFmxUL/4iISA9c9JRa7Z6h9bXvlqI5Gl7mMm6+CENHrRoGc1CJSe4i7oIyhNPnn
B3WTuCZbbjxvUPa4DfWR3EKtjdM4BrQrl1GrMp61+XPf563R8hHP26dpXy0UZ2W0du2WDHDqoAjT
D2GhjQT+oRCRrgXf1KwSxR+KcUkPjiOt3os4Lnz24nhs8JmgCIFmaVvpRBL9QmgfdlZ3ycWRTOzH
RlofEjpvyc8ZF2b2SYdDU9qUG/YB5h3/nXrhcOu4nOiBOTAwdGtr/auAf8SmCX0eHsukSOwvt81E
YCtF1vBmcMT5m5kh4SYOlzMljjWVHmB9/heLKcHMzfRhLupv7z0kyTPrCvQMZ5PX4M4pHuSHaEOj
I+a3HleSmSU5d2AKxtK5o0ePWZGBFeXp6LM/S/JEylUXxouLFx4nnEWB5+TsF6QEKVKVtXKx4tKW
owQxYJ+gGIYBD8RTYvifUpylCwWFkIS56MauYUXPj9GfqQw01NyV3nY07KRBwN1cTqab4upgtjlp
abzTdawFhh/y3xKsCVN55Yv+K1inbd6K+xOaAPyEQiJyV8WIZxqWLIQwD+F9cZMuR7SD4KPin8tA
ffu8DdS65FLlM1uwG5g9AXAjdabfrlK1kkztIRPlGv9d5JbyM6IsOLYG8UkajeNYZlWtHwxiur3K
aamqS0Y/yEPWJiLPCZ/3CXWbg47ys6xiJQQFlrWHJ/4wtDmD1YnhvkM+1oDt+mTOF/68rpB81hW6
6BvWBBC0RGCBWk8Zz+0epCd21gKESzz+XcZMWz2blE3+0OX8qNRuhXg+S1xXp3CVGgZhUuRQAs0K
K3QTyeeiJFuKdsXcM5fNCK2bT1XNQ/Vf6ItejHerpEteZsKV6nXejb5DWmN1we2IxU+10TNA478R
kxAVV2AGCgWF5rgfT3h2M+OAomHRX/PgUQYR/q7rwFhpPcZ7t9d2EGjhX3ivQNzyve1+6ENpwBZW
bI4c69UyN5T+bYZUiEUnpQ0ygYs+SvGXWt83shNSPISrSbHWsrGQLzvCJe4mTtP0bcEiLgbTVhwC
2+KJdqQtVn0LpJ79m67DwIWpby3ZUpuUtQHjeoU5Z5W1wDlfJm4JW11vN8/3F50Zv7tkVX3m3NJu
822i1Lb3AppZmMYfoDoG62/5sLhOzNVQHSKnR8AH+f5DMSoDPF1HYcV3S5aFBq90HZLoEiHDE63L
UZ7v/4GCSXYgTiWhKHJr7s3pDt3cBjvrCNB49k9QCkwC87KMmj7eGIh7gRBi52J4aNANHktmsWvI
5t40k4bGQOb8bMXlIuv06k9IDizX3pF0FkLIttNExx4c6u7IRiXO7OYbwF2mUOnxwXdLs5IkCjGB
CjPMZgUh/M2LeRatQlAhtDqWn+kO2dafB/wEWVk9A9YZG2GYcaF030Bh3IpFlXAqcGI0Yca7UZDR
h/9gqhF4s+0lF0b/Hk6mn02qIuhA5iLH5GVSkwKQT5Dsu2C0bkKTVL+VHYBPb7/zjthMpUOqT5pu
c2zm/cWpFPae8uaw7dz0eC+pnwDA1L4dCNN88seEznrHjP0aRv3bhtPn62j7nWHRRv6hZOuH3a0Y
Sky2ifxb8c/q8NYZ7m1WxdutlOy96h/QPTpywC11T0d8FO4zp73gcrbIUNsivMV57Zgz0BxKuZ7g
9yApOygIARfUUwdgYY2cLKJtL5ZCQ0idjZ5Psbf4XXGAyKmgEncRNZ38PzLFr7hKJpoRpt/4Ji4J
iy1F4uKnpbta3s84+8scr89YOWKYbfhs2dv1yVAA5mXlDXvLH7gh9FFmGvpq5Wlh8PWDkMSZjxAn
yCytlW3fyA4Is6UzqcC9ZGCdNZUN8dKrpy1InEBv9jafAY6p55V8zKFQyCLAQdAx02EgKvKAVAzT
Uw0Yy2g9GoDEw0MDCQJJ6lAMRQfg1nB7xacXmpq2R/pDyGAKaYZsHjJPlXbv5zKtVtXmO5WUFgLl
C07pG0M0D11di4KzNCh+f2rIWZ46E9jOQyzMMwcFHOeeuXlxfFb9rS/FMmK0wRLuA4GPEVbdBuvj
CbKGa85X2LHVUvArmOGsvBIz9Y1SI5bwse2aJdj8ZW757SXAsb57c7V1fnMlTZPFVKRvDzO5+4Rt
F2Lyd+cVLqFkwIBv+BBlqtqEzhWE6E5VbyVv97qjbia6xpumUicL2ZwKNdnHE23lXfRiHP2lhqg3
P2grC3FDjtIYFFl3yOdSGMY8g+9G1fF6PCzsBa1F45HIykz47iFUb/rsIZSBQcPzv44+N4rF75eJ
3XQtMy20CrxTd0e+ZN9TImRp/qiJ4ZNJtxySS9OG6cyctK/3HrTPImzMTl7uQ0t2GAmh+aDEjH0u
sTp8kqFwojh66nqYM8LfjE+H7Tuf6952jvsMKKEUCJxaKF3iCSyQmyQfpUm4gwEZOcwRQuKYlcGo
it3zAK8LaGDKrjiC2DOXD3st63OSUNV6+FOqnC9q7RbbKRQ5z1B75eie+Xu9NgCAOoMTnLcvBNaC
eER6qFu4LSFBTpPff5aCPN9qAqJvEBqQ4BeHm9sDlc2J9pJrUbbuuBJ3VpkLWkQHtks/lwoodFwv
kx/LyITYeIUgcXF4em3X9WDh0vNHgifcxUxBMkgJ4isteoAHW3hrEzGJKtMsy6DNOgDm022CSb5J
kcExeNhx2zWadba4zKRWW5+IEEkOXPoBAdkYnXnFtKvkjC6k1s1dpin94zFJJ7CFLkGpTCuSlffA
rOQYwKBtfzt+CHCoGSP5KkHAFWT0DZQjCZV/sJSC6BDbmLhfuR/0GGMKT5p8WCxphQp9Dfxajp9X
Wt7PUkUM/mJHn2Su+tvUuEEUCS3mAV203i9WGQneGOPehFpryvWQPg7Sx1/NHFb1aXXL8LA2g3TX
xFn8WppJAgKxFFo3KpTiOViDzVftr8rd6aOUnhEMiN6Lcf+/sjkDmXlWPpAEK5RrRrzRMxkVpvXD
Vw/H0eZP5Vkg9C89AdpCmMIoZsH6ETHICOVmAJhzEyygnxsj88+OdBIx3uRa2Gqh6mBx85nhEYaV
MNm7DucVs15cVgWKyhW2kYBOT4NaFK1EZN2Lc6kcKuhf0OeS+EjWxfs2Ra0g8PfEb4VxWlNKjttk
XrVlGGmA/6EXdRG0aXSJe5XPlqnStQEPO0R+45G9Gp2SbWQF/fnQP/Lb9wz/vBU08tghsS50Mdn2
DB2nMeHAY4XSdHK9/vkYxVlhCWRrj+LnUUmzsnKAUvtWw6kppuznmMUm6ocTt7LorwtV9/NMDcmh
R+6GkexZ10apZkXmWrY84fislnLQfKTsD/CSp4OXLXf23OLUD409tBZQ22q+3vWb0AvWysS6iu88
q5ppICV5VjClMNTq4Wnb7Ixi0ADd4VOyyZaMC4CdWSMlj2IDUhulQfRvjKvsi2zv5PA/zB63LUok
E0WEOqCyIGBFE2QrVyxmJEfJwxp1St8Sr8iRNQsKq7/SC8lQZSNGGIf4WOpPff52mmiaFY8qn8CB
oWV70wPHgBwVCJeykGO3BWjUl/Hoa7VkzeQKMAfqAp1yuUXhDAIp8raytQJi4HD5hz4yrUVz7KzU
5IEsvrFDyF3/vlILte8J2zbe6rEdIQJecKq4YQbznGP52BkBDLzzoxEqifY9zLZr051bA6USmPJ+
0XYDMWoSCjZGJGHvK9Sx2gI25NIpEDbrwg3OlAwv+e8N9lsJDffMNwLAEegITPqI8yIq6tgF0+Hh
3fE82brZ1BF1lLOun1s3xMnmysnPHB3gK1DnOeZ/bX301H1NGjNrosCyPjy7gyumkIEJECqhFREb
664g/wPinOU1ZmFsS0ihaTpfy1HYWdcLsP3tzZgLiX//Rt+qHqlZlgflBpHOrEu7cwbfzhaezEAM
9IEnAuX5/nndI65tAsEmpGdHaCf5yJr2cjzAews0V3ul9H4iMZKbpX1h8x2IVH0Ys/NypLJpiYy7
f+wfrxfCOKiaJudLq4JdOEb1CvLey3Z2PNtQmfMJ3sUayHcnWWNF6ypqEHm2s73gmZ83rVxoVjLI
4otcgZs1ZJREEs0glrJ2uYSrEmETml2UXnCVYL9qvr3STBHoeWR8RgxFBIF21XMg9URjtDMZThZ9
iw88N3kkBQSfNm8Y8VHsBoxTTD3wuIoWTAdY1yvWfRvibgLryETn8WirvwTDdGswnw4W+w4eTvoP
gT4Ej/vyXe680TWdOJgz7+gs8Ec46WQzi59ry5QfXzmrC78tMHaO/XeT/LPTPvXHYu6WNzHGeFAG
ZG5vWmr+LcExnAgHWdtMtaCy2qoOVPVTRKei1wMCFo/tYeCxEd6IlFWSAcS25TVmrM2pAb+CAQ8d
cv8EPGozqPk+8RW0ECy2I/WssIXIMtCC9lU/m/jkHcAHKJNBLD8UobE3QCezTAjTtWdGhP8ShDnv
r8+xtEdaVTDw9E6QHpOXedDC5R+PdJdQSuRNiMAnA1vgt5NC/Uc5Bbl0W8OvSfIMSfQwe148bpKg
j7KCUE6mrs2A6xlUPvLP+RO467i5FQpMNIt/j/13wCOGcYxqG9cPTu4wolbJIgtoMxaYV/a5+FyI
UpO+PxnpRzmY5yg6iKqWWAP1lDY7OXc6JIvyRwuNQAjfUiTsmaWTYU3RQ/KXFepU+lcGXWhiklvD
MEhcCdst9Eh94KLez1uiVXzP8RAZiRRsGlqirdGBIEQl9fqs9ukDI06GIwQpuAcd/l1ACWkj5U4z
gctdYMDpx8WttoPDOqaFGQDnK0yYs0ce7zWrZUChGxyFAwbukDOOi9yv2T1iyaF6iBmWtCJS+8gb
HFYTpLnyRa/eYcQ/2iEsJ5xIP+idbh/HrxZhXACD9o6O1cuGuBBVP39ie2Hr2vE2Jjx/v2ydIhpU
s8rwKrstI47p2cWchUvlJ/iwrniSUuCKMhAch68zOS84L6nDT/N60sX79085hjkP8F7jonUiooSb
A+Vpk7lIYBi3E8+GbgpMMqw4MbBs0hSPPuVezrvfghd7Pj/P22u3CxFqV+2nkLW5PgJLzjWoCIzD
77vWtvfNy6xs+W0G8Hs+73nGW9LuZJvXCc94jjGnSYT/KM1hhYvNBEs+EeySe3rmu3s+pH3wui44
Ro1y5DK03vjv0+AFp/sVZkn27RCwIhdj+DPYC2fKLgSDfZEMi4/oxI34GNLLCaVgYZMunTXSBikP
/rOC5jhLU+LA8fOzKBv0v4fNsElYU9hSFt9rRBuGtc36VAnYurMQvOOKiC4x8HMV6mqx+DQlprjp
zFeb+Wbbw+QidrV6dWjRxL7GsooWCD+kqXaWZqpNvm8rdUfqdSRXGZCgXn+/K+nQ6uwH366Bwk9y
jae5XYH5N+LXbj+SZQvkg81/7HG3NKjyCcRzyJutrvFz9jqr4jU2vJzYPpzT40QNJtWiyZNIgZZA
acsrBdPhgXzkYRUSM4mQGEyvXhcep/uVNKJZYO1t0zp20DLi4XtBYHGj2uF2h/BSCYQsyO/7xsp9
wLxOZHr9/JSlalWxH+sfsz6VJt4bF1mnWU+UbDt4Hc5XjNDZTKtQoWLeGXOBYI/A36VWwT/T/HeP
ptCPy9+S8zknNA0y16o098V5zMp9kv/XhcB4AlWEvjdunRnJIXn10zv/Yj3tKOCV358UfN0jMG3I
VvP7X5nGCimgVF969i9pz1eu/C61w7dLiqM0iCdhvS0OkE7GS2V982ogkGr5j64cdD9xQ7MyACUq
8YVkNCVkOTJsPxnwSvqKF0a4zCkXx+kNchJnipmazpGKfV4kdtn9X7rVSMOzdzCVhU9D91kRYHn9
0Qr6T3J/VKAD1sTHAzX3w3UmWkbZe+kSmxw4FcFzlAySpSUDpXHeA0hZFRUo2OU2ezHzVrjH9yhw
4TBEAxOqv1FEQi7s8ap4AdjleeU+vI0hlltqn9IbZItHh7ma/54Isb7Cqj7I1+DQo9aYVUUgHdvB
ZNMVClrbAMVQje/AIY7iwK6sWfLa/wzue/ttiYnyxOXB0Mk3C4ECR6TkWxLfbp9p6869w+c0ZJ6G
ZJ7FuEka4OfCMlF7SaWeG3K+TnT18x8rGdL35ocov5l6qRjroTmIa3ANcsAuwQC3+A7FbviWQGCI
g2hKwoexyLfTkGxshhdrYLiKCQCjkQBy9T/95HOvvcb2tkdiZZoXqkA+u+gSiXcJcjTuWHs2f4WD
IRG7BZNdPf7se0qU0C+Azq3iJYSupLmhnsH8bo7hWjuRkN1EL6FtM6SGZ1w72BDp53k1J+92AULK
SexBC2mxubE3G5B8SlcbMync4YW+8U7EaVi6j5maMR88EpkYo9qbhv4LcedUFN8BHvYMAjEMENc7
wVFN7PyIP62FPfCBeXqDFCCeLDYWBmELVMCGJazlBW5iktX6xgs4KZ7b5lI2GtSkDLvzzvpRp/Cb
LgEQHn2ASP7vb/Ssv6dnYl0RbiXpxG2cCLIfxsssj3TevZ2OcCez85KdZlbc7JoaLl7+W+si6cXl
bnfur22f9swYzwOeg6MOqXgVWY1ydXyuH0mCBql/rYMXdyLQUk/xepXEKtn+vvsWKdpIKm+RB3hW
AZyrtNiwn0otjQKNK33GXumkGWH5y6uQg9rXTYPIwf4AS2jMCPamfPSv/2OKTc5pQIz4l3i3FK7+
/N9syzX2E5XOSsZGnqsmI7bNC8Gvk9E3GfpzB1dOoG9F1Xocii10lB5ADmLE6+0sY+/vXzLDJSOe
bCMphI4pwfQIYfvUys+XWtiLQSVDxN/5uw30TeHGyQj+4QgNKzGqRxEjXMQJBkNjbcynZbcSKYq8
8P7l2mMUv1qXwd1jCd6CzSrqDrHt5qcH+ZYbt8QCJyxddgbAOgfrtNnb0+WCCKBtNCUmrTAa+XiK
8ZTjR6wPH/rhRfcU6ww4wStpkej1+ws1u5rhAv9YVFw5TICosdRDJC5SndE/F14biEQkcd8F17vq
hxqju2x9fEZSiVMF6ybcUGCMK1+u3ssdRQFZAowq8o8MQrm7o8c+HmFXmDsPA5AiyTnvKAQQZigc
C12mvF3qLiKxGAV1cbOvtTO/8yk0LAgn4jA84Ktf0CwrojMSQFaPF77Dc6QyAyadhs2iM2ZcezpO
DWKpFKpAtcl43rq8YSL2jfQSfo+nIHWQ6v/k9+75rXtVPs4I3y6TolsvBdq66BXfDbAELWCOC8PA
T7FCVp7B1/0TEgLALb3dyVdqlz3ZnyjVVl5Zpxuoe7oaNsrRFQKihhZqbOXMtkrEzQFXdkNESekL
oTc6bSXVa786IV4eOW7n6u90+yHXQ6vjkZn3Ni62Dzh1M+Wgb6ODV/tCxcX7/jOFopo8NU6PFbQJ
hlZoxu37y4pMrdDprCGf0097FlNcVjtoHQyJ+P4OkPccOt1q/g+UsezE4WaCiolhjzJJhPvG0rqy
UYpaflL2r1RS+Pu1q+xqtHuFHEwS786oUuOfn8R6SsO4AhGcTptEY2sLSarm67n7JMSiaEeE+iU2
vdNlv/tomb57gRDSRYmAmbFIzOMNDZDHDN8WrG4BwlpzWvNEVMSAjvBBbJfbVstXSJohrHFLfuNt
S7fc1T/cp5dNzSX9IcqFjiIhkz9OiMbvQyqfHlmBSvHt6FKfES2YQKYFCLAlcqf52xMBDD1+wF9o
fsdX3RLvtCrocs66mqRqxr3OlKsPWKiuMlG9iyrHoupkakNnES44ZuKzVv3ilw1cmt3bjDqXlczr
uEbBOScaSa9QNPJLDsJbY9j23BhqcWmFXCTfEI+DGInGO3A1YRY1x7YCgQjNX8HeVfmhrflKyjJo
IyAIbi6d/YpHysqAp4QkHdta8/Q87/vzSjKbp/q/zH1PhCtv5UCd119XCSQ4+S1MlYBRGh2L7Oay
FA5VY7Z8pgvwojHdKSd1SVzmUBnhQcQxyos1TYsfcA84RZk1Abb2QXMhIzQnbuKF8mZXJsWmD1al
796xUoXuvzbZCoLMerTY9mHQA7r5pvZYjPivvEUiotTVO48nuFtTols6pAD++hBdjRnepsdhh7+r
w0vVOzt4ABltwdoYgbMYBcOGQHiC51Kyj3YflyHb1MAocD38x5kSYrGxpDEcsf5Y6DVJffgr6kW5
gRd4TNqNbMlU+4a51mF7NukjmJPI4Ds3vquxY8ZsPs26Dh1iShevW0ZNGvXmgW4+WImKGM4/lzdR
1ebWA8pcdh0FfTOAz77mCrPY9E29EOKuM278APdkZRdQiDtomis+tDgqmi7Q+JA4gsTGoxfOAyXL
tEFJoZ768W48q9H0K88YBEHY7U5mh/rs5MaADSjlHxZFouxzbYK1UivNdcCm5PJ7lmPWVeibq4gu
aXp2qJS5G2c87nu5wkHqW6jXZgvvrXfBy2Q4eFFql+S+HacdV+T4NLeGYPDoWiGnI48LPPssim4c
orx2GftqYVUrNnSscjZXSK8bD4KnkYg5btIucxNKPhaJaaGon8L5FkeiuROxLnwCRipkaZZmdunZ
XJ24KyLsNTcuPvhggI+m6B3u3rIScocSDbvp0udv1lG5aij1RGwIaq6Jj0aNmxbE32vx+wsrulwV
TxFsqPbBWB8AOK57t+RYcEMawa/AGMvU6xxWyz5HKPAlucXd+YbFyozY/I+muSNcrdrl3JWnyoVi
O0s007bO6wP4XdaXlUxx8/A2BDjAUYnwNnX9lSz9dR8RXHUtaaOidjk1YIGF8bsB2M7IVpT44aaD
YQBTpR3mjQRFouQ9NVuoZyOWz/P1QNbIYJAee4p1EqeyMWnxQzAMHjxCOLBHz5p58YEP0mHB4HEh
1i0XPPAzefjFzEHRbkrTTv/X3b9PWC/4p5xzPL4kXSJBqMcQ7coPeAytX/c4blj2Mbs/oUykRqz+
hPC/pdRra7z8Vc2en1ydhxe4w5aj/gDlduY1+pcA3XayvSxJYxi3q1W52k7PhEFOXpQiKLIUlhLZ
wLBYCdYq+Z+qYmAT9iXN2HHREL2G2PJiDxhKGx0p6lpYuIzsW9RwfN9nZRoYjOwFXoz/0zk78r90
/t23psK2c61ixUUYNvp6sDSbGsHbnTz61DNKI++Q36Zuwd3IU8xD+siicrQOstt9nSSkAVSVkoJj
Qek6jCNI6un7hDykhTm+7nOab5CSqmZxd7ZexWMp+6JYku2LR+2bQ7nHofIMyX3G+UViEHvhCglg
VT5kmVh93eDpbaZ/2SUCAFqVJKPxYuxnGIR+q71Zeh9LmMggIR/MzLmyi71XYue5oexQg+/kzaYX
tpNnOrgeFJnNHG0xUWN3ChWBKYIBzIcSxTXgAb7LPe/a0L2EqXzuskb+gYPdnbGTPGYsolDhyN2b
WS2dqG/3LRML42sNlaUlhO66ETASA5EOyY6TtlDOFXAb/W9pZ2301wB4oacdHYk537PX5JiU6n4d
+WRWbFzG89gyhk8jkWX+pJQEJf/5MJr8NkgEMaMEc21bfLJj4E5KCTWFwE7nEa6ifjQauAaXiHh+
5lJG95R2ggdNfMjaiBMC35ayMiBGW1KMYy6lefvPl3txoYu/W6f+EdySpJZectOfJvXIwm0AY6Y7
MO+13ZEC+V0kY641wYlW1DgX9t6kr0eJCigHR4NiX/D7BGtosyx/rLg2SKY+eHzYUpTD4Lm4e14Y
oipGkW6Z2Qlqr3gBtx3BFOVvNSHx0jv5uu056CUBK99cgEVhJVmqimaGj4w6YM7XYYn2TdRVWRnu
VqCJnswi4/vLv46H1cZqtziSSn5a7tuIl+n69rlITXGBXjQaDCty1A085hTTX7QOU899gU/0IevE
6YQWtEW6G2Xx4SEIa9Kd8YlsEL5SA0IyzezXDuHWEZcMylHthtZwFRYS2+nxzBpCpkEbE/DoEb+x
R6Ch6lsRGQp+dqqgxf7odbGdW7C/nStzMT5fpKGCpHHGpam7i9h49qTE6lAALh8OIK/gcQTkS0RQ
ccDEyYG4Cmq8RZAC1sNxPLltpg8CIgdtW4PUr6+VRmqeLEup/Jg4J2m+KmeDSG8HhVvgi3ltl/HE
z4mILjP+0YjckkVq5DslB6OJmru40xMwbG7DFk9diX3DfU0DKfw80qFgakp3GPp/EnXgzBFaTQy7
pk3tzmUFP/cDD5h7Srv8Q8D7IsyQ94ldyznXzTfFw9SIx39paIiZcfPK0o+GN+RIJZWomIftzcXo
kooD6mRoG18u/9LA6yHyoHHLU7uLN/BBkl1URxEEXnINWEVXSoR9K1o7CcFTe7+rlLBJfr/ilqE9
bwAH3Brih1oUug7jp1+MZuUl1znFvbAxEdo6o+jsg5Gqyz6JRZ6MzVmJjzPmobJfurUiFDsXuQym
3C/FiJ5vtjHwOPMqWiH+2hmpiCnKjrKbw+IovBAPxCnXXz1lCl8d9O/mPIO46564fCBXRiTEskLA
K7amY6iAFQkUaNO0fnTlEPrbc/jl7rGHBkyvm+fywC1VNzW6P5ZoHPvRASeFL3M/V5xSLkqtGTPa
4s6o6VRd2Kbajt/Jui9WEwn6IqXQPGp+TAtqQ8jus34Nk6+ynuIZoq/kkc/cVE6UVGCRIOIC/MX5
E1BiC0G4mAHIj/Gm8H4bd+zsjV16Uofs7hIJcbz8RnsBd2HQtv+pMzP7EteApMlnqOO0sazSklGA
5L0Lcfo+MrRyyonDyMYWKzhotAcPjfLY20VILgCLlH+yXUMgSqwQ8xUgrdlWQS68FzcrX5GwYHJD
AcCUbUU3xHOA2iIgNq9G6S9XVcSKxGKqVbj8V8pKTVlI6mOyduXJ8ZOPw3f8pTq/nHf/SD/vjKK/
w6hgTKGVxm7eM/+6lmtDlsu2FXXWQWN8ITyDlpYzSMpDYQ3HsaT3ihcbFBZK0T0NP0h9NDH6jOkb
/rLAS0wIYhKR8fSJHJcLzUi3CBIDlmrax9sVW81kEj2qqvYmTQQ26VyGBxtJ5tjNraJLv/fNxH7g
QBHjHeJ2D3jPP0kqFKjmQm5F9mmCO9IT8rMzduFVzjE1nAxjG8gP0FFHn1syM+4C5i+4NmSurbmQ
w55sVWIH+vizx5ufI7AjZw47FNkfwy4xXoM0JNs5bD5TFpIJJr0gc+WBn/ChcPlEqb2AoFHKB42k
AmS1atTSbD5zodSutIk2kTrUKQpOjsHVut59OQLDg6doqCfOD2A9cJO9twksQWEq9AOTvKU+EWSy
mtCEQ5qfbfaKT7s7dduaMzzPnJQSRvtC2h0nKWuLYgRGYykY6HaBlj2BsCdtgdshK2H7q3Sch5f7
5gOjKc8IDVeve6PfzAuq68lKNgnpOnBcH3Wc+6zmAK8ufiHo0HSp7OXcNRHHpXo3MG7EnAF+i1dz
HllJp26QK0i+Hsgre/3FIYZaTjXUo5E//1svf79YrZ+JxFo7VqNb9tUaTYZQrRYXBbekzhqN6qkl
fe72t8fJOXObJ5cY29FzAtGF1rBDbjq/4wNRXxXmFK1DFzE6Za5cRfQcPgeBMDaL0YzyxfTBJ+WZ
KjV0ZmSdYI3dlwiJa2twcktriZRbmvsW48SYrHrYBleJfUvrSQq8Ba1o5yP4Sbp06wHi2lm0jbaJ
6UJilp6zKjP9aoyPT4tQiI7FcGDUWPa3Tjbd0RSe1A8XbFTGapzkjaALH2mNDRwOyFbdiDQXq0ZH
UvPmzlbjGXlTiSVf4gwNstc+joAKTd/rhCbtTSVXrk1qdLWKFHhewzFX5zNwyl+m8VQLD2DPe5YM
t0MUlSRsca1DNHTihXEQraZDgz5XXgIVVIG0QVnAUxN7iB83mA50PTjf8oP9G+V5sqQ6WCAwESxo
4/AKSAvXOH9mqB2o3SxXEZE5rPxG9m5zmqw+QzqXP+hcZap9VzFBVQieCi7qlR8yHMU/ov0+aFOz
vlQ3D9nlK8sWFk2VwzkbfQW/i+juJXbiUj6V8XPjOK3NAr+SDLSWuL90RuTqKXw3Lzk2JwXY08q7
1FZLXlnk6jdccIAKaX//9/gH/T9wSRZt9extME8Rrd/7w/LjqkjLjrhbFp2ApxzhMMpY0aLtwaQd
SqvGdApg+/NziuH5AoW0xXGKssaf07/p74Wjt9x0OHWyZsFWd8EaNpxRFmWxd6W//3KVXiBnMZvS
XZjJvk0LRJtjphwTS/mkbWtdLUuVYyyFZsNj4tS7MX6aM0rohWirmchuQtF3tutJDtAC9gN8vCfS
0CjFG1mIDE9KvPFU8SoXWJbFPcU0GhDhdI1C/ofiPgavayeDiEiLf1/XW0Cfa2RZIIzSIH74w238
m8I+xTWZD0gGQLZGuh8Fqx/DL5rs7+yGKxvh3LgSYs3B4JX++ui+4QN5KtJXl6Fh71I02B0ba0K0
+flnr9pJoceP+wAfYVFbtBGOugguFn6I8nwODNq8n+Pb0gDn852kOYm3j4yGAdPMFvwKHzsr6PU4
UX05c9ta8yvelmUs1bOHGbP2P31xcYkZwA3aVGt7vmO8we6GaCxUv/obKWGuAkMc0mX9jAuvFjfb
hyXr83uu2xaR6cG+PXasp8bfqV9QmFTowWD8Pao5uT+U2Gwcyu+AnvJ0yoCJprJpGgz23tcvb+F0
Ca9B2ySc/x0fMPLx4XBpyx9ukZuGWiS1e884ZobXvvPpGtO+k+Q03Bz0NIl66cdBJvEhLPYaMHIk
JjWl0S+HjtD8MrAwc9HW+eCmVPZ7eLuxE1r/AwpVEIM29gYPWnBHJQDXBD3yCdJwmqTAST52q500
9XVmEljpg+RECm7Yr2p4LP2zYCihQFqO0iN1njVOjjyiYmZPtMFptIqIMMyGnmNvUf4KElp4lNlW
2aAdyD4HJ6hOfJohBzStqyXaDIt8velbesdJSf15mCJe+HlG/53xJRbtpOOuqYCP4mK48Fa6KJsp
JXeSlT119vkE8CWT9qIGqV33yUdL+WxMByZa32dYKfscwF60AcWkwLRMFcHgvzO5kNAF1nhHdzYr
FdZA7UtKP6IDQ/tVq3+AeKbvJyspmsLoIRAnAmfnk8wjIRs4YBi9uXK3+9dkaraM7unpvlo4BaST
B41j9x4BEPDcviSHEQiYcn7WpCjWPePjZobIgZZktA64fSyvOSKXrZj2zP3lkYnjBZjPLsKphcA4
+pf/eYb/ent5YuI3ipuN0XkhXTm0snBgbjBdlK4jljR0v2BkvkT5UFTYTZkccJCEQJwnx94tXZvT
TmRRR1k34af1xqDNqYHlbl0oBIgathRLEB5crIqKFDJLVe1urpf3gj5EK7TTOyAp/OIUiAqlJn9E
sFFXv5fCCMbpBvtGXpTYwiE2lJZJjQaRyZxXzlFu+sqYEEAiC+3rL34pt7KjZQLRcb4hl8ZMXGfK
3Zggjh/kkkK7tnZSm/VWurpYcqaQP/MAXtGrQ2QoZL6MIKqwZ7Hb2GQgWYmTMmi1kWbioS0d8iLX
Pz0tkixBhZb9RWVjmLRB8hYo1uSSgm3hPZMfUIAupaaR84qcNaIpws8k9P4DSCbZpoNAfkGsZjUH
ETgrrBuE0xEB+2CvBQ06TSS9EuPE1tF41DbNlXnagDsm7gfucLP3YbOgs3K14NoiIx0G7QMq3rNr
ydgV4l8YYendIAat5HSb4Th1BZsTx6pE5XIRfVtuG8uBckY8C45QpNc2ram7rKjkP8MsllwmRjzL
rJOk2blPgKZVpCT1KJ541gpdw9nkRxCReU3GOaR7Ae4Vq9cFZP1zz3R8/EG3mRhPTxGUEgGjUHG6
Nf7fVjzb1y9Nx3rgIwdA8Q1DT5mA05ECqHgWRTpVBU4kPbXt/Sogd+8joztjVBniqbwuccJhEy0s
1NFuVdZ98CLcDW+IaELl/t+mEN9g2ZpJH6Qxf1VWMh1LjNep+yprfhnCR9bFxhq8tRvjmrhZXW0T
9cFPfzarmfbmsseORWb/h/WquNQaDQf8fSVVjmc4kZn1OPiusj+wdEwlLPSFH5mVZFXEfK5oWcRS
PN6CqCQYRylz4QgIPQrTsSGhDljEeapgBSkk29b6szkP/NUu/mstXUpKBB2UKf31CJ2i83NXpfDe
TcjLmylFX3dFWGcumd+cD8ab2wHJxbu/qEsQJ4xqelEvPXobnHXuzgrD4Zq9SQPMnXNVLV2D0MfT
RpEZQqQxXfvE3BXawE6Xk78pTcOgNtDTUuitBU9MqmgKY3ypmNiV9AKhkJ3r6P9WGP+qghJ67eHh
qJLpsRohn1PCkFr95OfHx9w0ZyLFs30OPy6F2xUEGMfOncq59YovAUOGA6XJmshdiz0BuSrS7P2T
iFNEZIJDFHEH/PoBTGcJX+IwLEsGC6gDZjWtdJhKemJK19R/GPsvNe1ummp8p75W6FNfHPp6mwSv
v4Gf5wmEWan7zn14eRiiBiu9+WcQkdyArGOtLdiLBeE7jjStLDi5M7SQ9+zIvij2doQCGeArM2b7
Ucgq2ZyrVShTK2f8pN1IspJ1pFDYtRn5aWqGaogJEv4YQvV+V6kv2R6vS8PEZ4RxH5op6p4e449M
nCDpWXc40gdeEWVYcr10XMtf7ZwMW+xxq+SbE8oU6SDb99R481m9O94c4JzjT4FYwEzDM2TwLuy/
+uuHyrCn7xZDbGOJW36gX7p3DjdTEx6y/Yw5r0CE7IOO7168WcKgqO+l/RV0LLlBACQbWzQ2ZdoV
ZwXJwvGOFZ+EYasNCfs0sJX/DXe3bbz8J6mww3D0bj/iSiqyacqYFHzYr4ck16x9bxPjCiSudkWw
ESeLp2h9jHnyhILD8r8uyQZG3yhK+eECj9O3UnztkUXYjCkaxLIjmObNBWV+dfKyrrXTxO5pg2XJ
cNAdxVFwRQlStrM3Ic6LmE39AnrN+/dpqAknQUNnnKsYQAlU
`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package command_if_pkg is
constant c_cif_io_slot_base : unsigned(3 downto 0) := X"0";
constant c_cif_io_slot_enable : unsigned(3 downto 0) := X"1";
constant c_cif_io_handshake_out : unsigned(3 downto 0) := X"2"; -- write will also cause pointers to be reset
constant c_cif_io_handshake_in : unsigned(3 downto 0) := X"3";
constant c_cif_io_command_start : unsigned(3 downto 0) := X"4"; -- read only; tells software where the buffers are.
constant c_cif_io_command_end : unsigned(3 downto 0) := X"5";
constant c_cif_io_response_start : unsigned(3 downto 0) := X"6"; -- read only; tells software where the buffers are.
constant c_cif_io_response_end : unsigned(3 downto 0) := X"7";
constant c_cif_io_status_start : unsigned(3 downto 0) := X"8"; -- read only; tells software where the buffers are.
constant c_cif_io_status_end : unsigned(3 downto 0) := X"9";
constant c_cif_io_status_length : unsigned(3 downto 0) := X"A"; -- write will reset status readout
constant c_cif_io_irq_mask : unsigned(3 downto 0) := X"B"; -- read/write
constant c_cif_io_response_len_l : unsigned(3 downto 0) := X"C"; -- write will reset response readout
constant c_cif_io_response_len_h : unsigned(3 downto 0) := X"D"; -- read will return the current pointer
constant c_cif_io_command_len_l : unsigned(3 downto 0) := X"E"; -- read only
constant c_cif_io_command_len_h : unsigned(3 downto 0) := X"F";
constant c_cif_io_irq_mask_set : unsigned(3 downto 0) := X"4"; -- write only
constant c_cif_io_irq_mask_clear : unsigned(3 downto 0) := X"5"; -- write only
constant c_cif_bus_id : unsigned(2 downto 0) := "011"; -- RO
constant c_cif_slot_control : unsigned(2 downto 0) := "100"; -- R/W
constant c_cif_slot_command : unsigned(2 downto 0) := "101"; -- WO
constant c_cif_slot_response : unsigned(2 downto 0) := "110"; -- RO
constant c_cif_slot_status : unsigned(2 downto 0) := "111"; -- RO
constant c_cmd_if_command_buffer_addr : unsigned(10 downto 0) := to_unsigned( 0, 11);
constant c_cmd_if_response_buffer_addr : unsigned(10 downto 0) := to_unsigned( 896, 11);
constant c_cmd_if_status_buffer_addr : unsigned(10 downto 0) := to_unsigned(1792, 11);
constant c_cmd_if_command_buffer_size : integer := 896;
constant c_cmd_if_response_buffer_size : integer := 896;
constant c_cmd_if_status_buffer_size : integer := 256;
constant c_cmd_if_command_buffer_end : unsigned(10 downto 0) := to_unsigned( 0 + c_cmd_if_command_buffer_size-1, 11);
constant c_cmd_if_response_buffer_end : unsigned(10 downto 0) := to_unsigned( 896 + c_cmd_if_response_buffer_size-1, 11);
constant c_cmd_if_status_buffer_end : unsigned(10 downto 0) := to_unsigned(1792 + c_cmd_if_status_buffer_size-1, 11);
end package;
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_adder_subtractor - Structural
-- Description: Adds/subtracts two IEEE-754 floating point numbers
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ieee754_fp_adder_subtractor is
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0)
);
end ieee754_fp_adder_subtractor;
architecture Structural of ieee754_fp_adder_subtractor is
signal x_sign, y_sign, z_sign : std_logic;
signal x_exponent, y_exponent, z_exponent : std_logic_vector(7 downto 0);
signal x_mantissa, y_mantissa : std_logic_vector(24 downto 0);
signal z_mantissa : std_logic_vector(22 downto 0);
begin
x_sign <= x(31);
y_sign <= y(31);
z(31) <= z_sign;
x_exponent <= x(30 downto 23);
y_exponent <= y(30 downto 23);
z(30 downto 23) <= z_exponent;
x_mantissa(24) <= '0';
x_mantissa(23) <= '1';
x_mantissa(22 downto 0) <= x(22 downto 0);
y_mantissa(24) <= '0';
y_mantissa(23) <= '1';
y_mantissa(22 downto 0) <= y(22 downto 0);
z(22 downto 0) <= z_mantissa;
process(x_sign, y_sign, x_exponent, y_exponent, x_mantissa, y_mantissa)
variable sign : std_logic := '0';
variable large_exp, small_exp, msb : integer;
variable sum, shifted_sum : unsigned(24 downto 0);
variable large_mant, small_mant: unsigned(24 downto 0);
begin
-- determine which is of greater magnitude: x or y
if unsigned(x_exponent) > unsigned(y_exponent) then
large_exp := to_integer(unsigned(x_exponent));
small_exp := to_integer(unsigned(y_exponent));
large_mant := unsigned(x_mantissa);
small_mant := unsigned(y_mantissa);
sign := x_sign;
else
large_exp := to_integer(unsigned(y_exponent));
small_exp := to_integer(unsigned(x_exponent));
large_mant := unsigned(y_mantissa);
small_mant := unsigned(x_mantissa);
sign := y_sign;
end if;
-- shift the smaller to match the larger, add if the signs match, subtract if not
if (x_sign xor y_sign) = '0' then
sum := large_mant + (small_mant srl (large_exp - small_exp));
else
sum := large_mant - (small_mant srl (large_exp - small_exp));
end if;
msb := 0;
-- shift back the result
for i in 0 to 24 loop
if sum(i) = '1' then
msb := i;
end if;
end loop;
shifted_sum := sum sll 23 - msb;
z_mantissa <= std_logic_vector(shifted_sum(22 downto 0));
z_exponent <= std_logic_vector(to_signed(large_exp, 8) - to_signed(23 - msb, 8));
-- if the result was zero, make the sign positive
if sum = "000000000000000000000000" then
sign := '0';
end if;
z_sign <= sign;
end process;
end Structural;
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_adder_subtractor - Structural
-- Description: Adds/subtracts two IEEE-754 floating point numbers
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ieee754_fp_adder_subtractor is
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0)
);
end ieee754_fp_adder_subtractor;
architecture Structural of ieee754_fp_adder_subtractor is
signal x_sign, y_sign, z_sign : std_logic;
signal x_exponent, y_exponent, z_exponent : std_logic_vector(7 downto 0);
signal x_mantissa, y_mantissa : std_logic_vector(24 downto 0);
signal z_mantissa : std_logic_vector(22 downto 0);
begin
x_sign <= x(31);
y_sign <= y(31);
z(31) <= z_sign;
x_exponent <= x(30 downto 23);
y_exponent <= y(30 downto 23);
z(30 downto 23) <= z_exponent;
x_mantissa(24) <= '0';
x_mantissa(23) <= '1';
x_mantissa(22 downto 0) <= x(22 downto 0);
y_mantissa(24) <= '0';
y_mantissa(23) <= '1';
y_mantissa(22 downto 0) <= y(22 downto 0);
z(22 downto 0) <= z_mantissa;
process(x_sign, y_sign, x_exponent, y_exponent, x_mantissa, y_mantissa)
variable sign : std_logic := '0';
variable large_exp, small_exp, msb : integer;
variable sum, shifted_sum : unsigned(24 downto 0);
variable large_mant, small_mant: unsigned(24 downto 0);
begin
-- determine which is of greater magnitude: x or y
if unsigned(x_exponent) > unsigned(y_exponent) then
large_exp := to_integer(unsigned(x_exponent));
small_exp := to_integer(unsigned(y_exponent));
large_mant := unsigned(x_mantissa);
small_mant := unsigned(y_mantissa);
sign := x_sign;
else
large_exp := to_integer(unsigned(y_exponent));
small_exp := to_integer(unsigned(x_exponent));
large_mant := unsigned(y_mantissa);
small_mant := unsigned(x_mantissa);
sign := y_sign;
end if;
-- shift the smaller to match the larger, add if the signs match, subtract if not
if (x_sign xor y_sign) = '0' then
sum := large_mant + (small_mant srl (large_exp - small_exp));
else
sum := large_mant - (small_mant srl (large_exp - small_exp));
end if;
msb := 0;
-- shift back the result
for i in 0 to 24 loop
if sum(i) = '1' then
msb := i;
end if;
end loop;
shifted_sum := sum sll 23 - msb;
z_mantissa <= std_logic_vector(shifted_sum(22 downto 0));
z_exponent <= std_logic_vector(to_signed(large_exp, 8) - to_signed(23 - msb, 8));
-- if the result was zero, make the sign positive
if sum = "000000000000000000000000" then
sign := '0';
end if;
z_sign <= sign;
end process;
end Structural;
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: ieee754_fp_adder_subtractor - Structural
-- Description: Adds/subtracts two IEEE-754 floating point numbers
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ieee754_fp_adder_subtractor is
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0)
);
end ieee754_fp_adder_subtractor;
architecture Structural of ieee754_fp_adder_subtractor is
signal x_sign, y_sign, z_sign : std_logic;
signal x_exponent, y_exponent, z_exponent : std_logic_vector(7 downto 0);
signal x_mantissa, y_mantissa : std_logic_vector(24 downto 0);
signal z_mantissa : std_logic_vector(22 downto 0);
begin
x_sign <= x(31);
y_sign <= y(31);
z(31) <= z_sign;
x_exponent <= x(30 downto 23);
y_exponent <= y(30 downto 23);
z(30 downto 23) <= z_exponent;
x_mantissa(24) <= '0';
x_mantissa(23) <= '1';
x_mantissa(22 downto 0) <= x(22 downto 0);
y_mantissa(24) <= '0';
y_mantissa(23) <= '1';
y_mantissa(22 downto 0) <= y(22 downto 0);
z(22 downto 0) <= z_mantissa;
process(x_sign, y_sign, x_exponent, y_exponent, x_mantissa, y_mantissa)
variable sign : std_logic := '0';
variable large_exp, small_exp, msb : integer;
variable sum, shifted_sum : unsigned(24 downto 0);
variable large_mant, small_mant: unsigned(24 downto 0);
begin
-- determine which is of greater magnitude: x or y
if unsigned(x_exponent) > unsigned(y_exponent) then
large_exp := to_integer(unsigned(x_exponent));
small_exp := to_integer(unsigned(y_exponent));
large_mant := unsigned(x_mantissa);
small_mant := unsigned(y_mantissa);
sign := x_sign;
else
large_exp := to_integer(unsigned(y_exponent));
small_exp := to_integer(unsigned(x_exponent));
large_mant := unsigned(y_mantissa);
small_mant := unsigned(x_mantissa);
sign := y_sign;
end if;
-- shift the smaller to match the larger, add if the signs match, subtract if not
if (x_sign xor y_sign) = '0' then
sum := large_mant + (small_mant srl (large_exp - small_exp));
else
sum := large_mant - (small_mant srl (large_exp - small_exp));
end if;
msb := 0;
-- shift back the result
for i in 0 to 24 loop
if sum(i) = '1' then
msb := i;
end if;
end loop;
shifted_sum := sum sll 23 - msb;
z_mantissa <= std_logic_vector(shifted_sum(22 downto 0));
z_exponent <= std_logic_vector(to_signed(large_exp, 8) - to_signed(23 - msb, 8));
-- if the result was zero, make the sign positive
if sum = "000000000000000000000000" then
sign := '0';
end if;
z_sign <= sign;
end process;
end Structural;
|
library ieee;
use ieee.std_logic_1164.all;
use work.exploration_pkg.all;
entity ExplorationGrid is port (
currentCellsInView: in gridArray;
grid : out gridArray);
end ExplorationGrid;
architecture explorationGrid of ExplorationGrid is
signal exploredGrid : gridArray;
begin
process(currentCellsInView)
begin
for i in 0 to currentCellsInView'length-1 loop
exploredGrid(i) <= '1';
end loop;
end process;
process(exploredGrid)
begin
grid <= exploredGrid;
end process;
end explorationGrid; |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split2 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split2;
architecture augh of output_split2 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split2 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split2;
architecture augh of output_split2 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_snhumanio_b3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2014.4; ghdl 0.31
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-16 636 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
end package sys_conf;
|
--*****************************************************************************
-- (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : bank_cntrl.vhd
-- /___/ /\ Date Last Modified : $date$
-- \ \ / \ Date Created : Tue Jun 30 2009
-- \___\/\___\
--
--Device : Virtex-6
--Design Name : DDR3 SDRAM
--Purpose :
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Structural block instantiating the three sub blocks that make up
-- a bank machine.
entity bank_cntrl is
generic (
TCQ : integer := 100;
ADDR_CMD_MODE : string := "1T";
BANK_WIDTH : integer := 3;
BM_CNT_WIDTH : integer := 2;
BURST_MODE : string := "8";
COL_WIDTH : integer := 12;
CWL : integer := 5;
DATA_BUF_ADDR_WIDTH : integer := 8;
DRAM_TYPE : string := "DDR3";
ECC : string := "OFF";
ID : integer := 4;
nBANK_MACHS : integer := 4;
nCK_PER_CLK : integer := 2;
nCNFG2RD_EN : integer := 2;
nCNFG2WR : integer := 2;
nOP_WAIT : integer := 0;
nRAS_CLKS : integer := 10;
nRCD : integer := 5;
nRTP : integer := 4;
nRP : integer := 10;
nWTP_CLKS : integer := 5;
ORDERING : string := "NORM";
RANK_WIDTH : integer := 2;
RANKS : integer := 4;
RAS_TIMER_WIDTH : integer := 5;
ROW_WIDTH : integer := 16;
STARVE_LIMIT : integer := 2
);
port (
wr_this_rank_r : out std_logic_vector(RANKS - 1 downto 0); -- From bank_state0 of bank_state.v
start_rcd : out std_logic;
start_pre_wait : out std_logic;
rts_row : out std_logic;
rts_col : out std_logic;
rtc : out std_logic;
row_cmd_wr : out std_logic;
row_addr : out std_logic_vector(ROW_WIDTH - 1 downto 0);
req_size_r : out std_logic;
req_row_r : out std_logic_vector(ROW_WIDTH - 1 downto 0);
req_ras : out std_logic;
req_periodic_rd_r : out std_logic;
req_cas : out std_logic;
req_bank_r : out std_logic_vector(BANK_WIDTH - 1 downto 0);
rd_this_rank_r : out std_logic_vector(RANKS - 1 downto 0);
rb_hit_busy_ns : out std_logic;
ras_timer_ns : out std_logic_vector(RAS_TIMER_WIDTH - 1 downto 0);
rank_busy_r : out std_logic_vector(RANKS - 1 downto 0);
ordered_r : out std_logic;
ordered_issued : out std_logic;
op_exit_req : out std_logic;
end_rtp : out std_logic;
demand_priority : out std_logic;
demand_act_priority : out std_logic;
col_rdy_wr : out std_logic;
col_addr : out std_logic_vector(ROW_WIDTH - 1 downto 0);
act_this_rank_r : out std_logic_vector(RANKS - 1 downto 0);
idle_ns : out std_logic;
req_wr_r : out std_logic;
rd_wr_r : out std_logic;
bm_end : out std_logic;
idle_r : out std_logic;
head_r : out std_logic;
req_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0);
rb_hit_busy_r : out std_logic;
passing_open_bank : out std_logic;
maint_hit : out std_logic;
req_data_buf_addr_r : out std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
wtr_inhbt_config_r : in std_logic_vector(RANKS - 1 downto 0);
was_wr : in std_logic;
was_priority : in std_logic;
use_addr : in std_logic;
start_rcd_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
size : in std_logic;
sent_row : in std_logic;
sent_col : in std_logic;
sending_row : in std_logic;
sending_col : in std_logic;
rst : in std_logic;
row : in std_logic_vector(ROW_WIDTH - 1 downto 0);
req_rank_r_in : in std_logic_vector((RANK_WIDTH * nBANK_MACHS * 2) - 1 downto 0);
rd_rmw : in std_logic;
rd_data_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
rb_hit_busy_ns_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
rb_hit_busy_cnt : in std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
ras_timer_ns_in : in std_logic_vector((2 * (RAS_TIMER_WIDTH * nBANK_MACHS)) - 1 downto 0);
rank : in std_logic_vector(RANK_WIDTH - 1 downto 0);
periodic_rd_rank_r : in std_logic_vector(RANK_WIDTH - 1 downto 0);
periodic_rd_insert : in std_logic;
periodic_rd_ack_r : in std_logic;
passing_open_bank_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
order_cnt : in std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
op_exit_grant : in std_logic;
maint_zq_r : in std_logic;
maint_req_r : in std_logic;
maint_rank_r : in std_logic_vector(RANK_WIDTH - 1 downto 0);
maint_idle : in std_logic;
low_idle_cnt_r : in std_logic;
io_config_valid_r : in std_logic;
io_config_strobe : in std_logic;
io_config : in std_logic_vector(RANK_WIDTH downto 0);
inhbt_wr_config : in std_logic;
inhbt_rd_r : in std_logic_vector(RANKS - 1 downto 0);
inhbt_rd_config : in std_logic;
inhbt_act_faw_r : in std_logic_vector(RANKS - 1 downto 0);
idle_cnt : in std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
hi_priority : in std_logic;
dq_busy_data : in std_logic;
dfi_rddata_valid : in std_logic;
demand_priority_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
demand_act_priority_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
data_buf_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
col : in std_logic_vector(COL_WIDTH - 1 downto 0);
cmd : in std_logic_vector(2 downto 0);
clk : in std_logic;
bm_end_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
bank : in std_logic_vector(BANK_WIDTH - 1 downto 0);
adv_order_q : in std_logic;
accept_req : in std_logic;
accept_internal_r : in std_logic
);
end entity bank_cntrl;
architecture trans of bank_cntrl is
component bank_compare
generic (
BANK_WIDTH : integer := 3;
TCQ : integer := 100;
BURST_MODE : string := "8";
COL_WIDTH : integer := 12;
DATA_BUF_ADDR_WIDTH : integer := 8;
ECC : string := "OFF";
RANK_WIDTH : integer := 2;
RANKS : integer := 4;
ROW_WIDTH : integer := 16
);
port (
req_data_buf_addr_r : out std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
req_periodic_rd_r : out std_logic;
req_size_r : out std_logic;
rd_wr_r : out std_logic;
req_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0);
req_bank_r : out std_logic_vector(BANK_WIDTH - 1 downto 0);
req_row_r : out std_logic_vector(ROW_WIDTH - 1 downto 0);
req_wr_r : out std_logic;
req_priority_r : out std_logic;
rb_hit_busy_r : out std_logic; -- rank-bank hit on non idle row machine
rb_hit_busy_ns : out std_logic;
row_hit_r : out std_logic;
maint_hit : out std_logic;
col_addr : out std_logic_vector(ROW_WIDTH - 1 downto 0);
req_ras : out std_logic;
req_cas : out std_logic;
row_cmd_wr : out std_logic;
row_addr : out std_logic_vector(ROW_WIDTH - 1 downto 0);
rank_busy_r : out std_logic_vector(RANKS - 1 downto 0);
clk : in std_logic;
idle_ns : in std_logic;
idle_r : in std_logic;
data_buf_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
periodic_rd_insert : in std_logic;
size : in std_logic;
cmd : in std_logic_vector(2 downto 0);
sending_col : in std_logic;
rank : in std_logic_vector(RANK_WIDTH - 1 downto 0);
periodic_rd_rank_r : in std_logic_vector(RANK_WIDTH - 1 downto 0);
bank : in std_logic_vector(BANK_WIDTH - 1 downto 0);
row : in std_logic_vector(ROW_WIDTH - 1 downto 0);
col : in std_logic_vector(COL_WIDTH - 1 downto 0);
hi_priority : in std_logic;
maint_rank_r : in std_logic_vector(RANK_WIDTH - 1 downto 0);
maint_zq_r : in std_logic;
auto_pre_r : in std_logic;
rd_half_rmw : in std_logic;
act_wait_r : in std_logic
);
end component;
component bank_queue
generic (
TCQ : integer := 100;
BM_CNT_WIDTH : integer := 2;
nBANK_MACHS : integer := 4;
ORDERING : string := "NORM";
ID : integer := 0
);
port (
head_r : out std_logic;
tail_r : out std_logic;
idle_ns : out std_logic;
idle_r : out std_logic;
pass_open_bank_ns : out std_logic;
pass_open_bank_r : out std_logic;
auto_pre_r : out std_logic;
bm_end : out std_logic;
passing_open_bank : out std_logic;
ordered_issued : out std_logic;
ordered_r : out std_logic;
order_q_zero : out std_logic;
rcv_open_bank : out std_logic; --= 1'b0;
rb_hit_busies_r : out std_logic_vector(nBANK_MACHS * 2 - 1 downto 0);
q_has_rd : out std_logic;
q_has_priority : out std_logic;
wait_for_maint_r : out std_logic;
clk : in std_logic;
rst : in std_logic;
accept_internal_r : in std_logic;
use_addr : in std_logic;
periodic_rd_ack_r : in std_logic;
bm_end_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
idle_cnt : in std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
rb_hit_busy_cnt : in std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
accept_req : in std_logic;
rb_hit_busy_r : in std_logic;
maint_idle : in std_logic;
maint_hit : in std_logic;
row_hit_r : in std_logic;
pre_wait_r : in std_logic;
allow_auto_pre : in std_logic;
sending_col : in std_logic;
bank_wait_in_progress : in std_logic;
precharge_bm_end : in std_logic;
req_wr_r : in std_logic;
rd_wr_r : in std_logic;
adv_order_q : in std_logic;
order_cnt : in std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
rb_hit_busy_ns_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
passing_open_bank_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
was_wr : in std_logic;
maint_req_r : in std_logic;
was_priority : in std_logic
);
end component;
component bank_state
generic (
TCQ : integer := 100;
ADDR_CMD_MODE : string := "1T";
BM_CNT_WIDTH : integer := 2;
BURST_MODE : string := "8";
CWL : integer := 5;
DATA_BUF_ADDR_WIDTH : integer := 8;
DRAM_TYPE : string := "DDR3";
ECC : string := "OFF";
ID : integer := 0;
nBANK_MACHS : integer := 4;
nCK_PER_CLK : integer := 2;
nCNFG2RD_EN : integer := 2;
nCNFG2WR : integer := 2;
nOP_WAIT : integer := 0;
nRAS_CLKS : integer := 10;
nRP : integer := 10;
nRTP : integer := 4;
nRCD : integer := 5;
nWTP_CLKS : integer := 5;
ORDERING : string := "NORM";
RANKS : integer := 4;
RANK_WIDTH : integer := 4;
RAS_TIMER_WIDTH : integer := 5;
STARVE_LIMIT : integer := 2
);
port (
start_rcd : out std_logic;
act_wait_r : out std_logic;
ras_timer_ns : out std_logic_vector(RAS_TIMER_WIDTH - 1 downto 0);
rd_half_rmw : out std_logic;
end_rtp : out std_logic;
bank_wait_in_progress : out std_logic;
start_pre_wait : out std_logic;
op_exit_req : out std_logic;
pre_wait_r : out std_logic;
allow_auto_pre : out std_logic;
precharge_bm_end : out std_logic;
demand_act_priority : out std_logic;
rts_row : out std_logic;
act_this_rank_r : out std_logic_vector(RANKS - 1 downto 0);
demand_priority : out std_logic;
rtc : out std_logic;
col_rdy_wr : out std_logic;
rts_col : out std_logic;
wr_this_rank_r : out std_logic_vector(RANKS - 1 downto 0);
rd_this_rank_r : out std_logic_vector(RANKS - 1 downto 0);
clk : in std_logic;
rst : in std_logic;
bm_end : in std_logic;
pass_open_bank_r : in std_logic;
sending_row : in std_logic;
rcv_open_bank : in std_logic;
sending_col : in std_logic;
rd_wr_r : in std_logic;
req_wr_r : in std_logic;
rd_data_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
req_data_buf_addr_r : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
dfi_rddata_valid : in std_logic;
rd_rmw : in std_logic;
ras_timer_ns_in : in std_logic_vector((2 * (RAS_TIMER_WIDTH * nBANK_MACHS)) - 1 downto 0);
rb_hit_busies_r : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
idle_r : in std_logic;
passing_open_bank : in std_logic;
low_idle_cnt_r : in std_logic;
op_exit_grant : in std_logic;
tail_r : in std_logic;
auto_pre_r : in std_logic;
pass_open_bank_ns : in std_logic;
req_rank_r : in std_logic_vector(RANK_WIDTH - 1 downto 0);
req_rank_r_in : in std_logic_vector((RANK_WIDTH * nBANK_MACHS * 2) - 1 downto 0);
start_rcd_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
inhbt_act_faw_r : in std_logic_vector(RANKS - 1 downto 0);
wait_for_maint_r : in std_logic;
head_r : in std_logic;
sent_row : in std_logic;
demand_act_priority_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
order_q_zero : in std_logic;
sent_col : in std_logic;
q_has_rd : in std_logic;
q_has_priority : in std_logic;
req_priority_r : in std_logic;
idle_ns : in std_logic;
demand_priority_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
io_config_strobe : in std_logic;
io_config_valid_r : in std_logic;
io_config : in std_logic_vector(RANK_WIDTH downto 0);
wtr_inhbt_config_r : in std_logic_vector(RANKS - 1 downto 0);
inhbt_rd_config : in std_logic;
inhbt_wr_config : in std_logic;
inhbt_rd_r : in std_logic_vector(RANKS - 1 downto 0);
dq_busy_data : in std_logic
);
end component;
signal act_wait_r : std_logic;
signal allow_auto_pre : std_logic;
signal auto_pre_r : std_logic;
signal bank_wait_in_progress : std_logic;
signal order_q_zero : std_logic;
signal pass_open_bank_ns : std_logic;
signal pass_open_bank_r : std_logic;
signal pre_wait_r : std_logic;
signal precharge_bm_end : std_logic;
signal q_has_priority : std_logic;
signal q_has_rd : std_logic;
signal rb_hit_busies_r : std_logic_vector(nBANK_MACHS * 2 - 1 downto 0);
signal rcv_open_bank : std_logic;
signal rd_half_rmw : std_logic;
signal req_priority_r : std_logic;
signal row_hit_r : std_logic;
signal tail_r : std_logic;
signal wait_for_maint_r : std_logic;
-- Declare intermediate signals for referenced outputs
signal wr_this_rank_r_i : std_logic_vector(RANKS - 1 downto 0);
signal start_rcd_i : std_logic;
signal start_pre_wait_i : std_logic;
signal rts_row_i : std_logic;
signal rts_col_i : std_logic;
signal rtc_i : std_logic;
signal row_cmd_wr_i : std_logic;
signal row_addr_i : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal req_size_r_i : std_logic;
signal req_row_r_i : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal req_ras_i : std_logic;
signal req_periodic_rd_r_i : std_logic;
signal req_cas_i : std_logic;
signal req_bank_r_i : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal rd_this_rank_r_i : std_logic_vector(RANKS - 1 downto 0);
signal rb_hit_busy_ns_i : std_logic;
signal ras_timer_ns_i : std_logic_vector(RAS_TIMER_WIDTH - 1 downto 0);
signal rank_busy_r_i : std_logic_vector(RANKS - 1 downto 0);
signal ordered_r_i : std_logic;
signal ordered_issued_i : std_logic;
signal op_exit_req_i : std_logic;
signal end_rtp_i : std_logic;
signal demand_priority_i : std_logic;
signal demand_act_priority_i : std_logic;
signal col_rdy_wr_i : std_logic;
signal col_addr_i : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal act_this_rank_r_i : std_logic_vector(RANKS - 1 downto 0);
signal idle_ns_i : std_logic;
signal req_wr_r_i : std_logic;
signal rd_wr_r_i : std_logic;
signal bm_end_i : std_logic;
signal idle_r_i : std_logic;
signal head_r_i : std_logic;
signal req_rank_r_i : std_logic_vector(RANK_WIDTH - 1 downto 0);
signal rb_hit_busy_r_i : std_logic;
signal passing_open_bank_i : std_logic;
signal maint_hit_i : std_logic;
signal req_data_buf_addr_r_i : std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
begin
-- Drive referenced outputs
wr_this_rank_r <= wr_this_rank_r_i;
start_rcd <= start_rcd_i;
start_pre_wait <= start_pre_wait_i;
rts_row <= rts_row_i;
rts_col <= rts_col_i;
rtc <= rtc_i;
row_cmd_wr <= row_cmd_wr_i;
row_addr <= row_addr_i;
req_size_r <= req_size_r_i;
req_row_r <= req_row_r_i;
req_ras <= req_ras_i;
req_periodic_rd_r <= req_periodic_rd_r_i;
req_cas <= req_cas_i;
req_bank_r <= req_bank_r_i;
rd_this_rank_r <= rd_this_rank_r_i;
rb_hit_busy_ns <= rb_hit_busy_ns_i;
ras_timer_ns <= ras_timer_ns_i;
rank_busy_r <= rank_busy_r_i;
ordered_r <= ordered_r_i;
ordered_issued <= ordered_issued_i;
op_exit_req <= op_exit_req_i;
end_rtp <= end_rtp_i;
demand_priority <= demand_priority_i;
demand_act_priority <= demand_act_priority_i;
col_rdy_wr <= col_rdy_wr_i;
col_addr <= col_addr_i;
act_this_rank_r <= act_this_rank_r_i;
idle_ns <= idle_ns_i;
req_wr_r <= req_wr_r_i;
rd_wr_r <= rd_wr_r_i;
bm_end <= bm_end_i;
idle_r <= idle_r_i;
head_r <= head_r_i;
req_rank_r <= req_rank_r_i;
rb_hit_busy_r <= rb_hit_busy_r_i;
passing_open_bank <= passing_open_bank_i;
maint_hit <= maint_hit_i;
req_data_buf_addr_r <= req_data_buf_addr_r_i;
bank_compare0 : bank_compare
generic map (
BANK_WIDTH => BANK_WIDTH,
TCQ => TCQ,
BURST_MODE => BURST_MODE,
COL_WIDTH => COL_WIDTH,
DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
ECC => ECC,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
ROW_WIDTH => ROW_WIDTH
)
port map (
-- Outputs
req_data_buf_addr_r => req_data_buf_addr_r_i(DATA_BUF_ADDR_WIDTH - 1 downto 0),
req_periodic_rd_r => req_periodic_rd_r_i,
req_size_r => req_size_r_i,
rd_wr_r => rd_wr_r_i,
req_rank_r => req_rank_r_i(RANK_WIDTH - 1 downto 0),
req_bank_r => req_bank_r_i(BANK_WIDTH - 1 downto 0),
req_row_r => req_row_r_i(ROW_WIDTH - 1 downto 0),
req_wr_r => req_wr_r_i,
req_priority_r => req_priority_r,
rb_hit_busy_r => rb_hit_busy_r_i,
rb_hit_busy_ns => rb_hit_busy_ns_i,
row_hit_r => row_hit_r,
maint_hit => maint_hit_i,
col_addr => col_addr_i(ROW_WIDTH - 1 downto 0),
req_ras => req_ras_i,
req_cas => req_cas_i,
row_cmd_wr => row_cmd_wr_i,
row_addr => row_addr_i(ROW_WIDTH - 1 downto 0),
rank_busy_r => rank_busy_r_i(RANKS - 1 downto 0),
-- Inputs
clk => clk,
idle_ns => idle_ns_i,
idle_r => idle_r_i,
data_buf_addr => data_buf_addr(DATA_BUF_ADDR_WIDTH - 1 downto 0),
periodic_rd_insert => periodic_rd_insert,
size => size,
cmd => cmd(2 downto 0),
sending_col => sending_col,
rank => rank(RANK_WIDTH - 1 downto 0),
periodic_rd_rank_r => periodic_rd_rank_r(RANK_WIDTH - 1 downto 0),
bank => bank(BANK_WIDTH - 1 downto 0),
row => row(ROW_WIDTH - 1 downto 0),
col => col(COL_WIDTH - 1 downto 0),
hi_priority => hi_priority,
maint_rank_r => maint_rank_r(RANK_WIDTH - 1 downto 0),
maint_zq_r => maint_zq_r,
auto_pre_r => auto_pre_r,
rd_half_rmw => rd_half_rmw,
act_wait_r => act_wait_r
);
bank_state0 : bank_state
generic map (
TCQ => TCQ,
ADDR_CMD_MODE => ADDR_CMD_MODE,
BM_CNT_WIDTH => BM_CNT_WIDTH,
BURST_MODE => BURST_MODE,
CWL => CWL,
DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
DRAM_TYPE => DRAM_TYPE,
ECC => ECC,
ID => ID,
NBANK_MACHS => nBANK_MACHS,
NCK_PER_CLK => nCK_PER_CLK,
NCNFG2RD_EN => nCNFG2RD_EN,
NCNFG2WR => nCNFG2WR,
NOP_WAIT => nOP_WAIT,
NRAS_CLKS => nRAS_CLKS,
NRP => nRP,
NRTP => nRTP,
NRCD => nRCD,
NWTP_CLKS => nWTP_CLKS,
ORDERING => ORDERING,
RANKS => RANKS,
RANK_WIDTH => RANK_WIDTH,
RAS_TIMER_WIDTH => RAS_TIMER_WIDTH,
STARVE_LIMIT => STARVE_LIMIT
)
port map (
-- Outputs
start_rcd => start_rcd_i,
act_wait_r => act_wait_r,
ras_timer_ns => ras_timer_ns_i(RAS_TIMER_WIDTH - 1 downto 0),
end_rtp => end_rtp_i,
bank_wait_in_progress => bank_wait_in_progress,
start_pre_wait => start_pre_wait_i,
op_exit_req => op_exit_req_i,
pre_wait_r => pre_wait_r,
allow_auto_pre => allow_auto_pre,
precharge_bm_end => precharge_bm_end,
demand_act_priority => demand_act_priority_i,
rts_row => rts_row_i,
act_this_rank_r => act_this_rank_r_i(RANKS - 1 downto 0),
demand_priority => demand_priority_i,
rtc => rtc_i,
col_rdy_wr => col_rdy_wr_i,
rts_col => rts_col_i,
wr_this_rank_r => wr_this_rank_r_i(RANKS - 1 downto 0),
rd_this_rank_r => rd_this_rank_r_i(RANKS - 1 downto 0),
rd_half_rmw => rd_half_rmw,
-- Inputs
clk => clk,
rst => rst,
bm_end => bm_end_i,
pass_open_bank_r => pass_open_bank_r,
sending_row => sending_row,
rcv_open_bank => rcv_open_bank,
sending_col => sending_col,
rd_wr_r => rd_wr_r_i,
req_wr_r => req_wr_r_i,
rd_data_addr => rd_data_addr(DATA_BUF_ADDR_WIDTH - 1 downto 0),
req_data_buf_addr_r => req_data_buf_addr_r_i(DATA_BUF_ADDR_WIDTH - 1 downto 0),
dfi_rddata_valid => dfi_rddata_valid,
rd_rmw => rd_rmw,
ras_timer_ns_in => ras_timer_ns_in((2 * (RAS_TIMER_WIDTH * nBANK_MACHS)) - 1 downto 0),
rb_hit_busies_r => rb_hit_busies_r((nBANK_MACHS * 2) - 1 downto 0),
idle_r => idle_r_i,
passing_open_bank => passing_open_bank_i,
low_idle_cnt_r => low_idle_cnt_r,
op_exit_grant => op_exit_grant,
tail_r => tail_r,
auto_pre_r => auto_pre_r,
pass_open_bank_ns => pass_open_bank_ns,
req_rank_r => req_rank_r_i(RANK_WIDTH - 1 downto 0),
req_rank_r_in => req_rank_r_in((RANK_WIDTH * nBANK_MACHS * 2) - 1 downto 0),
start_rcd_in => start_rcd_in((nBANK_MACHS * 2) - 1 downto 0),
inhbt_act_faw_r => inhbt_act_faw_r(RANKS - 1 downto 0),
wait_for_maint_r => wait_for_maint_r,
head_r => head_r_i,
sent_row => sent_row,
demand_act_priority_in => demand_act_priority_in((nBANK_MACHS * 2) - 1 downto 0),
order_q_zero => order_q_zero,
sent_col => sent_col,
q_has_rd => q_has_rd,
q_has_priority => q_has_priority,
req_priority_r => req_priority_r,
idle_ns => idle_ns_i,
demand_priority_in => demand_priority_in((nBANK_MACHS * 2) - 1 downto 0),
io_config_strobe => io_config_strobe,
io_config_valid_r => io_config_valid_r,
io_config => io_config(RANK_WIDTH downto 0),
wtr_inhbt_config_r => wtr_inhbt_config_r(RANKS - 1 downto 0),
inhbt_rd_config => inhbt_rd_config,
inhbt_wr_config => inhbt_wr_config,
inhbt_rd_r => inhbt_rd_r(RANKS - 1 downto 0),
dq_busy_data => dq_busy_data
);
bank_queue0 : bank_queue
generic map (
TCQ => TCQ,
BM_CNT_WIDTH => BM_CNT_WIDTH,
NBANK_MACHS => nBANK_MACHS,
ORDERING => ORDERING,
ID => ID
)
port map (
-- Outputs
head_r => head_r_i,
tail_r => tail_r,
idle_ns => idle_ns_i,
idle_r => idle_r_i,
pass_open_bank_ns => pass_open_bank_ns,
pass_open_bank_r => pass_open_bank_r,
auto_pre_r => auto_pre_r,
bm_end => bm_end_i,
passing_open_bank => passing_open_bank_i,
ordered_issued => ordered_issued_i,
ordered_r => ordered_r_i,
order_q_zero => order_q_zero,
rcv_open_bank => rcv_open_bank,
rb_hit_busies_r => rb_hit_busies_r(nBANK_MACHS * 2 - 1 downto 0),
q_has_rd => q_has_rd,
q_has_priority => q_has_priority,
wait_for_maint_r => wait_for_maint_r,
-- Inputs
clk => clk,
rst => rst,
accept_internal_r => accept_internal_r,
use_addr => use_addr,
periodic_rd_ack_r => periodic_rd_ack_r,
bm_end_in => bm_end_in((nBANK_MACHS * 2) - 1 downto 0),
idle_cnt => idle_cnt(BM_CNT_WIDTH - 1 downto 0),
rb_hit_busy_cnt => rb_hit_busy_cnt(BM_CNT_WIDTH - 1 downto 0),
accept_req => accept_req,
rb_hit_busy_r => rb_hit_busy_r_i,
maint_idle => maint_idle,
maint_hit => maint_hit_i,
row_hit_r => row_hit_r,
pre_wait_r => pre_wait_r,
allow_auto_pre => allow_auto_pre,
sending_col => sending_col,
req_wr_r => req_wr_r_i,
rd_wr_r => rd_wr_r_i,
bank_wait_in_progress => bank_wait_in_progress,
precharge_bm_end => precharge_bm_end,
adv_order_q => adv_order_q,
order_cnt => order_cnt(BM_CNT_WIDTH - 1 downto 0),
rb_hit_busy_ns_in => rb_hit_busy_ns_in((nBANK_MACHS * 2) - 1 downto 0),
passing_open_bank_in => passing_open_bank_in((nBANK_MACHS * 2) - 1 downto 0),
was_wr => was_wr,
maint_req_r => maint_req_r,
was_priority => was_priority
);
end architecture trans;
|
architecture rtl of fifo is
begin
procedure_call_label : postponed wr_en(a, b);
procedure_call_label : postponed wr_en(a, b);
end architecture rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:03:30 06/04/2011
-- Design Name:
-- Module Name: tx_arbitrator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: arbitrate between two sources that want to transmit onto a bus
-- handles arbitration and multiplexing
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - Made sticky on port M1 to optimise access on this port and allow immediate grant
-- Revision 0.03 - Added first
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tx_arbitrator is
port (
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_1 : in std_logic; -- tdata is valid
first_1 : in std_logic; -- indicates first byte of frame
last_1 : in std_logic; -- indicates last byte of frame
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in std_logic_vector(7 downto 0); -- data byte to tx
valid_2 : in std_logic; -- tdata is valid
first_2 : in std_logic; -- indicates first byte of frame
last_2 : in std_logic; -- indicates last byte of frame
data : out std_logic_vector(7 downto 0); -- data byte to tx
valid : out std_logic; -- tdata is valid
first : out std_logic; -- indicates first byte of frame
last : out std_logic -- indicates last byte of frame
);
end tx_arbitrator;
architecture Behavioral of tx_arbitrator is
type grant_type is (M1,M2);
signal grant : grant_type;
begin
combinatorial : process (
grant,
data_1, valid_1, first_1, last_1,
data_2, valid_2, first_2, last_2
)
begin
-- grant outputs
case grant is
when M1 =>
grant_1 <= '1';
grant_2 <= '0';
when M2 =>
grant_1 <= '0';
grant_2 <= '1';
end case;
-- multiplexer
if grant = M1 then
data <= data_1;
valid <= valid_1;
first <= first_1;
last <= last_1;
else
data <= data_2;
valid <= valid_2;
first <= first_2;
last <= last_2;
end if;
end process;
sequential : process (clk, reset, req_1, req_2, grant)
begin
if rising_edge(clk) then
if reset = '1' then
grant <= M1;
else
case grant is
when M1 =>
if req_1 = '1' then
grant <= M1;
elsif req_2 = '1' then
grant <= M2;
end if;
when M2 =>
if req_2 = '1' then
grant <= M2;
else
grant <= M1;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.